Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 97.84 93.81 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2809
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html
T2757 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3796450885 Jul 04 06:59:42 PM PDT 24 Jul 04 06:59:44 PM PDT 24 61370909 ps
T2758 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3587847083 Jul 04 07:00:03 PM PDT 24 Jul 04 07:00:04 PM PDT 24 51467974 ps
T2759 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1593962763 Jul 04 06:59:58 PM PDT 24 Jul 04 06:59:59 PM PDT 24 71216527 ps
T2760 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3398705062 Jul 04 06:59:57 PM PDT 24 Jul 04 07:00:02 PM PDT 24 1546732903 ps
T2761 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.769152989 Jul 04 06:59:54 PM PDT 24 Jul 04 06:59:55 PM PDT 24 65541166 ps
T310 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1714029141 Jul 04 06:59:55 PM PDT 24 Jul 04 07:00:01 PM PDT 24 1129768714 ps
T2762 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1867174191 Jul 04 07:00:03 PM PDT 24 Jul 04 07:00:05 PM PDT 24 110175422 ps
T2763 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2545049557 Jul 04 06:59:50 PM PDT 24 Jul 04 06:59:53 PM PDT 24 261887285 ps
T315 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2751710980 Jul 04 06:59:46 PM PDT 24 Jul 04 06:59:51 PM PDT 24 907421242 ps
T2764 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.60319328 Jul 04 06:59:41 PM PDT 24 Jul 04 06:59:42 PM PDT 24 59827935 ps
T2765 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.65703976 Jul 04 07:00:03 PM PDT 24 Jul 04 07:00:04 PM PDT 24 46728320 ps
T2766 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.415339670 Jul 04 07:00:07 PM PDT 24 Jul 04 07:00:07 PM PDT 24 47201421 ps
T2767 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3685471492 Jul 04 06:59:28 PM PDT 24 Jul 04 06:59:30 PM PDT 24 66925075 ps
T2768 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3717430480 Jul 04 06:59:56 PM PDT 24 Jul 04 06:59:57 PM PDT 24 33068003 ps
T311 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2227582073 Jul 04 06:59:34 PM PDT 24 Jul 04 06:59:39 PM PDT 24 872124481 ps
T312 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2361671392 Jul 04 06:59:44 PM PDT 24 Jul 04 06:59:46 PM PDT 24 277659945 ps
T313 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3831267247 Jul 04 06:59:23 PM PDT 24 Jul 04 06:59:28 PM PDT 24 755074844 ps
T2769 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.661963575 Jul 04 06:59:57 PM PDT 24 Jul 04 06:59:58 PM PDT 24 51895118 ps
T2770 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3732880521 Jul 04 07:00:08 PM PDT 24 Jul 04 07:00:09 PM PDT 24 36471895 ps
T2771 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.816064677 Jul 04 06:59:45 PM PDT 24 Jul 04 06:59:47 PM PDT 24 110580193 ps
T2772 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.948467267 Jul 04 06:59:52 PM PDT 24 Jul 04 06:59:53 PM PDT 24 57898524 ps
T2773 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1250545558 Jul 04 06:59:55 PM PDT 24 Jul 04 06:59:55 PM PDT 24 38498897 ps
T2774 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3895182536 Jul 04 06:59:58 PM PDT 24 Jul 04 07:00:01 PM PDT 24 314757845 ps
T2775 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2597460637 Jul 04 06:59:26 PM PDT 24 Jul 04 06:59:28 PM PDT 24 253514620 ps
T2776 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1513909985 Jul 04 07:00:04 PM PDT 24 Jul 04 07:00:05 PM PDT 24 46410284 ps
T2777 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3175575015 Jul 04 06:59:56 PM PDT 24 Jul 04 06:59:59 PM PDT 24 174206612 ps
T2778 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.329194482 Jul 04 06:59:27 PM PDT 24 Jul 04 06:59:36 PM PDT 24 1196503770 ps
T2779 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1005614100 Jul 04 06:59:55 PM PDT 24 Jul 04 06:59:57 PM PDT 24 92123917 ps
T2780 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2556378813 Jul 04 06:59:27 PM PDT 24 Jul 04 06:59:29 PM PDT 24 206857278 ps
T2781 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2578183318 Jul 04 07:00:02 PM PDT 24 Jul 04 07:00:04 PM PDT 24 469557265 ps
T2782 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2643823836 Jul 04 06:59:41 PM PDT 24 Jul 04 06:59:42 PM PDT 24 40458132 ps
T2783 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2426761329 Jul 04 06:59:54 PM PDT 24 Jul 04 06:59:55 PM PDT 24 45656214 ps
T2784 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1588309854 Jul 04 06:59:46 PM PDT 24 Jul 04 06:59:48 PM PDT 24 189131818 ps
T2785 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2475755390 Jul 04 06:59:34 PM PDT 24 Jul 04 06:59:37 PM PDT 24 349941798 ps
T2786 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1314139024 Jul 04 06:59:50 PM PDT 24 Jul 04 06:59:50 PM PDT 24 41078834 ps
T2787 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2585890553 Jul 04 07:00:01 PM PDT 24 Jul 04 07:00:02 PM PDT 24 36537515 ps
T2788 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2529931553 Jul 04 07:00:03 PM PDT 24 Jul 04 07:00:04 PM PDT 24 85082673 ps
T2789 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1611835238 Jul 04 06:59:29 PM PDT 24 Jul 04 06:59:34 PM PDT 24 180345200 ps
T2790 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1097259678 Jul 04 06:59:57 PM PDT 24 Jul 04 07:00:02 PM PDT 24 755346503 ps
T2791 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1794751012 Jul 04 06:59:34 PM PDT 24 Jul 04 06:59:42 PM PDT 24 1267829826 ps
T2792 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.189460695 Jul 04 06:59:55 PM PDT 24 Jul 04 06:59:55 PM PDT 24 78500044 ps
T2793 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3728266616 Jul 04 06:59:49 PM PDT 24 Jul 04 06:59:51 PM PDT 24 106990759 ps
T319 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1202212195 Jul 04 06:59:45 PM PDT 24 Jul 04 06:59:50 PM PDT 24 1321427738 ps
T2794 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.316433413 Jul 04 06:59:55 PM PDT 24 Jul 04 06:59:56 PM PDT 24 41969482 ps
T2795 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3527747589 Jul 04 06:59:41 PM PDT 24 Jul 04 06:59:43 PM PDT 24 258632681 ps
T2796 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.270651524 Jul 04 06:59:27 PM PDT 24 Jul 04 06:59:28 PM PDT 24 53740185 ps
T2797 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.4012309304 Jul 04 06:59:51 PM PDT 24 Jul 04 06:59:52 PM PDT 24 88137703 ps
T2798 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1870721494 Jul 04 06:59:20 PM PDT 24 Jul 04 06:59:21 PM PDT 24 40016540 ps
T2799 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2841411895 Jul 04 06:59:42 PM PDT 24 Jul 04 06:59:43 PM PDT 24 42089996 ps
T2800 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1079442431 Jul 04 06:59:35 PM PDT 24 Jul 04 06:59:36 PM PDT 24 40223814 ps
T2801 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3151524213 Jul 04 06:59:28 PM PDT 24 Jul 04 06:59:28 PM PDT 24 44391218 ps
T2802 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1099320480 Jul 04 06:59:52 PM PDT 24 Jul 04 06:59:53 PM PDT 24 52057421 ps
T2803 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1001534946 Jul 04 07:00:04 PM PDT 24 Jul 04 07:00:05 PM PDT 24 43173712 ps
T2804 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3680987745 Jul 04 06:59:45 PM PDT 24 Jul 04 06:59:46 PM PDT 24 60558951 ps
T2805 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.870972480 Jul 04 06:59:37 PM PDT 24 Jul 04 06:59:43 PM PDT 24 1132339677 ps
T2806 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1546151437 Jul 04 06:59:41 PM PDT 24 Jul 04 06:59:44 PM PDT 24 96221507 ps
T2807 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3557403675 Jul 04 06:59:28 PM PDT 24 Jul 04 06:59:29 PM PDT 24 68939811 ps
T2808 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2976191493 Jul 04 06:59:56 PM PDT 24 Jul 04 06:59:57 PM PDT 24 85835729 ps
T2809 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1000440374 Jul 04 06:59:51 PM PDT 24 Jul 04 06:59:54 PM PDT 24 118905124 ps

Test location /workspace/coverage/default/4.usbdev_rand_suspends.906856447
Short name T4
Test name
Test status
Simulation time 14665246728 ps
CPU time 103.19 seconds
Started Jul 04 06:07:10 PM PDT 24
Finished Jul 04 06:08:53 PM PDT 24
Peak memory 206544 kb
Host smart-ace2e97c-56df-4279-ac15-40239ee99d96
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=906856447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.906856447
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1639259067
Short name T302
Test name
Test status
Simulation time 43005309 ps
CPU time 0.7 seconds
Started Jul 04 07:00:01 PM PDT 24
Finished Jul 04 07:00:02 PM PDT 24
Peak memory 205800 kb
Host smart-9ab9c45b-b7b9-4efb-8c80-b8d1a93e8c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1639259067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1639259067
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.896220739
Short name T2
Test name
Test status
Simulation time 1041695883 ps
CPU time 2.7 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:10:07 PM PDT 24
Peak memory 206664 kb
Host smart-6b048e55-63e3-4a48-9318-e82979e2b4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89622
0739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.896220739
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1737953069
Short name T216
Test name
Test status
Simulation time 587753194 ps
CPU time 2.87 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 07:00:00 PM PDT 24
Peak memory 206036 kb
Host smart-b7c24b68-6573-4280-abf9-8d7b69ca2ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1737953069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1737953069
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3758692137
Short name T10
Test name
Test status
Simulation time 23390858947 ps
CPU time 23.3 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:14:18 PM PDT 24
Peak memory 206516 kb
Host smart-657156c5-d3c6-4478-9c60-dcae2a0899ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3758692137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3758692137
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3319948407
Short name T81
Test name
Test status
Simulation time 488756303 ps
CPU time 1.4 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:04:58 PM PDT 24
Peak memory 206172 kb
Host smart-319afcb9-a830-4a8a-9009-2d9aa56e2b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33199
48407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3319948407
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2545064386
Short name T575
Test name
Test status
Simulation time 245437284 ps
CPU time 0.87 seconds
Started Jul 04 06:04:23 PM PDT 24
Finished Jul 04 06:04:24 PM PDT 24
Peak memory 206196 kb
Host smart-d0eb979e-64d8-452f-b9d3-636879ced6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25450
64386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2545064386
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2951397639
Short name T229
Test name
Test status
Simulation time 65233631 ps
CPU time 0.76 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 205792 kb
Host smart-a9975a81-38d7-483f-a416-0b6eaa35e465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2951397639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2951397639
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3391069487
Short name T241
Test name
Test status
Simulation time 78927160 ps
CPU time 1.91 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 222116 kb
Host smart-98e9a279-28d1-4c2c-91e9-78113ac179d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3391069487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3391069487
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3910796640
Short name T3
Test name
Test status
Simulation time 172642672 ps
CPU time 0.79 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:21 PM PDT 24
Peak memory 206120 kb
Host smart-c5bca33e-9257-44ef-8dc1-21f52edf0dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39107
96640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3910796640
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2081162672
Short name T45
Test name
Test status
Simulation time 161431799 ps
CPU time 0.8 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206188 kb
Host smart-a37a6f9b-30e0-4bb9-aede-4177d4913063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20811
62672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2081162672
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2888912541
Short name T106
Test name
Test status
Simulation time 214026458 ps
CPU time 0.87 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206124 kb
Host smart-2f939f0a-f631-451c-8f1b-a643c24ac4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28889
12541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2888912541
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.259683357
Short name T196
Test name
Test status
Simulation time 346143930 ps
CPU time 1.26 seconds
Started Jul 04 06:11:03 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206196 kb
Host smart-180e40c1-c16a-435f-a9ed-fd531da42a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
3357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.259683357
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.85184089
Short name T28
Test name
Test status
Simulation time 55580855 ps
CPU time 0.69 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:15 PM PDT 24
Peak memory 206212 kb
Host smart-96fb487b-c3b1-467c-b506-2d3327c51d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85184
089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.85184089
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1750228005
Short name T48
Test name
Test status
Simulation time 231206965 ps
CPU time 0.96 seconds
Started Jul 04 06:16:18 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206004 kb
Host smart-43ddec2b-9e62-4929-b009-144a7324064d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
28005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1750228005
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3630343729
Short name T225
Test name
Test status
Simulation time 49166367 ps
CPU time 0.66 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 205836 kb
Host smart-ecb0571f-1c42-4111-a592-a6083e667abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3630343729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3630343729
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3904841271
Short name T215
Test name
Test status
Simulation time 496791330 ps
CPU time 1.52 seconds
Started Jul 04 06:04:49 PM PDT 24
Finished Jul 04 06:04:51 PM PDT 24
Peak memory 224084 kb
Host smart-cf69529f-4f6b-4a82-8cad-9dac82472026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3904841271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3904841271
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1190760901
Short name T43
Test name
Test status
Simulation time 10903748939 ps
CPU time 98.42 seconds
Started Jul 04 06:05:46 PM PDT 24
Finished Jul 04 06:07:24 PM PDT 24
Peak memory 206568 kb
Host smart-bd32a838-5d68-4fd4-854e-7a19bc8a0e95
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1190760901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1190760901
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1928589057
Short name T543
Test name
Test status
Simulation time 47468848 ps
CPU time 0.67 seconds
Started Jul 04 06:05:44 PM PDT 24
Finished Jul 04 06:05:45 PM PDT 24
Peak memory 206212 kb
Host smart-023a2af9-4414-40a1-a4c5-377b2b905283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1928589057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1928589057
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.918868589
Short name T80
Test name
Test status
Simulation time 309361094 ps
CPU time 1 seconds
Started Jul 04 06:04:36 PM PDT 24
Finished Jul 04 06:04:38 PM PDT 24
Peak memory 206192 kb
Host smart-a546478e-f4de-4dfa-b232-c9420dda7286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91886
8589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.918868589
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.818399508
Short name T534
Test name
Test status
Simulation time 13307764537 ps
CPU time 13.55 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206240 kb
Host smart-42fe5af4-2cef-473b-843a-5f93f6766b86
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=818399508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.818399508
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.999479103
Short name T46
Test name
Test status
Simulation time 20243734550 ps
CPU time 18.04 seconds
Started Jul 04 06:04:33 PM PDT 24
Finished Jul 04 06:04:51 PM PDT 24
Peak memory 206240 kb
Host smart-9fac2d8c-e82a-44ba-8d39-11e2e1c8d8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99947
9103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.999479103
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1068854746
Short name T62
Test name
Test status
Simulation time 860135241 ps
CPU time 2.11 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:23 PM PDT 24
Peak memory 206448 kb
Host smart-965a61a7-64be-461c-8167-735006d8b48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
54746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1068854746
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2508781080
Short name T276
Test name
Test status
Simulation time 141165690 ps
CPU time 1.06 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:29 PM PDT 24
Peak memory 206008 kb
Host smart-a98c3106-21f1-4705-83a6-84e2b46c09cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2508781080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2508781080
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3866202056
Short name T2752
Test name
Test status
Simulation time 36946234 ps
CPU time 0.67 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:45 PM PDT 24
Peak memory 205804 kb
Host smart-2c15891a-8aa5-4dae-82a2-793a7f4ef72f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3866202056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3866202056
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3176635939
Short name T20
Test name
Test status
Simulation time 188724770 ps
CPU time 0.89 seconds
Started Jul 04 06:09:14 PM PDT 24
Finished Jul 04 06:09:15 PM PDT 24
Peak memory 206188 kb
Host smart-64ffb082-4a71-4bbd-a332-be6d1e45aba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31766
35939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3176635939
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1224077471
Short name T152
Test name
Test status
Simulation time 10350026333 ps
CPU time 251.88 seconds
Started Jul 04 06:08:59 PM PDT 24
Finished Jul 04 06:13:11 PM PDT 24
Peak memory 206548 kb
Host smart-4fefbeb7-c254-4517-8bb3-4554c25fbd6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1224077471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1224077471
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1240561368
Short name T262
Test name
Test status
Simulation time 970026172 ps
CPU time 5.3 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:33 PM PDT 24
Peak memory 205940 kb
Host smart-5d60a024-4e95-48bf-934b-b00c6bedbc9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1240561368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1240561368
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3538016010
Short name T76
Test name
Test status
Simulation time 198708636 ps
CPU time 0.83 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:04:59 PM PDT 24
Peak memory 206168 kb
Host smart-33d39218-0eed-4cc7-a641-b9221324a121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
16010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3538016010
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1076514604
Short name T93
Test name
Test status
Simulation time 10748003625 ps
CPU time 21.18 seconds
Started Jul 04 06:08:06 PM PDT 24
Finished Jul 04 06:08:27 PM PDT 24
Peak memory 206528 kb
Host smart-d617cc4b-ff6a-41ff-a1ee-a714c553b304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10765
14604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1076514604
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.659261753
Short name T72
Test name
Test status
Simulation time 529928266 ps
CPU time 1.42 seconds
Started Jul 04 06:03:57 PM PDT 24
Finished Jul 04 06:03:58 PM PDT 24
Peak memory 206128 kb
Host smart-a81b253a-13a9-4960-b5e3-4e5c6b2105b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65926
1753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.659261753
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.316433413
Short name T2794
Test name
Test status
Simulation time 41969482 ps
CPU time 0.67 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 205800 kb
Host smart-72297c1c-554c-472a-b51d-fc0050fc653e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316433413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.316433413
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.189799733
Short name T397
Test name
Test status
Simulation time 3628348396 ps
CPU time 4.94 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 206288 kb
Host smart-0ca00487-2e04-4315-8349-7c1075c531f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=189799733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.189799733
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.167009855
Short name T54
Test name
Test status
Simulation time 283923683 ps
CPU time 0.97 seconds
Started Jul 04 06:04:41 PM PDT 24
Finished Jul 04 06:04:43 PM PDT 24
Peak memory 206224 kb
Host smart-92a5f169-05fd-458b-af55-6ef661ecf6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16700
9855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.167009855
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.238985127
Short name T67
Test name
Test status
Simulation time 167718652 ps
CPU time 0.74 seconds
Started Jul 04 06:03:41 PM PDT 24
Finished Jul 04 06:03:42 PM PDT 24
Peak memory 206176 kb
Host smart-df85c644-19b2-4027-84eb-1f4ed034b748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
5127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.238985127
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2747959921
Short name T104
Test name
Test status
Simulation time 11983099713 ps
CPU time 223.21 seconds
Started Jul 04 06:04:49 PM PDT 24
Finished Jul 04 06:08:32 PM PDT 24
Peak memory 206548 kb
Host smart-a92587b3-ad99-43a4-a2ef-9c992365a19d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2747959921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2747959921
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3831267247
Short name T313
Test name
Test status
Simulation time 755074844 ps
CPU time 4.85 seconds
Started Jul 04 06:59:23 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 206072 kb
Host smart-88aa059f-fc2e-467e-8804-f77960c621bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3831267247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3831267247
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2751710980
Short name T315
Test name
Test status
Simulation time 907421242 ps
CPU time 4.69 seconds
Started Jul 04 06:59:46 PM PDT 24
Finished Jul 04 06:59:51 PM PDT 24
Peak memory 205972 kb
Host smart-3a32315a-fae7-4561-9e30-2aaf8381d6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2751710980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2751710980
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1714029141
Short name T310
Test name
Test status
Simulation time 1129768714 ps
CPU time 5.9 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 07:00:01 PM PDT 24
Peak memory 205992 kb
Host smart-d73a8252-869c-47ed-9d4e-b478e7b9ac81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1714029141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1714029141
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1202212195
Short name T319
Test name
Test status
Simulation time 1321427738 ps
CPU time 5.13 seconds
Started Jul 04 06:59:45 PM PDT 24
Finished Jul 04 06:59:50 PM PDT 24
Peak memory 205968 kb
Host smart-e76740e3-86a4-4b5a-a1de-e6b7a78ff655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1202212195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1202212195
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.4271393153
Short name T164
Test name
Test status
Simulation time 8881852328 ps
CPU time 58.5 seconds
Started Jul 04 06:06:51 PM PDT 24
Finished Jul 04 06:07:50 PM PDT 24
Peak memory 206452 kb
Host smart-475d574f-46bb-4ec3-973d-5c8e3df878f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4271393153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.4271393153
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2430108912
Short name T2719
Test name
Test status
Simulation time 262450850 ps
CPU time 2.95 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:53 PM PDT 24
Peak memory 214224 kb
Host smart-051021c5-b67a-4776-9fa5-79a727a3ed71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430108912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2430108912
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1818081671
Short name T175
Test name
Test status
Simulation time 1157808349 ps
CPU time 2.5 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:09:52 PM PDT 24
Peak memory 206396 kb
Host smart-8ebad63b-6d24-497f-96fe-ec8e5eaf6a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18180
81671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1818081671
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1877252565
Short name T155
Test name
Test status
Simulation time 168095989 ps
CPU time 0.76 seconds
Started Jul 04 06:06:41 PM PDT 24
Finished Jul 04 06:06:42 PM PDT 24
Peak memory 206184 kb
Host smart-66da793c-3101-4916-bde0-cf317be68409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18772
52565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1877252565
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.587174756
Short name T210
Test name
Test status
Simulation time 142786096 ps
CPU time 0.76 seconds
Started Jul 04 06:11:06 PM PDT 24
Finished Jul 04 06:11:07 PM PDT 24
Peak memory 206188 kb
Host smart-7972508f-906a-4a85-a780-806a41e2940c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58717
4756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.587174756
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1680586934
Short name T208
Test name
Test status
Simulation time 23488247516 ps
CPU time 25.96 seconds
Started Jul 04 06:11:51 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206504 kb
Host smart-41ac9ecc-b9c9-4624-b395-a911ec90d361
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1680586934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1680586934
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2416882335
Short name T84
Test name
Test status
Simulation time 144330838 ps
CPU time 0.77 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:04:59 PM PDT 24
Peak memory 206216 kb
Host smart-44f55324-6853-4a20-a1a1-a37b33b468a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24168
82335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2416882335
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2552745741
Short name T203
Test name
Test status
Simulation time 390451546 ps
CPU time 2.24 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:07 PM PDT 24
Peak memory 206348 kb
Host smart-f18755ee-6661-41a9-8758-ac338436fcc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
45741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2552745741
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.22748346
Short name T168
Test name
Test status
Simulation time 1370214495 ps
CPU time 3.14 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:16 PM PDT 24
Peak memory 206348 kb
Host smart-6060a0a9-3544-4a79-be8b-5b555f8853bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22748
346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.22748346
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2020048067
Short name T59
Test name
Test status
Simulation time 154603552 ps
CPU time 0.79 seconds
Started Jul 04 06:03:43 PM PDT 24
Finished Jul 04 06:03:44 PM PDT 24
Peak memory 206200 kb
Host smart-df9f9c00-09bf-4444-bcbf-7eec4f4fcd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20200
48067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2020048067
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3027587122
Short name T69
Test name
Test status
Simulation time 4165894670 ps
CPU time 9.49 seconds
Started Jul 04 06:03:56 PM PDT 24
Finished Jul 04 06:04:06 PM PDT 24
Peak memory 206464 kb
Host smart-618c657f-c63a-41e8-a11b-ebf526204174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275
87122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3027587122
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3392939908
Short name T70
Test name
Test status
Simulation time 183766734 ps
CPU time 0.76 seconds
Started Jul 04 06:04:12 PM PDT 24
Finished Jul 04 06:04:13 PM PDT 24
Peak memory 206176 kb
Host smart-686778e2-b2dc-4cd7-b761-d013aa523d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
39908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3392939908
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.507404559
Short name T2405
Test name
Test status
Simulation time 188513634 ps
CPU time 0.84 seconds
Started Jul 04 06:04:41 PM PDT 24
Finished Jul 04 06:04:42 PM PDT 24
Peak memory 206164 kb
Host smart-4047fb58-e779-439e-b65e-6bdab6db1de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50740
4559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.507404559
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.896202582
Short name T200
Test name
Test status
Simulation time 152088409 ps
CPU time 0.76 seconds
Started Jul 04 06:11:01 PM PDT 24
Finished Jul 04 06:11:02 PM PDT 24
Peak memory 206196 kb
Host smart-c87b3d32-0330-4e36-8026-8da71efd3b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89620
2582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.896202582
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3702464727
Short name T51
Test name
Test status
Simulation time 184244976 ps
CPU time 0.92 seconds
Started Jul 04 06:05:48 PM PDT 24
Finished Jul 04 06:05:49 PM PDT 24
Peak memory 206152 kb
Host smart-006cdc49-2cd1-4e0e-9b8e-65d69b16ca07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37024
64727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3702464727
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4063663761
Short name T838
Test name
Test status
Simulation time 60713995 ps
CPU time 0.66 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:15 PM PDT 24
Peak memory 206172 kb
Host smart-e25c5e15-9039-4cc4-bd9a-55e17681afce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636
63761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4063663761
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3196031777
Short name T170
Test name
Test status
Simulation time 8134137473 ps
CPU time 73.06 seconds
Started Jul 04 06:07:16 PM PDT 24
Finished Jul 04 06:08:29 PM PDT 24
Peak memory 206484 kb
Host smart-ed75cb85-334f-48e2-aa00-b44fb31fd41f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3196031777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3196031777
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3089004164
Short name T2714
Test name
Test status
Simulation time 92093176 ps
CPU time 1.17 seconds
Started Jul 04 06:59:48 PM PDT 24
Finished Jul 04 06:59:49 PM PDT 24
Peak memory 205976 kb
Host smart-8e731271-b3ea-42ab-b500-d9935640ea6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3089004164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3089004164
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4034557993
Short name T135
Test name
Test status
Simulation time 202456614 ps
CPU time 0.84 seconds
Started Jul 04 06:04:20 PM PDT 24
Finished Jul 04 06:04:21 PM PDT 24
Peak memory 206172 kb
Host smart-6d39c39d-fff6-4b65-97c1-85b5948411ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
57993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4034557993
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3526236592
Short name T55
Test name
Test status
Simulation time 445301256 ps
CPU time 1.32 seconds
Started Jul 04 06:04:42 PM PDT 24
Finished Jul 04 06:04:44 PM PDT 24
Peak memory 206208 kb
Host smart-a201b96d-ead7-4899-a974-8adfbcb3d8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262
36592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3526236592
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1053991113
Short name T123
Test name
Test status
Simulation time 228366233 ps
CPU time 0.89 seconds
Started Jul 04 06:05:17 PM PDT 24
Finished Jul 04 06:05:18 PM PDT 24
Peak memory 206192 kb
Host smart-97dca448-01b2-4036-bd99-7922f2c8b985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10539
91113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1053991113
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3635599311
Short name T126
Test name
Test status
Simulation time 227546376 ps
CPU time 0.88 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 206212 kb
Host smart-cafcc251-a00d-4b28-8b62-331af381f3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
99311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3635599311
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3922912530
Short name T2234
Test name
Test status
Simulation time 17558104053 ps
CPU time 36.82 seconds
Started Jul 04 06:09:16 PM PDT 24
Finished Jul 04 06:09:53 PM PDT 24
Peak memory 206448 kb
Host smart-7524606f-3659-4c0b-98ed-6a43e29f0d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229
12530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3922912530
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1677938695
Short name T361
Test name
Test status
Simulation time 159348535 ps
CPU time 0.82 seconds
Started Jul 04 06:09:14 PM PDT 24
Finished Jul 04 06:09:15 PM PDT 24
Peak memory 206180 kb
Host smart-dda5a396-805c-4d63-abcd-ed2f379e82e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
38695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1677938695
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1948250815
Short name T1184
Test name
Test status
Simulation time 1077672033 ps
CPU time 2.41 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:37 PM PDT 24
Peak memory 206404 kb
Host smart-0d504086-5962-402e-bdd9-c92df1e66246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19482
50815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1948250815
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3024683715
Short name T141
Test name
Test status
Simulation time 247389007 ps
CPU time 0.88 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:40 PM PDT 24
Peak memory 206176 kb
Host smart-fdae38c1-766f-4082-8654-50ba278700c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30246
83715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3024683715
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2023682406
Short name T2095
Test name
Test status
Simulation time 181214209 ps
CPU time 0.87 seconds
Started Jul 04 06:10:02 PM PDT 24
Finished Jul 04 06:10:03 PM PDT 24
Peak memory 206188 kb
Host smart-2c1a307f-bc1b-4f93-a3a1-85ec84be1897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236
82406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2023682406
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3333690415
Short name T122
Test name
Test status
Simulation time 166915116 ps
CPU time 0.83 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206224 kb
Host smart-1b4db288-8336-4cec-80ed-f98251233317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33336
90415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3333690415
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3879791500
Short name T130
Test name
Test status
Simulation time 206088311 ps
CPU time 0.89 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206180 kb
Host smart-e0830f8a-b5fd-48cd-be17-23b9b11bad8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38797
91500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3879791500
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.752826577
Short name T144
Test name
Test status
Simulation time 193371333 ps
CPU time 0.85 seconds
Started Jul 04 06:12:04 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206200 kb
Host smart-4c0c15b8-d13a-4ad7-9ec7-0784d00dd36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75282
6577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.752826577
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3288956983
Short name T1489
Test name
Test status
Simulation time 184912613 ps
CPU time 0.88 seconds
Started Jul 04 06:12:08 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206168 kb
Host smart-355e3312-57a8-49c7-8aed-fcb845da61e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32889
56983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3288956983
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1086371406
Short name T142
Test name
Test status
Simulation time 214683070 ps
CPU time 0.88 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:13:14 PM PDT 24
Peak memory 206132 kb
Host smart-681617ec-8026-43f3-89d1-2a158b6dc2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10863
71406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1086371406
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2129562161
Short name T129
Test name
Test status
Simulation time 182518357 ps
CPU time 0.89 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206176 kb
Host smart-b3d7cbf7-6c4c-47dd-b5a4-3772b61d0b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21295
62161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2129562161
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.50463166
Short name T279
Test name
Test status
Simulation time 78406928 ps
CPU time 1.95 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:30 PM PDT 24
Peak memory 206024 kb
Host smart-6a9c3d78-1a06-4a3f-bee5-68c1eaed1ad7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=50463166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.50463166
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3273630695
Short name T278
Test name
Test status
Simulation time 1518739818 ps
CPU time 8.93 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:37 PM PDT 24
Peak memory 205928 kb
Host smart-9e3a52de-3777-4143-84bf-847df5bbe56c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3273630695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3273630695
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.270651524
Short name T2796
Test name
Test status
Simulation time 53740185 ps
CPU time 0.79 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 205784 kb
Host smart-f65ab04b-cda7-47c5-855f-7e436f73d6ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=270651524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.270651524
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.962523227
Short name T2721
Test name
Test status
Simulation time 100441653 ps
CPU time 1.27 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:29 PM PDT 24
Peak memory 214292 kb
Host smart-2676a96c-3f02-4546-9cd6-ae94c87ed930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962523227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.962523227
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4158646873
Short name T291
Test name
Test status
Simulation time 52681577 ps
CPU time 0.97 seconds
Started Jul 04 06:59:29 PM PDT 24
Finished Jul 04 06:59:30 PM PDT 24
Peak memory 206040 kb
Host smart-3ab605bc-2eaa-456a-ba21-573c725eebe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4158646873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.4158646873
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1870721494
Short name T2798
Test name
Test status
Simulation time 40016540 ps
CPU time 0.7 seconds
Started Jul 04 06:59:20 PM PDT 24
Finished Jul 04 06:59:21 PM PDT 24
Peak memory 205804 kb
Host smart-01945fed-6e76-47e9-b376-9b0eff0cc490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1870721494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1870721494
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1132393494
Short name T2739
Test name
Test status
Simulation time 185885025 ps
CPU time 2.35 seconds
Started Jul 04 06:59:26 PM PDT 24
Finished Jul 04 06:59:29 PM PDT 24
Peak memory 214212 kb
Host smart-6220e371-82ea-4903-a555-d20972fed517
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1132393494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1132393494
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3729761062
Short name T2706
Test name
Test status
Simulation time 754102558 ps
CPU time 5.13 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:32 PM PDT 24
Peak memory 205996 kb
Host smart-ff1459c8-39f0-448e-be64-d25967ddb6c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3729761062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3729761062
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2597460637
Short name T2775
Test name
Test status
Simulation time 253514620 ps
CPU time 1.67 seconds
Started Jul 04 06:59:26 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 206012 kb
Host smart-14bc3d13-ccd8-4c66-bf25-44b0d4c5d752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2597460637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2597460637
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3499936416
Short name T248
Test name
Test status
Simulation time 188472267 ps
CPU time 2.11 seconds
Started Jul 04 06:59:23 PM PDT 24
Finished Jul 04 06:59:26 PM PDT 24
Peak memory 206132 kb
Host smart-d5143524-d5b4-401a-8b7f-f7ce88f2bb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3499936416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3499936416
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2556378813
Short name T2780
Test name
Test status
Simulation time 206857278 ps
CPU time 2.14 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:29 PM PDT 24
Peak memory 205976 kb
Host smart-89272885-6175-42c1-a8a6-829f6becdeda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2556378813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2556378813
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.329194482
Short name T2778
Test name
Test status
Simulation time 1196503770 ps
CPU time 8.32 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:36 PM PDT 24
Peak memory 205948 kb
Host smart-6cc48417-0803-47b4-b8ad-023dff26aab3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=329194482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.329194482
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2494543992
Short name T2710
Test name
Test status
Simulation time 55799967 ps
CPU time 0.81 seconds
Started Jul 04 06:59:29 PM PDT 24
Finished Jul 04 06:59:30 PM PDT 24
Peak memory 205800 kb
Host smart-589b7535-127d-44ae-88ce-27e7c4a1627b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2494543992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2494543992
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.882022317
Short name T264
Test name
Test status
Simulation time 113812436 ps
CPU time 1.21 seconds
Started Jul 04 06:59:29 PM PDT 24
Finished Jul 04 06:59:31 PM PDT 24
Peak memory 214240 kb
Host smart-178db691-4394-4b7e-ab42-6bde1c74412b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882022317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.882022317
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3151524213
Short name T2801
Test name
Test status
Simulation time 44391218 ps
CPU time 0.69 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 205796 kb
Host smart-31670167-5cfc-418e-8b1a-733a26af5d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151524213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3151524213
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3396981861
Short name T282
Test name
Test status
Simulation time 112688149 ps
CPU time 1.49 seconds
Started Jul 04 06:59:26 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 214368 kb
Host smart-5453ce01-3614-4f90-aadd-e0d529f9600e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3396981861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3396981861
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3796765805
Short name T2715
Test name
Test status
Simulation time 108310070 ps
CPU time 2.41 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:30 PM PDT 24
Peak memory 205924 kb
Host smart-1868c377-8c7e-428a-9637-f20b78b45b3f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3796765805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3796765805
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.632771017
Short name T293
Test name
Test status
Simulation time 90671916 ps
CPU time 1.67 seconds
Started Jul 04 06:59:26 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 206036 kb
Host smart-62fc3811-6b6c-4324-9727-577ad1a09e49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=632771017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.632771017
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1697011015
Short name T250
Test name
Test status
Simulation time 111233744 ps
CPU time 2.6 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:31 PM PDT 24
Peak memory 214320 kb
Host smart-8cf2211e-f207-4b8b-9573-a3ef288afc1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1697011015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1697011015
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4082381856
Short name T316
Test name
Test status
Simulation time 1119946976 ps
CPU time 5.19 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:32 PM PDT 24
Peak memory 206056 kb
Host smart-39a8af4b-ca9a-465b-b892-099a5d8628a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4082381856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4082381856
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3728266616
Short name T2793
Test name
Test status
Simulation time 106990759 ps
CPU time 1.31 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:51 PM PDT 24
Peak memory 214228 kb
Host smart-95c57b81-ec36-49ff-a317-371f5d2fb458
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728266616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3728266616
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.4012309304
Short name T2797
Test name
Test status
Simulation time 88137703 ps
CPU time 0.98 seconds
Started Jul 04 06:59:51 PM PDT 24
Finished Jul 04 06:59:52 PM PDT 24
Peak memory 205968 kb
Host smart-27e58e03-4a79-443a-ad67-9a306fb9c9b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4012309304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.4012309304
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3961404261
Short name T303
Test name
Test status
Simulation time 67065994 ps
CPU time 0.73 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:50 PM PDT 24
Peak memory 205820 kb
Host smart-05d9077f-481e-4d38-924e-477c6244a8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3961404261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3961404261
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.276821502
Short name T257
Test name
Test status
Simulation time 192784605 ps
CPU time 2.33 seconds
Started Jul 04 06:59:52 PM PDT 24
Finished Jul 04 06:59:54 PM PDT 24
Peak memory 214344 kb
Host smart-153c1bec-3f5a-4153-9df7-60d255f56a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276821502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.276821502
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2985331495
Short name T318
Test name
Test status
Simulation time 435342483 ps
CPU time 2.69 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:51 PM PDT 24
Peak memory 206024 kb
Host smart-ec3f0fd8-388b-4961-b0b5-3dfec959b1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2985331495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2985331495
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1000440374
Short name T2809
Test name
Test status
Simulation time 118905124 ps
CPU time 2.19 seconds
Started Jul 04 06:59:51 PM PDT 24
Finished Jul 04 06:59:54 PM PDT 24
Peak memory 214228 kb
Host smart-b199ecac-5981-4a80-b84e-948c3883d7fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000440374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1000440374
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2678748279
Short name T286
Test name
Test status
Simulation time 46353867 ps
CPU time 0.97 seconds
Started Jul 04 06:59:51 PM PDT 24
Finished Jul 04 06:59:52 PM PDT 24
Peak memory 205992 kb
Host smart-d0b877c3-6c4a-4109-be84-9528cfb54cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2678748279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2678748279
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1314139024
Short name T2786
Test name
Test status
Simulation time 41078834 ps
CPU time 0.71 seconds
Started Jul 04 06:59:50 PM PDT 24
Finished Jul 04 06:59:50 PM PDT 24
Peak memory 205844 kb
Host smart-91f636c0-aca5-4209-ad7d-a7e603263430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1314139024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1314139024
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1997622519
Short name T290
Test name
Test status
Simulation time 97598297 ps
CPU time 1.6 seconds
Started Jul 04 06:59:51 PM PDT 24
Finished Jul 04 06:59:53 PM PDT 24
Peak memory 205992 kb
Host smart-bfbe2c1a-8d5b-4c5a-a76b-c2e408b53feb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997622519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1997622519
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2545049557
Short name T2763
Test name
Test status
Simulation time 261887285 ps
CPU time 2.92 seconds
Started Jul 04 06:59:50 PM PDT 24
Finished Jul 04 06:59:53 PM PDT 24
Peak memory 222168 kb
Host smart-23f4994f-163b-4e2e-b3b4-1a6e6c5dbfeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2545049557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2545049557
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4230178102
Short name T2753
Test name
Test status
Simulation time 502851316 ps
CPU time 2.77 seconds
Started Jul 04 06:59:48 PM PDT 24
Finished Jul 04 06:59:51 PM PDT 24
Peak memory 205940 kb
Host smart-1e9dc6dc-f987-447b-a4c9-d5d241837266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4230178102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4230178102
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1588309854
Short name T2784
Test name
Test status
Simulation time 189131818 ps
CPU time 2.11 seconds
Started Jul 04 06:59:46 PM PDT 24
Finished Jul 04 06:59:48 PM PDT 24
Peak memory 214252 kb
Host smart-65873d41-3841-41d6-8a98-464aa136c064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588309854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1588309854
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1995118763
Short name T2727
Test name
Test status
Simulation time 68500840 ps
CPU time 1 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:51 PM PDT 24
Peak memory 205912 kb
Host smart-cd81076e-e1b3-4b63-a451-a0ed4f586d91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1995118763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1995118763
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.948467267
Short name T2772
Test name
Test status
Simulation time 57898524 ps
CPU time 0.72 seconds
Started Jul 04 06:59:52 PM PDT 24
Finished Jul 04 06:59:53 PM PDT 24
Peak memory 205788 kb
Host smart-ca62bd48-4bcc-453b-bf5c-37aafa1dfeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=948467267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.948467267
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3088130699
Short name T2711
Test name
Test status
Simulation time 175274283 ps
CPU time 1.12 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:51 PM PDT 24
Peak memory 206020 kb
Host smart-6d822d1f-e34b-4ea9-998c-aa9445f8cdd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3088130699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3088130699
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1099320480
Short name T2802
Test name
Test status
Simulation time 52057421 ps
CPU time 1.3 seconds
Started Jul 04 06:59:52 PM PDT 24
Finished Jul 04 06:59:53 PM PDT 24
Peak memory 206076 kb
Host smart-392c3704-f7f5-4176-b3f2-e28c28b1ef73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1099320480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1099320480
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1005614100
Short name T2779
Test name
Test status
Simulation time 92123917 ps
CPU time 1.89 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 214248 kb
Host smart-79cb1d69-e2d4-49fd-a786-4f0b55d56981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005614100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1005614100
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3951603836
Short name T283
Test name
Test status
Simulation time 73987054 ps
CPU time 1.05 seconds
Started Jul 04 06:59:58 PM PDT 24
Finished Jul 04 06:59:59 PM PDT 24
Peak memory 206028 kb
Host smart-f6aa6be8-0cee-4cf5-a43c-3840644e1ae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3951603836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3951603836
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2426761329
Short name T2783
Test name
Test status
Simulation time 45656214 ps
CPU time 0.67 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:55 PM PDT 24
Peak memory 205812 kb
Host smart-e318ae3c-6e24-4c4f-87bc-69d9c2577010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2426761329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2426761329
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.737899380
Short name T292
Test name
Test status
Simulation time 106592483 ps
CPU time 1.19 seconds
Started Jul 04 07:00:01 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 205940 kb
Host smart-46fd1a95-af55-4f98-aa94-9d00b0fc0998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=737899380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.737899380
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3189951451
Short name T317
Test name
Test status
Simulation time 267770865 ps
CPU time 2.53 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:52 PM PDT 24
Peak memory 205972 kb
Host smart-14ddb3eb-24d9-4a1d-b842-63ffde268e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3189951451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3189951451
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3319832410
Short name T2750
Test name
Test status
Simulation time 189900721 ps
CPU time 1.76 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 214272 kb
Host smart-d73b2fc5-d96c-4562-8021-a85859def0d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319832410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3319832410
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3383369232
Short name T2726
Test name
Test status
Simulation time 120943534 ps
CPU time 0.96 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 206020 kb
Host smart-88fa2214-23cb-4783-8f3d-5aaa9d4d875d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3383369232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3383369232
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3938512327
Short name T2743
Test name
Test status
Simulation time 70578050 ps
CPU time 0.75 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 205824 kb
Host smart-d0eaa331-ce89-44c2-b2a0-98951f31cb56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3938512327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3938512327
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.411677817
Short name T2742
Test name
Test status
Simulation time 366106478 ps
CPU time 1.66 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205956 kb
Host smart-82c9f7dc-a1ed-4673-b09c-517fd00507ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=411677817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.411677817
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3895182536
Short name T2774
Test name
Test status
Simulation time 314757845 ps
CPU time 3.38 seconds
Started Jul 04 06:59:58 PM PDT 24
Finished Jul 04 07:00:01 PM PDT 24
Peak memory 214264 kb
Host smart-2925e16d-e95c-4be3-80c3-1d8fc13806db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3895182536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3895182536
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2361286240
Short name T2722
Test name
Test status
Simulation time 1094028703 ps
CPU time 5.55 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 07:00:01 PM PDT 24
Peak memory 206052 kb
Host smart-8a538e39-5da6-4b50-9749-edaa1921506c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2361286240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2361286240
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.350757452
Short name T2733
Test name
Test status
Simulation time 112658057 ps
CPU time 2.88 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 214304 kb
Host smart-1ede1285-cf71-47d9-bce6-3daeff81fa16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350757452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.350757452
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.163046213
Short name T280
Test name
Test status
Simulation time 66302182 ps
CPU time 1.04 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 205960 kb
Host smart-caa94e20-b3ca-43b3-9afc-85c78da24388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=163046213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.163046213
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2976191493
Short name T2808
Test name
Test status
Simulation time 85835729 ps
CPU time 0.72 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 205808 kb
Host smart-8c9537c3-1349-45fb-a02a-ecdc92657515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2976191493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2976191493
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1867174191
Short name T2762
Test name
Test status
Simulation time 110175422 ps
CPU time 1.55 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205896 kb
Host smart-b670af9c-2d0c-48dd-92c9-fc707d7d66a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1867174191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1867174191
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4275457913
Short name T2716
Test name
Test status
Simulation time 185574623 ps
CPU time 1.93 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 222252 kb
Host smart-21a5682f-6a43-4970-b74a-f644f2b7af8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4275457913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4275457913
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2992765155
Short name T254
Test name
Test status
Simulation time 190538409 ps
CPU time 1.87 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 217764 kb
Host smart-8e8e7e5a-c174-44c6-b1d4-0cf2850a0cd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992765155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2992765155
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2217734982
Short name T2713
Test name
Test status
Simulation time 46149192 ps
CPU time 0.86 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205852 kb
Host smart-aa52b4cf-765c-4e01-aaa1-c773d803d939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2217734982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2217734982
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3536507758
Short name T228
Test name
Test status
Simulation time 68412933 ps
CPU time 0.72 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:55 PM PDT 24
Peak memory 205800 kb
Host smart-9d7fbdc6-ae09-4df9-aa49-5528454bf0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3536507758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3536507758
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.123127197
Short name T2748
Test name
Test status
Simulation time 374010519 ps
CPU time 1.83 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 206004 kb
Host smart-ffbb5c67-31f7-4317-a07c-6fef0bf59b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=123127197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.123127197
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3398705062
Short name T2760
Test name
Test status
Simulation time 1546732903 ps
CPU time 5.04 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 07:00:02 PM PDT 24
Peak memory 206040 kb
Host smart-d212493c-e1ec-4e76-adcc-3166e97ca371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3398705062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3398705062
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2039270872
Short name T2725
Test name
Test status
Simulation time 94645538 ps
CPU time 1.31 seconds
Started Jul 04 07:00:01 PM PDT 24
Finished Jul 04 07:00:02 PM PDT 24
Peak memory 214200 kb
Host smart-56156356-3853-49e0-91cf-79bbe63eb65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039270872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2039270872
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.547381546
Short name T284
Test name
Test status
Simulation time 76766901 ps
CPU time 0.99 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 206032 kb
Host smart-6e11cbfe-7cd7-4a7e-be69-ba1c08856275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=547381546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.547381546
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1807612924
Short name T2728
Test name
Test status
Simulation time 33654462 ps
CPU time 0.68 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205796 kb
Host smart-7c0a08c1-ed35-45dc-9943-44a478f8d279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1807612924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1807612924
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1371947732
Short name T2723
Test name
Test status
Simulation time 527317059 ps
CPU time 2.04 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 205956 kb
Host smart-1c78ab52-8c2a-4aa8-bf86-1ee52c0abaa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1371947732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1371947732
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3175575015
Short name T2777
Test name
Test status
Simulation time 174206612 ps
CPU time 2.34 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:59 PM PDT 24
Peak memory 214300 kb
Host smart-d45b603f-22bc-45ca-ae64-382758033c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3175575015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3175575015
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1097259678
Short name T2790
Test name
Test status
Simulation time 755346503 ps
CPU time 4.88 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 07:00:02 PM PDT 24
Peak memory 206036 kb
Host smart-f940b7e5-8276-4a9e-844b-da7f8f5cce63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1097259678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1097259678
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3875754155
Short name T240
Test name
Test status
Simulation time 136836831 ps
CPU time 1.44 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 214244 kb
Host smart-faf6567a-b89b-4442-b1b0-23d618d8cc03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875754155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3875754155
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.900340470
Short name T2738
Test name
Test status
Simulation time 43206089 ps
CPU time 0.8 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:55 PM PDT 24
Peak memory 205784 kb
Host smart-4f69750b-056a-4464-a01f-bf88346a549c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=900340470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.900340470
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3581886286
Short name T2720
Test name
Test status
Simulation time 53883498 ps
CPU time 0.72 seconds
Started Jul 04 06:59:58 PM PDT 24
Finished Jul 04 06:59:59 PM PDT 24
Peak memory 205772 kb
Host smart-d689f923-a7f1-460b-9b0e-8c71371a951b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3581886286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3581886286
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2228438225
Short name T2737
Test name
Test status
Simulation time 182564167 ps
CPU time 1.64 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205996 kb
Host smart-f1107549-22ef-46f2-9fb8-5b81c9278831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2228438225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2228438225
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2878161215
Short name T255
Test name
Test status
Simulation time 117057173 ps
CPU time 3.34 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 222084 kb
Host smart-aa5007f3-b67f-4932-aa64-6a934204e12e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2878161215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2878161215
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4092279124
Short name T258
Test name
Test status
Simulation time 236676884 ps
CPU time 1.8 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 214284 kb
Host smart-3cc9d3c3-a4f2-426e-953f-b1ab7c8937bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092279124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4092279124
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2821296094
Short name T287
Test name
Test status
Simulation time 144313089 ps
CPU time 1.05 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 206036 kb
Host smart-1669ce9d-03c9-4baa-931a-1c39f6adadf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2821296094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2821296094
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3587847083
Short name T2758
Test name
Test status
Simulation time 51467974 ps
CPU time 0.7 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 205708 kb
Host smart-46255986-24dd-4bf6-a575-0579fa6290bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3587847083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3587847083
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1009753473
Short name T289
Test name
Test status
Simulation time 175722905 ps
CPU time 1.3 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 205964 kb
Host smart-f06b9a87-8b92-4c1e-91f7-f3c133f3cc86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1009753473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1009753473
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2237940490
Short name T2717
Test name
Test status
Simulation time 106040037 ps
CPU time 2.93 seconds
Started Jul 04 07:00:00 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 222256 kb
Host smart-c0e15a76-7ff6-4cb1-94f7-7efd3c08a274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2237940490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2237940490
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2578183318
Short name T2781
Test name
Test status
Simulation time 469557265 ps
CPU time 2.76 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 205932 kb
Host smart-5fc8177a-57e9-4784-bb0b-28dafc42decc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2578183318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2578183318
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.578004323
Short name T2746
Test name
Test status
Simulation time 169218921 ps
CPU time 2.14 seconds
Started Jul 04 06:59:36 PM PDT 24
Finished Jul 04 06:59:38 PM PDT 24
Peak memory 205936 kb
Host smart-32535ad7-c1d3-416e-85ff-ac07acf45dc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=578004323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.578004323
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2834160574
Short name T242
Test name
Test status
Simulation time 808159631 ps
CPU time 8.98 seconds
Started Jul 04 06:59:37 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 205968 kb
Host smart-395937c5-cf24-4757-a47a-ea0f6f89e8ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2834160574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2834160574
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3557403675
Short name T2807
Test name
Test status
Simulation time 68939811 ps
CPU time 0.81 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:29 PM PDT 24
Peak memory 205812 kb
Host smart-fc2e4cb1-7edb-40d7-ac5d-334b4f611a67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3557403675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3557403675
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4258136986
Short name T2744
Test name
Test status
Simulation time 104492761 ps
CPU time 1.25 seconds
Started Jul 04 06:59:37 PM PDT 24
Finished Jul 04 06:59:39 PM PDT 24
Peak memory 214212 kb
Host smart-95558229-3b06-40c9-becd-380da486ce42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258136986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.4258136986
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1985189462
Short name T2708
Test name
Test status
Simulation time 70529961 ps
CPU time 1 seconds
Started Jul 04 06:59:39 PM PDT 24
Finished Jul 04 06:59:40 PM PDT 24
Peak memory 205968 kb
Host smart-b168dd71-98be-4eb3-9d5e-e7bfab1ba37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1985189462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1985189462
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2843956585
Short name T309
Test name
Test status
Simulation time 83877923 ps
CPU time 0.73 seconds
Started Jul 04 06:59:27 PM PDT 24
Finished Jul 04 06:59:28 PM PDT 24
Peak memory 205800 kb
Host smart-70a7dc2c-da35-47c4-9136-ecc9ae499ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2843956585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2843956585
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3685471492
Short name T2767
Test name
Test status
Simulation time 66925075 ps
CPU time 2.2 seconds
Started Jul 04 06:59:28 PM PDT 24
Finished Jul 04 06:59:30 PM PDT 24
Peak memory 214176 kb
Host smart-7db119f7-99bd-4010-8f45-e71d36f248ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3685471492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3685471492
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1611835238
Short name T2789
Test name
Test status
Simulation time 180345200 ps
CPU time 4.09 seconds
Started Jul 04 06:59:29 PM PDT 24
Finished Jul 04 06:59:34 PM PDT 24
Peak memory 205936 kb
Host smart-f05d33df-7dfc-49e3-91a9-470e2451095e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1611835238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1611835238
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2021767692
Short name T2747
Test name
Test status
Simulation time 95893609 ps
CPU time 1.11 seconds
Started Jul 04 06:59:34 PM PDT 24
Finished Jul 04 06:59:36 PM PDT 24
Peak memory 205900 kb
Host smart-36705486-596b-42c7-b6bb-3c824d5f03ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2021767692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2021767692
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1669788624
Short name T252
Test name
Test status
Simulation time 220743884 ps
CPU time 2.86 seconds
Started Jul 04 06:59:29 PM PDT 24
Finished Jul 04 06:59:32 PM PDT 24
Peak memory 206104 kb
Host smart-bdb2daef-d097-41a7-bd74-cfc8b72185f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1669788624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1669788624
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3717430480
Short name T2768
Test name
Test status
Simulation time 33068003 ps
CPU time 0.66 seconds
Started Jul 04 06:59:56 PM PDT 24
Finished Jul 04 06:59:57 PM PDT 24
Peak memory 205800 kb
Host smart-2f12f449-c3cd-4fbe-bab5-768ba833e857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3717430480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3717430480
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.769152989
Short name T2761
Test name
Test status
Simulation time 65541166 ps
CPU time 0.66 seconds
Started Jul 04 06:59:54 PM PDT 24
Finished Jul 04 06:59:55 PM PDT 24
Peak memory 205832 kb
Host smart-a3c98248-cbfc-4227-b4a2-ab0ce5908ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=769152989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.769152989
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1250545558
Short name T2773
Test name
Test status
Simulation time 38498897 ps
CPU time 0.67 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:55 PM PDT 24
Peak memory 205804 kb
Host smart-c29a4780-4523-4207-a7d5-685c1db84a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1250545558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1250545558
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2562210183
Short name T2755
Test name
Test status
Simulation time 80713662 ps
CPU time 0.74 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 205816 kb
Host smart-ac50e5ff-3b77-4b41-a76b-6715d4ac147e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562210183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2562210183
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.661963575
Short name T2769
Test name
Test status
Simulation time 51895118 ps
CPU time 0.71 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205804 kb
Host smart-be079b81-ed89-4d3e-b571-e79a7d193fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=661963575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.661963575
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2184233779
Short name T226
Test name
Test status
Simulation time 75924864 ps
CPU time 0.71 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:56 PM PDT 24
Peak memory 205808 kb
Host smart-78d63f42-36aa-4f6f-b5ab-c3158ff5e23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2184233779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2184233779
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3169988
Short name T2751
Test name
Test status
Simulation time 49956347 ps
CPU time 0.7 seconds
Started Jul 04 06:59:57 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205804 kb
Host smart-68afaed0-f906-4948-9c51-744010d0d7a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3169988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3169988
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4121657749
Short name T301
Test name
Test status
Simulation time 55777764 ps
CPU time 0.66 seconds
Started Jul 04 06:59:58 PM PDT 24
Finished Jul 04 06:59:58 PM PDT 24
Peak memory 205812 kb
Host smart-739c242f-2c65-414b-bfeb-7084eaa6fc69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4121657749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4121657749
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.189460695
Short name T2792
Test name
Test status
Simulation time 78500044 ps
CPU time 0.69 seconds
Started Jul 04 06:59:55 PM PDT 24
Finished Jul 04 06:59:55 PM PDT 24
Peak memory 205820 kb
Host smart-0174aa5b-800c-4b65-8681-1b63284589fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=189460695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.189460695
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1593962763
Short name T2759
Test name
Test status
Simulation time 71216527 ps
CPU time 0.72 seconds
Started Jul 04 06:59:58 PM PDT 24
Finished Jul 04 06:59:59 PM PDT 24
Peak memory 205804 kb
Host smart-e1851256-4f24-4cba-936a-fd82f87b31b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1593962763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1593962763
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2980556741
Short name T2709
Test name
Test status
Simulation time 200393564 ps
CPU time 2.11 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:38 PM PDT 24
Peak memory 205944 kb
Host smart-f31f922a-00f4-4b34-b60b-18c7bb42bf26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2980556741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2980556741
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.870972480
Short name T2805
Test name
Test status
Simulation time 1132339677 ps
CPU time 5.88 seconds
Started Jul 04 06:59:37 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 205964 kb
Host smart-b056ba70-8a78-44d7-affe-d95cea11be2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=870972480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.870972480
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2478903543
Short name T2745
Test name
Test status
Simulation time 195281403 ps
CPU time 1.03 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:36 PM PDT 24
Peak memory 205808 kb
Host smart-01a97bcd-0b8d-4e4a-8d0f-f3838ce9fcfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2478903543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2478903543
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.367901969
Short name T218
Test name
Test status
Simulation time 81094157 ps
CPU time 1.98 seconds
Started Jul 04 06:59:38 PM PDT 24
Finished Jul 04 06:59:41 PM PDT 24
Peak memory 214280 kb
Host smart-fb14654c-5cf0-4559-9d87-62ab4ba5fa79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367901969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.367901969
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1572982535
Short name T260
Test name
Test status
Simulation time 64002679 ps
CPU time 0.95 seconds
Started Jul 04 06:59:34 PM PDT 24
Finished Jul 04 06:59:36 PM PDT 24
Peak memory 205972 kb
Host smart-0675d8c6-a9f0-4477-b547-e37be9641718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1572982535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1572982535
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1779103758
Short name T2736
Test name
Test status
Simulation time 70246596 ps
CPU time 0.73 seconds
Started Jul 04 06:59:36 PM PDT 24
Finished Jul 04 06:59:37 PM PDT 24
Peak memory 205792 kb
Host smart-4accbeea-ecff-4308-87c9-750546d1b09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1779103758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1779103758
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2596993912
Short name T277
Test name
Test status
Simulation time 173700723 ps
CPU time 2.35 seconds
Started Jul 04 06:59:36 PM PDT 24
Finished Jul 04 06:59:39 PM PDT 24
Peak memory 214224 kb
Host smart-afa884d8-0d01-4bc4-9611-3002ed053434
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2596993912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2596993912
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.993571035
Short name T2705
Test name
Test status
Simulation time 287783406 ps
CPU time 2.57 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:37 PM PDT 24
Peak memory 206000 kb
Host smart-58bd4d62-b5e8-4e5b-b7ad-ddf13e72748a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=993571035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.993571035
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3847913029
Short name T288
Test name
Test status
Simulation time 151218633 ps
CPU time 1.22 seconds
Started Jul 04 06:59:36 PM PDT 24
Finished Jul 04 06:59:37 PM PDT 24
Peak memory 206020 kb
Host smart-c2c3b972-4923-4c89-a92e-bb22dc29adee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847913029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3847913029
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.314447304
Short name T2718
Test name
Test status
Simulation time 324580215 ps
CPU time 3.42 seconds
Started Jul 04 06:59:34 PM PDT 24
Finished Jul 04 06:59:38 PM PDT 24
Peak memory 222172 kb
Host smart-00cd5170-9c62-40a4-a6a3-8fb560c325d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=314447304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.314447304
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2475755390
Short name T2785
Test name
Test status
Simulation time 349941798 ps
CPU time 2.81 seconds
Started Jul 04 06:59:34 PM PDT 24
Finished Jul 04 06:59:37 PM PDT 24
Peak memory 206008 kb
Host smart-9c44314e-fb3c-403e-8289-95c2f3cc8353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2475755390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2475755390
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.65703976
Short name T2765
Test name
Test status
Simulation time 46728320 ps
CPU time 0.72 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 205820 kb
Host smart-7d2a7274-ae34-4594-9761-76a9afa0283e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65703976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.65703976
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1548280519
Short name T2729
Test name
Test status
Simulation time 29488255 ps
CPU time 0.7 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 205812 kb
Host smart-91e34160-0c5a-4213-a37a-df4c396804f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1548280519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1548280519
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2286907741
Short name T2754
Test name
Test status
Simulation time 43843565 ps
CPU time 0.72 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 205828 kb
Host smart-ee39501d-24e3-4efa-a677-282081130c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2286907741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2286907741
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2585890553
Short name T2787
Test name
Test status
Simulation time 36537515 ps
CPU time 0.67 seconds
Started Jul 04 07:00:01 PM PDT 24
Finished Jul 04 07:00:02 PM PDT 24
Peak memory 205832 kb
Host smart-5087df8a-376a-4ab3-a5af-81fda1ca6965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2585890553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2585890553
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2051725755
Short name T307
Test name
Test status
Simulation time 36871069 ps
CPU time 0.71 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:00:03 PM PDT 24
Peak memory 205800 kb
Host smart-4cb48ea1-d88e-4d66-8df4-2199738f7042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2051725755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2051725755
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2495502807
Short name T299
Test name
Test status
Simulation time 36100340 ps
CPU time 0.66 seconds
Started Jul 04 07:00:00 PM PDT 24
Finished Jul 04 07:00:01 PM PDT 24
Peak memory 205792 kb
Host smart-278532d3-2e55-492b-b119-2eb5aeb2f26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2495502807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2495502807
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2529931553
Short name T2788
Test name
Test status
Simulation time 85082673 ps
CPU time 0.74 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 205796 kb
Host smart-8806946f-dd7a-4786-b487-f4281af549dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529931553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2529931553
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1123141990
Short name T2731
Test name
Test status
Simulation time 106519377 ps
CPU time 0.76 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205796 kb
Host smart-8e878553-6e27-4f19-9c21-581186e5a585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1123141990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1123141990
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1622326905
Short name T297
Test name
Test status
Simulation time 227433876 ps
CPU time 2.22 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:52 PM PDT 24
Peak memory 205956 kb
Host smart-864df375-6c49-4cf2-a6a1-e113dcb9d2c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1622326905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1622326905
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1794751012
Short name T2791
Test name
Test status
Simulation time 1267829826 ps
CPU time 8.07 seconds
Started Jul 04 06:59:34 PM PDT 24
Finished Jul 04 06:59:42 PM PDT 24
Peak memory 206044 kb
Host smart-df0698c7-ea64-4260-b9ff-ec43527925a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1794751012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1794751012
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.51643850
Short name T2756
Test name
Test status
Simulation time 272751816 ps
CPU time 1.1 seconds
Started Jul 04 06:59:37 PM PDT 24
Finished Jul 04 06:59:38 PM PDT 24
Peak memory 205852 kb
Host smart-41d3c5d9-af21-4392-b15b-7acad368768b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=51643850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.51643850
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.601168787
Short name T261
Test name
Test status
Simulation time 126178054 ps
CPU time 1.23 seconds
Started Jul 04 06:59:41 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 214200 kb
Host smart-66aacc4c-d22f-4412-b990-1c55590fb29f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601168787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.601168787
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3459166475
Short name T2712
Test name
Test status
Simulation time 45111504 ps
CPU time 0.98 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:37 PM PDT 24
Peak memory 205956 kb
Host smart-520b3a6a-e8d3-4d71-9930-47cd679f6282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3459166475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3459166475
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1079442431
Short name T2800
Test name
Test status
Simulation time 40223814 ps
CPU time 0.67 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:36 PM PDT 24
Peak memory 205788 kb
Host smart-98dd78a0-01bc-4022-a666-82519fc683e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1079442431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1079442431
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.894589627
Short name T2749
Test name
Test status
Simulation time 80672940 ps
CPU time 2.24 seconds
Started Jul 04 06:59:36 PM PDT 24
Finished Jul 04 06:59:39 PM PDT 24
Peak memory 222380 kb
Host smart-95c92210-6767-4e28-8c48-77472ba94199
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=894589627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.894589627
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3993420022
Short name T2741
Test name
Test status
Simulation time 708224801 ps
CPU time 4.95 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:41 PM PDT 24
Peak memory 205956 kb
Host smart-f7549068-18a3-4802-977e-cbfb0c2ec120
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3993420022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3993420022
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3500511790
Short name T2724
Test name
Test status
Simulation time 175194770 ps
CPU time 1.83 seconds
Started Jul 04 06:59:52 PM PDT 24
Finished Jul 04 06:59:54 PM PDT 24
Peak memory 205928 kb
Host smart-dd9ca43b-f753-4b8f-9812-5dfc04f690d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3500511790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3500511790
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.844656808
Short name T256
Test name
Test status
Simulation time 106569027 ps
CPU time 2.75 seconds
Started Jul 04 06:59:35 PM PDT 24
Finished Jul 04 06:59:39 PM PDT 24
Peak memory 214312 kb
Host smart-9d0cf86a-287e-4349-a481-6c93c3b0d139
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844656808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.844656808
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2227582073
Short name T311
Test name
Test status
Simulation time 872124481 ps
CPU time 5 seconds
Started Jul 04 06:59:34 PM PDT 24
Finished Jul 04 06:59:39 PM PDT 24
Peak memory 205996 kb
Host smart-5cedf6ed-2067-4580-bab5-95b8234b444e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2227582073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2227582073
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3538255460
Short name T300
Test name
Test status
Simulation time 53350706 ps
CPU time 0.7 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:04 PM PDT 24
Peak memory 205824 kb
Host smart-60af5d83-c147-4d54-8b1a-199feb13bbbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3538255460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3538255460
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1001534946
Short name T2803
Test name
Test status
Simulation time 43173712 ps
CPU time 0.7 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205788 kb
Host smart-3d1c507a-39d7-49f8-aa6a-29d6f4c11446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1001534946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1001534946
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1513909985
Short name T2776
Test name
Test status
Simulation time 46410284 ps
CPU time 0.71 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205800 kb
Host smart-1149c29b-f997-42f8-813d-72e8167a1bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1513909985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1513909985
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3745146604
Short name T308
Test name
Test status
Simulation time 50428801 ps
CPU time 0.66 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205824 kb
Host smart-0d68c8cb-1093-471d-8344-b2a0f802c0f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3745146604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3745146604
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1584853916
Short name T298
Test name
Test status
Simulation time 39747354 ps
CPU time 0.69 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205824 kb
Host smart-f42f99b2-8c90-409b-8f42-16232e98b8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1584853916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1584853916
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.415339670
Short name T2766
Test name
Test status
Simulation time 47201421 ps
CPU time 0.64 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:07 PM PDT 24
Peak memory 205844 kb
Host smart-878db265-bd14-48df-bf01-e1c4aaa960ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=415339670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.415339670
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3732880521
Short name T2770
Test name
Test status
Simulation time 36471895 ps
CPU time 0.65 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:00:09 PM PDT 24
Peak memory 205820 kb
Host smart-5fae9640-f652-4517-9bab-b84024f31fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3732880521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3732880521
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2457683419
Short name T227
Test name
Test status
Simulation time 78538186 ps
CPU time 0.72 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:05 PM PDT 24
Peak memory 205812 kb
Host smart-ffa9804f-0ace-419f-9e7c-f9393b9f3dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2457683419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2457683419
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1546151437
Short name T2806
Test name
Test status
Simulation time 96221507 ps
CPU time 2.56 seconds
Started Jul 04 06:59:41 PM PDT 24
Finished Jul 04 06:59:44 PM PDT 24
Peak memory 214232 kb
Host smart-34a4ac08-d31b-4997-a3e2-c9cd85bb4861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546151437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1546151437
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3680987745
Short name T2804
Test name
Test status
Simulation time 60558951 ps
CPU time 0.83 seconds
Started Jul 04 06:59:45 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 205840 kb
Host smart-60402df9-bbe5-4956-9984-a43263596fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3680987745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3680987745
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2434706458
Short name T304
Test name
Test status
Simulation time 60606523 ps
CPU time 0.69 seconds
Started Jul 04 06:59:40 PM PDT 24
Finished Jul 04 06:59:41 PM PDT 24
Peak memory 205816 kb
Host smart-c835c8df-649b-4696-aad2-058eb6dc402d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2434706458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2434706458
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.60319328
Short name T2764
Test name
Test status
Simulation time 59827935 ps
CPU time 1.04 seconds
Started Jul 04 06:59:41 PM PDT 24
Finished Jul 04 06:59:42 PM PDT 24
Peak memory 205972 kb
Host smart-4ee41df2-5088-4f35-935c-17c8577be4f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=60319328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.60319328
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3754806906
Short name T251
Test name
Test status
Simulation time 105314384 ps
CPU time 2.58 seconds
Started Jul 04 06:59:43 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 221732 kb
Host smart-682dbe7e-0e99-47e5-803b-c1a695635965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3754806906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3754806906
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2361671392
Short name T312
Test name
Test status
Simulation time 277659945 ps
CPU time 2.39 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 205940 kb
Host smart-c6938895-89a4-4517-8218-fa2ce1eded16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2361671392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2361671392
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2505304700
Short name T2704
Test name
Test status
Simulation time 123031222 ps
CPU time 1.29 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:45 PM PDT 24
Peak memory 215544 kb
Host smart-070e508a-c9ad-44d1-a412-420722b9afe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505304700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2505304700
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2956133995
Short name T2740
Test name
Test status
Simulation time 43661191 ps
CPU time 0.8 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:45 PM PDT 24
Peak memory 205824 kb
Host smart-0a79ccd0-4515-4c21-a4c9-607e3b8ad868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2956133995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2956133995
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2841411895
Short name T2799
Test name
Test status
Simulation time 42089996 ps
CPU time 0.74 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 205848 kb
Host smart-d85ecaf7-21a6-4340-8c1d-5ea933b9e37d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2841411895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2841411895
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4098062151
Short name T2734
Test name
Test status
Simulation time 135128844 ps
CPU time 1.44 seconds
Started Jul 04 06:59:45 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 205948 kb
Host smart-6acaa304-6442-457e-b2ce-70730dd28187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4098062151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4098062151
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1239248122
Short name T253
Test name
Test status
Simulation time 147881290 ps
CPU time 1.74 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:44 PM PDT 24
Peak memory 214268 kb
Host smart-d037104f-ccbf-4fec-ac3e-3a2dc87db007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1239248122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1239248122
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.687043618
Short name T221
Test name
Test status
Simulation time 348929050 ps
CPU time 2.69 seconds
Started Jul 04 06:59:45 PM PDT 24
Finished Jul 04 06:59:48 PM PDT 24
Peak memory 205968 kb
Host smart-7e644852-1298-49f7-93c1-be56cde2dbee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=687043618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.687043618
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3307948561
Short name T217
Test name
Test status
Simulation time 49186062 ps
CPU time 1.2 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:44 PM PDT 24
Peak memory 214276 kb
Host smart-5436304a-eb60-4b27-9368-83ef1ede4529
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307948561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3307948561
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2467836784
Short name T281
Test name
Test status
Simulation time 57770487 ps
CPU time 0.82 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 205800 kb
Host smart-80ea16f3-395f-4a79-8c7c-8bf137b7cf03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2467836784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2467836784
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4112566071
Short name T295
Test name
Test status
Simulation time 186396693 ps
CPU time 1.27 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 205984 kb
Host smart-d2eb395f-a2c7-495f-a968-979aeb0fe5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4112566071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.4112566071
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3796450885
Short name T2757
Test name
Test status
Simulation time 61370909 ps
CPU time 1.53 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:44 PM PDT 24
Peak memory 206012 kb
Host smart-e822ae67-7059-4d8b-95fa-7e99421db7a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3796450885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3796450885
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2451284506
Short name T2732
Test name
Test status
Simulation time 89988700 ps
CPU time 1.24 seconds
Started Jul 04 06:59:45 PM PDT 24
Finished Jul 04 06:59:46 PM PDT 24
Peak memory 214204 kb
Host smart-538103e7-6301-4f0f-bfbd-ae56707e455d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451284506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2451284506
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3973946224
Short name T285
Test name
Test status
Simulation time 103134613 ps
CPU time 1.09 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 205960 kb
Host smart-008e99ab-40c6-4cad-bf91-d501cd9650ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3973946224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3973946224
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3222893845
Short name T2707
Test name
Test status
Simulation time 46846218 ps
CPU time 0.7 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:45 PM PDT 24
Peak memory 205796 kb
Host smart-05f54bff-85a8-41cb-b902-ab3c970de7be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3222893845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3222893845
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3527747589
Short name T2795
Test name
Test status
Simulation time 258632681 ps
CPU time 1.29 seconds
Started Jul 04 06:59:41 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 205940 kb
Host smart-3d9472f8-a403-4642-a425-7abb0743d914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3527747589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3527747589
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.816064677
Short name T2771
Test name
Test status
Simulation time 110580193 ps
CPU time 1.47 seconds
Started Jul 04 06:59:45 PM PDT 24
Finished Jul 04 06:59:47 PM PDT 24
Peak memory 214192 kb
Host smart-bc101c5b-102b-4de7-ad3b-f0143c6b80ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=816064677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.816064677
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1409579466
Short name T314
Test name
Test status
Simulation time 1756574296 ps
CPU time 5.87 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:48 PM PDT 24
Peak memory 206000 kb
Host smart-e91afee2-86a2-40f8-a382-02c70e33a9be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1409579466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1409579466
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4058626972
Short name T249
Test name
Test status
Simulation time 120808645 ps
CPU time 1.53 seconds
Started Jul 04 06:59:41 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 214244 kb
Host smart-d1b87f3a-c57d-49cb-9e5c-d1a2032a7630
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058626972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.4058626972
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2643823836
Short name T2782
Test name
Test status
Simulation time 40458132 ps
CPU time 0.88 seconds
Started Jul 04 06:59:41 PM PDT 24
Finished Jul 04 06:59:42 PM PDT 24
Peak memory 205860 kb
Host smart-ca95abf6-ce43-44c7-ab90-703098c81876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2643823836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2643823836
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4184210274
Short name T2730
Test name
Test status
Simulation time 73619776 ps
CPU time 0.69 seconds
Started Jul 04 06:59:42 PM PDT 24
Finished Jul 04 06:59:43 PM PDT 24
Peak memory 205796 kb
Host smart-648a6217-1ccb-41f6-8a52-c9ed7b33da28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4184210274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4184210274
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3189818753
Short name T294
Test name
Test status
Simulation time 114316237 ps
CPU time 1.19 seconds
Started Jul 04 06:59:43 PM PDT 24
Finished Jul 04 06:59:45 PM PDT 24
Peak memory 205924 kb
Host smart-2fadb25b-9e23-4d3b-a75c-621a6c6e0123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3189818753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3189818753
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1053045948
Short name T2735
Test name
Test status
Simulation time 125927401 ps
CPU time 2.66 seconds
Started Jul 04 06:59:49 PM PDT 24
Finished Jul 04 06:59:52 PM PDT 24
Peak memory 221588 kb
Host smart-67ce1731-ea6d-429b-bd49-8127e9f3f3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1053045948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1053045948
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2361483989
Short name T247
Test name
Test status
Simulation time 717769519 ps
CPU time 3.09 seconds
Started Jul 04 06:59:44 PM PDT 24
Finished Jul 04 06:59:48 PM PDT 24
Peak memory 206028 kb
Host smart-b3795e35-bee8-4bbf-a2f7-08a1882a8c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2361483989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2361483989
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.4053048830
Short name T1832
Test name
Test status
Simulation time 75219486 ps
CPU time 0.69 seconds
Started Jul 04 06:04:50 PM PDT 24
Finished Jul 04 06:04:51 PM PDT 24
Peak memory 206260 kb
Host smart-8e363441-26b1-453e-b439-d645cb088e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4053048830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.4053048830
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2771794588
Short name T1724
Test name
Test status
Simulation time 3626589917 ps
CPU time 4.21 seconds
Started Jul 04 06:03:35 PM PDT 24
Finished Jul 04 06:03:40 PM PDT 24
Peak memory 206288 kb
Host smart-fe5cbbb7-4704-490a-84e8-503174e39ec7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2771794588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2771794588
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3333191256
Short name T2378
Test name
Test status
Simulation time 13403431109 ps
CPU time 12.74 seconds
Started Jul 04 06:03:38 PM PDT 24
Finished Jul 04 06:03:51 PM PDT 24
Peak memory 206436 kb
Host smart-6be8605f-a078-4e65-900f-6e3d99250269
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3333191256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3333191256
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3123892345
Short name T1752
Test name
Test status
Simulation time 23402543656 ps
CPU time 27.47 seconds
Started Jul 04 06:03:38 PM PDT 24
Finished Jul 04 06:04:05 PM PDT 24
Peak memory 206272 kb
Host smart-83b15ef1-1326-4468-ad32-234f68097382
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3123892345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3123892345
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.882344111
Short name T925
Test name
Test status
Simulation time 173873287 ps
CPU time 0.84 seconds
Started Jul 04 06:03:35 PM PDT 24
Finished Jul 04 06:03:36 PM PDT 24
Peak memory 206212 kb
Host smart-ffd3ed24-f4d8-4420-bcea-8bcaf06f34c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88234
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.882344111
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1818351818
Short name T555
Test name
Test status
Simulation time 148740616 ps
CPU time 0.76 seconds
Started Jul 04 06:03:42 PM PDT 24
Finished Jul 04 06:03:43 PM PDT 24
Peak memory 206220 kb
Host smart-6c92821b-2221-4379-beb3-12c50e03cb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
51818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1818351818
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4143267819
Short name T1787
Test name
Test status
Simulation time 358991391 ps
CPU time 1.24 seconds
Started Jul 04 06:03:43 PM PDT 24
Finished Jul 04 06:03:45 PM PDT 24
Peak memory 206176 kb
Host smart-d6e794dd-fd85-4b42-9e41-826063322f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
67819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4143267819
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3270131352
Short name T174
Test name
Test status
Simulation time 1240804217 ps
CPU time 2.89 seconds
Started Jul 04 06:03:43 PM PDT 24
Finished Jul 04 06:03:46 PM PDT 24
Peak memory 206372 kb
Host smart-2d1b21da-06fe-4b3d-b3f5-2e71bd0a0499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32701
31352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3270131352
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1546923628
Short name T2148
Test name
Test status
Simulation time 6086911711 ps
CPU time 11.77 seconds
Started Jul 04 06:03:49 PM PDT 24
Finished Jul 04 06:04:01 PM PDT 24
Peak memory 206424 kb
Host smart-f3819534-3fd4-4773-92a1-9ccda1cd6c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15469
23628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1546923628
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.1966280397
Short name T199
Test name
Test status
Simulation time 359495842 ps
CPU time 1.25 seconds
Started Jul 04 06:03:50 PM PDT 24
Finished Jul 04 06:03:51 PM PDT 24
Peak memory 206192 kb
Host smart-a6a39589-2b3c-45e1-bdcc-c51aa309460b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19662
80397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.1966280397
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2465533076
Short name T795
Test name
Test status
Simulation time 152551516 ps
CPU time 0.82 seconds
Started Jul 04 06:03:51 PM PDT 24
Finished Jul 04 06:03:52 PM PDT 24
Peak memory 206180 kb
Host smart-8432ba75-439c-4c20-906d-3158f82fd992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24655
33076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2465533076
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.717071140
Short name T1509
Test name
Test status
Simulation time 5134237855 ps
CPU time 136.32 seconds
Started Jul 04 06:03:50 PM PDT 24
Finished Jul 04 06:06:07 PM PDT 24
Peak memory 206468 kb
Host smart-ab06ac05-54f5-4462-9189-c971134afe56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71707
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.717071140
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.183714119
Short name T864
Test name
Test status
Simulation time 53993479 ps
CPU time 0.66 seconds
Started Jul 04 06:03:50 PM PDT 24
Finished Jul 04 06:03:51 PM PDT 24
Peak memory 206196 kb
Host smart-feefa920-321c-4b19-b493-31f2273a4aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18371
4119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.183714119
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2343048353
Short name T684
Test name
Test status
Simulation time 995604089 ps
CPU time 2.16 seconds
Started Jul 04 06:03:49 PM PDT 24
Finished Jul 04 06:03:52 PM PDT 24
Peak memory 206380 kb
Host smart-9b9951ab-3d46-47f0-ad40-e1b19e7b6d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
48353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2343048353
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3283886869
Short name T2249
Test name
Test status
Simulation time 228658506 ps
CPU time 1.54 seconds
Started Jul 04 06:03:50 PM PDT 24
Finished Jul 04 06:03:52 PM PDT 24
Peak memory 206344 kb
Host smart-4f8f6bfe-2fc7-4083-b37e-9fc4c947f45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32838
86869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3283886869
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3087007013
Short name T1848
Test name
Test status
Simulation time 94234517369 ps
CPU time 140.61 seconds
Started Jul 04 06:03:50 PM PDT 24
Finished Jul 04 06:06:10 PM PDT 24
Peak memory 206476 kb
Host smart-f4724037-9550-4bb6-8a85-0fb867ca9228
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3087007013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3087007013
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.4159848132
Short name T646
Test name
Test status
Simulation time 98250062094 ps
CPU time 137.37 seconds
Started Jul 04 06:03:49 PM PDT 24
Finished Jul 04 06:06:07 PM PDT 24
Peak memory 206444 kb
Host smart-b62edf57-59dd-4b36-a2d1-22c717d503fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159848132 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.4159848132
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.2097449467
Short name T2435
Test name
Test status
Simulation time 114088253593 ps
CPU time 163.37 seconds
Started Jul 04 06:03:51 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 206484 kb
Host smart-936fa283-dbe8-4924-9865-1aef3050cfb0
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2097449467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.2097449467
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.4241297913
Short name T2262
Test name
Test status
Simulation time 98008794057 ps
CPU time 127.33 seconds
Started Jul 04 06:03:58 PM PDT 24
Finished Jul 04 06:06:05 PM PDT 24
Peak memory 206476 kb
Host smart-f51c89d4-942e-47d5-9e2c-66a2e41632d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241297913 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.4241297913
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.4173299018
Short name T2482
Test name
Test status
Simulation time 110127060355 ps
CPU time 151.96 seconds
Started Jul 04 06:03:58 PM PDT 24
Finished Jul 04 06:06:30 PM PDT 24
Peak memory 206468 kb
Host smart-7e10c8ae-1427-4caa-9676-ff0eae55d191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41732
99018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.4173299018
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1989846942
Short name T938
Test name
Test status
Simulation time 154655067 ps
CPU time 0.77 seconds
Started Jul 04 06:04:04 PM PDT 24
Finished Jul 04 06:04:05 PM PDT 24
Peak memory 206208 kb
Host smart-abe7364d-0947-4e38-b50e-8acb4d08818a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19898
46942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1989846942
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.790657130
Short name T872
Test name
Test status
Simulation time 157995935 ps
CPU time 0.78 seconds
Started Jul 04 06:04:06 PM PDT 24
Finished Jul 04 06:04:07 PM PDT 24
Peak memory 206172 kb
Host smart-67cf3c89-a222-460e-a5ff-502ef89a0620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79065
7130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.790657130
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3812018200
Short name T532
Test name
Test status
Simulation time 209831491 ps
CPU time 0.89 seconds
Started Jul 04 06:04:12 PM PDT 24
Finished Jul 04 06:04:13 PM PDT 24
Peak memory 206168 kb
Host smart-8d6abb8c-f497-4983-b333-4436bd1547c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38120
18200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3812018200
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.4082646362
Short name T2029
Test name
Test status
Simulation time 243384826 ps
CPU time 0.95 seconds
Started Jul 04 06:04:06 PM PDT 24
Finished Jul 04 06:04:07 PM PDT 24
Peak memory 206212 kb
Host smart-cbbc928d-c933-4245-9a0c-fd2d98c32484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40826
46362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.4082646362
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1740214701
Short name T73
Test name
Test status
Simulation time 442620718 ps
CPU time 1.28 seconds
Started Jul 04 06:04:14 PM PDT 24
Finished Jul 04 06:04:15 PM PDT 24
Peak memory 206164 kb
Host smart-98ad43b7-95fa-4205-9eec-830e3b48c16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17402
14701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1740214701
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.4131071087
Short name T326
Test name
Test status
Simulation time 23377794358 ps
CPU time 21.69 seconds
Started Jul 04 06:04:12 PM PDT 24
Finished Jul 04 06:04:34 PM PDT 24
Peak memory 206264 kb
Host smart-da034bab-a02a-4a17-923f-2556641c25da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41310
71087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.4131071087
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.4113875637
Short name T1376
Test name
Test status
Simulation time 3295238782 ps
CPU time 3.79 seconds
Started Jul 04 06:04:13 PM PDT 24
Finished Jul 04 06:04:17 PM PDT 24
Peak memory 206264 kb
Host smart-ed7071bf-f237-4cb0-84e2-0b4ed6fb8140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41138
75637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.4113875637
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.1467760240
Short name T1036
Test name
Test status
Simulation time 7456701365 ps
CPU time 216.68 seconds
Started Jul 04 06:04:13 PM PDT 24
Finished Jul 04 06:07:50 PM PDT 24
Peak memory 206528 kb
Host smart-9b430010-71a7-42bf-9a17-8e34a6193695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
60240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1467760240
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2877830250
Short name T2034
Test name
Test status
Simulation time 5207240454 ps
CPU time 49.86 seconds
Started Jul 04 06:04:14 PM PDT 24
Finished Jul 04 06:05:04 PM PDT 24
Peak memory 206468 kb
Host smart-ea55c110-b84b-42aa-9a8d-6fb9d2381c87
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2877830250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2877830250
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2486392643
Short name T2041
Test name
Test status
Simulation time 302429385 ps
CPU time 0.94 seconds
Started Jul 04 06:04:12 PM PDT 24
Finished Jul 04 06:04:13 PM PDT 24
Peak memory 206212 kb
Host smart-8e70b5e3-da30-405d-ab25-f9ebfde8e455
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2486392643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2486392643
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3021402336
Short name T862
Test name
Test status
Simulation time 197755839 ps
CPU time 0.86 seconds
Started Jul 04 06:04:19 PM PDT 24
Finished Jul 04 06:04:20 PM PDT 24
Peak memory 206204 kb
Host smart-c0252743-9e8e-4c2e-abf8-92ee89dc3b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
02336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3021402336
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2117683685
Short name T1885
Test name
Test status
Simulation time 8137978194 ps
CPU time 73.27 seconds
Started Jul 04 06:04:20 PM PDT 24
Finished Jul 04 06:05:33 PM PDT 24
Peak memory 206436 kb
Host smart-b97fabb4-ce35-42f1-b250-238c74473336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
83685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2117683685
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.4085795619
Short name T1716
Test name
Test status
Simulation time 5158748623 ps
CPU time 139.97 seconds
Started Jul 04 06:04:19 PM PDT 24
Finished Jul 04 06:06:40 PM PDT 24
Peak memory 206444 kb
Host smart-1104e11a-dc7e-470f-a642-7793bd9111f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4085795619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.4085795619
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.4097873048
Short name T606
Test name
Test status
Simulation time 157091901 ps
CPU time 0.77 seconds
Started Jul 04 06:04:20 PM PDT 24
Finished Jul 04 06:04:21 PM PDT 24
Peak memory 206204 kb
Host smart-42afb8ef-8554-4e00-81df-c48386ff816a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4097873048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.4097873048
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.687940803
Short name T2030
Test name
Test status
Simulation time 143504224 ps
CPU time 0.8 seconds
Started Jul 04 06:04:21 PM PDT 24
Finished Jul 04 06:04:22 PM PDT 24
Peak memory 206200 kb
Host smart-12de9368-0a01-4bd7-9ac6-00e95d9336d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68794
0803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.687940803
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1431161646
Short name T71
Test name
Test status
Simulation time 498565653 ps
CPU time 1.29 seconds
Started Jul 04 06:04:21 PM PDT 24
Finished Jul 04 06:04:22 PM PDT 24
Peak memory 206220 kb
Host smart-513d9382-506e-4e93-8c54-69cef10ae465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14311
61646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1431161646
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1863815262
Short name T1496
Test name
Test status
Simulation time 200832397 ps
CPU time 0.93 seconds
Started Jul 04 06:04:20 PM PDT 24
Finished Jul 04 06:04:21 PM PDT 24
Peak memory 206224 kb
Host smart-5d1b7fb6-26a3-4fc3-a4bf-c93732b12b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638
15262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1863815262
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2524559893
Short name T2487
Test name
Test status
Simulation time 167667925 ps
CPU time 0.82 seconds
Started Jul 04 06:04:22 PM PDT 24
Finished Jul 04 06:04:23 PM PDT 24
Peak memory 206208 kb
Host smart-495f8b40-6a51-4f63-9cd7-e4e6deebcc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
59893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2524559893
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.263535997
Short name T2564
Test name
Test status
Simulation time 161660725 ps
CPU time 0.76 seconds
Started Jul 04 06:04:20 PM PDT 24
Finished Jul 04 06:04:21 PM PDT 24
Peak memory 206228 kb
Host smart-2de88663-cea2-4653-8b00-483bd8b51955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
5997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.263535997
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2503184617
Short name T2620
Test name
Test status
Simulation time 175077722 ps
CPU time 0.86 seconds
Started Jul 04 06:04:27 PM PDT 24
Finished Jul 04 06:04:28 PM PDT 24
Peak memory 206204 kb
Host smart-a5e866db-58a4-4a0b-9847-f17b1af50a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
84617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2503184617
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1875846719
Short name T1332
Test name
Test status
Simulation time 252627379 ps
CPU time 0.97 seconds
Started Jul 04 06:04:29 PM PDT 24
Finished Jul 04 06:04:30 PM PDT 24
Peak memory 206172 kb
Host smart-dae744a0-5802-4918-abaf-eb9a3c4fc6fc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1875846719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1875846719
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.4277430090
Short name T1922
Test name
Test status
Simulation time 233039654 ps
CPU time 0.95 seconds
Started Jul 04 06:04:37 PM PDT 24
Finished Jul 04 06:04:38 PM PDT 24
Peak memory 206212 kb
Host smart-c4ca4abd-7cff-431c-a0ed-42a1ad99bc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
30090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.4277430090
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1668635160
Short name T421
Test name
Test status
Simulation time 206031436 ps
CPU time 0.86 seconds
Started Jul 04 06:04:35 PM PDT 24
Finished Jul 04 06:04:36 PM PDT 24
Peak memory 206220 kb
Host smart-cfeaaccf-2e8e-482e-bc12-471d37089638
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1668635160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1668635160
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.738510101
Short name T222
Test name
Test status
Simulation time 217235738 ps
CPU time 0.9 seconds
Started Jul 04 06:04:27 PM PDT 24
Finished Jul 04 06:04:28 PM PDT 24
Peak memory 206212 kb
Host smart-e63848ae-bde0-4777-9995-d499ac91e50c
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=738510101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.738510101
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1067247933
Short name T895
Test name
Test status
Simulation time 182665793 ps
CPU time 0.8 seconds
Started Jul 04 06:04:28 PM PDT 24
Finished Jul 04 06:04:29 PM PDT 24
Peak memory 206180 kb
Host smart-2fcb5e82-cc14-473d-a4c8-cca8bf7742a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
47933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1067247933
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2977518852
Short name T36
Test name
Test status
Simulation time 41400452 ps
CPU time 0.63 seconds
Started Jul 04 06:04:29 PM PDT 24
Finished Jul 04 06:04:30 PM PDT 24
Peak memory 206140 kb
Host smart-97c7057b-f5fe-4602-9b57-3d3222f061ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
18852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2977518852
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.132385827
Short name T735
Test name
Test status
Simulation time 19699740855 ps
CPU time 39.7 seconds
Started Jul 04 06:04:29 PM PDT 24
Finished Jul 04 06:05:09 PM PDT 24
Peak memory 206552 kb
Host smart-f58b9349-7a40-409a-bfe2-dfbfd53e5543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
5827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.132385827
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.386931224
Short name T832
Test name
Test status
Simulation time 179644120 ps
CPU time 0.87 seconds
Started Jul 04 06:04:29 PM PDT 24
Finished Jul 04 06:04:30 PM PDT 24
Peak memory 206184 kb
Host smart-a614894f-8a2a-46a2-9ef8-a683515f9fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
1224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.386931224
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2050989730
Short name T620
Test name
Test status
Simulation time 218716226 ps
CPU time 0.88 seconds
Started Jul 04 06:04:28 PM PDT 24
Finished Jul 04 06:04:29 PM PDT 24
Peak memory 206212 kb
Host smart-6cbe5005-5e72-48bd-a225-600bffc64bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20509
89730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2050989730
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2919088002
Short name T165
Test name
Test status
Simulation time 7300161631 ps
CPU time 34.26 seconds
Started Jul 04 06:04:35 PM PDT 24
Finished Jul 04 06:05:09 PM PDT 24
Peak memory 206548 kb
Host smart-d8d60aad-8856-419f-81ce-772545004c73
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2919088002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2919088002
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.454366555
Short name T2683
Test name
Test status
Simulation time 14183728537 ps
CPU time 399.05 seconds
Started Jul 04 06:04:36 PM PDT 24
Finished Jul 04 06:11:15 PM PDT 24
Peak memory 206468 kb
Host smart-019861f0-edd5-46f2-a74e-91a85575d085
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=454366555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.454366555
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.197328761
Short name T378
Test name
Test status
Simulation time 11785408676 ps
CPU time 87.15 seconds
Started Jul 04 06:04:35 PM PDT 24
Finished Jul 04 06:06:02 PM PDT 24
Peak memory 206448 kb
Host smart-89ddba3b-a101-4254-9957-17ff55b95064
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=197328761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.197328761
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3129393354
Short name T566
Test name
Test status
Simulation time 197696005 ps
CPU time 0.81 seconds
Started Jul 04 06:04:35 PM PDT 24
Finished Jul 04 06:04:36 PM PDT 24
Peak memory 206212 kb
Host smart-953d0e89-c5cf-41e3-abd0-80f25304815f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31293
93354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3129393354
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.358379361
Short name T1358
Test name
Test status
Simulation time 203959592 ps
CPU time 0.87 seconds
Started Jul 04 06:04:35 PM PDT 24
Finished Jul 04 06:04:36 PM PDT 24
Peak memory 206176 kb
Host smart-51c89e84-baf1-46dc-a433-dafa81d5763d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35837
9361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.358379361
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.325751094
Short name T765
Test name
Test status
Simulation time 226696099 ps
CPU time 0.85 seconds
Started Jul 04 06:04:34 PM PDT 24
Finished Jul 04 06:04:35 PM PDT 24
Peak memory 206160 kb
Host smart-fe7ca8d0-9eea-4dc3-ad5f-d909910ecc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32575
1094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.325751094
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1584595494
Short name T195
Test name
Test status
Simulation time 206716782 ps
CPU time 0.85 seconds
Started Jul 04 06:04:44 PM PDT 24
Finished Jul 04 06:04:45 PM PDT 24
Peak memory 206192 kb
Host smart-fc8d1dff-9783-4e1e-9e21-578ed7d87739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
95494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1584595494
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2626369133
Short name T2123
Test name
Test status
Simulation time 158127884 ps
CPU time 0.81 seconds
Started Jul 04 06:04:44 PM PDT 24
Finished Jul 04 06:04:45 PM PDT 24
Peak memory 206192 kb
Host smart-12835f88-4d0c-42c5-9a31-d739aa83d09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
69133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2626369133
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1936705379
Short name T1361
Test name
Test status
Simulation time 146694076 ps
CPU time 0.82 seconds
Started Jul 04 06:04:42 PM PDT 24
Finished Jul 04 06:04:43 PM PDT 24
Peak memory 206164 kb
Host smart-a3936914-d2ed-4092-b98a-b193500d2dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19367
05379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1936705379
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1190477079
Short name T380
Test name
Test status
Simulation time 190419388 ps
CPU time 0.89 seconds
Started Jul 04 06:04:41 PM PDT 24
Finished Jul 04 06:04:42 PM PDT 24
Peak memory 206188 kb
Host smart-5bd9cf51-9105-44d4-92c5-237e0a9c383f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11904
77079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1190477079
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2973009250
Short name T1891
Test name
Test status
Simulation time 5173356160 ps
CPU time 50.85 seconds
Started Jul 04 06:04:42 PM PDT 24
Finished Jul 04 06:05:33 PM PDT 24
Peak memory 206524 kb
Host smart-a81d2827-c943-4f41-936f-ab23958c5714
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2973009250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2973009250
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3951916203
Short name T2674
Test name
Test status
Simulation time 190806801 ps
CPU time 0.76 seconds
Started Jul 04 06:04:42 PM PDT 24
Finished Jul 04 06:04:42 PM PDT 24
Peak memory 206212 kb
Host smart-2e7f0324-3ad9-452d-9532-096ab6c2b789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
16203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3951916203
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2983994676
Short name T1312
Test name
Test status
Simulation time 160950419 ps
CPU time 0.86 seconds
Started Jul 04 06:04:43 PM PDT 24
Finished Jul 04 06:04:44 PM PDT 24
Peak memory 206196 kb
Host smart-06cc5249-43b4-4aa8-9f9c-7eb1f327e009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29839
94676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2983994676
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.156003887
Short name T582
Test name
Test status
Simulation time 520591126 ps
CPU time 1.41 seconds
Started Jul 04 06:04:52 PM PDT 24
Finished Jul 04 06:04:54 PM PDT 24
Peak memory 206216 kb
Host smart-fd921325-d58d-4b11-b2ca-da604f52831b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15600
3887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.156003887
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1158555450
Short name T2531
Test name
Test status
Simulation time 8273179437 ps
CPU time 77.34 seconds
Started Jul 04 06:04:41 PM PDT 24
Finished Jul 04 06:05:59 PM PDT 24
Peak memory 206452 kb
Host smart-099da360-7431-4603-ab1d-1c274a474468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11585
55450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1158555450
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1659338826
Short name T244
Test name
Test status
Simulation time 3615551521 ps
CPU time 4.98 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:05:02 PM PDT 24
Peak memory 206540 kb
Host smart-bff48cc8-b3a0-4ba2-86b1-e86eddfab9ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1659338826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1659338826
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2418445754
Short name T1707
Test name
Test status
Simulation time 13345122570 ps
CPU time 15.91 seconds
Started Jul 04 06:04:58 PM PDT 24
Finished Jul 04 06:05:14 PM PDT 24
Peak memory 206484 kb
Host smart-cdca4dd3-2cd2-45ac-a175-49949ed2da9b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2418445754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2418445754
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1333720640
Short name T1768
Test name
Test status
Simulation time 23403321550 ps
CPU time 21.65 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:05:19 PM PDT 24
Peak memory 206496 kb
Host smart-a58d42d6-2c27-471f-9186-e21887776575
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1333720640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1333720640
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2398603852
Short name T1565
Test name
Test status
Simulation time 209340878 ps
CPU time 0.86 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:04:58 PM PDT 24
Peak memory 206192 kb
Host smart-15a91cf0-5695-472c-9b76-13df62fb2ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23986
03852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2398603852
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2387751456
Short name T58
Test name
Test status
Simulation time 164899938 ps
CPU time 0.75 seconds
Started Jul 04 06:04:55 PM PDT 24
Finished Jul 04 06:04:56 PM PDT 24
Peak memory 206124 kb
Host smart-de0bfa9d-9ce7-45cb-bf0d-0d6d33915fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23877
51456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2387751456
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.398818086
Short name T116
Test name
Test status
Simulation time 334187271 ps
CPU time 1.13 seconds
Started Jul 04 06:04:55 PM PDT 24
Finished Jul 04 06:04:57 PM PDT 24
Peak memory 206204 kb
Host smart-295f9f7a-66c2-4efa-809b-da7c2552e169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39881
8086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.398818086
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.724178124
Short name T812
Test name
Test status
Simulation time 897678185 ps
CPU time 2.36 seconds
Started Jul 04 06:04:56 PM PDT 24
Finished Jul 04 06:04:59 PM PDT 24
Peak memory 206412 kb
Host smart-ee54c9c1-ba2d-406e-baf9-4607c1d45465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72417
8124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.724178124
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.4232846727
Short name T2698
Test name
Test status
Simulation time 6537519081 ps
CPU time 13.53 seconds
Started Jul 04 06:04:57 PM PDT 24
Finished Jul 04 06:05:11 PM PDT 24
Peak memory 206536 kb
Host smart-972300b8-eece-480c-b637-7d76273cde81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42328
46727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.4232846727
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.23013843
Short name T2145
Test name
Test status
Simulation time 182407699 ps
CPU time 0.79 seconds
Started Jul 04 06:04:55 PM PDT 24
Finished Jul 04 06:04:56 PM PDT 24
Peak memory 206164 kb
Host smart-d09f2fca-014b-49af-aa8a-4b32648c3972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23013
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.23013843
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1012870691
Short name T2441
Test name
Test status
Simulation time 44194551 ps
CPU time 0.68 seconds
Started Jul 04 06:05:05 PM PDT 24
Finished Jul 04 06:05:06 PM PDT 24
Peak memory 206208 kb
Host smart-2164d7e7-b9fb-40bb-8159-25568ba513e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10128
70691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1012870691
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3279049302
Short name T1479
Test name
Test status
Simulation time 840496016 ps
CPU time 2.24 seconds
Started Jul 04 06:05:03 PM PDT 24
Finished Jul 04 06:05:05 PM PDT 24
Peak memory 206304 kb
Host smart-f1e60c7f-4f74-4b0b-9b6f-9206c6c0cbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
49302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3279049302
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2110836451
Short name T1962
Test name
Test status
Simulation time 191645626 ps
CPU time 2.14 seconds
Started Jul 04 06:05:04 PM PDT 24
Finished Jul 04 06:05:06 PM PDT 24
Peak memory 206404 kb
Host smart-1323fe08-807d-4e1b-aeea-e5b570caa4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
36451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2110836451
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2240703706
Short name T2169
Test name
Test status
Simulation time 92179018702 ps
CPU time 126.3 seconds
Started Jul 04 06:05:04 PM PDT 24
Finished Jul 04 06:07:10 PM PDT 24
Peak memory 206468 kb
Host smart-c45f8ba4-fc7d-4e71-8868-829dd6e023a1
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2240703706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2240703706
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.4055800444
Short name T21
Test name
Test status
Simulation time 110176789724 ps
CPU time 165.17 seconds
Started Jul 04 06:05:03 PM PDT 24
Finished Jul 04 06:07:48 PM PDT 24
Peak memory 206484 kb
Host smart-875fa04c-c020-4d38-8f9d-21196bb386a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055800444 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.4055800444
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.178122868
Short name T2362
Test name
Test status
Simulation time 108130646398 ps
CPU time 142.56 seconds
Started Jul 04 06:05:03 PM PDT 24
Finished Jul 04 06:07:26 PM PDT 24
Peak memory 206464 kb
Host smart-9a045cf3-e174-4380-8ea1-266d85290e70
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=178122868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.178122868
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2724817164
Short name T30
Test name
Test status
Simulation time 83239287025 ps
CPU time 118.27 seconds
Started Jul 04 06:05:03 PM PDT 24
Finished Jul 04 06:07:02 PM PDT 24
Peak memory 206472 kb
Host smart-c278f003-4f90-4a58-b27d-ea7ac22ada8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724817164 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2724817164
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1404970774
Short name T705
Test name
Test status
Simulation time 111205436093 ps
CPU time 148.83 seconds
Started Jul 04 06:05:10 PM PDT 24
Finished Jul 04 06:07:39 PM PDT 24
Peak memory 206496 kb
Host smart-d83882f3-b4da-4c70-a2a8-ea39637983fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
70774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1404970774
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3141319093
Short name T2343
Test name
Test status
Simulation time 202273913 ps
CPU time 0.84 seconds
Started Jul 04 06:05:10 PM PDT 24
Finished Jul 04 06:05:11 PM PDT 24
Peak memory 206144 kb
Host smart-6c43ebda-10fd-45f1-835a-025cb8c15cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31413
19093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3141319093
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4200041488
Short name T2099
Test name
Test status
Simulation time 137048901 ps
CPU time 0.78 seconds
Started Jul 04 06:05:09 PM PDT 24
Finished Jul 04 06:05:10 PM PDT 24
Peak memory 206204 kb
Host smart-f3295531-80fe-4b4c-b6ee-8bb11f85df89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42000
41488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4200041488
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2601214046
Short name T437
Test name
Test status
Simulation time 219913555 ps
CPU time 0.93 seconds
Started Jul 04 06:05:09 PM PDT 24
Finished Jul 04 06:05:11 PM PDT 24
Peak memory 206208 kb
Host smart-347dba04-b22b-4964-98f0-7e8c95af864d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26012
14046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2601214046
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2419309570
Short name T1313
Test name
Test status
Simulation time 198915921 ps
CPU time 0.87 seconds
Started Jul 04 06:05:09 PM PDT 24
Finished Jul 04 06:05:10 PM PDT 24
Peak memory 206144 kb
Host smart-9a2c68c9-4099-4965-9990-af31c7e4d811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24193
09570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2419309570
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.82373221
Short name T2421
Test name
Test status
Simulation time 23295067029 ps
CPU time 24.72 seconds
Started Jul 04 06:05:09 PM PDT 24
Finished Jul 04 06:05:34 PM PDT 24
Peak memory 206284 kb
Host smart-bcf368c5-256f-47fa-8aba-81a219a71b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82373
221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.82373221
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.475913739
Short name T502
Test name
Test status
Simulation time 3300979005 ps
CPU time 3.74 seconds
Started Jul 04 06:05:11 PM PDT 24
Finished Jul 04 06:05:15 PM PDT 24
Peak memory 206264 kb
Host smart-2fa26232-8529-4ab6-9c75-0678ff679310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47591
3739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.475913739
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2957709763
Short name T1099
Test name
Test status
Simulation time 10598680636 ps
CPU time 99.54 seconds
Started Jul 04 06:05:10 PM PDT 24
Finished Jul 04 06:06:50 PM PDT 24
Peak memory 206524 kb
Host smart-635f495d-cfd4-438e-932b-2b5d234f147f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
09763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2957709763
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3097465516
Short name T401
Test name
Test status
Simulation time 5258374185 ps
CPU time 48.58 seconds
Started Jul 04 06:05:19 PM PDT 24
Finished Jul 04 06:06:07 PM PDT 24
Peak memory 206472 kb
Host smart-f04eff77-6521-45fb-a9eb-f5c623cc7d70
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3097465516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3097465516
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2633160422
Short name T1924
Test name
Test status
Simulation time 254726780 ps
CPU time 0.91 seconds
Started Jul 04 06:05:17 PM PDT 24
Finished Jul 04 06:05:18 PM PDT 24
Peak memory 206164 kb
Host smart-0eae29c6-b07b-4bc3-93c3-ecc9e8e4b746
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2633160422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2633160422
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1588603182
Short name T1194
Test name
Test status
Simulation time 198959008 ps
CPU time 0.94 seconds
Started Jul 04 06:05:19 PM PDT 24
Finished Jul 04 06:05:20 PM PDT 24
Peak memory 206172 kb
Host smart-e4410edf-a885-4063-802c-2aad08aa0f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15886
03182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1588603182
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1835114340
Short name T2560
Test name
Test status
Simulation time 5085032433 ps
CPU time 35.78 seconds
Started Jul 04 06:05:18 PM PDT 24
Finished Jul 04 06:05:54 PM PDT 24
Peak memory 206496 kb
Host smart-f2e95b38-a546-4154-bd5c-41313b377017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18351
14340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1835114340
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.89376142
Short name T940
Test name
Test status
Simulation time 5596363056 ps
CPU time 51.55 seconds
Started Jul 04 06:05:19 PM PDT 24
Finished Jul 04 06:06:11 PM PDT 24
Peak memory 206448 kb
Host smart-8c18e216-4163-4f14-a425-a8c956da86b4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=89376142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.89376142
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1090018833
Short name T1700
Test name
Test status
Simulation time 192333375 ps
CPU time 0.81 seconds
Started Jul 04 06:05:18 PM PDT 24
Finished Jul 04 06:05:19 PM PDT 24
Peak memory 206212 kb
Host smart-45cd2681-9c7c-40a8-8484-291c04c27a97
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1090018833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1090018833
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.854565093
Short name T1935
Test name
Test status
Simulation time 145428802 ps
CPU time 0.8 seconds
Started Jul 04 06:05:21 PM PDT 24
Finished Jul 04 06:05:22 PM PDT 24
Peak memory 206192 kb
Host smart-90d079a5-9979-444e-a98b-d1b259da2f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85456
5093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.854565093
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3935311107
Short name T2702
Test name
Test status
Simulation time 198887779 ps
CPU time 0.81 seconds
Started Jul 04 06:05:18 PM PDT 24
Finished Jul 04 06:05:19 PM PDT 24
Peak memory 206208 kb
Host smart-83141020-18c4-43f1-8320-0f7e894c0e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
11107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3935311107
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1082227656
Short name T1296
Test name
Test status
Simulation time 201642804 ps
CPU time 0.86 seconds
Started Jul 04 06:05:20 PM PDT 24
Finished Jul 04 06:05:21 PM PDT 24
Peak memory 206192 kb
Host smart-a3748448-db11-4b55-a68b-ee378e660bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10822
27656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1082227656
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.191712964
Short name T2400
Test name
Test status
Simulation time 155776719 ps
CPU time 0.79 seconds
Started Jul 04 06:05:18 PM PDT 24
Finished Jul 04 06:05:19 PM PDT 24
Peak memory 206176 kb
Host smart-02208593-c272-44ab-afa5-07fba853a70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
2964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.191712964
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1140567883
Short name T1639
Test name
Test status
Simulation time 150562080 ps
CPU time 0.81 seconds
Started Jul 04 06:05:17 PM PDT 24
Finished Jul 04 06:05:18 PM PDT 24
Peak memory 206144 kb
Host smart-604d22b0-658c-40de-93a7-e7b1abc80671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11405
67883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1140567883
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1599879961
Short name T2303
Test name
Test status
Simulation time 277235700 ps
CPU time 0.95 seconds
Started Jul 04 06:05:18 PM PDT 24
Finished Jul 04 06:05:19 PM PDT 24
Peak memory 206232 kb
Host smart-3233f67f-dc7a-4480-a37b-9a287763a54a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1599879961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1599879961
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3088945264
Short name T2233
Test name
Test status
Simulation time 199082347 ps
CPU time 0.9 seconds
Started Jul 04 06:05:17 PM PDT 24
Finished Jul 04 06:05:18 PM PDT 24
Peak memory 206180 kb
Host smart-e37e972a-9192-4a39-8254-9456c95de800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30889
45264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3088945264
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2094500645
Short name T1580
Test name
Test status
Simulation time 141494560 ps
CPU time 0.73 seconds
Started Jul 04 06:05:25 PM PDT 24
Finished Jul 04 06:05:26 PM PDT 24
Peak memory 206192 kb
Host smart-7f5b02c7-1f96-4492-83ef-e7f38c68cb0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
00645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2094500645
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.68494107
Short name T40
Test name
Test status
Simulation time 35903002 ps
CPU time 0.69 seconds
Started Jul 04 06:05:25 PM PDT 24
Finished Jul 04 06:05:25 PM PDT 24
Peak memory 206144 kb
Host smart-fe994910-f454-4fb7-9520-0a7ef8420dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68494
107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.68494107
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3291007509
Short name T1123
Test name
Test status
Simulation time 17321249046 ps
CPU time 35.85 seconds
Started Jul 04 06:05:24 PM PDT 24
Finished Jul 04 06:06:00 PM PDT 24
Peak memory 206528 kb
Host smart-ccc2d47e-1c47-4219-b598-8692cac75cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32910
07509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3291007509
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2677583270
Short name T1577
Test name
Test status
Simulation time 226956859 ps
CPU time 0.85 seconds
Started Jul 04 06:05:24 PM PDT 24
Finished Jul 04 06:05:25 PM PDT 24
Peak memory 206200 kb
Host smart-6d88d1c9-3e24-43c4-8eca-91604e0d6b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
83270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2677583270
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2188717084
Short name T323
Test name
Test status
Simulation time 153453011 ps
CPU time 0.82 seconds
Started Jul 04 06:05:23 PM PDT 24
Finished Jul 04 06:05:24 PM PDT 24
Peak memory 206180 kb
Host smart-e5335bb1-88e1-4533-8ff5-fa7548d8bf09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887
17084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2188717084
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3105422843
Short name T890
Test name
Test status
Simulation time 20366365774 ps
CPU time 161.12 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:08:16 PM PDT 24
Peak memory 206540 kb
Host smart-afdfa17b-c985-4278-b889-d326035dafcc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3105422843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3105422843
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.4072744474
Short name T2216
Test name
Test status
Simulation time 9172579131 ps
CPU time 66.1 seconds
Started Jul 04 06:05:35 PM PDT 24
Finished Jul 04 06:06:41 PM PDT 24
Peak memory 206556 kb
Host smart-97a26736-385e-4f6f-a9c9-31cb5e6df7a8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4072744474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.4072744474
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3318365860
Short name T2138
Test name
Test status
Simulation time 12807089626 ps
CPU time 260.03 seconds
Started Jul 04 06:05:35 PM PDT 24
Finished Jul 04 06:09:55 PM PDT 24
Peak memory 206480 kb
Host smart-cd2ad00a-5a17-47a3-a3d1-fdb85e2e0ba0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3318365860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3318365860
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3986830141
Short name T969
Test name
Test status
Simulation time 228312426 ps
CPU time 0.86 seconds
Started Jul 04 06:05:35 PM PDT 24
Finished Jul 04 06:05:36 PM PDT 24
Peak memory 206160 kb
Host smart-3486b33a-97e9-4c1e-9230-c3b45780053e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
30141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3986830141
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1989331493
Short name T1774
Test name
Test status
Simulation time 172248598 ps
CPU time 0.83 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:05:35 PM PDT 24
Peak memory 206224 kb
Host smart-a716dbf2-e113-4fd8-b2e8-34f8d41f8aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893
31493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1989331493
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1150550212
Short name T1048
Test name
Test status
Simulation time 148355360 ps
CPU time 0.72 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:05:35 PM PDT 24
Peak memory 206220 kb
Host smart-7f9ffb28-9d2d-4427-8441-92ecee5bcc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
50212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1150550212
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3020461803
Short name T78
Test name
Test status
Simulation time 178018320 ps
CPU time 0.82 seconds
Started Jul 04 06:05:35 PM PDT 24
Finished Jul 04 06:05:36 PM PDT 24
Peak memory 206196 kb
Host smart-09838bd4-955f-4dd4-adda-5c95726a997d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30204
61803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3020461803
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3926166997
Short name T231
Test name
Test status
Simulation time 971916570 ps
CPU time 1.87 seconds
Started Jul 04 06:05:43 PM PDT 24
Finished Jul 04 06:05:45 PM PDT 24
Peak memory 225092 kb
Host smart-61abc0b2-f609-4438-9a00-04c4d75bfb86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3926166997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3926166997
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.3259262437
Short name T1591
Test name
Test status
Simulation time 455534124 ps
CPU time 1.23 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:05:35 PM PDT 24
Peak memory 206180 kb
Host smart-b474d883-2585-4bca-9e53-d615d1190eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32592
62437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.3259262437
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3946410592
Short name T1245
Test name
Test status
Simulation time 212095792 ps
CPU time 0.9 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:05:35 PM PDT 24
Peak memory 206176 kb
Host smart-be552c72-1976-4559-ae31-eff6849d51f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39464
10592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3946410592
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2048119465
Short name T1543
Test name
Test status
Simulation time 175036800 ps
CPU time 0.79 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:05:35 PM PDT 24
Peak memory 206176 kb
Host smart-85c65990-ff87-4434-905b-4d2525d02898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20481
19465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2048119465
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.4140476297
Short name T1899
Test name
Test status
Simulation time 156768038 ps
CPU time 0.79 seconds
Started Jul 04 06:05:35 PM PDT 24
Finished Jul 04 06:05:36 PM PDT 24
Peak memory 206212 kb
Host smart-b82d360f-eb72-4ce3-bcbe-5e0742f577ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
76297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.4140476297
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1622856639
Short name T2639
Test name
Test status
Simulation time 234855808 ps
CPU time 0.91 seconds
Started Jul 04 06:05:34 PM PDT 24
Finished Jul 04 06:05:35 PM PDT 24
Peak memory 206164 kb
Host smart-0b7afe3d-d949-4cca-8701-a0faa1446af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
56639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1622856639
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.839187825
Short name T1712
Test name
Test status
Simulation time 4452298559 ps
CPU time 30.77 seconds
Started Jul 04 06:05:43 PM PDT 24
Finished Jul 04 06:06:14 PM PDT 24
Peak memory 206424 kb
Host smart-fb42096e-254f-4f37-8425-3e0ff50c44a6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=839187825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.839187825
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4022237712
Short name T1898
Test name
Test status
Simulation time 177246441 ps
CPU time 0.76 seconds
Started Jul 04 06:05:42 PM PDT 24
Finished Jul 04 06:05:43 PM PDT 24
Peak memory 206232 kb
Host smart-f57d237e-84d9-4a26-9a3d-7e97d37d7141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40222
37712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4022237712
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2191642660
Short name T109
Test name
Test status
Simulation time 176388009 ps
CPU time 0.82 seconds
Started Jul 04 06:05:42 PM PDT 24
Finished Jul 04 06:05:43 PM PDT 24
Peak memory 206176 kb
Host smart-f4b59d47-a8f9-44d7-866b-fd861533c0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
42660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2191642660
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2778987550
Short name T1859
Test name
Test status
Simulation time 265501889 ps
CPU time 0.94 seconds
Started Jul 04 06:05:42 PM PDT 24
Finished Jul 04 06:05:43 PM PDT 24
Peak memory 206196 kb
Host smart-a7c450c4-1eac-42c9-a453-92a58ebcf89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789
87550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2778987550
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2179976633
Short name T442
Test name
Test status
Simulation time 5903906413 ps
CPU time 163.27 seconds
Started Jul 04 06:05:43 PM PDT 24
Finished Jul 04 06:08:27 PM PDT 24
Peak memory 206488 kb
Host smart-b0a131cf-d05c-415b-9e63-d868e7e1353f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21799
76633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2179976633
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2526820824
Short name T547
Test name
Test status
Simulation time 34154463 ps
CPU time 0.7 seconds
Started Jul 04 06:09:20 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206228 kb
Host smart-789d11b6-315f-4f41-b88b-06ddb2dee379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2526820824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2526820824
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2388457783
Short name T2196
Test name
Test status
Simulation time 4049968627 ps
CPU time 5.57 seconds
Started Jul 04 06:09:03 PM PDT 24
Finished Jul 04 06:09:09 PM PDT 24
Peak memory 206528 kb
Host smart-09fce762-8fd6-4e00-b5aa-2cb0c85649ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2388457783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2388457783
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.691688175
Short name T2695
Test name
Test status
Simulation time 13403355133 ps
CPU time 13.75 seconds
Started Jul 04 06:09:07 PM PDT 24
Finished Jul 04 06:09:21 PM PDT 24
Peak memory 206536 kb
Host smart-16b23b7f-58ef-43e1-89fa-b9b2a25fcae8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=691688175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.691688175
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3400865046
Short name T2149
Test name
Test status
Simulation time 23347145442 ps
CPU time 25.39 seconds
Started Jul 04 06:09:07 PM PDT 24
Finished Jul 04 06:09:32 PM PDT 24
Peak memory 206280 kb
Host smart-9f64ddc7-e4c4-44bf-bdcd-6c33e03cbe95
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3400865046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3400865046
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2938718056
Short name T1680
Test name
Test status
Simulation time 161841433 ps
CPU time 0.76 seconds
Started Jul 04 06:09:07 PM PDT 24
Finished Jul 04 06:09:08 PM PDT 24
Peak memory 206200 kb
Host smart-d88154b6-7356-4d06-99c3-96dab5b3e595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29387
18056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2938718056
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2617091445
Short name T2265
Test name
Test status
Simulation time 146844862 ps
CPU time 0.78 seconds
Started Jul 04 06:09:07 PM PDT 24
Finished Jul 04 06:09:08 PM PDT 24
Peak memory 206204 kb
Host smart-8229e6d6-6dc8-48c4-b94e-f828a90216d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26170
91445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2617091445
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3206214298
Short name T772
Test name
Test status
Simulation time 358146220 ps
CPU time 1.15 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:06 PM PDT 24
Peak memory 206168 kb
Host smart-305d8468-9402-4c5d-b177-0cb3c747a9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
14298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3206214298
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1540725077
Short name T739
Test name
Test status
Simulation time 462201281 ps
CPU time 1.27 seconds
Started Jul 04 06:09:04 PM PDT 24
Finished Jul 04 06:09:06 PM PDT 24
Peak memory 206212 kb
Host smart-ff901b6a-5063-416e-a9e5-98f5b1b26dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15407
25077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1540725077
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2562768744
Short name T1475
Test name
Test status
Simulation time 20646060579 ps
CPU time 38.28 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:44 PM PDT 24
Peak memory 206520 kb
Host smart-fa0264d6-ae97-4c19-a752-e87cfb330f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
68744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2562768744
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2300106554
Short name T780
Test name
Test status
Simulation time 472206642 ps
CPU time 1.31 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:06 PM PDT 24
Peak memory 206176 kb
Host smart-6f6a9fc1-fdd1-41d7-afe4-4b5d2647f0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23001
06554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2300106554
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.625390607
Short name T2178
Test name
Test status
Simulation time 145080704 ps
CPU time 0.78 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:06 PM PDT 24
Peak memory 206164 kb
Host smart-40818edc-fa96-4a06-bee7-c937591f7125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62539
0607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.625390607
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.916815283
Short name T1731
Test name
Test status
Simulation time 39008253 ps
CPU time 0.66 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:06 PM PDT 24
Peak memory 206200 kb
Host smart-7e117e50-b262-4010-8276-9e91b55348b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91681
5283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.916815283
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2022608169
Short name T1588
Test name
Test status
Simulation time 980863811 ps
CPU time 2.28 seconds
Started Jul 04 06:09:04 PM PDT 24
Finished Jul 04 06:09:07 PM PDT 24
Peak memory 206436 kb
Host smart-4d1089cd-2210-4691-87aa-6a45166da575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20226
08169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2022608169
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.594447432
Short name T797
Test name
Test status
Simulation time 235371082 ps
CPU time 0.9 seconds
Started Jul 04 06:09:04 PM PDT 24
Finished Jul 04 06:09:05 PM PDT 24
Peak memory 206140 kb
Host smart-a7c1f05a-8d92-4c37-8dba-9227fb31ad0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59444
7432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.594447432
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.690812037
Short name T1243
Test name
Test status
Simulation time 178832595 ps
CPU time 0.8 seconds
Started Jul 04 06:09:05 PM PDT 24
Finished Jul 04 06:09:06 PM PDT 24
Peak memory 206168 kb
Host smart-03109e29-91d6-49bc-8787-aed66056e132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69081
2037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.690812037
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3809787608
Short name T1720
Test name
Test status
Simulation time 173436888 ps
CPU time 0.89 seconds
Started Jul 04 06:09:14 PM PDT 24
Finished Jul 04 06:09:15 PM PDT 24
Peak memory 206192 kb
Host smart-6e45fe45-3c94-47c8-af0a-ad618a637302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38097
87608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3809787608
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1937956146
Short name T1342
Test name
Test status
Simulation time 190015238 ps
CPU time 0.85 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 206196 kb
Host smart-1d6acd62-b9e4-49b8-a572-b8eb5a121560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
56146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1937956146
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1010884779
Short name T1539
Test name
Test status
Simulation time 23346491582 ps
CPU time 20.78 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:33 PM PDT 24
Peak memory 206264 kb
Host smart-40c221f2-c839-43fe-aa62-4db7d4ea25ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
84779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1010884779
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3233112283
Short name T1025
Test name
Test status
Simulation time 3322853473 ps
CPU time 3.55 seconds
Started Jul 04 06:09:16 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206224 kb
Host smart-56bb6cf2-a74d-4432-9e93-72c876105bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
12283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3233112283
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3781743558
Short name T2395
Test name
Test status
Simulation time 8115559395 ps
CPU time 218.5 seconds
Started Jul 04 06:09:11 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206536 kb
Host smart-2295a267-803f-4cba-af66-d3d514fdce43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37817
43558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3781743558
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.2311754011
Short name T1664
Test name
Test status
Simulation time 5147482002 ps
CPU time 39.07 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:09:52 PM PDT 24
Peak memory 206504 kb
Host smart-70daf0eb-788c-4df5-bc14-aa0470a09594
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2311754011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.2311754011
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.3122952478
Short name T2635
Test name
Test status
Simulation time 263378291 ps
CPU time 0.93 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 206216 kb
Host smart-d499f8f6-cfe8-4411-b8cc-b30fccf4c6a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3122952478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.3122952478
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3276925110
Short name T1945
Test name
Test status
Simulation time 189770872 ps
CPU time 0.85 seconds
Started Jul 04 06:09:10 PM PDT 24
Finished Jul 04 06:09:11 PM PDT 24
Peak memory 206196 kb
Host smart-503a88ea-9b8e-40f2-9348-1fafcabb80b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32769
25110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3276925110
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3467391574
Short name T2359
Test name
Test status
Simulation time 4652782923 ps
CPU time 124.79 seconds
Started Jul 04 06:09:19 PM PDT 24
Finished Jul 04 06:11:24 PM PDT 24
Peak memory 206424 kb
Host smart-7abf3888-0a9f-4660-bd11-a883e2af319a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34673
91574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3467391574
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.568028823
Short name T2456
Test name
Test status
Simulation time 6669940973 ps
CPU time 48.42 seconds
Started Jul 04 06:09:17 PM PDT 24
Finished Jul 04 06:10:05 PM PDT 24
Peak memory 206452 kb
Host smart-3eb08c1f-85e5-48dc-a2b6-bbcba8208d1d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=568028823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.568028823
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.241227455
Short name T1531
Test name
Test status
Simulation time 154296606 ps
CPU time 0.76 seconds
Started Jul 04 06:09:16 PM PDT 24
Finished Jul 04 06:09:17 PM PDT 24
Peak memory 206160 kb
Host smart-d60c7389-34b5-43b7-83e2-89d510b6d54c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=241227455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.241227455
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3589840605
Short name T1685
Test name
Test status
Simulation time 145619361 ps
CPU time 0.77 seconds
Started Jul 04 06:09:11 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206188 kb
Host smart-bac3690f-02d0-4cd7-9e19-8753e7143b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35898
40605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3589840605
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2047225154
Short name T432
Test name
Test status
Simulation time 173337375 ps
CPU time 0.84 seconds
Started Jul 04 06:09:17 PM PDT 24
Finished Jul 04 06:09:18 PM PDT 24
Peak memory 206168 kb
Host smart-20ede135-1dc6-413d-8351-3845fabfc48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20472
25154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2047225154
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.238070404
Short name T1394
Test name
Test status
Simulation time 192189214 ps
CPU time 0.97 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206144 kb
Host smart-e323bbbe-2f36-4df5-8fd9-4f8066df7cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23807
0404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.238070404
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3853196025
Short name T748
Test name
Test status
Simulation time 158869806 ps
CPU time 0.76 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206172 kb
Host smart-ec473b3d-14b3-4a63-add0-4b0e3633abd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531
96025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3853196025
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1691087138
Short name T2345
Test name
Test status
Simulation time 152560667 ps
CPU time 0.8 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206172 kb
Host smart-37313c0a-c273-4085-b541-8c83937718d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
87138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1691087138
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3464662447
Short name T1767
Test name
Test status
Simulation time 217885161 ps
CPU time 0.92 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206144 kb
Host smart-08038876-14d2-460e-8a17-3cc5f583747a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3464662447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3464662447
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3617894773
Short name T1600
Test name
Test status
Simulation time 148154851 ps
CPU time 0.77 seconds
Started Jul 04 06:09:14 PM PDT 24
Finished Jul 04 06:09:15 PM PDT 24
Peak memory 206168 kb
Host smart-03a89270-1284-4b76-b3ba-5fec49bb3bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
94773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3617894773
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1483989053
Short name T2195
Test name
Test status
Simulation time 43005908 ps
CPU time 0.66 seconds
Started Jul 04 06:09:11 PM PDT 24
Finished Jul 04 06:09:12 PM PDT 24
Peak memory 206180 kb
Host smart-ea7d6d49-6936-4053-a8bb-88868fe6ce45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14839
89053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1483989053
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2308627405
Short name T2304
Test name
Test status
Simulation time 175596789 ps
CPU time 0.83 seconds
Started Jul 04 06:09:18 PM PDT 24
Finished Jul 04 06:09:19 PM PDT 24
Peak memory 206160 kb
Host smart-192d2998-7e36-4e30-b846-1b31bdc9c87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
27405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2308627405
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2455973013
Short name T2381
Test name
Test status
Simulation time 214283535 ps
CPU time 0.87 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 206180 kb
Host smart-272eabe3-ae28-442f-ab12-1d08c555a97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
73013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2455973013
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2080864780
Short name T2521
Test name
Test status
Simulation time 172974662 ps
CPU time 0.85 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 206200 kb
Host smart-a7eaccd2-4693-416f-ab87-b2377d8918e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
64780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2080864780
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1128198361
Short name T995
Test name
Test status
Simulation time 164627258 ps
CPU time 0.76 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206188 kb
Host smart-673d4444-dc41-4008-b67c-3cbb0d4a96dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11281
98361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1128198361
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3813174117
Short name T1425
Test name
Test status
Simulation time 205161140 ps
CPU time 0.81 seconds
Started Jul 04 06:09:16 PM PDT 24
Finished Jul 04 06:09:17 PM PDT 24
Peak memory 206156 kb
Host smart-da48e8e5-8570-4347-8855-a4a61ab1a06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38131
74117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3813174117
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2596778872
Short name T2004
Test name
Test status
Simulation time 224796462 ps
CPU time 1.05 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206220 kb
Host smart-0f116383-9fa0-40a7-a37e-bb092e161695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25967
78872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2596778872
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.360498815
Short name T1603
Test name
Test status
Simulation time 6134157104 ps
CPU time 177.33 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206556 kb
Host smart-482c968b-5a57-4c4b-ab73-e2f0cff602bc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=360498815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.360498815
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3024006467
Short name T2293
Test name
Test status
Simulation time 180505770 ps
CPU time 0.86 seconds
Started Jul 04 06:09:12 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206176 kb
Host smart-4a01df5e-6d43-4469-958b-4475c1424533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
06467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3024006467
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4215335002
Short name T2625
Test name
Test status
Simulation time 170381407 ps
CPU time 0.76 seconds
Started Jul 04 06:09:10 PM PDT 24
Finished Jul 04 06:09:11 PM PDT 24
Peak memory 206180 kb
Host smart-b88e0570-f191-4867-848b-43258d51f9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
35002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4215335002
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.4242468135
Short name T329
Test name
Test status
Simulation time 284644311 ps
CPU time 0.99 seconds
Started Jul 04 06:09:10 PM PDT 24
Finished Jul 04 06:09:11 PM PDT 24
Peak memory 206176 kb
Host smart-3ba050d9-46bd-4373-b3a6-b3d65301a09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42424
68135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.4242468135
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3759522398
Short name T916
Test name
Test status
Simulation time 6529589256 ps
CPU time 46.04 seconds
Started Jul 04 06:09:13 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206432 kb
Host smart-a6be1345-c7ce-49ff-93a2-8a34d1444398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37595
22398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3759522398
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.953907454
Short name T1311
Test name
Test status
Simulation time 37992333 ps
CPU time 0.73 seconds
Started Jul 04 06:09:37 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 206244 kb
Host smart-d98b2ee9-d0ff-4101-b12f-e1a0d31ff6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=953907454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.953907454
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2902067420
Short name T1790
Test name
Test status
Simulation time 4085262532 ps
CPU time 4.8 seconds
Started Jul 04 06:09:18 PM PDT 24
Finished Jul 04 06:09:23 PM PDT 24
Peak memory 206524 kb
Host smart-c730f760-f5fe-4b0e-b7e4-b1d2f41f1f42
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2902067420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2902067420
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2627945990
Short name T2245
Test name
Test status
Simulation time 13321141801 ps
CPU time 12.02 seconds
Started Jul 04 06:09:22 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206428 kb
Host smart-56595f26-63fa-4363-b8ee-085714d71bcd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2627945990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2627945990
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3475129603
Short name T14
Test name
Test status
Simulation time 23371031163 ps
CPU time 23.51 seconds
Started Jul 04 06:09:25 PM PDT 24
Finished Jul 04 06:09:48 PM PDT 24
Peak memory 206276 kb
Host smart-58fc7c91-8915-487f-b2a2-431bdf06edb7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3475129603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3475129603
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1873822783
Short name T1811
Test name
Test status
Simulation time 182603002 ps
CPU time 0.82 seconds
Started Jul 04 06:09:17 PM PDT 24
Finished Jul 04 06:09:18 PM PDT 24
Peak memory 206196 kb
Host smart-a51ebf05-4e51-4562-b92f-1bfb8520e466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18738
22783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1873822783
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.634253527
Short name T836
Test name
Test status
Simulation time 168046628 ps
CPU time 0.78 seconds
Started Jul 04 06:09:24 PM PDT 24
Finished Jul 04 06:09:25 PM PDT 24
Peak memory 206204 kb
Host smart-03f1a4a3-5f33-432b-b31e-7f0c0a846591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63425
3527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.634253527
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1566641919
Short name T2552
Test name
Test status
Simulation time 420298302 ps
CPU time 1.37 seconds
Started Jul 04 06:09:18 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206144 kb
Host smart-7a141719-09b7-449b-bb28-b231d69e7d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15666
41919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1566641919
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.290866458
Short name T2033
Test name
Test status
Simulation time 1028203934 ps
CPU time 2.2 seconds
Started Jul 04 06:09:24 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206452 kb
Host smart-f12eb376-def0-4b0e-9e54-11821fef9da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
6458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.290866458
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3102629841
Short name T1914
Test name
Test status
Simulation time 10645333575 ps
CPU time 22.25 seconds
Started Jul 04 06:09:18 PM PDT 24
Finished Jul 04 06:09:41 PM PDT 24
Peak memory 206516 kb
Host smart-75f63cce-83e7-4a95-9c5c-38b01c762953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026
29841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3102629841
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1612076504
Short name T2541
Test name
Test status
Simulation time 383829692 ps
CPU time 1.24 seconds
Started Jul 04 06:09:18 PM PDT 24
Finished Jul 04 06:09:19 PM PDT 24
Peak memory 206192 kb
Host smart-598b68f5-6388-4921-aaa9-3b0aac570e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
76504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1612076504
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3825782717
Short name T556
Test name
Test status
Simulation time 153986757 ps
CPU time 0.88 seconds
Started Jul 04 06:09:22 PM PDT 24
Finished Jul 04 06:09:23 PM PDT 24
Peak memory 206172 kb
Host smart-9e5a1f2b-30e5-4184-8581-f363b0d5a69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38257
82717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3825782717
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1355373422
Short name T1094
Test name
Test status
Simulation time 60636748 ps
CPU time 0.68 seconds
Started Jul 04 06:09:25 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206180 kb
Host smart-57849398-b43e-49e7-9c97-bff706b8c925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13553
73422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1355373422
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1406664524
Short name T2025
Test name
Test status
Simulation time 910805856 ps
CPU time 2.02 seconds
Started Jul 04 06:09:18 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206396 kb
Host smart-a83d28e3-5113-4506-8d71-7d9f44efe74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
64524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1406664524
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1410631807
Short name T2098
Test name
Test status
Simulation time 161981232 ps
CPU time 1.44 seconds
Started Jul 04 06:09:17 PM PDT 24
Finished Jul 04 06:09:19 PM PDT 24
Peak memory 206460 kb
Host smart-f5707009-bca5-4628-8fb7-7bc1f269167e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14106
31807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1410631807
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1153006625
Short name T1877
Test name
Test status
Simulation time 195673369 ps
CPU time 0.94 seconds
Started Jul 04 06:09:24 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206188 kb
Host smart-bb765c86-6d8e-4d7c-b438-3d484f5d5a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11530
06625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1153006625
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.605154555
Short name T963
Test name
Test status
Simulation time 149413851 ps
CPU time 0.78 seconds
Started Jul 04 06:09:16 PM PDT 24
Finished Jul 04 06:09:17 PM PDT 24
Peak memory 206220 kb
Host smart-8d5e1360-fa5b-4e26-b606-fdff85cae634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60515
4555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.605154555
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2541381559
Short name T998
Test name
Test status
Simulation time 228134397 ps
CPU time 0.93 seconds
Started Jul 04 06:09:19 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206208 kb
Host smart-c7cee3ec-9aaa-40cc-a6f8-03ed8219eb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25413
81559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2541381559
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1929139517
Short name T1901
Test name
Test status
Simulation time 234007609 ps
CPU time 0.94 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206200 kb
Host smart-8539eec0-a56d-4f19-951e-07e92d2e92fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
39517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1929139517
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.860253479
Short name T1994
Test name
Test status
Simulation time 23297233197 ps
CPU time 22.48 seconds
Started Jul 04 06:09:26 PM PDT 24
Finished Jul 04 06:09:49 PM PDT 24
Peak memory 206204 kb
Host smart-fcb74935-d053-4f60-b3b7-0b87333372bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86025
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.860253479
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2377168029
Short name T2670
Test name
Test status
Simulation time 3335425878 ps
CPU time 4.33 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:31 PM PDT 24
Peak memory 206256 kb
Host smart-b2aca02f-7737-4b81-b277-6e8d8a571e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23771
68029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2377168029
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.742833327
Short name T1273
Test name
Test status
Simulation time 9250766342 ps
CPU time 93.58 seconds
Started Jul 04 06:09:26 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206536 kb
Host smart-289819c4-5652-4d6a-8353-6cdaaf804a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74283
3327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.742833327
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.760737240
Short name T1315
Test name
Test status
Simulation time 5019141646 ps
CPU time 135.43 seconds
Started Jul 04 06:09:25 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206444 kb
Host smart-4676fce3-ff2f-4b7b-8eb6-43e80c02b37f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=760737240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.760737240
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1191078751
Short name T2612
Test name
Test status
Simulation time 248274491 ps
CPU time 0.86 seconds
Started Jul 04 06:09:31 PM PDT 24
Finished Jul 04 06:09:32 PM PDT 24
Peak memory 206212 kb
Host smart-dedbdd8a-b8ef-4157-a928-2948f800ddff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1191078751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1191078751
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3566454437
Short name T2232
Test name
Test status
Simulation time 213200098 ps
CPU time 0.91 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206160 kb
Host smart-4f4047e8-a6f3-4884-a55f-eaadd1574e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35664
54437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3566454437
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.4114130431
Short name T634
Test name
Test status
Simulation time 3636006433 ps
CPU time 99.03 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:11:06 PM PDT 24
Peak memory 206448 kb
Host smart-aa9d6508-b233-4266-9006-df607e7ffb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41141
30431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.4114130431
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.748248626
Short name T493
Test name
Test status
Simulation time 4824542963 ps
CPU time 43.6 seconds
Started Jul 04 06:09:25 PM PDT 24
Finished Jul 04 06:10:09 PM PDT 24
Peak memory 206512 kb
Host smart-44e419ce-8f25-4552-9b3f-24075035d2a4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=748248626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.748248626
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.571204668
Short name T2360
Test name
Test status
Simulation time 154267340 ps
CPU time 0.82 seconds
Started Jul 04 06:09:25 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206128 kb
Host smart-5a61dcda-a581-4414-b343-4038bdd9ee32
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=571204668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.571204668
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1043722709
Short name T1523
Test name
Test status
Simulation time 149732455 ps
CPU time 0.87 seconds
Started Jul 04 06:09:26 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206216 kb
Host smart-05465401-404c-4b7c-82db-a1cbe7652f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
22709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1043722709
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1158796961
Short name T139
Test name
Test status
Simulation time 221644570 ps
CPU time 0.87 seconds
Started Jul 04 06:09:29 PM PDT 24
Finished Jul 04 06:09:30 PM PDT 24
Peak memory 206212 kb
Host smart-ac81ef53-571a-4974-97a8-ef41e65b660c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
96961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1158796961
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1948607359
Short name T1944
Test name
Test status
Simulation time 172985099 ps
CPU time 0.83 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206224 kb
Host smart-52c74a4b-34e4-4333-9840-2f189dfbd91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19486
07359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1948607359
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2486106074
Short name T417
Test name
Test status
Simulation time 201786985 ps
CPU time 0.85 seconds
Started Jul 04 06:09:26 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206236 kb
Host smart-d08aa1c8-f69e-436d-83bc-d54700f5a03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24861
06074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2486106074
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3804331782
Short name T1093
Test name
Test status
Simulation time 167064078 ps
CPU time 0.81 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:29 PM PDT 24
Peak memory 206172 kb
Host smart-851a8ee5-40c3-416c-9d65-75e72fb33ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38043
31782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3804331782
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2690773845
Short name T2213
Test name
Test status
Simulation time 215329567 ps
CPU time 0.81 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206192 kb
Host smart-868625f6-33d4-4cbf-b09e-402bd4d54c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907
73845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2690773845
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3901699772
Short name T2422
Test name
Test status
Simulation time 257145093 ps
CPU time 0.9 seconds
Started Jul 04 06:09:25 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206188 kb
Host smart-d43011c9-20f4-4098-b020-0a8cda496bc9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3901699772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3901699772
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3807557956
Short name T2562
Test name
Test status
Simulation time 161342535 ps
CPU time 0.85 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:29 PM PDT 24
Peak memory 206156 kb
Host smart-7389e483-248e-46e5-adb3-3767019c6f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38075
57956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3807557956
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2485935566
Short name T1277
Test name
Test status
Simulation time 46227098 ps
CPU time 0.7 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206184 kb
Host smart-22f0489a-76ca-414e-818a-d2f606321e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24859
35566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2485935566
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4053258222
Short name T269
Test name
Test status
Simulation time 15052764472 ps
CPU time 34.09 seconds
Started Jul 04 06:09:26 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206488 kb
Host smart-d779eb7c-7fb7-49e2-b949-c4b241ee6ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532
58222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4053258222
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1750092787
Short name T2130
Test name
Test status
Simulation time 229802493 ps
CPU time 0.84 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:29 PM PDT 24
Peak memory 206216 kb
Host smart-ca573f10-0a08-4ea5-8058-98890bad74c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
92787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1750092787
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2197572204
Short name T1203
Test name
Test status
Simulation time 161364782 ps
CPU time 0.89 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:29 PM PDT 24
Peak memory 206144 kb
Host smart-e65f8530-917d-40ff-b8b1-90f87c6e61ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21975
72204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2197572204
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.449918986
Short name T987
Test name
Test status
Simulation time 225721196 ps
CPU time 0.87 seconds
Started Jul 04 06:09:27 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 206200 kb
Host smart-ee288eeb-249c-42ee-9083-dbbcb37bb7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44991
8986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.449918986
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1784712762
Short name T1476
Test name
Test status
Simulation time 204169808 ps
CPU time 0.95 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206192 kb
Host smart-dfcb495f-3bfb-4e26-94b4-cc090dbb0658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847
12762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1784712762
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1989367227
Short name T2618
Test name
Test status
Simulation time 158203863 ps
CPU time 0.82 seconds
Started Jul 04 06:09:31 PM PDT 24
Finished Jul 04 06:09:32 PM PDT 24
Peak memory 206188 kb
Host smart-665006bb-6121-48f9-b22d-ca76babeb944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893
67227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1989367227
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.973969921
Short name T2387
Test name
Test status
Simulation time 172610197 ps
CPU time 0.79 seconds
Started Jul 04 06:09:32 PM PDT 24
Finished Jul 04 06:09:33 PM PDT 24
Peak memory 206140 kb
Host smart-618ef1ea-7994-48cc-8b41-718808937be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97396
9921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.973969921
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1874350756
Short name T536
Test name
Test status
Simulation time 200938044 ps
CPU time 0.88 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:35 PM PDT 24
Peak memory 206200 kb
Host smart-963b189f-dceb-4b9d-9e82-db6d0e49c29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18743
50756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1874350756
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1793668827
Short name T877
Test name
Test status
Simulation time 234219885 ps
CPU time 0.91 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206188 kb
Host smart-53ff0e5d-058b-4ea7-a20f-a2fe68326bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
68827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1793668827
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1486220497
Short name T1131
Test name
Test status
Simulation time 4311722862 ps
CPU time 34.35 seconds
Started Jul 04 06:09:32 PM PDT 24
Finished Jul 04 06:10:07 PM PDT 24
Peak memory 206444 kb
Host smart-95b37096-31ed-4f3c-a84d-2b2ed9b311c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1486220497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1486220497
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1958051114
Short name T1564
Test name
Test status
Simulation time 175261650 ps
CPU time 0.81 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:35 PM PDT 24
Peak memory 206192 kb
Host smart-af41030c-7eb6-45ec-b465-f7834f275451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
51114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1958051114
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2419617540
Short name T1225
Test name
Test status
Simulation time 187778891 ps
CPU time 0.83 seconds
Started Jul 04 06:09:35 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206196 kb
Host smart-81d29cde-a29c-41ba-a221-8315ab400457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24196
17540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2419617540
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.2772736670
Short name T2018
Test name
Test status
Simulation time 882736780 ps
CPU time 1.88 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:37 PM PDT 24
Peak memory 206344 kb
Host smart-a1516fe3-33ea-4625-988d-e6a3061aa4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27727
36670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.2772736670
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2217789319
Short name T1163
Test name
Test status
Simulation time 5015244501 ps
CPU time 48.71 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:10:22 PM PDT 24
Peak memory 206444 kb
Host smart-058b72b8-2b64-4d35-8504-61890777bfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22177
89319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2217789319
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.4102826934
Short name T621
Test name
Test status
Simulation time 63548856 ps
CPU time 0.67 seconds
Started Jul 04 06:09:50 PM PDT 24
Finished Jul 04 06:09:51 PM PDT 24
Peak memory 206256 kb
Host smart-f2f6b166-9d2c-47f6-a17d-6167442c88f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4102826934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.4102826934
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1469298304
Short name T1861
Test name
Test status
Simulation time 13354319122 ps
CPU time 14.59 seconds
Started Jul 04 06:09:36 PM PDT 24
Finished Jul 04 06:09:51 PM PDT 24
Peak memory 206424 kb
Host smart-2afae357-5248-440a-be47-673636e61f1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1469298304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1469298304
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2329742863
Short name T1817
Test name
Test status
Simulation time 23364854913 ps
CPU time 28.11 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:10:03 PM PDT 24
Peak memory 206460 kb
Host smart-d412096b-c802-4a6f-8a25-4355dda2fd9e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2329742863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2329742863
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.200285792
Short name T1663
Test name
Test status
Simulation time 180880772 ps
CPU time 0.81 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206188 kb
Host smart-f8214aab-0478-468c-b941-e4e6fe753bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
5792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.200285792
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.927396938
Short name T2570
Test name
Test status
Simulation time 146746478 ps
CPU time 0.74 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:35 PM PDT 24
Peak memory 206224 kb
Host smart-6aee53d1-1a43-4237-82ad-556814f7afc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92739
6938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.927396938
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3975437774
Short name T425
Test name
Test status
Simulation time 558905368 ps
CPU time 1.81 seconds
Started Jul 04 06:09:36 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 206360 kb
Host smart-09301f0e-91b5-4185-ba1c-f272f30fdac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
37774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3975437774
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3659216184
Short name T1826
Test name
Test status
Simulation time 17625391217 ps
CPU time 41.71 seconds
Started Jul 04 06:09:32 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206488 kb
Host smart-ff652d89-0208-45f7-b4e0-032cbd4f5c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36592
16184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3659216184
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2795833981
Short name T96
Test name
Test status
Simulation time 400565330 ps
CPU time 1.34 seconds
Started Jul 04 06:09:35 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206148 kb
Host smart-39bc74f6-8911-4089-a283-ac2a42b95b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27958
33981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2795833981
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2419420064
Short name T1295
Test name
Test status
Simulation time 155099481 ps
CPU time 0.75 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206204 kb
Host smart-f0a045ab-5ac4-4c7e-982a-b768858fe35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
20064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2419420064
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.148739195
Short name T2500
Test name
Test status
Simulation time 36934593 ps
CPU time 0.67 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206168 kb
Host smart-4e0a301a-df34-4559-8c4c-7ce8f534d184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14873
9195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.148739195
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1466249708
Short name T2580
Test name
Test status
Simulation time 1026195809 ps
CPU time 2.25 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206424 kb
Host smart-e2e7d246-3cfd-4c29-ba41-a8e967c2e3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14662
49708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1466249708
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1513725471
Short name T1526
Test name
Test status
Simulation time 165164003 ps
CPU time 1.41 seconds
Started Jul 04 06:09:37 PM PDT 24
Finished Jul 04 06:09:39 PM PDT 24
Peak memory 206400 kb
Host smart-f49b7334-d4e0-417d-bd65-2351d15a1793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
25471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1513725471
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3295186575
Short name T541
Test name
Test status
Simulation time 215410945 ps
CPU time 0.93 seconds
Started Jul 04 06:09:35 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206188 kb
Host smart-b10d77ca-a0d4-419f-8759-4b2a8be5da75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
86575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3295186575
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2601458349
Short name T542
Test name
Test status
Simulation time 152071821 ps
CPU time 0.77 seconds
Started Jul 04 06:09:37 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 206168 kb
Host smart-666a4c1f-7a02-469e-84ec-f035b719b209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26014
58349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2601458349
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2110042905
Short name T867
Test name
Test status
Simulation time 206504315 ps
CPU time 0.86 seconds
Started Jul 04 06:09:35 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206212 kb
Host smart-6e33c7a3-b1c9-43f5-91c7-3c307b77a638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21100
42905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2110042905
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.15248452
Short name T680
Test name
Test status
Simulation time 248890384 ps
CPU time 0.86 seconds
Started Jul 04 06:09:37 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 206172 kb
Host smart-72c61fdc-fd6b-49b5-a256-d2f06ef9c9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15248
452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.15248452
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1853708812
Short name T1561
Test name
Test status
Simulation time 23278547563 ps
CPU time 23.14 seconds
Started Jul 04 06:09:37 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206232 kb
Host smart-b6b2220d-8b66-4493-ae4f-88cb318528f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18537
08812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1853708812
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3284869113
Short name T798
Test name
Test status
Simulation time 3321840040 ps
CPU time 4.23 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:39 PM PDT 24
Peak memory 206272 kb
Host smart-69114015-9ff1-41e6-8b55-8733f4d5b6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
69113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3284869113
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1787236174
Short name T2091
Test name
Test status
Simulation time 8184323825 ps
CPU time 79.31 seconds
Started Jul 04 06:09:33 PM PDT 24
Finished Jul 04 06:10:52 PM PDT 24
Peak memory 206576 kb
Host smart-22f47b57-0765-497e-bb4b-5ffad735a6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17872
36174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1787236174
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.760242397
Short name T1316
Test name
Test status
Simulation time 3191057909 ps
CPU time 32.55 seconds
Started Jul 04 06:09:36 PM PDT 24
Finished Jul 04 06:10:09 PM PDT 24
Peak memory 206436 kb
Host smart-024ad1f7-8346-40d3-9812-74682acbb655
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=760242397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.760242397
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.596860915
Short name T1119
Test name
Test status
Simulation time 283005180 ps
CPU time 0.94 seconds
Started Jul 04 06:09:37 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 206212 kb
Host smart-0dd0d5d8-51f7-4519-95d3-7452f8fd1b7e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=596860915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.596860915
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1891097921
Short name T2274
Test name
Test status
Simulation time 222106624 ps
CPU time 0.89 seconds
Started Jul 04 06:09:34 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206172 kb
Host smart-907d1d47-32f5-4a37-81ac-33f380655826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18910
97921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1891097921
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2954012037
Short name T1053
Test name
Test status
Simulation time 5288779893 ps
CPU time 40.93 seconds
Started Jul 04 06:09:42 PM PDT 24
Finished Jul 04 06:10:24 PM PDT 24
Peak memory 206448 kb
Host smart-25ecd637-1a0b-4f2c-9b28-c9e88a3b5a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
12037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2954012037
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.362680135
Short name T464
Test name
Test status
Simulation time 4542454008 ps
CPU time 125.27 seconds
Started Jul 04 06:09:41 PM PDT 24
Finished Jul 04 06:11:47 PM PDT 24
Peak memory 206484 kb
Host smart-70248c3d-ba5f-4379-92ba-d4573e9b7e1a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=362680135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.362680135
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1006092113
Short name T334
Test name
Test status
Simulation time 158961741 ps
CPU time 0.77 seconds
Started Jul 04 06:09:41 PM PDT 24
Finished Jul 04 06:09:42 PM PDT 24
Peak memory 206204 kb
Host smart-2d2f5f21-7a6e-49d7-8657-285c982a5812
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1006092113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1006092113
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.336065488
Short name T2646
Test name
Test status
Simulation time 143262979 ps
CPU time 0.72 seconds
Started Jul 04 06:09:40 PM PDT 24
Finished Jul 04 06:09:41 PM PDT 24
Peak memory 206176 kb
Host smart-b81e6db5-5881-4a9b-b7ac-e7db9ec17650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33606
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.336065488
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.21611913
Short name T1052
Test name
Test status
Simulation time 196397134 ps
CPU time 0.89 seconds
Started Jul 04 06:09:41 PM PDT 24
Finished Jul 04 06:09:42 PM PDT 24
Peak memory 206140 kb
Host smart-d6ca76b4-e86f-4e58-b11b-a35aa37c72f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21611
913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.21611913
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.865565104
Short name T1928
Test name
Test status
Simulation time 179226923 ps
CPU time 0.83 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:40 PM PDT 24
Peak memory 206220 kb
Host smart-1ca9e276-53ba-4808-bd25-a8c99e8b4984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86556
5104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.865565104
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.670559594
Short name T690
Test name
Test status
Simulation time 203812297 ps
CPU time 0.87 seconds
Started Jul 04 06:09:41 PM PDT 24
Finished Jul 04 06:09:42 PM PDT 24
Peak memory 206228 kb
Host smart-0f6c9f26-71c3-4a7f-933a-b779a46e201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67055
9594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.670559594
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2735619853
Short name T2368
Test name
Test status
Simulation time 168908327 ps
CPU time 0.8 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:40 PM PDT 24
Peak memory 206192 kb
Host smart-d6b01e02-5061-4133-bc54-28ce9c58ba32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27356
19853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2735619853
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3820645512
Short name T899
Test name
Test status
Simulation time 232420540 ps
CPU time 0.92 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:40 PM PDT 24
Peak memory 206212 kb
Host smart-a303f3b6-9e8a-4152-8f26-e1e02b02a6bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3820645512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3820645512
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1516836826
Short name T698
Test name
Test status
Simulation time 137457754 ps
CPU time 0.74 seconds
Started Jul 04 06:09:42 PM PDT 24
Finished Jul 04 06:09:43 PM PDT 24
Peak memory 206192 kb
Host smart-b5e9b0c5-5745-4623-ac1c-4b986228b0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
36826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1516836826
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.556837649
Short name T1778
Test name
Test status
Simulation time 39223802 ps
CPU time 0.63 seconds
Started Jul 04 06:09:40 PM PDT 24
Finished Jul 04 06:09:41 PM PDT 24
Peak memory 206192 kb
Host smart-22f5a574-e218-44d2-945c-19073522e0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55683
7649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.556837649
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3640573246
Short name T2525
Test name
Test status
Simulation time 18217991685 ps
CPU time 37.72 seconds
Started Jul 04 06:09:41 PM PDT 24
Finished Jul 04 06:10:19 PM PDT 24
Peak memory 206552 kb
Host smart-3ffd933b-c698-4944-93ad-8be8fc6207d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405
73246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3640573246
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1031806009
Short name T2165
Test name
Test status
Simulation time 193593200 ps
CPU time 0.84 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:40 PM PDT 24
Peak memory 206176 kb
Host smart-901e4785-1f40-4d51-aabc-aacbc47ebf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10318
06009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1031806009
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3437048663
Short name T1262
Test name
Test status
Simulation time 265789033 ps
CPU time 0.96 seconds
Started Jul 04 06:09:40 PM PDT 24
Finished Jul 04 06:09:41 PM PDT 24
Peak memory 206172 kb
Host smart-70a2aa49-cc07-4318-a0ae-5a1bbb956c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34370
48663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3437048663
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.601394109
Short name T1836
Test name
Test status
Simulation time 302410304 ps
CPU time 0.92 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:41 PM PDT 24
Peak memory 206188 kb
Host smart-581c8ab0-f796-4d1e-a21a-bd60ab78c40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60139
4109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.601394109
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.992772201
Short name T1934
Test name
Test status
Simulation time 155177416 ps
CPU time 0.8 seconds
Started Jul 04 06:09:39 PM PDT 24
Finished Jul 04 06:09:40 PM PDT 24
Peak memory 206212 kb
Host smart-ac8d602d-eb05-47d8-b46b-b26b8a130d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99277
2201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.992772201
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.4091983596
Short name T2229
Test name
Test status
Simulation time 144275152 ps
CPU time 0.78 seconds
Started Jul 04 06:09:50 PM PDT 24
Finished Jul 04 06:09:51 PM PDT 24
Peak memory 206188 kb
Host smart-323c58b3-cf89-4c57-ba07-74b534df7330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40919
83596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.4091983596
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.265500745
Short name T1687
Test name
Test status
Simulation time 145515018 ps
CPU time 0.77 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:09:51 PM PDT 24
Peak memory 206204 kb
Host smart-dcf63756-14fb-4d09-9f1d-60ca69dde27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26550
0745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.265500745
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1965996508
Short name T2156
Test name
Test status
Simulation time 179292817 ps
CPU time 0.78 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:09:51 PM PDT 24
Peak memory 206204 kb
Host smart-baff74f5-4fad-4a9f-95af-a57144a4817b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659
96508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1965996508
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4041374711
Short name T2513
Test name
Test status
Simulation time 221573103 ps
CPU time 0.96 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:09:50 PM PDT 24
Peak memory 206208 kb
Host smart-5255c30e-9025-4d7d-a652-f82ba87dcbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40413
74711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4041374711
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1536902243
Short name T2318
Test name
Test status
Simulation time 6264726480 ps
CPU time 188.74 seconds
Started Jul 04 06:09:48 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 206524 kb
Host smart-8f1cdc2a-7d38-4530-8c22-4c9a50def07e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1536902243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1536902243
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2113652601
Short name T2323
Test name
Test status
Simulation time 140215615 ps
CPU time 0.76 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:09:50 PM PDT 24
Peak memory 206176 kb
Host smart-e759a3d3-83e5-4e66-bbc0-2002167ca180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21136
52601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2113652601
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3078067058
Short name T1920
Test name
Test status
Simulation time 155600113 ps
CPU time 0.73 seconds
Started Jul 04 06:09:51 PM PDT 24
Finished Jul 04 06:09:52 PM PDT 24
Peak memory 206156 kb
Host smart-f2d071ba-ae4f-4993-89ce-1d604f1abe43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30780
67058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3078067058
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.1511392673
Short name T676
Test name
Test status
Simulation time 196323451 ps
CPU time 0.9 seconds
Started Jul 04 06:09:50 PM PDT 24
Finished Jul 04 06:09:52 PM PDT 24
Peak memory 206172 kb
Host smart-4f6d9122-1f52-47e8-a109-ec3b748bfc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15113
92673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1511392673
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3306704734
Short name T1216
Test name
Test status
Simulation time 5361975715 ps
CPU time 37.17 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206472 kb
Host smart-dc25a6b3-a16d-4632-a21a-4b9dc21b6e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
04734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3306704734
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3047452575
Short name T1486
Test name
Test status
Simulation time 35578145 ps
CPU time 0.7 seconds
Started Jul 04 06:10:00 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206224 kb
Host smart-23865024-acb5-4f9b-8ef2-eda8b005b3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3047452575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3047452575
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3545732548
Short name T642
Test name
Test status
Simulation time 3986207351 ps
CPU time 5.19 seconds
Started Jul 04 06:09:50 PM PDT 24
Finished Jul 04 06:09:56 PM PDT 24
Peak memory 206484 kb
Host smart-8db77e0f-9b83-499e-9121-6d22a828b87f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3545732548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3545732548
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2648657086
Short name T685
Test name
Test status
Simulation time 13332285907 ps
CPU time 12.05 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:10:02 PM PDT 24
Peak memory 206288 kb
Host smart-7af1f793-a7c6-40c3-b1fd-beb8a477c970
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2648657086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2648657086
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1332423301
Short name T1314
Test name
Test status
Simulation time 23365459801 ps
CPU time 22.52 seconds
Started Jul 04 06:09:49 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 206528 kb
Host smart-8e61b87d-cb50-4cba-97c3-3644d6d6e64c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1332423301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1332423301
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.668724041
Short name T385
Test name
Test status
Simulation time 161321649 ps
CPU time 0.8 seconds
Started Jul 04 06:09:48 PM PDT 24
Finished Jul 04 06:09:50 PM PDT 24
Peak memory 206180 kb
Host smart-7dad6159-9267-4d7b-b119-76392518438a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66872
4041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.668724041
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2115964070
Short name T1323
Test name
Test status
Simulation time 150883359 ps
CPU time 0.78 seconds
Started Jul 04 06:09:50 PM PDT 24
Finished Jul 04 06:09:51 PM PDT 24
Peak memory 206196 kb
Host smart-d882fa41-7fb6-4bc3-b2f6-8143adaa0f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21159
64070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2115964070
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2135434341
Short name T1842
Test name
Test status
Simulation time 284100927 ps
CPU time 1.07 seconds
Started Jul 04 06:09:51 PM PDT 24
Finished Jul 04 06:09:52 PM PDT 24
Peak memory 206192 kb
Host smart-a245e417-b805-448c-9411-929acfba0c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21354
34341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2135434341
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3289990885
Short name T1066
Test name
Test status
Simulation time 22354873801 ps
CPU time 43.19 seconds
Started Jul 04 06:09:56 PM PDT 24
Finished Jul 04 06:10:39 PM PDT 24
Peak memory 206528 kb
Host smart-70e89e7e-3add-403b-a526-7ca644529185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32899
90885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3289990885
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2608903992
Short name T581
Test name
Test status
Simulation time 447979931 ps
CPU time 1.31 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:09:58 PM PDT 24
Peak memory 206148 kb
Host smart-afb9445e-7637-463e-ad5b-5fc6567a1255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26089
03992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2608903992
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.25295649
Short name T2264
Test name
Test status
Simulation time 146031336 ps
CPU time 0.79 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206176 kb
Host smart-c170477a-2ac4-428b-a41d-7505f4ef604e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25295
649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.25295649
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.191450168
Short name T1158
Test name
Test status
Simulation time 40255542 ps
CPU time 0.68 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206180 kb
Host smart-ec981af0-c193-487b-aa8f-a2fcd7a8b0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19145
0168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.191450168
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.636705491
Short name T1951
Test name
Test status
Simulation time 884039301 ps
CPU time 2.25 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:02 PM PDT 24
Peak memory 206360 kb
Host smart-f80cf9bd-0239-4be0-868f-b2595f03eef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63670
5491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.636705491
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.481797294
Short name T741
Test name
Test status
Simulation time 209444382 ps
CPU time 1.47 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206452 kb
Host smart-3f424d62-15c3-483d-b46a-bca6ee74fb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48179
7294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.481797294
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3758714146
Short name T2374
Test name
Test status
Simulation time 263557736 ps
CPU time 0.93 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:09:58 PM PDT 24
Peak memory 206212 kb
Host smart-c7b5039a-69f2-4508-a80d-c6c78f6b0799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
14146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3758714146
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1561290106
Short name T549
Test name
Test status
Simulation time 165673763 ps
CPU time 0.79 seconds
Started Jul 04 06:10:00 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206192 kb
Host smart-3d94e4df-3c70-4233-b722-66be0f04c295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15612
90106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1561290106
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3825743277
Short name T1633
Test name
Test status
Simulation time 245979482 ps
CPU time 0.92 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206208 kb
Host smart-b232b50f-5850-4ccb-bf60-af32d10d2583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38257
43277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3825743277
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.826663463
Short name T1136
Test name
Test status
Simulation time 9298240064 ps
CPU time 74.45 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206536 kb
Host smart-08534b1d-9a79-4006-91f9-ffe185b0764b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=826663463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.826663463
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.680654371
Short name T1009
Test name
Test status
Simulation time 230428710 ps
CPU time 0.9 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206140 kb
Host smart-b80e98d3-47eb-43ec-a094-5030c110fa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68065
4371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.680654371
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1975626400
Short name T2701
Test name
Test status
Simulation time 23299242334 ps
CPU time 22.06 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:10:19 PM PDT 24
Peak memory 206288 kb
Host smart-433c899d-c2c4-4de6-808c-2881a8291255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19756
26400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1975626400
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.980846473
Short name T2257
Test name
Test status
Simulation time 3280077670 ps
CPU time 4.59 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:04 PM PDT 24
Peak memory 206232 kb
Host smart-34c33b82-2ceb-4ac7-8018-0aeea3833237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98084
6473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.980846473
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2078097270
Short name T1878
Test name
Test status
Simulation time 12165888476 ps
CPU time 358.68 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:15:57 PM PDT 24
Peak memory 206544 kb
Host smart-31febbc2-0f63-4c91-a718-d5295f3ff0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20780
97270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2078097270
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.228560867
Short name T2014
Test name
Test status
Simulation time 5079812719 ps
CPU time 141.75 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206528 kb
Host smart-546ae6ba-7a6a-469a-b7e6-82dba50f41f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=228560867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.228560867
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1666515538
Short name T1776
Test name
Test status
Simulation time 243398714 ps
CPU time 0.99 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:09:58 PM PDT 24
Peak memory 206192 kb
Host smart-ba85848e-47bd-4a67-9b76-66033cfa38a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1666515538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1666515538
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.794341446
Short name T1406
Test name
Test status
Simulation time 215335188 ps
CPU time 0.87 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206172 kb
Host smart-a66bef00-7f27-45fe-a841-b6879e55f974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79434
1446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.794341446
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3673662066
Short name T5
Test name
Test status
Simulation time 3785454837 ps
CPU time 25.99 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206456 kb
Host smart-80e55e9d-0d46-43e5-98e3-c602bbdada40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36736
62066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3673662066
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1951037284
Short name T1656
Test name
Test status
Simulation time 4236879560 ps
CPU time 115.85 seconds
Started Jul 04 06:10:00 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206484 kb
Host smart-316a6380-5611-4178-882f-891ecec0d6a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1951037284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1951037284
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1488714713
Short name T2599
Test name
Test status
Simulation time 165408597 ps
CPU time 0.82 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206216 kb
Host smart-090298b6-863e-49b2-8c14-72cabb1b792c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1488714713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1488714713
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.355400132
Short name T452
Test name
Test status
Simulation time 154189494 ps
CPU time 0.78 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206176 kb
Host smart-366d60bc-10b3-450b-af6b-51f3f95fa463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35540
0132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.355400132
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.272850157
Short name T2272
Test name
Test status
Simulation time 220655610 ps
CPU time 0.93 seconds
Started Jul 04 06:10:01 PM PDT 24
Finished Jul 04 06:10:02 PM PDT 24
Peak memory 206124 kb
Host smart-ae222d74-5b25-4ec2-ac7a-de5157311ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
0157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.272850157
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1661530786
Short name T1955
Test name
Test status
Simulation time 175780844 ps
CPU time 0.82 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206212 kb
Host smart-30375da6-f2dc-4316-a7c5-6414bd28f424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16615
30786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1661530786
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.898881026
Short name T1167
Test name
Test status
Simulation time 219932011 ps
CPU time 0.87 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206192 kb
Host smart-91df0412-3fb2-4094-9a46-d292cc239547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89888
1026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.898881026
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1792928566
Short name T2568
Test name
Test status
Simulation time 221306098 ps
CPU time 0.87 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206196 kb
Host smart-cd99501d-b233-4958-8fa2-eb08f51fbc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17929
28566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1792928566
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3274834508
Short name T2566
Test name
Test status
Simulation time 152427005 ps
CPU time 0.82 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206124 kb
Host smart-5490ab32-5ca7-4be9-ae00-49ecb5f4d2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32748
34508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3274834508
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.1188093387
Short name T220
Test name
Test status
Simulation time 271379866 ps
CPU time 1.05 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206228 kb
Host smart-fa59981e-5cb8-4c96-9c81-5e642a89d1ce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1188093387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.1188093387
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.673433451
Short name T950
Test name
Test status
Simulation time 173675558 ps
CPU time 0.81 seconds
Started Jul 04 06:10:02 PM PDT 24
Finished Jul 04 06:10:03 PM PDT 24
Peak memory 206196 kb
Host smart-5f204e3b-a12c-4322-afe8-ee1ebb24d9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67343
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.673433451
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.688891525
Short name T1556
Test name
Test status
Simulation time 39853660 ps
CPU time 0.66 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206204 kb
Host smart-e97b065c-1d33-4716-8f05-6c84d362d707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68889
1525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.688891525
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2918254535
Short name T150
Test name
Test status
Simulation time 6525557788 ps
CPU time 14.32 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:10:11 PM PDT 24
Peak memory 206544 kb
Host smart-fa7e3771-c06f-4e8b-bb74-34e5dd3f764f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
54535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2918254535
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1992379773
Short name T856
Test name
Test status
Simulation time 234471474 ps
CPU time 0.97 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206228 kb
Host smart-c41a1d6b-f748-42d1-bed3-82e1d26586bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19923
79773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1992379773
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1346507191
Short name T930
Test name
Test status
Simulation time 262220216 ps
CPU time 0.98 seconds
Started Jul 04 06:10:02 PM PDT 24
Finished Jul 04 06:10:03 PM PDT 24
Peak memory 206124 kb
Host smart-614ab5a3-4e21-41f0-acda-12b6a5c2fc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13465
07191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1346507191
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.320396291
Short name T1614
Test name
Test status
Simulation time 196897557 ps
CPU time 0.9 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206224 kb
Host smart-b48c649f-8a02-4646-8c0c-1387e75b9c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32039
6291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.320396291
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.359295373
Short name T1970
Test name
Test status
Simulation time 152223838 ps
CPU time 0.84 seconds
Started Jul 04 06:10:01 PM PDT 24
Finished Jul 04 06:10:02 PM PDT 24
Peak memory 206212 kb
Host smart-886ac914-d59a-46a8-9c37-a51404c26308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
5373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.359295373
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3289110522
Short name T1275
Test name
Test status
Simulation time 201970036 ps
CPU time 0.88 seconds
Started Jul 04 06:10:01 PM PDT 24
Finished Jul 04 06:10:02 PM PDT 24
Peak memory 206124 kb
Host smart-e0d85e3a-eb8c-4623-b7aa-bd1e55a5dd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32891
10522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3289110522
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2200396463
Short name T891
Test name
Test status
Simulation time 152151023 ps
CPU time 0.8 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:00 PM PDT 24
Peak memory 206212 kb
Host smart-b693d88e-179c-4230-b559-1a13124c0b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
96463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2200396463
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2133043283
Short name T2215
Test name
Test status
Simulation time 162143961 ps
CPU time 0.81 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:09:58 PM PDT 24
Peak memory 206212 kb
Host smart-e46517a0-65de-477d-8654-93a7c5074983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21330
43283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2133043283
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3977157898
Short name T1250
Test name
Test status
Simulation time 256328476 ps
CPU time 1 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206220 kb
Host smart-c291be35-ac97-4498-9e6a-5ab0ab4fc199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39771
57898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3977157898
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.831579716
Short name T2472
Test name
Test status
Simulation time 5664992226 ps
CPU time 39.69 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:10:38 PM PDT 24
Peak memory 206436 kb
Host smart-456e3078-a088-4469-880b-092b48b5b219
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=831579716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.831579716
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1616615849
Short name T379
Test name
Test status
Simulation time 223171089 ps
CPU time 0.86 seconds
Started Jul 04 06:10:00 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206180 kb
Host smart-136eccf4-7481-4d2a-bf83-e082596dac64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16166
15849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1616615849
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.580751123
Short name T1047
Test name
Test status
Simulation time 192654641 ps
CPU time 0.83 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:09:59 PM PDT 24
Peak memory 206136 kb
Host smart-88a61348-37e0-4bb7-8855-d8db16dd0238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58075
1123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.580751123
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1879744583
Short name T983
Test name
Test status
Simulation time 1136224641 ps
CPU time 2.33 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206440 kb
Host smart-d9c5f8bf-bdde-488d-bebc-978dbbd1795a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
44583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1879744583
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2718401263
Short name T1205
Test name
Test status
Simulation time 6405702323 ps
CPU time 180.43 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:12:58 PM PDT 24
Peak memory 206448 kb
Host smart-877d5f4b-cf75-46a2-9bbb-b11a4171aa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184
01263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2718401263
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1291635052
Short name T563
Test name
Test status
Simulation time 49006748 ps
CPU time 0.68 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206284 kb
Host smart-4d11993c-2ed2-4e08-8f5a-ca8553d898cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1291635052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1291635052
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3112668747
Short name T522
Test name
Test status
Simulation time 4045128165 ps
CPU time 4.79 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:10:03 PM PDT 24
Peak memory 206240 kb
Host smart-67dbf34e-cde0-4746-afad-8c33a84885a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3112668747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3112668747
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2734119315
Short name T1607
Test name
Test status
Simulation time 13521026746 ps
CPU time 13.23 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:10:11 PM PDT 24
Peak memory 206520 kb
Host smart-3d61a2eb-ec87-47cd-b4e6-4912e3b891da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2734119315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2734119315
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.23793475
Short name T1676
Test name
Test status
Simulation time 23336191616 ps
CPU time 23.21 seconds
Started Jul 04 06:09:58 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206512 kb
Host smart-eb994f35-6271-4afc-9b39-09cbc09146c3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=23793475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.23793475
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2238032633
Short name T2295
Test name
Test status
Simulation time 221954874 ps
CPU time 0.87 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206196 kb
Host smart-ae92b430-e6b4-423a-bea8-8969f851cce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
32633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2238032633
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3724343959
Short name T1159
Test name
Test status
Simulation time 161875482 ps
CPU time 0.81 seconds
Started Jul 04 06:09:59 PM PDT 24
Finished Jul 04 06:10:01 PM PDT 24
Peak memory 206208 kb
Host smart-afeb0d98-48b6-4db0-956b-5dbc11c8629b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37243
43959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3724343959
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1388885298
Short name T1560
Test name
Test status
Simulation time 451462753 ps
CPU time 1.41 seconds
Started Jul 04 06:09:57 PM PDT 24
Finished Jul 04 06:09:58 PM PDT 24
Peak memory 206212 kb
Host smart-16fe6dac-4e44-4f5c-bf66-c45e634f5b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
85298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1388885298
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3592933027
Short name T2236
Test name
Test status
Simulation time 1448233047 ps
CPU time 3.04 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:10:08 PM PDT 24
Peak memory 206444 kb
Host smart-096ee56a-bac2-4e04-9d49-d54187f1b463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
33027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3592933027
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.447705623
Short name T1504
Test name
Test status
Simulation time 21151424762 ps
CPU time 45.33 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:10:49 PM PDT 24
Peak memory 206488 kb
Host smart-3027e022-1ae1-4a1e-bcdc-e05812291a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44770
5623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.447705623
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1135020963
Short name T462
Test name
Test status
Simulation time 394210529 ps
CPU time 1.27 seconds
Started Jul 04 06:10:05 PM PDT 24
Finished Jul 04 06:10:07 PM PDT 24
Peak memory 206216 kb
Host smart-99266969-85c2-4cc3-b276-f3a0bcfc80ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11350
20963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1135020963
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3122587302
Short name T846
Test name
Test status
Simulation time 154125135 ps
CPU time 0.78 seconds
Started Jul 04 06:10:09 PM PDT 24
Finished Jul 04 06:10:10 PM PDT 24
Peak memory 206216 kb
Host smart-fc5598fd-45aa-49b8-8e08-e6fc3774e522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31225
87302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3122587302
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1822625703
Short name T1532
Test name
Test status
Simulation time 34950977 ps
CPU time 0.67 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:10:05 PM PDT 24
Peak memory 206152 kb
Host smart-4b88e865-8372-4397-b4de-aa0bf6f9c0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18226
25703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1822625703
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3352596881
Short name T1027
Test name
Test status
Simulation time 216351165 ps
CPU time 1.53 seconds
Started Jul 04 06:10:08 PM PDT 24
Finished Jul 04 06:10:09 PM PDT 24
Peak memory 206420 kb
Host smart-ad5eab74-ae95-41a5-821d-ef818e5ecf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33525
96881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3352596881
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.189486389
Short name T558
Test name
Test status
Simulation time 175215892 ps
CPU time 0.82 seconds
Started Jul 04 06:10:03 PM PDT 24
Finished Jul 04 06:10:04 PM PDT 24
Peak memory 206192 kb
Host smart-939bac28-cc82-4236-ab88-a05ce6e55afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18948
6389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.189486389
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1344123813
Short name T449
Test name
Test status
Simulation time 199224067 ps
CPU time 0.79 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:10:05 PM PDT 24
Peak memory 206412 kb
Host smart-b9d852fa-5754-40d0-bdaf-a3ba7d5d48c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
23813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1344123813
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1552720203
Short name T1740
Test name
Test status
Simulation time 224387130 ps
CPU time 0.95 seconds
Started Jul 04 06:10:02 PM PDT 24
Finished Jul 04 06:10:03 PM PDT 24
Peak memory 206124 kb
Host smart-e5b48926-4869-4efd-bad3-efb905cebcb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15527
20203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1552720203
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.2243537353
Short name T2663
Test name
Test status
Simulation time 8891145619 ps
CPU time 231.13 seconds
Started Jul 04 06:10:06 PM PDT 24
Finished Jul 04 06:13:57 PM PDT 24
Peak memory 206572 kb
Host smart-6e891dc4-fe8d-416f-bcdf-46d9a63278b7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2243537353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2243537353
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.144157808
Short name T2655
Test name
Test status
Simulation time 235137114 ps
CPU time 0.89 seconds
Started Jul 04 06:10:06 PM PDT 24
Finished Jul 04 06:10:07 PM PDT 24
Peak memory 206220 kb
Host smart-f58b63cf-1ed4-4086-b87a-1e4d75b96cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14415
7808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.144157808
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3740426914
Short name T1435
Test name
Test status
Simulation time 23363246679 ps
CPU time 22.9 seconds
Started Jul 04 06:10:09 PM PDT 24
Finished Jul 04 06:10:32 PM PDT 24
Peak memory 206276 kb
Host smart-98f60455-3f6d-43ac-9589-0afcd2946053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37404
26914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3740426914
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.4032070714
Short name T2085
Test name
Test status
Simulation time 3320809896 ps
CPU time 3.54 seconds
Started Jul 04 06:10:08 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 204452 kb
Host smart-486539f6-acd6-4722-882d-2a6d66c8aefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40320
70714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.4032070714
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2689458257
Short name T1420
Test name
Test status
Simulation time 11445032017 ps
CPU time 112.95 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:11:57 PM PDT 24
Peak memory 206556 kb
Host smart-bf8fb8d1-dafb-4978-8c12-f34f20c1572a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
58257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2689458257
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1173549673
Short name T1448
Test name
Test status
Simulation time 5536718201 ps
CPU time 41.2 seconds
Started Jul 04 06:10:08 PM PDT 24
Finished Jul 04 06:10:50 PM PDT 24
Peak memory 204960 kb
Host smart-055c557d-7bb5-4b9e-9614-601bd57d7e0e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1173549673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1173549673
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3498754312
Short name T1067
Test name
Test status
Simulation time 273964675 ps
CPU time 0.9 seconds
Started Jul 04 06:10:03 PM PDT 24
Finished Jul 04 06:10:04 PM PDT 24
Peak memory 206196 kb
Host smart-e66c5730-cd97-4044-aaca-df691112c969
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3498754312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3498754312
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.549473385
Short name T1140
Test name
Test status
Simulation time 208860683 ps
CPU time 0.84 seconds
Started Jul 04 06:10:01 PM PDT 24
Finished Jul 04 06:10:02 PM PDT 24
Peak memory 206180 kb
Host smart-c26f4332-00e4-4ea4-8f59-c983d94567e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54947
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.549473385
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2143765731
Short name T2559
Test name
Test status
Simulation time 5110340305 ps
CPU time 143.15 seconds
Started Jul 04 06:10:07 PM PDT 24
Finished Jul 04 06:12:30 PM PDT 24
Peak memory 206468 kb
Host smart-a4bcb63e-8aa9-4457-8d31-7723eaa17116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21437
65731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2143765731
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2970198833
Short name T1412
Test name
Test status
Simulation time 3938402358 ps
CPU time 108.27 seconds
Started Jul 04 06:10:03 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206460 kb
Host smart-d761aba0-5000-454e-bb16-12a00dad6c4e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2970198833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2970198833
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.4017639020
Short name T408
Test name
Test status
Simulation time 159439421 ps
CPU time 0.8 seconds
Started Jul 04 06:10:04 PM PDT 24
Finished Jul 04 06:10:05 PM PDT 24
Peak memory 206216 kb
Host smart-8f75a629-51ee-4245-ae8e-d04f386a826e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4017639020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.4017639020
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.202790715
Short name T847
Test name
Test status
Simulation time 152106272 ps
CPU time 0.78 seconds
Started Jul 04 06:10:06 PM PDT 24
Finished Jul 04 06:10:07 PM PDT 24
Peak memory 206168 kb
Host smart-dc3325c9-9e2d-4d45-8ced-e9d84349bafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20279
0715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.202790715
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.248740065
Short name T1759
Test name
Test status
Simulation time 152799998 ps
CPU time 0.8 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 206192 kb
Host smart-a137b6a9-2dee-49f5-91c1-269e708321be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
0065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.248740065
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3355998657
Short name T108
Test name
Test status
Simulation time 175815538 ps
CPU time 0.85 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206236 kb
Host smart-dfa2f13b-5c31-43ba-8c11-c804263fd0f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33559
98657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3355998657
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1693554227
Short name T2517
Test name
Test status
Simulation time 174595703 ps
CPU time 0.83 seconds
Started Jul 04 06:10:11 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 206180 kb
Host smart-454177a3-397f-4274-ac94-8c88ff57c2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16935
54227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1693554227
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2913963969
Short name T773
Test name
Test status
Simulation time 152976778 ps
CPU time 0.85 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:13 PM PDT 24
Peak memory 206176 kb
Host smart-14845727-5785-4ed0-bb8e-f3d9da0ee973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29139
63969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2913963969
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1957633448
Short name T1326
Test name
Test status
Simulation time 197000190 ps
CPU time 0.89 seconds
Started Jul 04 06:10:16 PM PDT 24
Finished Jul 04 06:10:17 PM PDT 24
Peak memory 206220 kb
Host smart-c9144527-6605-4b4d-9b51-164a7f22236d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1957633448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1957633448
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1149355323
Short name T932
Test name
Test status
Simulation time 172138142 ps
CPU time 0.78 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206156 kb
Host smart-df0b3597-2abb-4e73-8548-938f97c7baaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11493
55323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1149355323
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2761981477
Short name T38
Test name
Test status
Simulation time 39897984 ps
CPU time 0.68 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 206160 kb
Host smart-b033976b-005e-4ee3-9b73-4d7f3a392c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619
81477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2761981477
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3992400203
Short name T1684
Test name
Test status
Simulation time 20248288867 ps
CPU time 43.65 seconds
Started Jul 04 06:10:11 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206476 kb
Host smart-6ba50b43-5e91-4e95-8923-ed4089768ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39924
00203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3992400203
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1143144860
Short name T2533
Test name
Test status
Simulation time 177701745 ps
CPU time 0.84 seconds
Started Jul 04 06:10:14 PM PDT 24
Finished Jul 04 06:10:15 PM PDT 24
Peak memory 206188 kb
Host smart-fbd85eb4-1fab-4db0-84c6-b8908118f119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11431
44860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1143144860
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.203057938
Short name T978
Test name
Test status
Simulation time 185054552 ps
CPU time 0.82 seconds
Started Jul 04 06:10:10 PM PDT 24
Finished Jul 04 06:10:11 PM PDT 24
Peak memory 206172 kb
Host smart-a7daf343-2aef-4a49-91d6-3e85d6d78f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20305
7938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.203057938
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.668274248
Short name T1879
Test name
Test status
Simulation time 160565953 ps
CPU time 0.79 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:13 PM PDT 24
Peak memory 206168 kb
Host smart-1c9b16b0-a809-4723-b866-09231260c445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66827
4248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.668274248
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.213767291
Short name T1363
Test name
Test status
Simulation time 171198151 ps
CPU time 0.84 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206212 kb
Host smart-a4afbecb-8003-4fa8-9b4e-0dc08b775e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
7291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.213767291
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2200619471
Short name T1045
Test name
Test status
Simulation time 211708480 ps
CPU time 0.8 seconds
Started Jul 04 06:10:14 PM PDT 24
Finished Jul 04 06:10:15 PM PDT 24
Peak memory 206160 kb
Host smart-6fd8a063-fde1-45aa-89e9-edee0ef811a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
19471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2200619471
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2007694744
Short name T1940
Test name
Test status
Simulation time 168038812 ps
CPU time 0.77 seconds
Started Jul 04 06:10:11 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 206168 kb
Host smart-f9369a5b-5b2d-48c8-a0e3-ea30d5041d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076
94744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2007694744
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.4029708032
Short name T1546
Test name
Test status
Simulation time 154349754 ps
CPU time 0.79 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206208 kb
Host smart-912d4fd1-3c75-405f-8ced-e3cbfe374c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40297
08032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.4029708032
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4024982269
Short name T2103
Test name
Test status
Simulation time 219821505 ps
CPU time 0.93 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206224 kb
Host smart-28ff9116-56b8-4855-a4f4-3ad33756ef51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40249
82269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4024982269
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.332131009
Short name T350
Test name
Test status
Simulation time 4803738526 ps
CPU time 46.96 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206432 kb
Host smart-fb3a1c80-ce8b-41c5-93bf-9e8fcaf2f7d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=332131009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.332131009
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.583664423
Short name T885
Test name
Test status
Simulation time 157895700 ps
CPU time 0.8 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206188 kb
Host smart-638a21b8-08ee-4b4e-954c-a1800ee56528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58366
4423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.583664423
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1642019975
Short name T1089
Test name
Test status
Simulation time 161325225 ps
CPU time 0.82 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:13 PM PDT 24
Peak memory 206172 kb
Host smart-276fb449-1dff-4b6e-a429-5cee97a9a861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420
19975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1642019975
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1063225947
Short name T2565
Test name
Test status
Simulation time 816978063 ps
CPU time 1.97 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206440 kb
Host smart-c457298a-e521-4a95-9529-c172e9e279e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10632
25947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1063225947
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2095137720
Short name T1377
Test name
Test status
Simulation time 6401817995 ps
CPU time 184.99 seconds
Started Jul 04 06:10:14 PM PDT 24
Finished Jul 04 06:13:19 PM PDT 24
Peak memory 206512 kb
Host smart-2ac891d1-04b1-470d-ac69-bd360be423d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951
37720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2095137720
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3732438778
Short name T1090
Test name
Test status
Simulation time 80101802 ps
CPU time 0.74 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206228 kb
Host smart-95b0ffa9-5912-4556-ad03-98292ee9271e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3732438778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3732438778
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2099610362
Short name T1144
Test name
Test status
Simulation time 3632857517 ps
CPU time 4.79 seconds
Started Jul 04 06:10:16 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206472 kb
Host smart-63d00404-f3ef-4492-9439-f2bd2131159b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2099610362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2099610362
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1293833870
Short name T552
Test name
Test status
Simulation time 13419576311 ps
CPU time 12.58 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:25 PM PDT 24
Peak memory 206452 kb
Host smart-de0b8c6b-94f9-4f48-bd0e-571ffcfdfcb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1293833870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1293833870
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1089246217
Short name T16
Test name
Test status
Simulation time 23337531961 ps
CPU time 25.13 seconds
Started Jul 04 06:10:16 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206284 kb
Host smart-2fc6f474-f29e-49bc-9abe-70725b771149
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1089246217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1089246217
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.873384450
Short name T787
Test name
Test status
Simulation time 168729937 ps
CPU time 0.83 seconds
Started Jul 04 06:10:14 PM PDT 24
Finished Jul 04 06:10:15 PM PDT 24
Peak memory 206124 kb
Host smart-75ea5f08-7bd3-4c6d-ba3e-5083619c9148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87338
4450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.873384450
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1984685430
Short name T1780
Test name
Test status
Simulation time 153724046 ps
CPU time 0.78 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:13 PM PDT 24
Peak memory 206196 kb
Host smart-567086b7-8f3b-4841-abfe-2f394138f84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846
85430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1984685430
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2588267534
Short name T60
Test name
Test status
Simulation time 541884629 ps
CPU time 1.57 seconds
Started Jul 04 06:10:13 PM PDT 24
Finished Jul 04 06:10:15 PM PDT 24
Peak memory 206452 kb
Host smart-dc57bce6-26f7-4e3c-9f1f-ca0377c9702f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25882
67534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2588267534
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3592497761
Short name T2488
Test name
Test status
Simulation time 17160945727 ps
CPU time 31.87 seconds
Started Jul 04 06:10:10 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206468 kb
Host smart-e70bdcb3-3d30-4eea-aee2-652332797a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
97761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3592497761
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.903184963
Short name T1820
Test name
Test status
Simulation time 507738598 ps
CPU time 1.47 seconds
Started Jul 04 06:10:12 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 206124 kb
Host smart-22c39a1f-57b1-4869-9543-54b9bc55b1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90318
4963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.903184963
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.629238001
Short name T570
Test name
Test status
Simulation time 141269826 ps
CPU time 0.77 seconds
Started Jul 04 06:10:11 PM PDT 24
Finished Jul 04 06:10:12 PM PDT 24
Peak memory 206204 kb
Host smart-a4ed7ecd-56b2-477a-93a5-189a461a4579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62923
8001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.629238001
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3416105563
Short name T919
Test name
Test status
Simulation time 72875216 ps
CPU time 0.69 seconds
Started Jul 04 06:10:22 PM PDT 24
Finished Jul 04 06:10:22 PM PDT 24
Peak memory 206188 kb
Host smart-936ced05-19cf-4741-984f-b262f3050c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34161
05563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3416105563
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.114353304
Short name T2544
Test name
Test status
Simulation time 858852617 ps
CPU time 2.09 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206440 kb
Host smart-aa6a2934-4519-4d53-a96e-bda4db34ec3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
3304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.114353304
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1332126042
Short name T1786
Test name
Test status
Simulation time 213874204 ps
CPU time 1.36 seconds
Started Jul 04 06:10:23 PM PDT 24
Finished Jul 04 06:10:25 PM PDT 24
Peak memory 206360 kb
Host smart-0c4c00c8-a5af-4f53-ae28-1d0923d1e4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13321
26042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1332126042
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.8729316
Short name T1280
Test name
Test status
Simulation time 168855229 ps
CPU time 0.8 seconds
Started Jul 04 06:10:18 PM PDT 24
Finished Jul 04 06:10:19 PM PDT 24
Peak memory 206176 kb
Host smart-8013ef2c-2982-4423-bf85-a5c7ef39b462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87293
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.8729316
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3756110857
Short name T1821
Test name
Test status
Simulation time 153381048 ps
CPU time 0.8 seconds
Started Jul 04 06:10:20 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206172 kb
Host smart-9ba38543-6029-4ef7-9c01-870bb14bad47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37561
10857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3756110857
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.904305838
Short name T2688
Test name
Test status
Simulation time 166655292 ps
CPU time 0.83 seconds
Started Jul 04 06:10:22 PM PDT 24
Finished Jul 04 06:10:23 PM PDT 24
Peak memory 206148 kb
Host smart-0f0ece02-bc31-46a6-998b-29e787b8e405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90430
5838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.904305838
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1409990370
Short name T1360
Test name
Test status
Simulation time 205695359 ps
CPU time 0.92 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:20 PM PDT 24
Peak memory 206180 kb
Host smart-0ec00e9d-c81e-4c79-afe4-aa207f931b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14099
90370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1409990370
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2667096986
Short name T2538
Test name
Test status
Simulation time 23294567297 ps
CPU time 22.5 seconds
Started Jul 04 06:10:22 PM PDT 24
Finished Jul 04 06:10:45 PM PDT 24
Peak memory 206220 kb
Host smart-a3c9486e-79ba-4c67-87d8-843d3655d1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
96986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2667096986
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1710171471
Short name T1226
Test name
Test status
Simulation time 3297406678 ps
CPU time 4.04 seconds
Started Jul 04 06:10:21 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206276 kb
Host smart-93069cc0-2934-4c48-bd7f-9990d50bb9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
71471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1710171471
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2692372314
Short name T1519
Test name
Test status
Simulation time 7105239436 ps
CPU time 204.94 seconds
Started Jul 04 06:10:24 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206544 kb
Host smart-36d54799-93cf-467b-923d-86a22e4b8c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
72314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2692372314
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2058798532
Short name T2429
Test name
Test status
Simulation time 5512647026 ps
CPU time 153.27 seconds
Started Jul 04 06:10:21 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206464 kb
Host smart-6098de28-c022-43ef-a178-6f99115b530c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2058798532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2058798532
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.221986521
Short name T2176
Test name
Test status
Simulation time 241540442 ps
CPU time 0.95 seconds
Started Jul 04 06:10:20 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206176 kb
Host smart-431ee749-4d50-476a-a0b1-90ac13bf610f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=221986521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.221986521
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.220796690
Short name T2255
Test name
Test status
Simulation time 191090437 ps
CPU time 0.84 seconds
Started Jul 04 06:10:18 PM PDT 24
Finished Jul 04 06:10:19 PM PDT 24
Peak memory 206192 kb
Host smart-fae4ad1e-cf9c-4724-88dd-de96ddf018af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22079
6690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.220796690
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3141263051
Short name T559
Test name
Test status
Simulation time 3736105682 ps
CPU time 33.03 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:52 PM PDT 24
Peak memory 206448 kb
Host smart-bafa9ff8-cd2d-4665-bcf4-2a2f8632bd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31412
63051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3141263051
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3271084337
Short name T1734
Test name
Test status
Simulation time 3596039162 ps
CPU time 26.78 seconds
Started Jul 04 06:10:18 PM PDT 24
Finished Jul 04 06:10:45 PM PDT 24
Peak memory 206460 kb
Host smart-2c960bbf-db67-48e2-b3b6-ed3435dd89ee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3271084337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3271084337
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1880930779
Short name T1794
Test name
Test status
Simulation time 147856386 ps
CPU time 0.81 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:20 PM PDT 24
Peak memory 206224 kb
Host smart-a6cbddd8-9277-492d-bfb0-629a98f77be9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1880930779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1880930779
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2990832848
Short name T2059
Test name
Test status
Simulation time 155786388 ps
CPU time 0.78 seconds
Started Jul 04 06:10:20 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206168 kb
Host smart-4125a39b-b6cd-46ba-ac5a-2a83be3ff75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
32848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2990832848
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.79178711
Short name T749
Test name
Test status
Simulation time 167999092 ps
CPU time 0.87 seconds
Started Jul 04 06:10:23 PM PDT 24
Finished Jul 04 06:10:24 PM PDT 24
Peak memory 206172 kb
Host smart-8a07aaba-3fd7-4d49-aae3-bccef518abcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79178
711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.79178711
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.113331555
Short name T444
Test name
Test status
Simulation time 213453215 ps
CPU time 0.9 seconds
Started Jul 04 06:10:20 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206208 kb
Host smart-c56033bc-7d47-492a-987c-b7f894416204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11333
1555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.113331555
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2563759319
Short name T2439
Test name
Test status
Simulation time 184034586 ps
CPU time 0.81 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206200 kb
Host smart-1a4bf246-7ac3-4e92-a955-ad2e223a73e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25637
59319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2563759319
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1284488231
Short name T1003
Test name
Test status
Simulation time 152298034 ps
CPU time 0.83 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206120 kb
Host smart-4f4362ab-a1f8-4d3c-8a55-0c90fded1a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
88231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1284488231
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2665397465
Short name T1535
Test name
Test status
Simulation time 206372166 ps
CPU time 0.89 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:20 PM PDT 24
Peak memory 206180 kb
Host smart-2db7ab59-f866-4d07-9426-495e2500e17b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2665397465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2665397465
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.176284963
Short name T2246
Test name
Test status
Simulation time 156309480 ps
CPU time 0.8 seconds
Started Jul 04 06:10:22 PM PDT 24
Finished Jul 04 06:10:23 PM PDT 24
Peak memory 206160 kb
Host smart-e5354e3e-a23c-44f9-b883-0e1e5c75b229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
4963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.176284963
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2117131743
Short name T2523
Test name
Test status
Simulation time 70676719 ps
CPU time 0.67 seconds
Started Jul 04 06:10:20 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206196 kb
Host smart-e52e4082-5897-4109-9106-b3f161f00d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21171
31743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2117131743
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2341146614
Short name T2235
Test name
Test status
Simulation time 15416023319 ps
CPU time 34.44 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206504 kb
Host smart-b4cae95b-d412-44e0-8251-191af6658ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
46614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2341146614
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2951739366
Short name T2349
Test name
Test status
Simulation time 198571781 ps
CPU time 0.85 seconds
Started Jul 04 06:10:23 PM PDT 24
Finished Jul 04 06:10:24 PM PDT 24
Peak memory 206212 kb
Host smart-34f21d6f-31cf-4aae-8287-12acaf584259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29517
39366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2951739366
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.4139576644
Short name T1815
Test name
Test status
Simulation time 279877638 ps
CPU time 0.99 seconds
Started Jul 04 06:10:23 PM PDT 24
Finished Jul 04 06:10:25 PM PDT 24
Peak memory 206172 kb
Host smart-d0f8c2ad-196d-41f3-8706-f5bf0813a8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41395
76644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.4139576644
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.654293176
Short name T921
Test name
Test status
Simulation time 160245182 ps
CPU time 0.81 seconds
Started Jul 04 06:10:23 PM PDT 24
Finished Jul 04 06:10:24 PM PDT 24
Peak memory 206212 kb
Host smart-da4ea69d-82cf-4adc-a52c-27b1307da49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65429
3176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.654293176
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.4116685887
Short name T382
Test name
Test status
Simulation time 201222983 ps
CPU time 0.82 seconds
Started Jul 04 06:10:20 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206200 kb
Host smart-d6a580f6-c8bb-4958-a11a-65f7533ca7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41166
85887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.4116685887
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.300359008
Short name T2461
Test name
Test status
Simulation time 206579624 ps
CPU time 0.81 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:19 PM PDT 24
Peak memory 206140 kb
Host smart-c881bfe4-85cc-4e30-b58f-f956f01e045a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035
9008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.300359008
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1203280088
Short name T23
Test name
Test status
Simulation time 151362607 ps
CPU time 0.79 seconds
Started Jul 04 06:10:19 PM PDT 24
Finished Jul 04 06:10:21 PM PDT 24
Peak memory 206140 kb
Host smart-bdd60829-c7f0-43fa-b83c-983fc57c58fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
80088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1203280088
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.278070234
Short name T456
Test name
Test status
Simulation time 183702331 ps
CPU time 0.82 seconds
Started Jul 04 06:10:26 PM PDT 24
Finished Jul 04 06:10:27 PM PDT 24
Peak memory 206192 kb
Host smart-ca1c0f5a-9353-43a0-876a-99691a065c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27807
0234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.278070234
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2187472437
Short name T2040
Test name
Test status
Simulation time 207745523 ps
CPU time 0.93 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:27 PM PDT 24
Peak memory 206200 kb
Host smart-b1873649-390d-4fea-b865-2efa3249fd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21874
72437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2187472437
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2514004510
Short name T2141
Test name
Test status
Simulation time 6357342235 ps
CPU time 177.28 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:13:22 PM PDT 24
Peak memory 206512 kb
Host smart-8697a696-e7b5-4baf-9746-12a8941c9bd6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2514004510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2514004510
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.4076868697
Short name T745
Test name
Test status
Simulation time 158014402 ps
CPU time 0.79 seconds
Started Jul 04 06:10:28 PM PDT 24
Finished Jul 04 06:10:29 PM PDT 24
Peak memory 206208 kb
Host smart-27f1a6ff-d667-4de0-8eaa-46d632111ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40768
68697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.4076868697
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.248322111
Short name T1129
Test name
Test status
Simulation time 194213933 ps
CPU time 0.87 seconds
Started Jul 04 06:10:29 PM PDT 24
Finished Jul 04 06:10:30 PM PDT 24
Peak memory 206208 kb
Host smart-b9520879-f8bc-4fcf-83ce-34e2c4b0cd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24832
2111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.248322111
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1891317626
Short name T628
Test name
Test status
Simulation time 768734384 ps
CPU time 2.07 seconds
Started Jul 04 06:10:29 PM PDT 24
Finished Jul 04 06:10:31 PM PDT 24
Peak memory 206456 kb
Host smart-19714edd-2cc0-46e2-a910-25cdf9b9431b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18913
17626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1891317626
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1805273507
Short name T1399
Test name
Test status
Simulation time 5036071807 ps
CPU time 47.48 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206512 kb
Host smart-0c2db3e6-e6a2-4ccf-8df2-22084cc9488a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18052
73507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1805273507
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1085329912
Short name T2480
Test name
Test status
Simulation time 92258225 ps
CPU time 0.74 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206236 kb
Host smart-1dfa4725-daca-48e2-8c47-d3df0cc57d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1085329912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1085329912
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3590006054
Short name T1948
Test name
Test status
Simulation time 3989945621 ps
CPU time 4.69 seconds
Started Jul 04 06:10:26 PM PDT 24
Finished Jul 04 06:10:31 PM PDT 24
Peak memory 206500 kb
Host smart-455434d4-d514-4c73-985a-03baaf7b9b63
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3590006054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3590006054
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.244907312
Short name T2536
Test name
Test status
Simulation time 13339132686 ps
CPU time 13.07 seconds
Started Jul 04 06:10:29 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206280 kb
Host smart-4558205a-785a-4a1b-bb4c-2a2a8facf914
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=244907312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.244907312
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1717528676
Short name T243
Test name
Test status
Simulation time 23421023541 ps
CPU time 30.07 seconds
Started Jul 04 06:10:23 PM PDT 24
Finished Jul 04 06:10:53 PM PDT 24
Peak memory 206528 kb
Host smart-e92d7283-3449-4451-9912-44ab6fb67381
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1717528676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.1717528676
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.836134314
Short name T869
Test name
Test status
Simulation time 168840857 ps
CPU time 0.83 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206200 kb
Host smart-69b6f98a-4b78-45cc-bd66-44b48634c385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83613
4314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.836134314
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1477937186
Short name T2367
Test name
Test status
Simulation time 166484961 ps
CPU time 0.84 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206204 kb
Host smart-190b6e31-2111-4fcd-a7c3-dff26c42f03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14779
37186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1477937186
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.4243796355
Short name T2291
Test name
Test status
Simulation time 458960993 ps
CPU time 1.41 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:27 PM PDT 24
Peak memory 206204 kb
Host smart-0096c12a-6dce-46fd-8d51-c6e630e757ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42437
96355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.4243796355
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.8488545
Short name T2167
Test name
Test status
Simulation time 1230420332 ps
CPU time 2.65 seconds
Started Jul 04 06:10:26 PM PDT 24
Finished Jul 04 06:10:29 PM PDT 24
Peak memory 206420 kb
Host smart-69a8f0f7-b82c-400c-acf1-79c681f14d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84885
45 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.8488545
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3053741415
Short name T729
Test name
Test status
Simulation time 22411139651 ps
CPU time 47.48 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206464 kb
Host smart-aaa9f897-7414-465b-bb72-96d291900598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537
41415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3053741415
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.2754053856
Short name T434
Test name
Test status
Simulation time 511483204 ps
CPU time 1.48 seconds
Started Jul 04 06:10:27 PM PDT 24
Finished Jul 04 06:10:29 PM PDT 24
Peak memory 206192 kb
Host smart-6581266d-ca6b-41b4-b566-0cb95a0329a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27540
53856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.2754053856
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.847441143
Short name T756
Test name
Test status
Simulation time 162708790 ps
CPU time 0.81 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:27 PM PDT 24
Peak memory 206164 kb
Host smart-afc1dddc-d021-4d02-b223-7254e331b498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84744
1143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.847441143
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2719737507
Short name T966
Test name
Test status
Simulation time 56066384 ps
CPU time 0.64 seconds
Started Jul 04 06:10:25 PM PDT 24
Finished Jul 04 06:10:26 PM PDT 24
Peak memory 206184 kb
Host smart-aa113004-afdc-4ca1-9ebd-5643e26c6a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27197
37507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2719737507
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.370869254
Short name T1305
Test name
Test status
Simulation time 1051699584 ps
CPU time 2.29 seconds
Started Jul 04 06:10:33 PM PDT 24
Finished Jul 04 06:10:35 PM PDT 24
Peak memory 206332 kb
Host smart-1196320c-ab5a-449b-8d1e-e8904660c5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37086
9254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.370869254
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4170224437
Short name T201
Test name
Test status
Simulation time 148526602 ps
CPU time 1.29 seconds
Started Jul 04 06:10:33 PM PDT 24
Finished Jul 04 06:10:35 PM PDT 24
Peak memory 206384 kb
Host smart-73a7155b-ff87-4260-94ab-17eb52e15502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41702
24437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4170224437
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1436890594
Short name T2333
Test name
Test status
Simulation time 173746591 ps
CPU time 0.84 seconds
Started Jul 04 06:10:32 PM PDT 24
Finished Jul 04 06:10:33 PM PDT 24
Peak memory 206204 kb
Host smart-9dc02009-534d-417c-9e3c-2ed405c8cf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14368
90594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1436890594
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2655347193
Short name T18
Test name
Test status
Simulation time 145355602 ps
CPU time 0.72 seconds
Started Jul 04 06:10:33 PM PDT 24
Finished Jul 04 06:10:34 PM PDT 24
Peak memory 206192 kb
Host smart-3640b6f1-9a1f-48a6-8b85-623289c70814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26553
47193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2655347193
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1288591985
Short name T524
Test name
Test status
Simulation time 254086840 ps
CPU time 0.93 seconds
Started Jul 04 06:10:31 PM PDT 24
Finished Jul 04 06:10:32 PM PDT 24
Peak memory 206208 kb
Host smart-7f53f03c-3d6c-4876-bf48-92c90a5a9c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12885
91985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1288591985
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2527481254
Short name T734
Test name
Test status
Simulation time 8204143770 ps
CPU time 72.13 seconds
Started Jul 04 06:10:32 PM PDT 24
Finished Jul 04 06:11:45 PM PDT 24
Peak memory 206524 kb
Host smart-8e3ed1bb-df50-4373-95d1-20123ba983dc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2527481254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2527481254
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2815012992
Short name T707
Test name
Test status
Simulation time 203004773 ps
CPU time 0.92 seconds
Started Jul 04 06:10:33 PM PDT 24
Finished Jul 04 06:10:35 PM PDT 24
Peak memory 206196 kb
Host smart-467d11f1-9617-4089-9bf6-af4189d32242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
12992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2815012992
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.4082239620
Short name T1653
Test name
Test status
Simulation time 23307858576 ps
CPU time 22.59 seconds
Started Jul 04 06:10:33 PM PDT 24
Finished Jul 04 06:10:56 PM PDT 24
Peak memory 206272 kb
Host smart-524bf618-71a3-465b-8d93-5ecd11848b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40822
39620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.4082239620
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3617065751
Short name T2409
Test name
Test status
Simulation time 3294381234 ps
CPU time 3.67 seconds
Started Jul 04 06:10:35 PM PDT 24
Finished Jul 04 06:10:39 PM PDT 24
Peak memory 206260 kb
Host smart-524679e0-2328-42d9-adde-6ec38184f37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36170
65751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3617065751
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.248483187
Short name T527
Test name
Test status
Simulation time 8933750436 ps
CPU time 65.92 seconds
Started Jul 04 06:10:34 PM PDT 24
Finished Jul 04 06:11:40 PM PDT 24
Peak memory 206472 kb
Host smart-7fc1e6b1-582e-4048-b5bc-4d471a3326cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
3187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.248483187
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3998715465
Short name T571
Test name
Test status
Simulation time 4806890260 ps
CPU time 33.35 seconds
Started Jul 04 06:10:32 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206448 kb
Host smart-c1ca3233-5649-4c93-ae34-cf8e3cce2d1e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3998715465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3998715465
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1086321316
Short name T2600
Test name
Test status
Simulation time 236068086 ps
CPU time 0.9 seconds
Started Jul 04 06:10:35 PM PDT 24
Finished Jul 04 06:10:36 PM PDT 24
Peak memory 206156 kb
Host smart-93f1ede8-8ccc-4346-972e-fd1713d4ecd1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1086321316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1086321316
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2697384635
Short name T393
Test name
Test status
Simulation time 225622321 ps
CPU time 0.91 seconds
Started Jul 04 06:10:35 PM PDT 24
Finished Jul 04 06:10:36 PM PDT 24
Peak memory 206172 kb
Host smart-cbc532d7-869d-44af-b33c-c8d8cd8cb724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26973
84635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2697384635
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.4166115497
Short name T2602
Test name
Test status
Simulation time 2878705606 ps
CPU time 79.33 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:12:04 PM PDT 24
Peak memory 206428 kb
Host smart-218b1739-9cb3-4984-8841-c60a6b58812d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
15497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.4166115497
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2639300811
Short name T1490
Test name
Test status
Simulation time 5862231417 ps
CPU time 57.57 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:11:39 PM PDT 24
Peak memory 206464 kb
Host smart-f71dfb8c-842a-493b-af0c-b9f3e7a8e78b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2639300811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2639300811
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.235747109
Short name T640
Test name
Test status
Simulation time 162182307 ps
CPU time 0.86 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:45 PM PDT 24
Peak memory 206164 kb
Host smart-250a5bfe-5fe0-4126-85b9-8e2e9c0679bc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=235747109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.235747109
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3068970356
Short name T1265
Test name
Test status
Simulation time 144094864 ps
CPU time 0.76 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206184 kb
Host smart-4278d6ce-adc3-4058-b133-12c6eb5ee5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30689
70356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3068970356
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3149074849
Short name T100
Test name
Test status
Simulation time 217019966 ps
CPU time 0.9 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206192 kb
Host smart-73671548-7e60-4f0b-9577-29c29473e423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31490
74849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3149074849
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2706906624
Short name T1015
Test name
Test status
Simulation time 186948643 ps
CPU time 0.85 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206164 kb
Host smart-fb79794c-dfd3-4ce4-8822-8869796dd26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
06624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2706906624
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1273726964
Short name T461
Test name
Test status
Simulation time 156508544 ps
CPU time 0.81 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206208 kb
Host smart-c2ffa563-8e8d-4e29-a129-5309aa6459d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
26964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1273726964
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.651332868
Short name T762
Test name
Test status
Simulation time 145249374 ps
CPU time 0.85 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206188 kb
Host smart-5341b9a3-a0d6-4536-ab2c-13edf4e092dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65133
2868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.651332868
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2197021228
Short name T1984
Test name
Test status
Simulation time 198945303 ps
CPU time 0.85 seconds
Started Jul 04 06:10:37 PM PDT 24
Finished Jul 04 06:10:38 PM PDT 24
Peak memory 206184 kb
Host smart-2b10d47f-91b7-4090-8351-5a34b998e340
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2197021228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2197021228
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1551429520
Short name T2613
Test name
Test status
Simulation time 139535069 ps
CPU time 0.75 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206144 kb
Host smart-3b428fae-409d-47e2-ac9c-335e8f66c62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
29520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1551429520
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1101288204
Short name T26
Test name
Test status
Simulation time 31865093 ps
CPU time 0.63 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:45 PM PDT 24
Peak memory 206204 kb
Host smart-74150199-57f5-4fb8-b2ef-a5f74bfdd171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11012
88204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1101288204
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2681034851
Short name T957
Test name
Test status
Simulation time 15661550873 ps
CPU time 36.92 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:11:16 PM PDT 24
Peak memory 206520 kb
Host smart-9f36aee6-52dc-4650-9940-8e1fee5ef445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26810
34851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2681034851
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3320758803
Short name T1589
Test name
Test status
Simulation time 206755951 ps
CPU time 0.88 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206180 kb
Host smart-c3723609-03e1-40df-8bc0-a9a4ac88ba42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33207
58803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3320758803
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.4135735305
Short name T2301
Test name
Test status
Simulation time 238014598 ps
CPU time 0.94 seconds
Started Jul 04 06:10:38 PM PDT 24
Finished Jul 04 06:10:39 PM PDT 24
Peak memory 206212 kb
Host smart-298e77ef-1947-4aaf-aaaf-1007150bf541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
35305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.4135735305
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.849186274
Short name T1080
Test name
Test status
Simulation time 230309140 ps
CPU time 0.9 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206148 kb
Host smart-3c63da1c-4548-461e-9b03-ba23025094df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84918
6274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.849186274
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.443178927
Short name T1145
Test name
Test status
Simulation time 229824011 ps
CPU time 0.91 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206236 kb
Host smart-3f0b3cc3-3f8d-4552-845d-03dfca8009bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44317
8927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.443178927
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4279957329
Short name T1801
Test name
Test status
Simulation time 172557769 ps
CPU time 0.75 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206192 kb
Host smart-05a7ed23-3259-4001-8058-af95b7518d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
57329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4279957329
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.385966339
Short name T1130
Test name
Test status
Simulation time 157800800 ps
CPU time 0.78 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206168 kb
Host smart-d5e4746d-5643-41d2-b114-f033542c277f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596
6339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.385966339
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2770876719
Short name T526
Test name
Test status
Simulation time 171469191 ps
CPU time 0.8 seconds
Started Jul 04 06:10:38 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206136 kb
Host smart-91108029-8bdc-4279-ba90-4cae3bfec8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708
76719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2770876719
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.797216432
Short name T2453
Test name
Test status
Simulation time 196099639 ps
CPU time 0.87 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206212 kb
Host smart-9b95a706-f07d-44a0-b820-ac93678b4ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79721
6432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.797216432
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1246082256
Short name T1383
Test name
Test status
Simulation time 5934370376 ps
CPU time 170.82 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:13:37 PM PDT 24
Peak memory 206472 kb
Host smart-39e5b945-c4c8-4852-947e-890ad2373979
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1246082256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1246082256
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1940824496
Short name T2239
Test name
Test status
Simulation time 167212282 ps
CPU time 0.78 seconds
Started Jul 04 06:10:38 PM PDT 24
Finished Jul 04 06:10:39 PM PDT 24
Peak memory 206180 kb
Host smart-42bb2689-f05d-49cb-bee7-727422368f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19408
24496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1940824496
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3131266376
Short name T850
Test name
Test status
Simulation time 153373917 ps
CPU time 0.78 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206212 kb
Host smart-3d6b7ba0-822f-4f5e-af75-73827ddebfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31312
66376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3131266376
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.321880053
Short name T1046
Test name
Test status
Simulation time 728323818 ps
CPU time 1.61 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206388 kb
Host smart-0fe2f6e4-4025-49c3-91fe-8ab179b446fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188
0053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.321880053
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2915041625
Short name T952
Test name
Test status
Simulation time 6340931462 ps
CPU time 184.23 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:13:44 PM PDT 24
Peak memory 206448 kb
Host smart-86f4f0af-92cd-4608-93d2-e946f0fa3bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29150
41625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2915041625
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.468011275
Short name T2077
Test name
Test status
Simulation time 46037580 ps
CPU time 0.67 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:10:53 PM PDT 24
Peak memory 206272 kb
Host smart-ec93df2e-092a-4592-b380-ffd000347f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=468011275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.468011275
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2851090079
Short name T457
Test name
Test status
Simulation time 4518574058 ps
CPU time 6.28 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206432 kb
Host smart-6aa7fc1a-9ead-415d-8c7c-ffca44547182
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2851090079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2851090079
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.4033111432
Short name T1594
Test name
Test status
Simulation time 13424923105 ps
CPU time 14.37 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:55 PM PDT 24
Peak memory 206152 kb
Host smart-203bec33-960d-4438-90fc-42d81819bef8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4033111432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.4033111432
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3512420484
Short name T9
Test name
Test status
Simulation time 23325517110 ps
CPU time 27.58 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:11:07 PM PDT 24
Peak memory 206292 kb
Host smart-4c02a7e9-5a61-4632-91d9-432f650b1fcb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3512420484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3512420484
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.477447210
Short name T364
Test name
Test status
Simulation time 214014580 ps
CPU time 0.83 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206124 kb
Host smart-b10dd8a6-b898-47e9-839c-0d79e8c3effe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47744
7210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.477447210
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2239189160
Short name T2311
Test name
Test status
Simulation time 156229583 ps
CPU time 0.8 seconds
Started Jul 04 06:10:41 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206196 kb
Host smart-02d7861a-f330-4e58-9639-19d8378bc051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22391
89160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2239189160
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2981908499
Short name T1007
Test name
Test status
Simulation time 306801944 ps
CPU time 1.12 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206212 kb
Host smart-c129d708-3c19-412f-8735-e2b977817fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819
08499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2981908499
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1897330248
Short name T1545
Test name
Test status
Simulation time 1424543662 ps
CPU time 3.26 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:48 PM PDT 24
Peak memory 206408 kb
Host smart-cdb7a1bf-5bf6-454e-8cc9-042edfd038fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18973
30248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1897330248
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2112410098
Short name T173
Test name
Test status
Simulation time 8798280658 ps
CPU time 18.79 seconds
Started Jul 04 06:10:41 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206452 kb
Host smart-2f023e66-03c9-47ef-975e-f99f033b6283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
10098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2112410098
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2977230383
Short name T2614
Test name
Test status
Simulation time 410331389 ps
CPU time 1.36 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206176 kb
Host smart-6890705f-7ecb-435b-9ed0-70c0825d6a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29772
30383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2977230383
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2614096890
Short name T1753
Test name
Test status
Simulation time 149964848 ps
CPU time 0.75 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206176 kb
Host smart-ee34b712-fdc4-40df-b32c-227b5ae154e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140
96890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2614096890
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1144835558
Short name T1303
Test name
Test status
Simulation time 55466404 ps
CPU time 0.73 seconds
Started Jul 04 06:10:41 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206192 kb
Host smart-eaefe779-dbd1-4cd6-ba8c-e23778375ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
35558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1144835558
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2236493195
Short name T1987
Test name
Test status
Simulation time 851198915 ps
CPU time 2.42 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:43 PM PDT 24
Peak memory 206360 kb
Host smart-995684b2-7ef9-4186-a41c-816ef689131f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22364
93195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2236493195
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3972898249
Short name T1487
Test name
Test status
Simulation time 224070332 ps
CPU time 1.68 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:43 PM PDT 24
Peak memory 206432 kb
Host smart-8b815549-79f4-4666-8b6e-8c89d2479bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728
98249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3972898249
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.180451488
Short name T761
Test name
Test status
Simulation time 152648622 ps
CPU time 0.82 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 205992 kb
Host smart-555fbd7c-8891-4ee9-a4eb-bf528a1832a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
1488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.180451488
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3571119357
Short name T1471
Test name
Test status
Simulation time 145614195 ps
CPU time 0.73 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206204 kb
Host smart-5e78ef8b-8d81-4b5f-87a3-a9ed893c794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35711
19357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3571119357
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3056768476
Short name T625
Test name
Test status
Simulation time 226458765 ps
CPU time 0.88 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:10:42 PM PDT 24
Peak memory 206052 kb
Host smart-43a6ae27-7fc1-4b76-b3db-f074f5454dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
68476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3056768476
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.719457459
Short name T2316
Test name
Test status
Simulation time 149034069 ps
CPU time 0.8 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206204 kb
Host smart-d562f5ad-5fe2-4c7f-b29f-f21f9e8c4bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71945
7459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.719457459
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2088926314
Short name T1590
Test name
Test status
Simulation time 23322442547 ps
CPU time 23 seconds
Started Jul 04 06:10:38 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206276 kb
Host smart-67fe5ffe-ea36-41ce-b8eb-fe45a4166fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20889
26314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2088926314
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1921501392
Short name T1274
Test name
Test status
Simulation time 3305246129 ps
CPU time 3.98 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:49 PM PDT 24
Peak memory 206276 kb
Host smart-4aa15a49-6329-4012-8614-bf8b90b5496c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
01392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1921501392
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.4077409489
Short name T1104
Test name
Test status
Simulation time 8772857970 ps
CPU time 60.51 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206512 kb
Host smart-f9bf18f8-09be-4d08-996a-e4bacd6a6a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
09489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.4077409489
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3346854831
Short name T1213
Test name
Test status
Simulation time 7328031870 ps
CPU time 53.55 seconds
Started Jul 04 06:10:40 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206476 kb
Host smart-661279aa-f9b1-43a6-833e-c9670c5fd311
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3346854831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3346854831
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3347035472
Short name T1155
Test name
Test status
Simulation time 234317168 ps
CPU time 1 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206028 kb
Host smart-135ed908-9420-4c1f-b57b-94ed88288fb6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3347035472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3347035472
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2905586026
Short name T376
Test name
Test status
Simulation time 258811988 ps
CPU time 0.88 seconds
Started Jul 04 06:10:39 PM PDT 24
Finished Jul 04 06:10:40 PM PDT 24
Peak memory 206164 kb
Host smart-8f79b67d-8f4a-4455-8bd7-876f9f7c63fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
86026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2905586026
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2359831379
Short name T1882
Test name
Test status
Simulation time 2992468017 ps
CPU time 27.97 seconds
Started Jul 04 06:10:41 PM PDT 24
Finished Jul 04 06:11:09 PM PDT 24
Peak memory 206484 kb
Host smart-1305b940-432b-46a1-850d-5c8b6ffa9e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
31379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2359831379
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2241709309
Short name T1386
Test name
Test status
Simulation time 7082584398 ps
CPU time 197.06 seconds
Started Jul 04 06:10:42 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206452 kb
Host smart-3ca3b8b4-db69-4e98-80bc-473c0e1f627a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2241709309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2241709309
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2298908492
Short name T889
Test name
Test status
Simulation time 159039760 ps
CPU time 0.79 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206216 kb
Host smart-5c9a3a6b-3700-4adf-9103-d6ceba550ab7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2298908492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2298908492
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.4220199032
Short name T763
Test name
Test status
Simulation time 157448674 ps
CPU time 0.79 seconds
Started Jul 04 06:10:48 PM PDT 24
Finished Jul 04 06:10:49 PM PDT 24
Peak memory 206172 kb
Host smart-cfbbd0c0-36f1-4c5d-a155-9db55603134a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
99032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.4220199032
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.154982232
Short name T107
Test name
Test status
Simulation time 188657363 ps
CPU time 0.84 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206208 kb
Host smart-d9cbf73d-e420-4b64-a3d8-3df924684384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15498
2232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.154982232
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.3930501705
Short name T2510
Test name
Test status
Simulation time 169824769 ps
CPU time 0.82 seconds
Started Jul 04 06:10:47 PM PDT 24
Finished Jul 04 06:10:48 PM PDT 24
Peak memory 206208 kb
Host smart-4ac72e1c-5274-43d3-b668-87a8dc10dd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39305
01705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3930501705
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2013792326
Short name T1770
Test name
Test status
Simulation time 168299914 ps
CPU time 0.82 seconds
Started Jul 04 06:10:46 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206172 kb
Host smart-65891389-3065-4bca-a06f-ebf758ad11f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137
92326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2013792326
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2428608871
Short name T1696
Test name
Test status
Simulation time 225978066 ps
CPU time 0.9 seconds
Started Jul 04 06:10:46 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206172 kb
Host smart-d420ca8c-885f-45f2-83d0-42e93fe866c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24286
08871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2428608871
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.692161166
Short name T1558
Test name
Test status
Simulation time 150208790 ps
CPU time 0.77 seconds
Started Jul 04 06:10:46 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206200 kb
Host smart-81cba1f9-42cd-4ff0-910c-a6c4caee05d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69216
1166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.692161166
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.4253181236
Short name T2058
Test name
Test status
Simulation time 243004859 ps
CPU time 0.98 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206180 kb
Host smart-abfdabbd-2dc7-4c15-9810-e15dc8674934
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4253181236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.4253181236
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1203550716
Short name T1598
Test name
Test status
Simulation time 167026961 ps
CPU time 0.78 seconds
Started Jul 04 06:10:48 PM PDT 24
Finished Jul 04 06:10:49 PM PDT 24
Peak memory 206104 kb
Host smart-0f7b76f8-dff5-4c2f-94ce-bd675c706879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12035
50716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1203550716
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2408787973
Short name T2638
Test name
Test status
Simulation time 112692302 ps
CPU time 0.68 seconds
Started Jul 04 06:10:46 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206176 kb
Host smart-6a63dd6d-5039-4293-8c9d-1ff28c0fa811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24087
87973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2408787973
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3330871738
Short name T1704
Test name
Test status
Simulation time 15649336598 ps
CPU time 32.72 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:11:19 PM PDT 24
Peak memory 214688 kb
Host smart-7745f720-469a-436c-be0d-75ed1a0b755a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33308
71738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3330871738
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2545686337
Short name T447
Test name
Test status
Simulation time 178156698 ps
CPU time 0.84 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206232 kb
Host smart-f0526f3e-8cb8-4176-bd81-335e1b90f360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25456
86337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2545686337
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.259288242
Short name T2250
Test name
Test status
Simulation time 166594564 ps
CPU time 0.85 seconds
Started Jul 04 06:10:46 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206180 kb
Host smart-1e386eb2-2e9e-46ca-8a53-bbb40bc0e652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
8242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.259288242
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2586590564
Short name T981
Test name
Test status
Simulation time 245480378 ps
CPU time 0.87 seconds
Started Jul 04 06:10:48 PM PDT 24
Finished Jul 04 06:10:49 PM PDT 24
Peak memory 206144 kb
Host smart-a55efa83-33d1-4ab9-b82c-be1a57be23ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25865
90564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2586590564
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1408602180
Short name T2072
Test name
Test status
Simulation time 186936616 ps
CPU time 0.87 seconds
Started Jul 04 06:10:46 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206180 kb
Host smart-bfbbc80a-6daf-4e84-9b66-2fc173f35ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14086
02180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1408602180
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3453851584
Short name T2127
Test name
Test status
Simulation time 156680242 ps
CPU time 0.76 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206172 kb
Host smart-dc214fa3-411a-4783-b40a-6ff3ec476ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
51584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3453851584
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1978488971
Short name T935
Test name
Test status
Simulation time 158419103 ps
CPU time 0.82 seconds
Started Jul 04 06:10:48 PM PDT 24
Finished Jul 04 06:10:49 PM PDT 24
Peak memory 206188 kb
Host smart-75f98472-2a1b-4cf2-8989-eb395e9ebb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19784
88971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1978488971
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.4259811372
Short name T469
Test name
Test status
Simulation time 155089121 ps
CPU time 0.89 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206192 kb
Host smart-99238091-9920-4ad4-908a-df3255780dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42598
11372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.4259811372
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3646127147
Short name T2202
Test name
Test status
Simulation time 240739645 ps
CPU time 0.99 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:10:45 PM PDT 24
Peak memory 206180 kb
Host smart-9122e4f3-ce7e-4e37-a2f4-bbf2f2e96eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
27147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3646127147
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1133157162
Short name T854
Test name
Test status
Simulation time 3525930999 ps
CPU time 98.19 seconds
Started Jul 04 06:10:44 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206540 kb
Host smart-5ee80b83-9af1-43b1-bf73-ba1f2a2f82ad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1133157162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1133157162
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3461739763
Short name T505
Test name
Test status
Simulation time 189408531 ps
CPU time 0.8 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:47 PM PDT 24
Peak memory 206220 kb
Host smart-70d4e736-2cd5-4c28-b9ba-4eaba72e1b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34617
39763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3461739763
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2642724144
Short name T1402
Test name
Test status
Simulation time 152715897 ps
CPU time 0.79 seconds
Started Jul 04 06:10:45 PM PDT 24
Finished Jul 04 06:10:46 PM PDT 24
Peak memory 206136 kb
Host smart-26da874e-d69e-467a-8a64-128367a58bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26427
24144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2642724144
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.854799983
Short name T1570
Test name
Test status
Simulation time 913245721 ps
CPU time 2.02 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206340 kb
Host smart-7af6fee2-36f4-45a2-ae54-49a48c4bf20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85479
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.854799983
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1092287870
Short name T1253
Test name
Test status
Simulation time 5247838367 ps
CPU time 51.13 seconds
Started Jul 04 06:10:53 PM PDT 24
Finished Jul 04 06:11:44 PM PDT 24
Peak memory 206488 kb
Host smart-38a8ce4c-b9a9-4cd2-99c8-c543c4d3e433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922
87870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1092287870
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3002799391
Short name T1667
Test name
Test status
Simulation time 31007411 ps
CPU time 0.68 seconds
Started Jul 04 06:10:58 PM PDT 24
Finished Jul 04 06:10:59 PM PDT 24
Peak memory 206288 kb
Host smart-9d4011aa-0988-4202-bad4-a76fd69fb13f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3002799391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3002799391
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.85860140
Short name T2425
Test name
Test status
Simulation time 3927517443 ps
CPU time 4.33 seconds
Started Jul 04 06:10:55 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206544 kb
Host smart-1423d9b9-4bc6-47db-ab81-686835bcfa30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=85860140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.85860140
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1006610191
Short name T1823
Test name
Test status
Simulation time 13373740226 ps
CPU time 13.12 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206480 kb
Host smart-14f580ad-27bb-4cb2-874d-bd48fa3bccb6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1006610191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1006610191
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.184045771
Short name T2667
Test name
Test status
Simulation time 23339017183 ps
CPU time 24.05 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:11:16 PM PDT 24
Peak memory 206264 kb
Host smart-3152bbf7-324b-4a2a-b6f6-d74c166b8933
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=184045771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.184045771
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1231683731
Short name T1081
Test name
Test status
Simulation time 179654203 ps
CPU time 0.8 seconds
Started Jul 04 06:10:54 PM PDT 24
Finished Jul 04 06:10:55 PM PDT 24
Peak memory 206212 kb
Host smart-c4682264-5cd5-4193-89d4-e1191e0f416b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12316
83731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1231683731
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.4193909314
Short name T2285
Test name
Test status
Simulation time 143575306 ps
CPU time 0.83 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:10:53 PM PDT 24
Peak memory 206188 kb
Host smart-77de87e4-5e4e-47c2-b10a-5d57f7253694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41939
09314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.4193909314
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3500695594
Short name T1409
Test name
Test status
Simulation time 294244809 ps
CPU time 1.08 seconds
Started Jul 04 06:10:57 PM PDT 24
Finished Jul 04 06:10:59 PM PDT 24
Peak memory 206040 kb
Host smart-9d3cec18-ad1d-4093-9a57-617b036207b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35006
95594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3500695594
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1356044091
Short name T371
Test name
Test status
Simulation time 525054762 ps
CPU time 1.39 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:10:52 PM PDT 24
Peak memory 206180 kb
Host smart-4c28824f-b490-489c-838c-e0135ba9f9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
44091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1356044091
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2309602886
Short name T1284
Test name
Test status
Simulation time 14916974371 ps
CPU time 26.42 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:11:18 PM PDT 24
Peak memory 206524 kb
Host smart-1dc16a49-c16b-4d53-b3fb-e479110d0138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23096
02886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2309602886
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.464780247
Short name T1626
Test name
Test status
Simulation time 371335930 ps
CPU time 1.2 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206192 kb
Host smart-62517870-8bc3-4b51-a1bd-005aa72c0119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46478
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.464780247
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1319623801
Short name T1049
Test name
Test status
Simulation time 142149035 ps
CPU time 0.73 seconds
Started Jul 04 06:10:53 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206200 kb
Host smart-1dbcb854-15bf-4aa2-9ded-1668eb67f98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13196
23801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1319623801
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3243542657
Short name T2673
Test name
Test status
Simulation time 81075509 ps
CPU time 0.67 seconds
Started Jul 04 06:10:54 PM PDT 24
Finished Jul 04 06:10:55 PM PDT 24
Peak memory 206188 kb
Host smart-24432f0d-b430-475b-a6f0-fdb21e33f1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32435
42657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3243542657
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2402447881
Short name T413
Test name
Test status
Simulation time 739066140 ps
CPU time 1.8 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:10:53 PM PDT 24
Peak memory 206380 kb
Host smart-b52512e1-7cc3-47a8-87ca-dab8400f11de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24024
47881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2402447881
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1971441241
Short name T2052
Test name
Test status
Simulation time 233523466 ps
CPU time 1.57 seconds
Started Jul 04 06:10:57 PM PDT 24
Finished Jul 04 06:10:59 PM PDT 24
Peak memory 206404 kb
Host smart-14541102-ceca-4c1a-b3cd-6b6190124d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714
41241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1971441241
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.827211049
Short name T1247
Test name
Test status
Simulation time 252523291 ps
CPU time 0.9 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:10:52 PM PDT 24
Peak memory 206140 kb
Host smart-6656701b-31a5-4af9-939f-45a8ac63b40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82721
1049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.827211049
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.469741781
Short name T1916
Test name
Test status
Simulation time 180583303 ps
CPU time 0.76 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:10:52 PM PDT 24
Peak memory 206220 kb
Host smart-46c3ff83-ea73-4128-a327-627ecefad9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46974
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.469741781
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.4060244015
Short name T451
Test name
Test status
Simulation time 165747384 ps
CPU time 0.77 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206192 kb
Host smart-85fa0495-89dc-4109-9a6e-039ecb800b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40602
44015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.4060244015
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2129200600
Short name T2300
Test name
Test status
Simulation time 5767584582 ps
CPU time 41.38 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206532 kb
Host smart-d51f1722-2494-43d7-8706-e1e8d3e377c6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2129200600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2129200600
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3200481339
Short name T2414
Test name
Test status
Simulation time 184842298 ps
CPU time 0.8 seconds
Started Jul 04 06:10:56 PM PDT 24
Finished Jul 04 06:10:57 PM PDT 24
Peak memory 206168 kb
Host smart-24cfe181-39bc-47aa-a8f1-0da738395734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32004
81339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3200481339
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.11474368
Short name T1530
Test name
Test status
Simulation time 23353534531 ps
CPU time 23.04 seconds
Started Jul 04 06:10:57 PM PDT 24
Finished Jul 04 06:11:20 PM PDT 24
Peak memory 206072 kb
Host smart-c9a2081b-18f8-4a3a-b21e-2df7e098e356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.11474368
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3783390005
Short name T992
Test name
Test status
Simulation time 3322002061 ps
CPU time 4.02 seconds
Started Jul 04 06:10:58 PM PDT 24
Finished Jul 04 06:11:02 PM PDT 24
Peak memory 206296 kb
Host smart-9b48eb76-05d5-45fb-abe1-81b0d37bc8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
90005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3783390005
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1714790848
Short name T158
Test name
Test status
Simulation time 6358023166 ps
CPU time 49.68 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206512 kb
Host smart-4e6aceb0-23c3-41d4-b151-6a099b3d3407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17147
90848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1714790848
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.615116607
Short name T2686
Test name
Test status
Simulation time 7542928732 ps
CPU time 214.27 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:14:26 PM PDT 24
Peak memory 206424 kb
Host smart-f1a988e3-c3f0-4860-80d8-90f33c83a72c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=615116607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.615116607
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3359591484
Short name T340
Test name
Test status
Simulation time 260035366 ps
CPU time 0.94 seconds
Started Jul 04 06:10:54 PM PDT 24
Finished Jul 04 06:10:55 PM PDT 24
Peak memory 206220 kb
Host smart-fb47cc56-bb2d-44bf-9951-d12681cc9058
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3359591484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3359591484
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3938796652
Short name T1960
Test name
Test status
Simulation time 193484836 ps
CPU time 0.84 seconds
Started Jul 04 06:10:53 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206148 kb
Host smart-9454723d-0b0c-4730-9297-693bf2e8c423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
96652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3938796652
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3731790021
Short name T1180
Test name
Test status
Simulation time 4724854126 ps
CPU time 43.45 seconds
Started Jul 04 06:10:51 PM PDT 24
Finished Jul 04 06:11:35 PM PDT 24
Peak memory 206452 kb
Host smart-11e93d7b-0eb3-4d28-992e-8aa70fc4a303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
90021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3731790021
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1055438742
Short name T2022
Test name
Test status
Simulation time 3976888644 ps
CPU time 30.76 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:11:23 PM PDT 24
Peak memory 206460 kb
Host smart-baa284b8-3c78-47f0-9055-5c989b1c66ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1055438742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1055438742
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1130564540
Short name T1187
Test name
Test status
Simulation time 156184657 ps
CPU time 0.76 seconds
Started Jul 04 06:10:55 PM PDT 24
Finished Jul 04 06:10:56 PM PDT 24
Peak memory 206220 kb
Host smart-5b00f780-9746-4ab8-aa92-cbaab7dd8416
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1130564540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1130564540
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2693602248
Short name T2002
Test name
Test status
Simulation time 170081353 ps
CPU time 0.79 seconds
Started Jul 04 06:10:55 PM PDT 24
Finished Jul 04 06:10:56 PM PDT 24
Peak memory 206196 kb
Host smart-08f755b3-a31e-4353-ba54-9d86f5ae357a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
02248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2693602248
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.893998539
Short name T138
Test name
Test status
Simulation time 235797631 ps
CPU time 0.91 seconds
Started Jul 04 06:10:54 PM PDT 24
Finished Jul 04 06:10:55 PM PDT 24
Peak memory 206192 kb
Host smart-09d3d3e8-99ca-42f1-a7e9-ad2caf13f0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89399
8539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.893998539
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.480941652
Short name T1854
Test name
Test status
Simulation time 221604656 ps
CPU time 0.88 seconds
Started Jul 04 06:10:53 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206188 kb
Host smart-5884f048-7b5d-467c-9df0-eb72507207ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48094
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.480941652
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.338670840
Short name T2450
Test name
Test status
Simulation time 178640622 ps
CPU time 0.81 seconds
Started Jul 04 06:10:53 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206188 kb
Host smart-55980bc2-eec0-49b3-9542-3f8f9bc16f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
0840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.338670840
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2012156651
Short name T2607
Test name
Test status
Simulation time 179364356 ps
CPU time 0.82 seconds
Started Jul 04 06:10:52 PM PDT 24
Finished Jul 04 06:10:54 PM PDT 24
Peak memory 206216 kb
Host smart-b5850ee7-c140-47f6-ab09-25f7afb7e83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121
56651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2012156651
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3029097066
Short name T2256
Test name
Test status
Simulation time 183071950 ps
CPU time 0.87 seconds
Started Jul 04 06:10:57 PM PDT 24
Finished Jul 04 06:10:58 PM PDT 24
Peak memory 206160 kb
Host smart-47764235-5a77-4565-b422-02c39d62803f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
97066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3029097066
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.838588119
Short name T2201
Test name
Test status
Simulation time 244331006 ps
CPU time 0.95 seconds
Started Jul 04 06:11:03 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206212 kb
Host smart-858214e4-1096-404f-a462-a314c153154f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=838588119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.838588119
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.238259597
Short name T1127
Test name
Test status
Simulation time 164695425 ps
CPU time 0.75 seconds
Started Jul 04 06:11:00 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206180 kb
Host smart-75311f38-ea63-4f63-bf6b-f8a777ecfdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23825
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.238259597
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1786500506
Short name T1586
Test name
Test status
Simulation time 64692703 ps
CPU time 0.72 seconds
Started Jul 04 06:11:02 PM PDT 24
Finished Jul 04 06:11:03 PM PDT 24
Peak memory 206120 kb
Host smart-871fcc1b-54d4-4c6d-88a4-86c274b63b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17865
00506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1786500506
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3537471294
Short name T1057
Test name
Test status
Simulation time 7003288542 ps
CPU time 17.51 seconds
Started Jul 04 06:10:58 PM PDT 24
Finished Jul 04 06:11:16 PM PDT 24
Peak memory 206488 kb
Host smart-f14d647e-68d7-44da-8763-6c9b331b6955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35374
71294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3537471294
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.761064430
Short name T406
Test name
Test status
Simulation time 213358799 ps
CPU time 0.84 seconds
Started Jul 04 06:11:04 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206204 kb
Host smart-05bbe3f2-026b-4400-87fc-e52f71fe6c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76106
4430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.761064430
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.205567860
Short name T2554
Test name
Test status
Simulation time 181059194 ps
CPU time 0.86 seconds
Started Jul 04 06:11:00 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206208 kb
Host smart-4f8ea80c-a6d5-4c96-a915-656f71c340d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
7860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.205567860
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3317039392
Short name T595
Test name
Test status
Simulation time 214859696 ps
CPU time 0.84 seconds
Started Jul 04 06:11:04 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206204 kb
Host smart-982eb4ed-a996-4e86-acee-4a85763cea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33170
39392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3317039392
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3645460840
Short name T330
Test name
Test status
Simulation time 227376474 ps
CPU time 0.84 seconds
Started Jul 04 06:11:00 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206200 kb
Host smart-591105db-25e6-46d5-8871-e4ed46a44c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
60840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3645460840
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3443746195
Short name T622
Test name
Test status
Simulation time 171628357 ps
CPU time 0.8 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:08 PM PDT 24
Peak memory 206160 kb
Host smart-6e27d54a-eb7c-4c6b-8dcd-6a21e3ce2c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34437
46195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3443746195
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2144491618
Short name T926
Test name
Test status
Simulation time 179561061 ps
CPU time 0.77 seconds
Started Jul 04 06:10:59 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206208 kb
Host smart-d6792248-dab1-4886-ae2a-5b2d8a6467a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21444
91618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2144491618
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3008077776
Short name T2260
Test name
Test status
Simulation time 144735438 ps
CPU time 0.76 seconds
Started Jul 04 06:10:59 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206184 kb
Host smart-52dc5cec-9c2d-4b8b-8d8c-51f746435234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30080
77776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3008077776
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1154154884
Short name T1709
Test name
Test status
Simulation time 214105441 ps
CPU time 0.92 seconds
Started Jul 04 06:10:59 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206172 kb
Host smart-76de2ff8-1866-4651-b168-7764763a4092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11541
54884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1154154884
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2766590619
Short name T865
Test name
Test status
Simulation time 4446871644 ps
CPU time 31.81 seconds
Started Jul 04 06:10:59 PM PDT 24
Finished Jul 04 06:11:31 PM PDT 24
Peak memory 206532 kb
Host smart-ef79b55a-bc33-40e7-87ec-abe1a4067599
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2766590619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2766590619
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3667301564
Short name T2679
Test name
Test status
Simulation time 159930530 ps
CPU time 0.77 seconds
Started Jul 04 06:11:00 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206212 kb
Host smart-d8b1cbc7-c888-43da-9b2a-e57a90b9f287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36673
01564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3667301564
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2640265457
Short name T1334
Test name
Test status
Simulation time 177256349 ps
CPU time 0.82 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:08 PM PDT 24
Peak memory 206168 kb
Host smart-8611b993-4138-4f81-87bd-d5d0d23fd76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26402
65457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2640265457
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1351455693
Short name T2495
Test name
Test status
Simulation time 1264023083 ps
CPU time 2.76 seconds
Started Jul 04 06:10:58 PM PDT 24
Finished Jul 04 06:11:01 PM PDT 24
Peak memory 206456 kb
Host smart-592bbadb-3d27-44fd-bc3f-c280ebb6354d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13514
55693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1351455693
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2735535332
Short name T884
Test name
Test status
Simulation time 7425271628 ps
CPU time 75.95 seconds
Started Jul 04 06:11:00 PM PDT 24
Finished Jul 04 06:12:16 PM PDT 24
Peak memory 206492 kb
Host smart-ccb45efd-8e6b-47f9-8c10-7fa06ddb7c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27355
35332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2735535332
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.3495267398
Short name T623
Test name
Test status
Simulation time 45687069 ps
CPU time 0.69 seconds
Started Jul 04 06:11:22 PM PDT 24
Finished Jul 04 06:11:23 PM PDT 24
Peak memory 206276 kb
Host smart-cf23b711-4f88-46dc-bcfa-38161c63e6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3495267398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3495267398
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2465136256
Short name T11
Test name
Test status
Simulation time 4358267858 ps
CPU time 5.43 seconds
Started Jul 04 06:10:58 PM PDT 24
Finished Jul 04 06:11:04 PM PDT 24
Peak memory 206236 kb
Host smart-6e198b7f-c8fb-413a-a981-89242950c990
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2465136256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2465136256
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3142481458
Short name T1825
Test name
Test status
Simulation time 13320839966 ps
CPU time 12.02 seconds
Started Jul 04 06:11:04 PM PDT 24
Finished Jul 04 06:11:17 PM PDT 24
Peak memory 206268 kb
Host smart-59e17a8f-0a82-48dd-9b8d-6814096924ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3142481458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3142481458
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.76086616
Short name T1880
Test name
Test status
Simulation time 23386506190 ps
CPU time 30.86 seconds
Started Jul 04 06:11:03 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206268 kb
Host smart-3b4881ad-9b9f-450c-9585-e51752e47ff9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=76086616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.76086616
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3110993848
Short name T767
Test name
Test status
Simulation time 177093372 ps
CPU time 0.81 seconds
Started Jul 04 06:10:59 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206196 kb
Host smart-ddedd6b7-905f-4252-bd92-ca9048d7fe65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3110993848
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1238569722
Short name T1200
Test name
Test status
Simulation time 850078134 ps
CPU time 2.2 seconds
Started Jul 04 06:10:58 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206368 kb
Host smart-28060bbd-6d1b-4adf-a4e3-f9d22558008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
69722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1238569722
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.277019937
Short name T2101
Test name
Test status
Simulation time 20369642290 ps
CPU time 36.44 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:44 PM PDT 24
Peak memory 206424 kb
Host smart-36cf34e0-6c70-4b34-8e8e-094cc3e0e31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27701
9937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.277019937
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4099487484
Short name T529
Test name
Test status
Simulation time 518354797 ps
CPU time 1.43 seconds
Started Jul 04 06:10:57 PM PDT 24
Finished Jul 04 06:10:58 PM PDT 24
Peak memory 206204 kb
Host smart-a2aac08e-1854-4200-ae2f-de79e56cbad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
87484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4099487484
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.549653358
Short name T769
Test name
Test status
Simulation time 134639873 ps
CPU time 0.76 seconds
Started Jul 04 06:10:59 PM PDT 24
Finished Jul 04 06:11:00 PM PDT 24
Peak memory 206144 kb
Host smart-bc227f1c-3757-43a6-bdc4-e3333307d525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54965
3358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.549653358
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3660440917
Short name T1525
Test name
Test status
Simulation time 50826559 ps
CPU time 0.68 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:08 PM PDT 24
Peak memory 206144 kb
Host smart-03db6506-489d-41a7-a092-554064d90215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36604
40917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3660440917
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1346046575
Short name T2258
Test name
Test status
Simulation time 713880420 ps
CPU time 1.9 seconds
Started Jul 04 06:11:11 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206384 kb
Host smart-dfa38caa-1caf-4f88-ad6a-77cf70023b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13460
46575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1346046575
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1052313536
Short name T1100
Test name
Test status
Simulation time 203036336 ps
CPU time 2.21 seconds
Started Jul 04 06:11:04 PM PDT 24
Finished Jul 04 06:11:07 PM PDT 24
Peak memory 206448 kb
Host smart-42248809-891b-4526-8105-74adecd03d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
13536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1052313536
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.937627218
Short name T1050
Test name
Test status
Simulation time 155907457 ps
CPU time 0.84 seconds
Started Jul 04 06:11:06 PM PDT 24
Finished Jul 04 06:11:07 PM PDT 24
Peak memory 206204 kb
Host smart-e04fb172-6769-4a72-8eb7-361eb1c800fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93762
7218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.937627218
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2265111722
Short name T2550
Test name
Test status
Simulation time 159954366 ps
CPU time 0.78 seconds
Started Jul 04 06:11:04 PM PDT 24
Finished Jul 04 06:11:05 PM PDT 24
Peak memory 206184 kb
Host smart-eba7edb3-d310-4b6d-a05e-8d0a0dd1d232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22651
11722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2265111722
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3329341586
Short name T2088
Test name
Test status
Simulation time 223428671 ps
CPU time 0.91 seconds
Started Jul 04 06:11:05 PM PDT 24
Finished Jul 04 06:11:06 PM PDT 24
Peak memory 206140 kb
Host smart-cde6fa01-8d89-4972-ac07-2d7ed98ee5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33293
41586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3329341586
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1663996032
Short name T2225
Test name
Test status
Simulation time 247925190 ps
CPU time 0.87 seconds
Started Jul 04 06:11:09 PM PDT 24
Finished Jul 04 06:11:10 PM PDT 24
Peak memory 206208 kb
Host smart-3b36fe4e-b0ac-4fc4-920a-80dd90ec03c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
96032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1663996032
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3213794937
Short name T2603
Test name
Test status
Simulation time 23316761972 ps
CPU time 25.77 seconds
Started Jul 04 06:11:05 PM PDT 24
Finished Jul 04 06:11:31 PM PDT 24
Peak memory 206260 kb
Host smart-431fa76e-69e2-4c28-ab70-9a96df6455f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32137
94937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3213794937
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.443743330
Short name T2220
Test name
Test status
Simulation time 3284099786 ps
CPU time 3.94 seconds
Started Jul 04 06:11:08 PM PDT 24
Finished Jul 04 06:11:12 PM PDT 24
Peak memory 205360 kb
Host smart-ae1cb8a5-b900-4c0d-afc7-d05ef21d10f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44374
3330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.443743330
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1390157134
Short name T1033
Test name
Test status
Simulation time 11511377778 ps
CPU time 77.65 seconds
Started Jul 04 06:11:05 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206516 kb
Host smart-c7bb45e6-9622-4c31-bfdb-b5be6cb6ef90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13901
57134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1390157134
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3323329266
Short name T2337
Test name
Test status
Simulation time 6668642586 ps
CPU time 51.99 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:59 PM PDT 24
Peak memory 206500 kb
Host smart-cad14371-fa44-4561-a602-0f865b04b6aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3323329266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3323329266
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1800493121
Short name T1338
Test name
Test status
Simulation time 249713631 ps
CPU time 0.96 seconds
Started Jul 04 06:11:06 PM PDT 24
Finished Jul 04 06:11:07 PM PDT 24
Peak memory 206144 kb
Host smart-c7b0ea8f-2787-4707-9c73-4f6f5db763f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1800493121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1800493121
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3417495345
Short name T1824
Test name
Test status
Simulation time 182208561 ps
CPU time 0.83 seconds
Started Jul 04 06:11:05 PM PDT 24
Finished Jul 04 06:11:06 PM PDT 24
Peak memory 206156 kb
Host smart-1d79b76e-8035-43e2-b356-cbe0a2315ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34174
95345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3417495345
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1802947186
Short name T579
Test name
Test status
Simulation time 4798268050 ps
CPU time 42.83 seconds
Started Jul 04 06:11:08 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206480 kb
Host smart-3e55bd6b-a79e-47b8-8ecb-8666b51b2ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029
47186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1802947186
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2180444395
Short name T1020
Test name
Test status
Simulation time 4819791431 ps
CPU time 45.45 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:53 PM PDT 24
Peak memory 206504 kb
Host smart-712a8a6d-7552-4b20-81a3-a41439407526
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2180444395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2180444395
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2575962011
Short name T366
Test name
Test status
Simulation time 157497039 ps
CPU time 0.8 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:08 PM PDT 24
Peak memory 206212 kb
Host smart-8888ed76-e22e-4c5e-8c33-8d9dd672ff2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2575962011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2575962011
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1790461425
Short name T766
Test name
Test status
Simulation time 148077769 ps
CPU time 0.79 seconds
Started Jul 04 06:11:07 PM PDT 24
Finished Jul 04 06:11:08 PM PDT 24
Peak memory 206180 kb
Host smart-96cec79d-487c-44e6-b3f9-c23034673ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17904
61425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1790461425
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1792395875
Short name T127
Test name
Test status
Simulation time 216132843 ps
CPU time 0.86 seconds
Started Jul 04 06:11:05 PM PDT 24
Finished Jul 04 06:11:06 PM PDT 24
Peak memory 206212 kb
Host smart-59ab9f09-98e6-4965-8924-db5f1b531642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17923
95875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1792395875
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3683010108
Short name T1563
Test name
Test status
Simulation time 214688770 ps
CPU time 0.91 seconds
Started Jul 04 06:11:06 PM PDT 24
Finished Jul 04 06:11:07 PM PDT 24
Peak memory 206200 kb
Host smart-040e3065-62ae-42c5-914f-ef3805628b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36830
10108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3683010108
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1038699142
Short name T1699
Test name
Test status
Simulation time 223655574 ps
CPU time 0.84 seconds
Started Jul 04 06:11:09 PM PDT 24
Finished Jul 04 06:11:10 PM PDT 24
Peak memory 206208 kb
Host smart-9673212e-2a3f-425f-988e-5198db6343be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
99142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1038699142
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2597423788
Short name T677
Test name
Test status
Simulation time 192525965 ps
CPU time 0.83 seconds
Started Jul 04 06:11:11 PM PDT 24
Finished Jul 04 06:11:12 PM PDT 24
Peak memory 206212 kb
Host smart-cb4d69ce-b091-4166-a9f8-86b56503e34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
23788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2597423788
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2502083078
Short name T939
Test name
Test status
Simulation time 158423598 ps
CPU time 0.81 seconds
Started Jul 04 06:11:03 PM PDT 24
Finished Jul 04 06:11:04 PM PDT 24
Peak memory 206196 kb
Host smart-967a61c4-0e85-42e1-8b3b-1dd0d7c47e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25020
83078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2502083078
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.822998554
Short name T2609
Test name
Test status
Simulation time 228772129 ps
CPU time 0.97 seconds
Started Jul 04 06:11:08 PM PDT 24
Finished Jul 04 06:11:09 PM PDT 24
Peak memory 205416 kb
Host smart-32bcd5ed-12fc-411d-8d00-0345483f0fd6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=822998554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.822998554
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1578995340
Short name T1647
Test name
Test status
Simulation time 33720829 ps
CPU time 0.69 seconds
Started Jul 04 06:11:14 PM PDT 24
Finished Jul 04 06:11:15 PM PDT 24
Peak memory 206164 kb
Host smart-322590ef-4e9a-4b26-958a-e7c68909a640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15789
95340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1578995340
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2798317397
Short name T1494
Test name
Test status
Simulation time 16575974917 ps
CPU time 37.75 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:59 PM PDT 24
Peak memory 206500 kb
Host smart-08018942-55d6-49e7-a5f7-e4b2247ed132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27983
17397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2798317397
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3809236990
Short name T716
Test name
Test status
Simulation time 189365022 ps
CPU time 0.8 seconds
Started Jul 04 06:11:12 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206192 kb
Host smart-41321cbe-31bd-4ce2-a471-eb2e4c2469da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
36990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3809236990
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.37595235
Short name T1408
Test name
Test status
Simulation time 195223642 ps
CPU time 0.88 seconds
Started Jul 04 06:11:13 PM PDT 24
Finished Jul 04 06:11:14 PM PDT 24
Peak memory 206176 kb
Host smart-a71811db-dd62-489e-b9cd-377f8dbd7e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37595
235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.37595235
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3524503576
Short name T1289
Test name
Test status
Simulation time 240679922 ps
CPU time 0.9 seconds
Started Jul 04 06:11:12 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206200 kb
Host smart-3e9e8971-5831-4a5a-acf1-cc33f9a9b997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245
03576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3524503576
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.689270310
Short name T1005
Test name
Test status
Simulation time 179195686 ps
CPU time 0.85 seconds
Started Jul 04 06:11:15 PM PDT 24
Finished Jul 04 06:11:16 PM PDT 24
Peak memory 206200 kb
Host smart-2f061eaa-f311-479c-a70a-a0e20182d014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68927
0310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.689270310
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1118447024
Short name T1290
Test name
Test status
Simulation time 146875984 ps
CPU time 0.74 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206208 kb
Host smart-f19b98ac-7341-4b46-84ab-0625f03c50f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11184
47024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1118447024
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.121181995
Short name T1851
Test name
Test status
Simulation time 175468596 ps
CPU time 0.87 seconds
Started Jul 04 06:11:13 PM PDT 24
Finished Jul 04 06:11:14 PM PDT 24
Peak memory 206204 kb
Host smart-5b9f279c-2c23-4f94-a132-b7aa9c1c2f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12118
1995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.121181995
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3696960262
Short name T971
Test name
Test status
Simulation time 148916518 ps
CPU time 0.78 seconds
Started Jul 04 06:11:12 PM PDT 24
Finished Jul 04 06:11:13 PM PDT 24
Peak memory 206208 kb
Host smart-56ba052c-c28d-4b7b-9003-9a99fd2262b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36969
60262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3696960262
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.747283206
Short name T1991
Test name
Test status
Simulation time 204773002 ps
CPU time 0.93 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206208 kb
Host smart-7f7cb4a4-296d-41e8-b270-cbc9b26faa67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74728
3206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.747283206
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.4149020181
Short name T894
Test name
Test status
Simulation time 4749316231 ps
CPU time 33.94 seconds
Started Jul 04 06:11:14 PM PDT 24
Finished Jul 04 06:11:48 PM PDT 24
Peak memory 206456 kb
Host smart-194caa2a-6130-4c7b-bc0e-3383dedc076f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4149020181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.4149020181
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.12358521
Short name T2468
Test name
Test status
Simulation time 169798488 ps
CPU time 0.83 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:19 PM PDT 24
Peak memory 206216 kb
Host smart-d708ab20-69b5-45d9-9493-acec8b940e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12358
521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.12358521
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.868015478
Short name T1651
Test name
Test status
Simulation time 165597744 ps
CPU time 0.87 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206200 kb
Host smart-81b5151b-a146-4025-97f0-abb0f527f14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86801
5478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.868015478
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.910665840
Short name T1717
Test name
Test status
Simulation time 268086141 ps
CPU time 1.01 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:20 PM PDT 24
Peak memory 206212 kb
Host smart-10084f1d-5423-43c8-943a-b460c4ea7d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91066
5840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.910665840
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.3902902888
Short name T958
Test name
Test status
Simulation time 2681578052 ps
CPU time 25.05 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:44 PM PDT 24
Peak memory 206484 kb
Host smart-397eb2c9-7101-48b8-a744-712caf6c3630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39029
02888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.3902902888
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.297063423
Short name T1112
Test name
Test status
Simulation time 114892376 ps
CPU time 0.75 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:06:19 PM PDT 24
Peak memory 206240 kb
Host smart-6470237d-faf4-4c94-8857-e3f61fbfa7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=297063423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.297063423
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.83752456
Short name T1166
Test name
Test status
Simulation time 3441033047 ps
CPU time 4.09 seconds
Started Jul 04 06:05:47 PM PDT 24
Finished Jul 04 06:05:52 PM PDT 24
Peak memory 206460 kb
Host smart-fbf03f14-af0c-429e-b696-fbb6f3395ab3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=83752456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.83752456
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.4218203410
Short name T2242
Test name
Test status
Simulation time 13429640345 ps
CPU time 11.7 seconds
Started Jul 04 06:05:42 PM PDT 24
Finished Jul 04 06:05:54 PM PDT 24
Peak memory 206480 kb
Host smart-56a2d4ca-70d7-41b4-a538-3687d30db377
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4218203410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.4218203410
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2130704897
Short name T1559
Test name
Test status
Simulation time 23429440648 ps
CPU time 24.1 seconds
Started Jul 04 06:05:41 PM PDT 24
Finished Jul 04 06:06:06 PM PDT 24
Peak memory 206248 kb
Host smart-f382518b-842d-4cf5-b545-7459599afc5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2130704897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2130704897
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.134145072
Short name T565
Test name
Test status
Simulation time 178941898 ps
CPU time 0.83 seconds
Started Jul 04 06:05:42 PM PDT 24
Finished Jul 04 06:05:43 PM PDT 24
Peak memory 206120 kb
Host smart-cd986e55-d47d-4be7-be81-b8ad0f6e26cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414
5072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.134145072
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2156793858
Short name T66
Test name
Test status
Simulation time 138322864 ps
CPU time 0.77 seconds
Started Jul 04 06:05:48 PM PDT 24
Finished Jul 04 06:05:49 PM PDT 24
Peak memory 206136 kb
Host smart-f3c2525f-b6a8-44d4-a09f-161170581131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567
93858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2156793858
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3283759026
Short name T2341
Test name
Test status
Simulation time 191321614 ps
CPU time 0.79 seconds
Started Jul 04 06:05:49 PM PDT 24
Finished Jul 04 06:05:50 PM PDT 24
Peak memory 206136 kb
Host smart-3c10193c-0918-43a1-97e3-a044a1b9f41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32837
59026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3283759026
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3205555719
Short name T1191
Test name
Test status
Simulation time 188994040 ps
CPU time 0.86 seconds
Started Jul 04 06:05:54 PM PDT 24
Finished Jul 04 06:05:55 PM PDT 24
Peak memory 206192 kb
Host smart-ef3c39ac-6afe-414c-9db6-bf3a3e50444e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32055
55719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3205555719
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3752386319
Short name T1264
Test name
Test status
Simulation time 793524939 ps
CPU time 2 seconds
Started Jul 04 06:05:54 PM PDT 24
Finished Jul 04 06:05:56 PM PDT 24
Peak memory 206244 kb
Host smart-11576845-97c0-4706-b651-a3b04dc4f889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37523
86319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3752386319
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3808277196
Short name T1269
Test name
Test status
Simulation time 16172403933 ps
CPU time 33.04 seconds
Started Jul 04 06:05:48 PM PDT 24
Finished Jul 04 06:06:21 PM PDT 24
Peak memory 206448 kb
Host smart-ab5e0a55-fd61-4158-bb5a-30dc3383f77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38082
77196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3808277196
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2552919748
Short name T1952
Test name
Test status
Simulation time 352212218 ps
CPU time 1.18 seconds
Started Jul 04 06:05:49 PM PDT 24
Finished Jul 04 06:05:51 PM PDT 24
Peak memory 206176 kb
Host smart-710bd45e-c2b1-4e99-ae1e-6bd1561d81c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25529
19748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2552919748
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.736659492
Short name T2581
Test name
Test status
Simulation time 141091187 ps
CPU time 0.78 seconds
Started Jul 04 06:05:49 PM PDT 24
Finished Jul 04 06:05:50 PM PDT 24
Peak memory 206144 kb
Host smart-082fbb84-7a9c-42b0-9200-34df8406b409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73665
9492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.736659492
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.893846591
Short name T2462
Test name
Test status
Simulation time 44684497 ps
CPU time 0.7 seconds
Started Jul 04 06:05:47 PM PDT 24
Finished Jul 04 06:05:48 PM PDT 24
Peak memory 206216 kb
Host smart-ea69c01b-215f-4b6c-8190-ac217ec290ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89384
6591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.893846591
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.101149867
Short name T1464
Test name
Test status
Simulation time 969598759 ps
CPU time 2.23 seconds
Started Jul 04 06:05:54 PM PDT 24
Finished Jul 04 06:05:56 PM PDT 24
Peak memory 206288 kb
Host smart-2671c99b-3099-4ed2-bdfb-55a1903e0a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10114
9867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.101149867
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2048397880
Short name T2669
Test name
Test status
Simulation time 187938404 ps
CPU time 1.67 seconds
Started Jul 04 06:05:48 PM PDT 24
Finished Jul 04 06:05:50 PM PDT 24
Peak memory 206456 kb
Host smart-5d19f538-00fb-43ca-8ea1-18aeb24c32fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483
97880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2048397880
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.313644865
Short name T2358
Test name
Test status
Simulation time 83196961845 ps
CPU time 104.46 seconds
Started Jul 04 06:05:49 PM PDT 24
Finished Jul 04 06:07:34 PM PDT 24
Peak memory 206476 kb
Host smart-d3790516-e206-45d8-9f0f-280b16d80479
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=313644865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.313644865
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.4254926885
Short name T1073
Test name
Test status
Simulation time 84090141561 ps
CPU time 122.62 seconds
Started Jul 04 06:05:47 PM PDT 24
Finished Jul 04 06:07:50 PM PDT 24
Peak memory 206468 kb
Host smart-fc21c171-cd1a-4446-980a-908848688a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254926885 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.4254926885
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2507026131
Short name T583
Test name
Test status
Simulation time 82131045757 ps
CPU time 104.47 seconds
Started Jul 04 06:05:55 PM PDT 24
Finished Jul 04 06:07:39 PM PDT 24
Peak memory 206464 kb
Host smart-d9c4cd2d-61d0-45d0-8f76-41878fe42e6e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2507026131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2507026131
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.540512939
Short name T1954
Test name
Test status
Simulation time 94252259112 ps
CPU time 141.42 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:08:23 PM PDT 24
Peak memory 206480 kb
Host smart-a68832d9-a1a5-4f3e-95ff-3e03ee0aa871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540512939 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.540512939
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1514644107
Short name T1822
Test name
Test status
Simulation time 115143786346 ps
CPU time 143.31 seconds
Started Jul 04 06:05:56 PM PDT 24
Finished Jul 04 06:08:20 PM PDT 24
Peak memory 206484 kb
Host smart-bc1cd003-7741-44fd-820e-8fdcb357dd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
44107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1514644107
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3364328374
Short name T791
Test name
Test status
Simulation time 195314888 ps
CPU time 0.84 seconds
Started Jul 04 06:05:55 PM PDT 24
Finished Jul 04 06:05:56 PM PDT 24
Peak memory 206160 kb
Host smart-8ecfb718-85d7-4958-9cf5-422945672698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643
28374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3364328374
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.336042247
Short name T1330
Test name
Test status
Simulation time 163087815 ps
CPU time 0.76 seconds
Started Jul 04 06:05:55 PM PDT 24
Finished Jul 04 06:05:56 PM PDT 24
Peak memory 206208 kb
Host smart-a6145350-9ee9-4b2e-a5f0-f08cd9a764aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33604
2247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.336042247
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1884016318
Short name T1601
Test name
Test status
Simulation time 205561229 ps
CPU time 0.85 seconds
Started Jul 04 06:06:01 PM PDT 24
Finished Jul 04 06:06:02 PM PDT 24
Peak memory 206216 kb
Host smart-b6c856e0-be2c-4170-9410-6fd9e8a4d4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18840
16318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1884016318
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.963668223
Short name T239
Test name
Test status
Simulation time 6013360137 ps
CPU time 164.02 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:08:47 PM PDT 24
Peak memory 206520 kb
Host smart-06d36e0c-818d-479f-9fb5-512c49a2bccf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=963668223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.963668223
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.240626253
Short name T1983
Test name
Test status
Simulation time 233386670 ps
CPU time 0.91 seconds
Started Jul 04 06:05:57 PM PDT 24
Finished Jul 04 06:05:58 PM PDT 24
Peak memory 206172 kb
Host smart-3c89fc12-ba52-422d-8db9-4f3e5f8cb64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
6253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.240626253
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1363380233
Short name T596
Test name
Test status
Simulation time 23287947088 ps
CPU time 22.45 seconds
Started Jul 04 06:05:55 PM PDT 24
Finished Jul 04 06:06:18 PM PDT 24
Peak memory 206268 kb
Host smart-409d340d-bc68-4b77-9a12-7f317ac01b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
80233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1363380233
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1760687914
Short name T1401
Test name
Test status
Simulation time 3272480260 ps
CPU time 3.99 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:06:06 PM PDT 24
Peak memory 206276 kb
Host smart-a3d9031f-e59a-48bd-bf79-54007ee4a895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
87914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1760687914
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2075025598
Short name T1765
Test name
Test status
Simulation time 5952547805 ps
CPU time 181.27 seconds
Started Jul 04 06:05:56 PM PDT 24
Finished Jul 04 06:08:57 PM PDT 24
Peak memory 206512 kb
Host smart-747a0b37-bf63-4f77-babe-f0d29968b7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
25598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2075025598
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.522964824
Short name T1364
Test name
Test status
Simulation time 4493288335 ps
CPU time 121.9 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:08:06 PM PDT 24
Peak memory 206464 kb
Host smart-099b2366-0f3c-49d5-960b-ce450be881f6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=522964824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.522964824
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4179829275
Short name T947
Test name
Test status
Simulation time 269885320 ps
CPU time 0.92 seconds
Started Jul 04 06:05:56 PM PDT 24
Finished Jul 04 06:05:57 PM PDT 24
Peak memory 206172 kb
Host smart-87cdd5dd-b4ae-4f4d-b5d7-88d1ee17e596
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4179829275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4179829275
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2995366424
Short name T2299
Test name
Test status
Simulation time 199742941 ps
CPU time 0.86 seconds
Started Jul 04 06:05:55 PM PDT 24
Finished Jul 04 06:05:56 PM PDT 24
Peak memory 206172 kb
Host smart-9f8a0bf6-0023-4e6d-9f92-e42910673fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29953
66424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2995366424
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1987758040
Short name T454
Test name
Test status
Simulation time 6265877819 ps
CPU time 45.3 seconds
Started Jul 04 06:05:55 PM PDT 24
Finished Jul 04 06:06:40 PM PDT 24
Peak memory 206484 kb
Host smart-1a67d7b6-65f8-4b8c-bfcf-03dc40465d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19877
58040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1987758040
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1245047464
Short name T2520
Test name
Test status
Simulation time 4068627848 ps
CPU time 113.06 seconds
Started Jul 04 06:05:56 PM PDT 24
Finished Jul 04 06:07:49 PM PDT 24
Peak memory 206476 kb
Host smart-3636dcd9-fd36-4e05-be13-07691f13c4bc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1245047464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1245047464
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1979376953
Short name T2427
Test name
Test status
Simulation time 227155730 ps
CPU time 0.94 seconds
Started Jul 04 06:05:56 PM PDT 24
Finished Jul 04 06:05:57 PM PDT 24
Peak memory 206212 kb
Host smart-76ec4c25-5471-4119-99cf-575a9a001908
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1979376953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1979376953
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.4107901224
Short name T1306
Test name
Test status
Simulation time 159313763 ps
CPU time 0.78 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:06:03 PM PDT 24
Peak memory 206196 kb
Host smart-68fc31ab-ed1b-4472-8c7e-bb351496de55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
01224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.4107901224
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2770051287
Short name T146
Test name
Test status
Simulation time 229624762 ps
CPU time 0.92 seconds
Started Jul 04 06:06:04 PM PDT 24
Finished Jul 04 06:06:05 PM PDT 24
Peak memory 206212 kb
Host smart-f5938203-ab16-4c9a-911a-45b98467de3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
51287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2770051287
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3022899576
Short name T624
Test name
Test status
Simulation time 222693152 ps
CPU time 0.87 seconds
Started Jul 04 06:06:04 PM PDT 24
Finished Jul 04 06:06:05 PM PDT 24
Peak memory 206176 kb
Host smart-9c92afec-db93-4d11-8fd1-198f6fb90838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
99576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3022899576
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2277154079
Short name T636
Test name
Test status
Simulation time 211571169 ps
CPU time 0.82 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:06:03 PM PDT 24
Peak memory 206212 kb
Host smart-7f4f9143-ff8a-4d17-b6e6-2dc3bc2a93ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22771
54079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2277154079
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3135729675
Short name T870
Test name
Test status
Simulation time 183399747 ps
CPU time 0.83 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:06:04 PM PDT 24
Peak memory 206176 kb
Host smart-95a425a6-ec1b-4cec-b7c8-29b0fec02778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
29675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3135729675
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.727055325
Short name T183
Test name
Test status
Simulation time 150987192 ps
CPU time 0.83 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:06:05 PM PDT 24
Peak memory 206204 kb
Host smart-9f9c2a0c-0768-49e3-95a3-ff9bf3be854b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72705
5325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.727055325
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.4152009290
Short name T946
Test name
Test status
Simulation time 272285747 ps
CPU time 0.92 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:06:05 PM PDT 24
Peak memory 206152 kb
Host smart-67f9607a-1165-4a85-b35e-d88fda649e4e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4152009290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.4152009290
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1610765704
Short name T1992
Test name
Test status
Simulation time 210247311 ps
CPU time 0.87 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:06:05 PM PDT 24
Peak memory 206180 kb
Host smart-73609d27-d54f-4b22-9781-0a8924708403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16107
65704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1610765704
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.442889651
Short name T513
Test name
Test status
Simulation time 152324471 ps
CPU time 0.82 seconds
Started Jul 04 06:06:08 PM PDT 24
Finished Jul 04 06:06:09 PM PDT 24
Peak memory 206172 kb
Host smart-eea07a16-7885-413b-8e6a-c1c65a47a19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44288
9651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.442889651
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4157176701
Short name T694
Test name
Test status
Simulation time 67821204 ps
CPU time 0.71 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:06:03 PM PDT 24
Peak memory 206164 kb
Host smart-b26474ed-278e-43a3-beed-917e741b0be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571
76701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4157176701
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1253787696
Short name T2622
Test name
Test status
Simulation time 19573298367 ps
CPU time 42.25 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:06:46 PM PDT 24
Peak memory 206468 kb
Host smart-31f3c264-e0a2-41c0-bc1f-8a0e8fe30777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
87696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1253787696
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1379645157
Short name T2384
Test name
Test status
Simulation time 164910861 ps
CPU time 0.85 seconds
Started Jul 04 06:06:08 PM PDT 24
Finished Jul 04 06:06:09 PM PDT 24
Peak memory 206172 kb
Host smart-40fd74ef-0967-4aab-9c6c-57368ea28598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
45157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1379645157
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.338108847
Short name T1252
Test name
Test status
Simulation time 187873484 ps
CPU time 0.83 seconds
Started Jul 04 06:06:02 PM PDT 24
Finished Jul 04 06:06:03 PM PDT 24
Peak memory 206200 kb
Host smart-ca3b4c8f-8a38-4f06-9b6e-5a81851803f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33810
8847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.338108847
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3702611395
Short name T2649
Test name
Test status
Simulation time 10673115705 ps
CPU time 196.06 seconds
Started Jul 04 06:06:09 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206520 kb
Host smart-cc7140fc-db6d-467d-ab4f-0131edaa4a74
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3702611395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3702611395
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.858810026
Short name T2142
Test name
Test status
Simulation time 11562966304 ps
CPU time 103.91 seconds
Started Jul 04 06:06:11 PM PDT 24
Finished Jul 04 06:07:56 PM PDT 24
Peak memory 206464 kb
Host smart-189d5423-2db0-4dca-80c3-114d466577ac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=858810026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.858810026
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2256586071
Short name T2068
Test name
Test status
Simulation time 11173760194 ps
CPU time 189.85 seconds
Started Jul 04 06:06:10 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206472 kb
Host smart-cb45b8dc-49b4-48a8-9f7b-fd7a0a4ae860
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2256586071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2256586071
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.158904480
Short name T564
Test name
Test status
Simulation time 252278801 ps
CPU time 0.9 seconds
Started Jul 04 06:06:03 PM PDT 24
Finished Jul 04 06:06:04 PM PDT 24
Peak memory 206224 kb
Host smart-cc74e3e1-5d36-4739-bd06-41d08eaab5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
4480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.158904480
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.392480611
Short name T686
Test name
Test status
Simulation time 162802320 ps
CPU time 0.79 seconds
Started Jul 04 06:06:11 PM PDT 24
Finished Jul 04 06:06:12 PM PDT 24
Peak memory 206180 kb
Host smart-c15f65ea-e8af-4251-8b55-8fe4040b6e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39248
0611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.392480611
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2711749110
Short name T1596
Test name
Test status
Simulation time 173164311 ps
CPU time 0.79 seconds
Started Jul 04 06:06:11 PM PDT 24
Finished Jul 04 06:06:12 PM PDT 24
Peak memory 206176 kb
Host smart-9c0f0af0-f9c6-4865-904f-2f79b4660614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
49110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2711749110
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1351391428
Short name T77
Test name
Test status
Simulation time 186059309 ps
CPU time 0.87 seconds
Started Jul 04 06:06:13 PM PDT 24
Finished Jul 04 06:06:14 PM PDT 24
Peak memory 206220 kb
Host smart-af884e6c-b92c-4416-bbff-edbbf922f6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
91428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1351391428
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1210383407
Short name T214
Test name
Test status
Simulation time 676048413 ps
CPU time 1.6 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:06:19 PM PDT 24
Peak memory 224060 kb
Host smart-5b2d0bc5-5a48-4817-abd8-22c887980af1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1210383407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1210383407
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2423978302
Short name T53
Test name
Test status
Simulation time 392181170 ps
CPU time 1.25 seconds
Started Jul 04 06:06:10 PM PDT 24
Finished Jul 04 06:06:11 PM PDT 24
Peak memory 206220 kb
Host smart-a6cfef1b-ead8-45e6-b232-ef0cb68c8e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24239
78302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2423978302
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1673762851
Short name T805
Test name
Test status
Simulation time 194956092 ps
CPU time 0.85 seconds
Started Jul 04 06:06:09 PM PDT 24
Finished Jul 04 06:06:10 PM PDT 24
Peak memory 206204 kb
Host smart-93fe063c-3f49-4b7b-808b-7cd35425b3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16737
62851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1673762851
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.21126527
Short name T1670
Test name
Test status
Simulation time 171064582 ps
CPU time 0.85 seconds
Started Jul 04 06:06:11 PM PDT 24
Finished Jul 04 06:06:12 PM PDT 24
Peak memory 206164 kb
Host smart-40b4387f-18c5-4f3d-9d2f-17aa1e54ab26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21126
527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.21126527
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1069887026
Short name T1599
Test name
Test status
Simulation time 161384334 ps
CPU time 0.75 seconds
Started Jul 04 06:06:10 PM PDT 24
Finished Jul 04 06:06:11 PM PDT 24
Peak memory 206212 kb
Host smart-8f425c33-cbd1-4240-91ea-964a317b2ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10698
87026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1069887026
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1053726733
Short name T2351
Test name
Test status
Simulation time 200826625 ps
CPU time 0.9 seconds
Started Jul 04 06:06:13 PM PDT 24
Finished Jul 04 06:06:14 PM PDT 24
Peak memory 206220 kb
Host smart-90cbb0fa-f2bf-4a51-873e-979daa8e78a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10537
26733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1053726733
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2233180705
Short name T151
Test name
Test status
Simulation time 4227261341 ps
CPU time 31.06 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:06:50 PM PDT 24
Peak memory 206476 kb
Host smart-032e31cc-7e2e-4078-b66c-d9ab487e653d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2233180705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2233180705
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1043794979
Short name T1300
Test name
Test status
Simulation time 186138156 ps
CPU time 0.87 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:06:19 PM PDT 24
Peak memory 206200 kb
Host smart-1946d186-00dd-4f7c-b942-8a2c492ac858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
94979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1043794979
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2852679527
Short name T2155
Test name
Test status
Simulation time 195707076 ps
CPU time 0.77 seconds
Started Jul 04 06:06:17 PM PDT 24
Finished Jul 04 06:06:18 PM PDT 24
Peak memory 206200 kb
Host smart-a9d8b477-79b6-460f-a54b-ce8e18548cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28526
79527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2852679527
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.3763761883
Short name T1147
Test name
Test status
Simulation time 709511597 ps
CPU time 1.64 seconds
Started Jul 04 06:06:23 PM PDT 24
Finished Jul 04 06:06:25 PM PDT 24
Peak memory 206364 kb
Host smart-1bae64aa-7ed8-4e7b-aab0-a5b19503cde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37637
61883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.3763761883
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2667921956
Short name T2306
Test name
Test status
Simulation time 3686164328 ps
CPU time 29.27 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:06:48 PM PDT 24
Peak memory 206484 kb
Host smart-fd51440c-0c2a-47e1-92aa-f0d3724fae69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679
21956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2667921956
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1328263368
Short name T1474
Test name
Test status
Simulation time 13276268684 ps
CPU time 264.83 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:10:43 PM PDT 24
Peak memory 206548 kb
Host smart-d199ec97-c1e6-449b-8d3d-ebc87c0152f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1328263368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1328263368
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.348242860
Short name T1079
Test name
Test status
Simulation time 66220627 ps
CPU time 0.72 seconds
Started Jul 04 06:11:31 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 206184 kb
Host smart-772744e6-1f23-4ba8-aac2-d3b26ad6f516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=348242860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.348242860
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.850592780
Short name T2013
Test name
Test status
Simulation time 3676386779 ps
CPU time 4.62 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:23 PM PDT 24
Peak memory 206204 kb
Host smart-cf2144c3-a07a-445f-b0d6-f6673013a631
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=850592780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.850592780
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3311535834
Short name T1348
Test name
Test status
Simulation time 23329782692 ps
CPU time 21.81 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:42 PM PDT 24
Peak memory 206516 kb
Host smart-93153b17-5f04-424e-a259-c5ac65a84c4c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3311535834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3311535834
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3404721610
Short name T1748
Test name
Test status
Simulation time 217597194 ps
CPU time 0.94 seconds
Started Jul 04 06:11:17 PM PDT 24
Finished Jul 04 06:11:18 PM PDT 24
Peak memory 206204 kb
Host smart-e8ab86c0-ee3d-4e08-b013-07f3fa5cf53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
21610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3404721610
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3523280799
Short name T599
Test name
Test status
Simulation time 143429856 ps
CPU time 0.75 seconds
Started Jul 04 06:11:21 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206168 kb
Host smart-87f36d83-d6d6-4573-bd50-c89912e6fd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232
80799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3523280799
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1462180567
Short name T2555
Test name
Test status
Simulation time 518898411 ps
CPU time 1.52 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206424 kb
Host smart-13e5c3ed-faf2-4458-bbec-f5943c34fe64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14621
80567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1462180567
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3552055780
Short name T1434
Test name
Test status
Simulation time 1148663185 ps
CPU time 2.65 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206348 kb
Host smart-dcf000b7-1e26-42d6-ba76-86034185fd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520
55780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3552055780
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3145938627
Short name T956
Test name
Test status
Simulation time 6539946482 ps
CPU time 11.28 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 206456 kb
Host smart-e4e95c83-bc36-4f9c-8b1b-0fd3be1543bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459
38627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3145938627
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3886224211
Short name T1224
Test name
Test status
Simulation time 387115856 ps
CPU time 1.11 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206124 kb
Host smart-158978c5-9414-4079-aab6-14e115a3beaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38862
24211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3886224211
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.82694385
Short name T1806
Test name
Test status
Simulation time 148814532 ps
CPU time 0.76 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:20 PM PDT 24
Peak memory 206212 kb
Host smart-61844c2f-16a4-483d-bc8c-e21654bc2269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82694
385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.82694385
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1282087431
Short name T488
Test name
Test status
Simulation time 33933365 ps
CPU time 0.69 seconds
Started Jul 04 06:11:21 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206140 kb
Host smart-083cef6f-4fed-4ac6-b2b6-157f81a8c1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12820
87431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1282087431
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1182764025
Short name T1217
Test name
Test status
Simulation time 936339614 ps
CPU time 2.14 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:23 PM PDT 24
Peak memory 206428 kb
Host smart-4c4f52d9-fcd9-4a17-9e84-6cd550cc316c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11827
64025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1182764025
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2281083531
Short name T1120
Test name
Test status
Simulation time 313503392 ps
CPU time 2.34 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206424 kb
Host smart-775f7019-ee0e-4ac3-95fb-f5e4f3d968f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
83531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2281083531
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2230037023
Short name T2000
Test name
Test status
Simulation time 213380672 ps
CPU time 0.85 seconds
Started Jul 04 06:11:24 PM PDT 24
Finished Jul 04 06:11:25 PM PDT 24
Peak memory 206188 kb
Host smart-196221a6-43a6-4276-a728-dfcfcfd5292e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
37023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2230037023
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3506299449
Short name T321
Test name
Test status
Simulation time 146593415 ps
CPU time 0.81 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206208 kb
Host smart-a454bb1c-dc44-43db-bba0-ae8fe01386db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35062
99449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3506299449
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1833881164
Short name T486
Test name
Test status
Simulation time 223214459 ps
CPU time 0.9 seconds
Started Jul 04 06:11:25 PM PDT 24
Finished Jul 04 06:11:26 PM PDT 24
Peak memory 206208 kb
Host smart-3c13bda5-e76d-4e1b-bead-491cabe566de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18338
81164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1833881164
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.313886933
Short name T1132
Test name
Test status
Simulation time 9837398421 ps
CPU time 92.09 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:12:51 PM PDT 24
Peak memory 206500 kb
Host smart-66249991-9a06-486b-84cf-1db646808712
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=313886933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.313886933
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1677315645
Short name T830
Test name
Test status
Simulation time 179274541 ps
CPU time 0.83 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:19 PM PDT 24
Peak memory 206216 kb
Host smart-c37dc589-8e62-4d0b-b151-40ab99680970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773
15645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1677315645
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.821862319
Short name T1950
Test name
Test status
Simulation time 23327337267 ps
CPU time 23.53 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206272 kb
Host smart-b6821823-7970-4127-9d1c-1f91d190a9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82186
2319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.821862319
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1568657567
Short name T2654
Test name
Test status
Simulation time 3340338862 ps
CPU time 4.37 seconds
Started Jul 04 06:11:22 PM PDT 24
Finished Jul 04 06:11:26 PM PDT 24
Peak memory 206280 kb
Host smart-286235a7-000d-42d3-9926-36e1042de46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15686
57567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1568657567
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.856323709
Short name T1621
Test name
Test status
Simulation time 8371010305 ps
CPU time 225.88 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:15:07 PM PDT 24
Peak memory 206492 kb
Host smart-758643d0-d79c-4305-8527-4892bd1c7536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85632
3709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.856323709
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3732864615
Short name T2651
Test name
Test status
Simulation time 6297673889 ps
CPU time 61.62 seconds
Started Jul 04 06:11:22 PM PDT 24
Finished Jul 04 06:12:24 PM PDT 24
Peak memory 206420 kb
Host smart-d1366de7-1380-4390-922a-bf0329b8276f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3732864615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3732864615
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2207912418
Short name T2048
Test name
Test status
Simulation time 240228021 ps
CPU time 0.92 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206180 kb
Host smart-02b325ce-8b08-4ff6-b7cf-f19678952f5b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2207912418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2207912418
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.101257648
Short name T2038
Test name
Test status
Simulation time 204084848 ps
CPU time 0.92 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206172 kb
Host smart-73735e19-e96e-48b3-ade6-c760af8362a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10125
7648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.101257648
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.147568174
Short name T1272
Test name
Test status
Simulation time 5862324063 ps
CPU time 56.77 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206452 kb
Host smart-dea09095-01d3-48a4-b1e0-adac1bd214ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14756
8174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.147568174
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.176498154
Short name T1098
Test name
Test status
Simulation time 3166540000 ps
CPU time 86.38 seconds
Started Jul 04 06:11:22 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206496 kb
Host smart-e97f1123-4cd5-40ec-8583-e2be066e203f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=176498154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.176498154
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.326801714
Short name T1868
Test name
Test status
Simulation time 149630774 ps
CPU time 0.79 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:19 PM PDT 24
Peak memory 206180 kb
Host smart-5b04d6e7-afd6-478d-844a-fbc709326f50
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=326801714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.326801714
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.554103497
Short name T436
Test name
Test status
Simulation time 139068967 ps
CPU time 0.77 seconds
Started Jul 04 06:11:19 PM PDT 24
Finished Jul 04 06:11:20 PM PDT 24
Peak memory 206184 kb
Host smart-4a5355a2-51a6-48db-ab72-2dcea89205f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55410
3497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.554103497
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1974640322
Short name T131
Test name
Test status
Simulation time 237132338 ps
CPU time 0.97 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206212 kb
Host smart-e8a9784d-746e-40e0-879b-c7ca5d070f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19746
40322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1974640322
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4254386623
Short name T1840
Test name
Test status
Simulation time 197145714 ps
CPU time 0.85 seconds
Started Jul 04 06:11:21 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206200 kb
Host smart-c2c80092-6f5e-4c86-abfc-51f0ef7243e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
86623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4254386623
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1066780837
Short name T868
Test name
Test status
Simulation time 179812413 ps
CPU time 0.83 seconds
Started Jul 04 06:11:21 PM PDT 24
Finished Jul 04 06:11:22 PM PDT 24
Peak memory 206200 kb
Host smart-3a0918b7-5f0d-42e4-8905-796f15bbab81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10667
80837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1066780837
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3368809886
Short name T866
Test name
Test status
Simulation time 212958446 ps
CPU time 0.87 seconds
Started Jul 04 06:11:23 PM PDT 24
Finished Jul 04 06:11:24 PM PDT 24
Peak memory 206208 kb
Host smart-7dd281ce-21c6-47e7-83ff-96f965abbd58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33688
09886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3368809886
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3976199417
Short name T1620
Test name
Test status
Simulation time 176593874 ps
CPU time 0.83 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:19 PM PDT 24
Peak memory 206208 kb
Host smart-415ef089-24b1-495f-a979-af70480ddd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761
99417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3976199417
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.391980167
Short name T1439
Test name
Test status
Simulation time 252660968 ps
CPU time 0.95 seconds
Started Jul 04 06:11:25 PM PDT 24
Finished Jul 04 06:11:26 PM PDT 24
Peak memory 206216 kb
Host smart-9b62bbb7-02bc-4aeb-801b-be346639bed8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=391980167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.391980167
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.119506147
Short name T910
Test name
Test status
Simulation time 175999941 ps
CPU time 0.78 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:21 PM PDT 24
Peak memory 206156 kb
Host smart-aa9c6b2d-f82f-480d-af88-b9ddd6c6dc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11950
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.119506147
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2877464414
Short name T1282
Test name
Test status
Simulation time 54414628 ps
CPU time 0.66 seconds
Started Jul 04 06:11:18 PM PDT 24
Finished Jul 04 06:11:19 PM PDT 24
Peak memory 206188 kb
Host smart-200fdadc-d26b-4160-b777-e2ead0a0efff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28774
64414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2877464414
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3241956135
Short name T2443
Test name
Test status
Simulation time 14889463697 ps
CPU time 34.27 seconds
Started Jul 04 06:11:20 PM PDT 24
Finished Jul 04 06:11:55 PM PDT 24
Peak memory 206520 kb
Host smart-5d9d0c72-a219-48ed-b64c-75509703a3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32419
56135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3241956135
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2631554404
Short name T651
Test name
Test status
Simulation time 194139411 ps
CPU time 0.87 seconds
Started Jul 04 06:11:23 PM PDT 24
Finished Jul 04 06:11:24 PM PDT 24
Peak memory 206208 kb
Host smart-0a70bd5c-f537-4624-88db-b7c561d79d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26315
54404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2631554404
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.163679007
Short name T1172
Test name
Test status
Simulation time 191453953 ps
CPU time 0.87 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:27 PM PDT 24
Peak memory 206232 kb
Host smart-933fadb6-843c-4e9e-86eb-c146c0dbd5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16367
9007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.163679007
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2587152289
Short name T2147
Test name
Test status
Simulation time 241543024 ps
CPU time 0.84 seconds
Started Jul 04 06:11:24 PM PDT 24
Finished Jul 04 06:11:25 PM PDT 24
Peak memory 206224 kb
Host smart-78f3fef2-c4ab-4ae1-9dfb-3ea4dd33a4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25871
52289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2587152289
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1902690987
Short name T2331
Test name
Test status
Simulation time 208879342 ps
CPU time 0.85 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:27 PM PDT 24
Peak memory 206168 kb
Host smart-0a447362-e8f2-4ac3-b739-dfac8f7418de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
90987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1902690987
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2327746346
Short name T2526
Test name
Test status
Simulation time 216431947 ps
CPU time 0.9 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:27 PM PDT 24
Peak memory 206132 kb
Host smart-3827b6ea-5aab-4718-a516-522f042a1eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23277
46346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2327746346
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3348446570
Short name T1631
Test name
Test status
Simulation time 164993951 ps
CPU time 0.75 seconds
Started Jul 04 06:11:28 PM PDT 24
Finished Jul 04 06:11:29 PM PDT 24
Peak memory 206208 kb
Host smart-bcf499e2-c5c6-40f4-a4de-4a219f6f5651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33484
46570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3348446570
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.831023843
Short name T1357
Test name
Test status
Simulation time 158850191 ps
CPU time 0.81 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:27 PM PDT 24
Peak memory 206192 kb
Host smart-03e22ad5-eae3-44d3-9de9-478a54305937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83102
3843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.831023843
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.127654769
Short name T500
Test name
Test status
Simulation time 319088308 ps
CPU time 0.98 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:27 PM PDT 24
Peak memory 206212 kb
Host smart-655bb69d-af4e-4d98-b005-a9e6db005b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12765
4769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.127654769
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2647043245
Short name T1857
Test name
Test status
Simulation time 4943115402 ps
CPU time 35.82 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206492 kb
Host smart-a4577737-6ffc-4589-bd9a-25ae040d0dc5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2647043245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2647043245
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1269944972
Short name T1782
Test name
Test status
Simulation time 168256114 ps
CPU time 0.86 seconds
Started Jul 04 06:11:27 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 206176 kb
Host smart-4e7d1349-4843-4d3c-9cd8-24f9b4dc2652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699
44972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1269944972
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.726377785
Short name T2408
Test name
Test status
Simulation time 147798298 ps
CPU time 0.75 seconds
Started Jul 04 06:11:25 PM PDT 24
Finished Jul 04 06:11:26 PM PDT 24
Peak memory 206200 kb
Host smart-d0940af0-1009-474f-8679-8758d1a04684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72637
7785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.726377785
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.3034455697
Short name T648
Test name
Test status
Simulation time 1213609887 ps
CPU time 2.46 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206472 kb
Host smart-a2e4459d-c658-4996-ae07-53600a36fb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30344
55697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.3034455697
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3392734121
Short name T1322
Test name
Test status
Simulation time 6635254312 ps
CPU time 46.79 seconds
Started Jul 04 06:11:31 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206348 kb
Host smart-199ecd0a-3146-4cc8-9312-667edbcd489b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
34121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3392734121
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.4214635710
Short name T510
Test name
Test status
Simulation time 54219620 ps
CPU time 0.68 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206224 kb
Host smart-f1da2365-511d-41f1-85ac-b1e8e6a55cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4214635710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.4214635710
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.987477055
Short name T2019
Test name
Test status
Simulation time 3745530205 ps
CPU time 5.23 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:38 PM PDT 24
Peak memory 206288 kb
Host smart-a428d7b1-9ecd-47bf-84b5-21ea06e7ed02
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=987477055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.987477055
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1441581320
Short name T1382
Test name
Test status
Simulation time 13361739476 ps
CPU time 15.24 seconds
Started Jul 04 06:11:27 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206248 kb
Host smart-f707b058-663e-4904-b8dc-5346a0c79a29
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1441581320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1441581320
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2002460188
Short name T2637
Test name
Test status
Simulation time 23319777043 ps
CPU time 22.88 seconds
Started Jul 04 06:11:27 PM PDT 24
Finished Jul 04 06:11:50 PM PDT 24
Peak memory 206460 kb
Host smart-b074e2e8-0e0b-4e3f-8353-b6e341c86eec
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2002460188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2002460188
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3697373483
Short name T1701
Test name
Test status
Simulation time 143548526 ps
CPU time 0.77 seconds
Started Jul 04 06:11:28 PM PDT 24
Finished Jul 04 06:11:29 PM PDT 24
Peak memory 206196 kb
Host smart-44f3a2a0-ebd4-464f-b05d-26da2ccc4dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36973
73483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3697373483
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.607208030
Short name T1230
Test name
Test status
Simulation time 162031862 ps
CPU time 0.75 seconds
Started Jul 04 06:11:28 PM PDT 24
Finished Jul 04 06:11:29 PM PDT 24
Peak memory 206208 kb
Host smart-2b1dfe70-4a15-4398-ac10-5362a6f908e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60720
8030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.607208030
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2574080519
Short name T1118
Test name
Test status
Simulation time 393773108 ps
CPU time 1.27 seconds
Started Jul 04 06:11:31 PM PDT 24
Finished Jul 04 06:11:33 PM PDT 24
Peak memory 206104 kb
Host smart-6216b8ab-f57c-4084-bb11-4336658dade7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25740
80519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2574080519
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.649040834
Short name T161
Test name
Test status
Simulation time 1027462328 ps
CPU time 2.32 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 206424 kb
Host smart-4f2759ae-be7b-4830-b023-aa66305ac3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64904
0834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.649040834
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.4270690647
Short name T1511
Test name
Test status
Simulation time 12486987397 ps
CPU time 25.01 seconds
Started Jul 04 06:11:25 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206472 kb
Host smart-a2cd089e-03d3-46da-8b26-9964767a5b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42706
90647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.4270690647
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3675811733
Short name T2016
Test name
Test status
Simulation time 415040585 ps
CPU time 1.26 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:35 PM PDT 24
Peak memory 206204 kb
Host smart-249b3d17-e7da-4ecd-87dc-3b07cfc97bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36758
11733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3675811733
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3158213431
Short name T1092
Test name
Test status
Simulation time 162124524 ps
CPU time 0.77 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:27 PM PDT 24
Peak memory 206208 kb
Host smart-fef5b94b-89a9-48c7-a84d-e38c2935a41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
13431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3158213431
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3551923055
Short name T259
Test name
Test status
Simulation time 40734780 ps
CPU time 0.68 seconds
Started Jul 04 06:11:25 PM PDT 24
Finished Jul 04 06:11:26 PM PDT 24
Peak memory 206116 kb
Host smart-3bc3fcc2-f87d-4801-aecf-42c5c36cb890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
23055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3551923055
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2736334458
Short name T997
Test name
Test status
Simulation time 961912639 ps
CPU time 2.25 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 206396 kb
Host smart-b8445577-89df-4571-8db1-784e02b84a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27363
34458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2736334458
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3950998687
Short name T2545
Test name
Test status
Simulation time 180945018 ps
CPU time 1.68 seconds
Started Jul 04 06:11:26 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 206364 kb
Host smart-630f3858-e37c-4283-82a7-be6d25114fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
98687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3950998687
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.982061332
Short name T1463
Test name
Test status
Simulation time 205118991 ps
CPU time 0.91 seconds
Started Jul 04 06:11:27 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 206196 kb
Host smart-49ae7e8d-235a-4fc3-a80e-810d5b218b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98206
1332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.982061332
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4034738405
Short name T715
Test name
Test status
Simulation time 135471609 ps
CPU time 0.76 seconds
Started Jul 04 06:11:27 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 206208 kb
Host smart-771560a3-2904-432f-94b1-d3a07ae974c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347
38405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4034738405
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.292813680
Short name T2530
Test name
Test status
Simulation time 234031868 ps
CPU time 0.94 seconds
Started Jul 04 06:11:30 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 206124 kb
Host smart-c6a9f6f5-828e-438a-8553-3ed492845b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29281
3680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.292813680
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.406427530
Short name T2078
Test name
Test status
Simulation time 267509358 ps
CPU time 1.04 seconds
Started Jul 04 06:11:28 PM PDT 24
Finished Jul 04 06:11:29 PM PDT 24
Peak memory 206172 kb
Host smart-ef340044-28cd-47e5-9bf6-22330b2a88c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
7530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.406427530
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.356919318
Short name T34
Test name
Test status
Simulation time 23381228102 ps
CPU time 27.24 seconds
Started Jul 04 06:11:31 PM PDT 24
Finished Jul 04 06:11:59 PM PDT 24
Peak memory 206204 kb
Host smart-6416f2e6-0665-477b-84b4-ff6b981189b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35691
9318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.356919318
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.770161658
Short name T2336
Test name
Test status
Simulation time 3349800609 ps
CPU time 4.03 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:37 PM PDT 24
Peak memory 206268 kb
Host smart-db08352f-7c5b-4af7-b407-c034c5e2ba48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77016
1658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.770161658
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.4175035455
Short name T2352
Test name
Test status
Simulation time 6212297184 ps
CPU time 153.87 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206536 kb
Host smart-f50f236f-a947-43f2-9094-e6bf5ec15434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41750
35455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.4175035455
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2500987702
Short name T817
Test name
Test status
Simulation time 5230090883 ps
CPU time 133.83 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206452 kb
Host smart-71538ce5-75aa-4ad4-b1fc-92dcef1d2f11
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2500987702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2500987702
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3776520261
Short name T1764
Test name
Test status
Simulation time 303826349 ps
CPU time 0.91 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206208 kb
Host smart-be66e12d-29c0-4430-98a8-ef380fe3cff7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3776520261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3776520261
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3486364915
Short name T2575
Test name
Test status
Simulation time 231568268 ps
CPU time 0.88 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206176 kb
Host smart-7a887185-0845-4aed-a81d-3596e8d6b754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
64915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3486364915
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1028871078
Short name T328
Test name
Test status
Simulation time 3736916893 ps
CPU time 28.64 seconds
Started Jul 04 06:11:35 PM PDT 24
Finished Jul 04 06:12:04 PM PDT 24
Peak memory 206484 kb
Host smart-a90b257b-2992-4350-aa13-31b570e5ae80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10288
71078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1028871078
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1307501969
Short name T994
Test name
Test status
Simulation time 5531558720 ps
CPU time 155.91 seconds
Started Jul 04 06:11:35 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206448 kb
Host smart-6cf9434a-5409-4750-aab7-5c6c22a6160d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1307501969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1307501969
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.4109849132
Short name T1070
Test name
Test status
Simulation time 164957294 ps
CPU time 0.8 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:11:33 PM PDT 24
Peak memory 206180 kb
Host smart-035139a3-26cc-46c1-b657-69c2c8cea7b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4109849132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.4109849132
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3741811691
Short name T2662
Test name
Test status
Simulation time 139976673 ps
CPU time 0.78 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206180 kb
Host smart-1ac015d1-d9b4-496b-859b-84f8f14cc415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
11691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3741811691
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.304685907
Short name T1725
Test name
Test status
Simulation time 229791604 ps
CPU time 0.89 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:35 PM PDT 24
Peak memory 206196 kb
Host smart-7a920ea5-881e-49e2-bda7-97629440ecac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
5907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.304685907
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3594937865
Short name T695
Test name
Test status
Simulation time 147210130 ps
CPU time 0.77 seconds
Started Jul 04 06:11:34 PM PDT 24
Finished Jul 04 06:11:35 PM PDT 24
Peak memory 206184 kb
Host smart-3d8e6cd3-1d38-4016-a7ee-b115ea4d52ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
37865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3594937865
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.521104107
Short name T914
Test name
Test status
Simulation time 157686611 ps
CPU time 0.77 seconds
Started Jul 04 06:11:39 PM PDT 24
Finished Jul 04 06:11:40 PM PDT 24
Peak memory 206224 kb
Host smart-e7ef0d51-180d-471e-aa38-806a8917ad03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52110
4107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.521104107
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1526070113
Short name T2518
Test name
Test status
Simulation time 183310714 ps
CPU time 0.88 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:11:33 PM PDT 24
Peak memory 206128 kb
Host smart-5edbff10-a83b-477e-9205-81dee5299fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15260
70113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1526070113
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2301782961
Short name T652
Test name
Test status
Simulation time 147608778 ps
CPU time 0.78 seconds
Started Jul 04 06:11:31 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 206200 kb
Host smart-6fb349b9-1f91-4a14-985a-0c97646ed005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23017
82961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2301782961
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2288391564
Short name T2471
Test name
Test status
Simulation time 247620345 ps
CPU time 0.95 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:35 PM PDT 24
Peak memory 206184 kb
Host smart-ae279879-1576-4f17-b6a1-7a59009501d8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2288391564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2288391564
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.4065911532
Short name T1460
Test name
Test status
Simulation time 160521749 ps
CPU time 0.76 seconds
Started Jul 04 06:11:34 PM PDT 24
Finished Jul 04 06:11:35 PM PDT 24
Peak memory 206188 kb
Host smart-e24be158-20e8-4e76-88a8-fe9dce17beba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40659
11532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.4065911532
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.718033540
Short name T1111
Test name
Test status
Simulation time 31607501 ps
CPU time 0.68 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206212 kb
Host smart-bccbf3df-9079-429f-8dc1-7341f1f6bc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71803
3540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.718033540
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2454118416
Short name T2309
Test name
Test status
Simulation time 10003207302 ps
CPU time 26.79 seconds
Started Jul 04 06:11:39 PM PDT 24
Finished Jul 04 06:12:06 PM PDT 24
Peak memory 206520 kb
Host smart-a6a6ea58-a162-42b1-936f-d635bc4d2848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24541
18416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2454118416
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1345845215
Short name T386
Test name
Test status
Simulation time 181236436 ps
CPU time 0.87 seconds
Started Jul 04 06:11:44 PM PDT 24
Finished Jul 04 06:11:45 PM PDT 24
Peak memory 206208 kb
Host smart-b717d30a-b9c9-47c5-9b36-d51379897910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
45215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1345845215
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2067013532
Short name T1637
Test name
Test status
Simulation time 224272847 ps
CPU time 0.87 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:11:33 PM PDT 24
Peak memory 206208 kb
Host smart-dd4e02e9-688c-454c-b05f-591b3369a245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20670
13532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2067013532
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2977042785
Short name T470
Test name
Test status
Simulation time 167175679 ps
CPU time 0.84 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206224 kb
Host smart-a674ae7a-85b2-4a7d-8db4-717db67d7210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29770
42785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2977042785
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2088518376
Short name T574
Test name
Test status
Simulation time 152215912 ps
CPU time 0.8 seconds
Started Jul 04 06:11:35 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 206172 kb
Host smart-9d4f5ff8-1bff-4b73-be71-6a9344d944a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20885
18376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2088518376
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.603285175
Short name T2404
Test name
Test status
Simulation time 169166450 ps
CPU time 0.81 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206168 kb
Host smart-5dbdd573-5dd9-4f5b-b2cb-3fa372099dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60328
5175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.603285175
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.790862938
Short name T611
Test name
Test status
Simulation time 150140592 ps
CPU time 0.75 seconds
Started Jul 04 06:11:35 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 206208 kb
Host smart-f7306126-7fe8-47f0-8d95-f203ec25d38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79086
2938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.790862938
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.79030037
Short name T2329
Test name
Test status
Simulation time 203162503 ps
CPU time 0.79 seconds
Started Jul 04 06:11:31 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 206212 kb
Host smart-24310d8d-85d8-4276-9705-db298c580d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79030
037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.79030037
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2503506468
Short name T1865
Test name
Test status
Simulation time 317812167 ps
CPU time 0.96 seconds
Started Jul 04 06:11:35 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 206188 kb
Host smart-069e8319-d2f1-4f6a-a655-39806206ebf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25035
06468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2503506468
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.54863127
Short name T1076
Test name
Test status
Simulation time 4765450364 ps
CPU time 46.05 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206484 kb
Host smart-cbcc09fe-c877-4472-948b-e4b8b01296cf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=54863127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.54863127
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.105789155
Short name T1165
Test name
Test status
Simulation time 197149431 ps
CPU time 0.83 seconds
Started Jul 04 06:11:35 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 206212 kb
Host smart-dd9622f0-111f-4292-a6d5-a02b7a20748f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10578
9155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.105789155
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.384751646
Short name T24
Test name
Test status
Simulation time 189628059 ps
CPU time 0.84 seconds
Started Jul 04 06:11:32 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206188 kb
Host smart-32663043-b8e1-4eff-8469-081cf5eda720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38475
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.384751646
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3092924780
Short name T2179
Test name
Test status
Simulation time 1035491955 ps
CPU time 2.23 seconds
Started Jul 04 06:11:33 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 206420 kb
Host smart-27836a8b-fdb9-45bb-a8c9-51de3c021c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
24780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3092924780
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.811772728
Short name T2070
Test name
Test status
Simulation time 6446547829 ps
CPU time 180.85 seconds
Started Jul 04 06:11:34 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206540 kb
Host smart-4f328b9b-ade4-4a96-9484-fb63034a5704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81177
2728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.811772728
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3992854341
Short name T1283
Test name
Test status
Simulation time 46699660 ps
CPU time 0.72 seconds
Started Jul 04 06:11:55 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206240 kb
Host smart-6e8e6829-f054-4422-8fbd-1158bd66b030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3992854341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3992854341
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2692079922
Short name T731
Test name
Test status
Simulation time 4542333544 ps
CPU time 6.21 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:11:46 PM PDT 24
Peak memory 206436 kb
Host smart-7c91b5ae-9663-40ea-89d0-187681d9e4e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2692079922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2692079922
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2145921643
Short name T2100
Test name
Test status
Simulation time 13328663053 ps
CPU time 14.4 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206264 kb
Host smart-ffb6ad52-47b3-42f6-bf86-34e7bea1967c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2145921643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2145921643
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3967651407
Short name T1568
Test name
Test status
Simulation time 23436019296 ps
CPU time 26.08 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206244 kb
Host smart-dcac33d2-acbd-4613-938c-aa444474310d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3967651407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.3967651407
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3896869092
Short name T824
Test name
Test status
Simulation time 160520930 ps
CPU time 0.79 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206188 kb
Host smart-f16f71ee-8f18-48cb-b203-57146aa94dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
69092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3896869092
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1167949293
Short name T1771
Test name
Test status
Simulation time 151027270 ps
CPU time 0.74 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206204 kb
Host smart-4f62b3c1-68de-41ba-bed0-63984ea67f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11679
49293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1167949293
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3737050930
Short name T2640
Test name
Test status
Simulation time 505371978 ps
CPU time 1.55 seconds
Started Jul 04 06:11:44 PM PDT 24
Finished Jul 04 06:11:46 PM PDT 24
Peak memory 206452 kb
Host smart-06e6704a-eb44-4563-b08f-36c612b12a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37370
50930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3737050930
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2835698304
Short name T111
Test name
Test status
Simulation time 689420745 ps
CPU time 1.65 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206408 kb
Host smart-2a0f30ba-a5e0-445d-81e8-ac7e131d2e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28356
98304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2835698304
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1689830975
Short name T198
Test name
Test status
Simulation time 13503271738 ps
CPU time 25.21 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:12:07 PM PDT 24
Peak memory 206464 kb
Host smart-a46586c6-9455-4e5a-9e1f-2361ae890173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
30975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1689830975
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.213879480
Short name T1086
Test name
Test status
Simulation time 464932201 ps
CPU time 1.32 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:11:42 PM PDT 24
Peak memory 206152 kb
Host smart-e8a24d74-d261-4534-bd37-8bfa72961885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21387
9480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.213879480
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.325658622
Short name T661
Test name
Test status
Simulation time 131177253 ps
CPU time 0.77 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206204 kb
Host smart-4c660ec6-9a96-4509-8d8d-2064341ff765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32565
8622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.325658622
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.236317370
Short name T1074
Test name
Test status
Simulation time 37002149 ps
CPU time 0.67 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206168 kb
Host smart-ee85bbe4-3237-4ea7-80b5-c024161193dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
7370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.236317370
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3021800405
Short name T2012
Test name
Test status
Simulation time 997968236 ps
CPU time 2.41 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206496 kb
Host smart-afa5d39c-b025-4c9f-8203-b7f09cf4ded2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30218
00405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3021800405
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4223665393
Short name T2617
Test name
Test status
Simulation time 209701654 ps
CPU time 1.87 seconds
Started Jul 04 06:11:44 PM PDT 24
Finished Jul 04 06:11:46 PM PDT 24
Peak memory 206400 kb
Host smart-66d1fa56-96ae-4c6e-8195-cf5d17ac2611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42236
65393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4223665393
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.929551467
Short name T1498
Test name
Test status
Simulation time 218158649 ps
CPU time 0.86 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:11:42 PM PDT 24
Peak memory 206192 kb
Host smart-bb8c16a6-7a71-4aeb-b2f8-800a5bc04796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92955
1467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.929551467
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2308116272
Short name T1041
Test name
Test status
Simulation time 151908266 ps
CPU time 0.75 seconds
Started Jul 04 06:11:44 PM PDT 24
Finished Jul 04 06:11:45 PM PDT 24
Peak memory 206204 kb
Host smart-e67a3ab2-f2f7-4bc6-917c-8aca66a1ffcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23081
16272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2308116272
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1498027150
Short name T1800
Test name
Test status
Simulation time 233475124 ps
CPU time 0.89 seconds
Started Jul 04 06:11:44 PM PDT 24
Finished Jul 04 06:11:45 PM PDT 24
Peak memory 206124 kb
Host smart-07736750-9735-4895-8f08-3d5ac5127a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
27150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1498027150
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1336959356
Short name T1206
Test name
Test status
Simulation time 6825338921 ps
CPU time 50.09 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:12:32 PM PDT 24
Peak memory 206432 kb
Host smart-ff4107a2-5775-483c-9fc2-36a00c50ebd6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1336959356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1336959356
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1957683987
Short name T1772
Test name
Test status
Simulation time 250669976 ps
CPU time 0.87 seconds
Started Jul 04 06:11:39 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206212 kb
Host smart-b5089b9b-5d20-4f1a-929b-4268a4cb9e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
83987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1957683987
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.2091478639
Short name T1925
Test name
Test status
Simulation time 23268924174 ps
CPU time 20.9 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:12:02 PM PDT 24
Peak memory 206264 kb
Host smart-5f508d07-a24d-4045-b057-666bbdd69163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20914
78639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.2091478639
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.412197159
Short name T2524
Test name
Test status
Simulation time 3350974417 ps
CPU time 3.83 seconds
Started Jul 04 06:11:39 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206236 kb
Host smart-29684552-d014-4abf-b796-26bc046c123b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41219
7159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.412197159
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2919636020
Short name T2010
Test name
Test status
Simulation time 11735744607 ps
CPU time 82.63 seconds
Started Jul 04 06:11:39 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206536 kb
Host smart-b798dc92-a60e-41c8-8c5b-f02e293f1e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29196
36020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2919636020
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2720634953
Short name T591
Test name
Test status
Simulation time 3143037967 ps
CPU time 30.12 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:12:11 PM PDT 24
Peak memory 206440 kb
Host smart-cc81538a-f274-47e0-910c-2697941cfabd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2720634953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2720634953
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1810154934
Short name T1689
Test name
Test status
Simulation time 242403531 ps
CPU time 0.96 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:11:42 PM PDT 24
Peak memory 206188 kb
Host smart-56977ab8-9fc2-43de-967f-ae9278a2bc31
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1810154934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1810154934
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3880714887
Short name T2005
Test name
Test status
Simulation time 260401029 ps
CPU time 0.97 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206192 kb
Host smart-f6696253-4925-4c08-af6b-dddf93382515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38807
14887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3880714887
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2340867626
Short name T1148
Test name
Test status
Simulation time 4593997194 ps
CPU time 129.67 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:13:50 PM PDT 24
Peak memory 206412 kb
Host smart-7673f9e8-a760-44e6-959c-432def0e3d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
67626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2340867626
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3297649128
Short name T446
Test name
Test status
Simulation time 6823724789 ps
CPU time 53.22 seconds
Started Jul 04 06:11:41 PM PDT 24
Finished Jul 04 06:12:34 PM PDT 24
Peak memory 206452 kb
Host smart-7dcd9c92-7392-4c4f-b70c-7caadbcb7aec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3297649128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3297649128
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1530429978
Short name T2594
Test name
Test status
Simulation time 167255337 ps
CPU time 0.8 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206148 kb
Host smart-2733ca60-4989-4d9c-8f91-ab7ae96cd00e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1530429978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1530429978
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3239335421
Short name T665
Test name
Test status
Simulation time 206254096 ps
CPU time 0.84 seconds
Started Jul 04 06:11:40 PM PDT 24
Finished Jul 04 06:11:41 PM PDT 24
Peak memory 206212 kb
Host smart-c54ec296-aaab-48b7-94ea-a7179aeac707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32393
35421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3239335421
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2123552033
Short name T1432
Test name
Test status
Simulation time 229227311 ps
CPU time 0.86 seconds
Started Jul 04 06:11:44 PM PDT 24
Finished Jul 04 06:11:45 PM PDT 24
Peak memory 206208 kb
Host smart-536542d4-7288-481b-b2ef-ba904f9b4eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21235
52033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2123552033
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3435181486
Short name T871
Test name
Test status
Simulation time 178199457 ps
CPU time 0.85 seconds
Started Jul 04 06:11:42 PM PDT 24
Finished Jul 04 06:11:43 PM PDT 24
Peak memory 206216 kb
Host smart-3dcfe5c2-2b79-4754-b605-754107ba7e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351
81486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3435181486
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2119780415
Short name T1887
Test name
Test status
Simulation time 173891970 ps
CPU time 0.85 seconds
Started Jul 04 06:11:55 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206176 kb
Host smart-e9e519d3-cc7a-4148-9a13-26f0452f67b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21197
80415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2119780415
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2824159412
Short name T783
Test name
Test status
Simulation time 170829646 ps
CPU time 0.79 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206144 kb
Host smart-0c805d7c-d096-4c5f-9623-899427612a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28241
59412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2824159412
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3946593938
Short name T1430
Test name
Test status
Simulation time 153985890 ps
CPU time 0.8 seconds
Started Jul 04 06:11:56 PM PDT 24
Finished Jul 04 06:11:57 PM PDT 24
Peak memory 206188 kb
Host smart-cc778293-d825-4be5-bd7f-a3998dadf864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
93938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3946593938
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1777257799
Short name T1000
Test name
Test status
Simulation time 197089094 ps
CPU time 0.91 seconds
Started Jul 04 06:11:54 PM PDT 24
Finished Jul 04 06:11:55 PM PDT 24
Peak memory 206168 kb
Host smart-82f04c06-514f-46e9-bbe8-be0dabc4339f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1777257799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1777257799
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.451919439
Short name T592
Test name
Test status
Simulation time 162702904 ps
CPU time 0.75 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206192 kb
Host smart-6c006c67-a981-4dd4-bdef-46f67a71eb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45191
9439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.451919439
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3544719164
Short name T1624
Test name
Test status
Simulation time 34313072 ps
CPU time 0.65 seconds
Started Jul 04 06:11:55 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206200 kb
Host smart-6f5ab308-8f16-4039-8b61-7b700b9ea9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
19164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3544719164
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.798584743
Short name T1785
Test name
Test status
Simulation time 22390698303 ps
CPU time 53.1 seconds
Started Jul 04 06:11:51 PM PDT 24
Finished Jul 04 06:12:44 PM PDT 24
Peak memory 206552 kb
Host smart-b20b0d0d-d19c-4f68-b77f-14170531bc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79858
4743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.798584743
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.604061348
Short name T1911
Test name
Test status
Simulation time 186910602 ps
CPU time 0.8 seconds
Started Jul 04 06:11:51 PM PDT 24
Finished Jul 04 06:11:52 PM PDT 24
Peak memory 206192 kb
Host smart-8efadea2-8484-4813-bdda-802e9d8749a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60406
1348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.604061348
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.166698699
Short name T1688
Test name
Test status
Simulation time 235837604 ps
CPU time 0.85 seconds
Started Jul 04 06:11:55 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206172 kb
Host smart-0c8aeb6a-d66a-4b71-aa77-a42045053550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
8699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.166698699
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.4002700992
Short name T495
Test name
Test status
Simulation time 190434534 ps
CPU time 0.82 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206180 kb
Host smart-9a4c9995-d784-4395-a37a-f13d1a20a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40027
00992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.4002700992
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.410206797
Short name T2527
Test name
Test status
Simulation time 190687556 ps
CPU time 0.84 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206208 kb
Host smart-97ae8149-ec73-4462-a894-dc1bfecd95d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41020
6797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.410206797
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2308684295
Short name T1844
Test name
Test status
Simulation time 157130959 ps
CPU time 0.81 seconds
Started Jul 04 06:11:52 PM PDT 24
Finished Jul 04 06:11:53 PM PDT 24
Peak memory 206208 kb
Host smart-4b02ff98-f999-435f-b5b4-33c4b9fb09be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
84295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2308684295
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.250981929
Short name T1514
Test name
Test status
Simulation time 152793353 ps
CPU time 0.77 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206172 kb
Host smart-41a60fb6-9d04-420d-a78f-838c1f953142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25098
1929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.250981929
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.700432728
Short name T961
Test name
Test status
Simulation time 158628635 ps
CPU time 0.81 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206176 kb
Host smart-7b1d2572-d61d-46a1-9678-3a21d57466ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70043
2728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.700432728
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2465896578
Short name T336
Test name
Test status
Simulation time 215445579 ps
CPU time 0.94 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206188 kb
Host smart-b1c1ec8c-b124-4b2d-ab7f-d81d23fd5bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
96578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2465896578
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1531273755
Short name T159
Test name
Test status
Simulation time 4568750631 ps
CPU time 129.29 seconds
Started Jul 04 06:11:54 PM PDT 24
Finished Jul 04 06:14:03 PM PDT 24
Peak memory 206512 kb
Host smart-f1d8c4dd-1b7d-4f29-9ee4-a4345c6454b5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1531273755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1531273755
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.4229033234
Short name T2137
Test name
Test status
Simulation time 151323910 ps
CPU time 0.75 seconds
Started Jul 04 06:11:53 PM PDT 24
Finished Jul 04 06:11:54 PM PDT 24
Peak memory 206164 kb
Host smart-90c52abf-6afe-4456-bee0-d7a2af1757e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42290
33234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4229033234
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3393115347
Short name T357
Test name
Test status
Simulation time 191666325 ps
CPU time 0.91 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206224 kb
Host smart-ac7385c8-3884-468b-9eb1-f4c261cfed43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33931
15347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3393115347
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.51359273
Short name T17
Test name
Test status
Simulation time 741567006 ps
CPU time 2.01 seconds
Started Jul 04 06:11:54 PM PDT 24
Finished Jul 04 06:11:56 PM PDT 24
Peak memory 206420 kb
Host smart-2ae2e5cc-5bd8-441e-97b0-1467ddacf54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51359
273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.51359273
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3463188465
Short name T2081
Test name
Test status
Simulation time 5882752287 ps
CPU time 45.74 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206456 kb
Host smart-b29ced82-4a40-4155-a989-68bdf22fda99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
88465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3463188465
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3548849362
Short name T1678
Test name
Test status
Simulation time 38301879 ps
CPU time 0.67 seconds
Started Jul 04 06:12:04 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206260 kb
Host smart-7fc414ab-d924-4717-8a7f-bbad520c001b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3548849362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3548849362
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.492900240
Short name T822
Test name
Test status
Simulation time 3791503046 ps
CPU time 4.37 seconds
Started Jul 04 06:11:53 PM PDT 24
Finished Jul 04 06:11:57 PM PDT 24
Peak memory 206272 kb
Host smart-2c19d3c7-6a29-46ce-a071-369fb90c6c09
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=492900240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.492900240
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.398475106
Short name T1860
Test name
Test status
Simulation time 13362327696 ps
CPU time 13.52 seconds
Started Jul 04 06:11:52 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206236 kb
Host smart-00ae6e3d-ba0c-49d8-855b-e921d25eb8d8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=398475106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.398475106
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1333530511
Short name T839
Test name
Test status
Simulation time 168217283 ps
CPU time 0.79 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:52 PM PDT 24
Peak memory 206200 kb
Host smart-4cc3e36d-ecd9-4656-b2a0-34714172c7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13335
30511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1333530511
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3646968537
Short name T2452
Test name
Test status
Simulation time 150131589 ps
CPU time 0.76 seconds
Started Jul 04 06:11:50 PM PDT 24
Finished Jul 04 06:11:51 PM PDT 24
Peak memory 206208 kb
Host smart-f8f54734-5f74-4e53-9ddb-906a03293173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36469
68537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3646968537
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.163745676
Short name T1354
Test name
Test status
Simulation time 470867238 ps
CPU time 1.49 seconds
Started Jul 04 06:11:52 PM PDT 24
Finished Jul 04 06:11:54 PM PDT 24
Peak memory 206200 kb
Host smart-ecc722b3-09f9-414c-9b7c-3394083999fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16374
5676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.163745676
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2784227396
Short name T2286
Test name
Test status
Simulation time 1393915610 ps
CPU time 2.94 seconds
Started Jul 04 06:11:55 PM PDT 24
Finished Jul 04 06:11:58 PM PDT 24
Peak memory 206420 kb
Host smart-0e3b6ad5-77bb-4a56-82d1-61bcf1daaf85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27842
27396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2784227396
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1390130864
Short name T113
Test name
Test status
Simulation time 9877985875 ps
CPU time 21.47 seconds
Started Jul 04 06:11:56 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206464 kb
Host smart-27838ab5-57b4-45c2-aca4-75fbb9f3e222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13901
30864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1390130864
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3128525558
Short name T1218
Test name
Test status
Simulation time 421411229 ps
CPU time 1.35 seconds
Started Jul 04 06:11:51 PM PDT 24
Finished Jul 04 06:11:53 PM PDT 24
Peak memory 206188 kb
Host smart-775a3b15-bc1b-4140-8d21-090ba4265c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31285
25558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3128525558
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1217190672
Short name T2386
Test name
Test status
Simulation time 137265587 ps
CPU time 0.8 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:03 PM PDT 24
Peak memory 206168 kb
Host smart-5c586c75-7e16-4648-b0c9-50ef93bdb2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12171
90672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1217190672
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.464244946
Short name T438
Test name
Test status
Simulation time 42079355 ps
CPU time 0.7 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206188 kb
Host smart-19eafec1-eec9-47b1-8640-4011b069e5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46424
4946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.464244946
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.24145222
Short name T1318
Test name
Test status
Simulation time 1014037189 ps
CPU time 2.71 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:08 PM PDT 24
Peak memory 206420 kb
Host smart-c0e7b1a3-0f35-4427-a7bc-c02541b58d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24145
222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.24145222
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2526269732
Short name T1648
Test name
Test status
Simulation time 193568825 ps
CPU time 2.38 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206404 kb
Host smart-58be3bac-1920-44cf-82f8-af06f4116468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25262
69732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2526269732
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.269289109
Short name T1847
Test name
Test status
Simulation time 168118453 ps
CPU time 0.84 seconds
Started Jul 04 06:11:58 PM PDT 24
Finished Jul 04 06:11:59 PM PDT 24
Peak memory 206144 kb
Host smart-b9110fbb-1300-40e0-b6d8-ffa117ce7962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
9109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.269289109
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3329883211
Short name T1108
Test name
Test status
Simulation time 146426228 ps
CPU time 0.82 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:03 PM PDT 24
Peak memory 206204 kb
Host smart-0e8b1171-87af-4cd5-9b36-8f059a70c7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33298
83211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3329883211
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1663751485
Short name T1792
Test name
Test status
Simulation time 245412997 ps
CPU time 0.97 seconds
Started Jul 04 06:12:03 PM PDT 24
Finished Jul 04 06:12:04 PM PDT 24
Peak memory 206208 kb
Host smart-ade9b12f-c295-4ecc-a1da-6719341736b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16637
51485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1663751485
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.4268816279
Short name T1807
Test name
Test status
Simulation time 6168613815 ps
CPU time 42.3 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:44 PM PDT 24
Peak memory 206520 kb
Host smart-c8a0c6e8-1106-414d-98c3-5ebb20b263da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4268816279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.4268816279
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3830063141
Short name T585
Test name
Test status
Simulation time 235091231 ps
CPU time 0.89 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:00 PM PDT 24
Peak memory 206180 kb
Host smart-0ebf70c0-c279-4fbb-b76f-660672e40446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38300
63141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3830063141
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.4001342662
Short name T1818
Test name
Test status
Simulation time 23303686689 ps
CPU time 21.72 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:27 PM PDT 24
Peak memory 206272 kb
Host smart-95194253-f07b-4980-b3a0-365e1ac7a47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40013
42662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.4001342662
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.569789187
Short name T915
Test name
Test status
Simulation time 3292350276 ps
CPU time 4.72 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:10 PM PDT 24
Peak memory 206272 kb
Host smart-fdd342bc-e76f-4256-abea-2308af03b457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56978
9187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.569789187
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.768821447
Short name T2665
Test name
Test status
Simulation time 13139557291 ps
CPU time 128.64 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206540 kb
Host smart-c6aff9c8-f8b5-43c3-b496-b96e0abd9e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76882
1447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.768821447
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.3424547958
Short name T1735
Test name
Test status
Simulation time 5560453101 ps
CPU time 40.01 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:39 PM PDT 24
Peak memory 206424 kb
Host smart-7274adcc-4326-4c3d-8d44-698121661b78
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3424547958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.3424547958
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3610289317
Short name T2044
Test name
Test status
Simulation time 238535029 ps
CPU time 0.92 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:03 PM PDT 24
Peak memory 206204 kb
Host smart-44428fbf-8a2a-4100-b1df-660a50bfe479
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3610289317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3610289317
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2378757307
Short name T2269
Test name
Test status
Simulation time 215457709 ps
CPU time 1 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:03 PM PDT 24
Peak memory 206184 kb
Host smart-e3a01a1a-8492-42c9-84fb-2fc626cac9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
57307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2378757307
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2223650654
Short name T1974
Test name
Test status
Simulation time 6014273245 ps
CPU time 43.77 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206488 kb
Host smart-81ceb3e2-2bf7-48a2-883c-9bd6635285db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22236
50654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2223650654
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3502375195
Short name T786
Test name
Test status
Simulation time 7482256010 ps
CPU time 71.92 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:13:11 PM PDT 24
Peak memory 206528 kb
Host smart-d48b8e38-ab37-4014-b2c7-bf433d4e695b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3502375195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3502375195
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.4170002236
Short name T605
Test name
Test status
Simulation time 164382839 ps
CPU time 0.8 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206172 kb
Host smart-dca3aa2a-d217-4428-b190-3494491899db
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4170002236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.4170002236
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.610434740
Short name T2634
Test name
Test status
Simulation time 149859350 ps
CPU time 0.89 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:00 PM PDT 24
Peak memory 206188 kb
Host smart-47d03843-4607-4318-ab5d-321576c11c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61043
4740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.610434740
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3894191004
Short name T2419
Test name
Test status
Simulation time 164837419 ps
CPU time 0.82 seconds
Started Jul 04 06:12:03 PM PDT 24
Finished Jul 04 06:12:04 PM PDT 24
Peak memory 206212 kb
Host smart-ecbf64a9-daf8-4af6-a563-f40c3d9544a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38941
91004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3894191004
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2155757310
Short name T1777
Test name
Test status
Simulation time 155484321 ps
CPU time 0.78 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:06 PM PDT 24
Peak memory 206224 kb
Host smart-eb875a15-9751-4f4a-b42c-b015183d8b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
57310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2155757310
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1305328190
Short name T784
Test name
Test status
Simulation time 223677578 ps
CPU time 0.87 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:06 PM PDT 24
Peak memory 206220 kb
Host smart-14e07446-cdf2-40e6-b775-ac51b4de0e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13053
28190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1305328190
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.389416959
Short name T179
Test name
Test status
Simulation time 159078549 ps
CPU time 0.8 seconds
Started Jul 04 06:12:04 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206180 kb
Host smart-fe1d1a67-aa7d-4e2c-abf3-7f23426ea9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38941
6959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.389416959
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2881517176
Short name T1939
Test name
Test status
Simulation time 241445909 ps
CPU time 1.08 seconds
Started Jul 04 06:12:04 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206216 kb
Host smart-9f86c8f3-3630-4087-aec5-be8bd1df4f91
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2881517176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2881517176
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1919823191
Short name T1576
Test name
Test status
Simulation time 161432298 ps
CPU time 0.78 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:00 PM PDT 24
Peak memory 206176 kb
Host smart-79ba2b5c-6b8b-491a-a618-db3ae7458ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
23191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1919823191
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1828033515
Short name T2223
Test name
Test status
Simulation time 41613161 ps
CPU time 0.73 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:03 PM PDT 24
Peak memory 206200 kb
Host smart-d37b3a3d-d451-468f-886a-2373c3f8f786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280
33515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1828033515
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.129983201
Short name T275
Test name
Test status
Simulation time 7697796069 ps
CPU time 17.26 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:20 PM PDT 24
Peak memory 206504 kb
Host smart-5d50c679-13aa-4bff-8e02-6e49cca5efc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12998
3201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.129983201
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2994540212
Short name T1796
Test name
Test status
Simulation time 163606475 ps
CPU time 0.8 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:00 PM PDT 24
Peak memory 206136 kb
Host smart-709edb4d-97ef-4ff3-ae87-2056a5a44f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
40212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2994540212
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1847688767
Short name T2682
Test name
Test status
Simulation time 219749854 ps
CPU time 0.96 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:02 PM PDT 24
Peak memory 206208 kb
Host smart-791995d8-9df8-4a83-8b5b-fc5771ea399e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
88767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1847688767
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3380958283
Short name T853
Test name
Test status
Simulation time 245584754 ps
CPU time 0.97 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:02 PM PDT 24
Peak memory 206212 kb
Host smart-00f8e64d-a829-4f5c-9bf0-f2e8d507087d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809
58283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3380958283
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3187586454
Short name T1232
Test name
Test status
Simulation time 163938700 ps
CPU time 0.8 seconds
Started Jul 04 06:11:58 PM PDT 24
Finished Jul 04 06:11:59 PM PDT 24
Peak memory 206216 kb
Host smart-0ad08ead-9aed-4fe3-93e2-3c6542d45b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31875
86454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3187586454
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2840399892
Short name T2446
Test name
Test status
Simulation time 182521438 ps
CPU time 0.85 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206212 kb
Host smart-299630c4-9bc5-4847-85a2-8d19e6032375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403
99892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2840399892
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3560405707
Short name T331
Test name
Test status
Simulation time 165384354 ps
CPU time 0.83 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206212 kb
Host smart-e34b8d73-9a4c-4bff-8608-df320ad727c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
05707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3560405707
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3871222809
Short name T455
Test name
Test status
Simulation time 174460315 ps
CPU time 0.81 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:00 PM PDT 24
Peak memory 206196 kb
Host smart-bce9cbfc-bbb4-45e4-b082-0830f676fd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
22809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3871222809
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3839848213
Short name T1366
Test name
Test status
Simulation time 263295749 ps
CPU time 0.98 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206164 kb
Host smart-095399ab-e82f-4a51-b2db-124de3e0eb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
48213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3839848213
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1957332150
Short name T2161
Test name
Test status
Simulation time 5609644799 ps
CPU time 54.01 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:59 PM PDT 24
Peak memory 206516 kb
Host smart-c67b3925-eb9b-4de8-bf14-9e18c4e77ded
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1957332150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1957332150
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3367442355
Short name T730
Test name
Test status
Simulation time 169257361 ps
CPU time 0.87 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:02 PM PDT 24
Peak memory 206180 kb
Host smart-6b20d9e0-deec-4ee2-a352-8e4095b585af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33674
42355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3367442355
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1370076542
Short name T1413
Test name
Test status
Simulation time 175828118 ps
CPU time 0.95 seconds
Started Jul 04 06:12:03 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206212 kb
Host smart-4aaaeb54-5991-4038-8e29-2ee037d04a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13700
76542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1370076542
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2941793945
Short name T2320
Test name
Test status
Simulation time 320457763 ps
CPU time 1.04 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206232 kb
Host smart-3492b775-7368-4bad-87c7-8a7a34f8c046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
93945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2941793945
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2232677050
Short name T2659
Test name
Test status
Simulation time 3665020469 ps
CPU time 107.16 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:13:48 PM PDT 24
Peak memory 206516 kb
Host smart-1a452abe-3f56-4378-b1bf-93d4195664db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
77050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2232677050
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.807492797
Short name T875
Test name
Test status
Simulation time 57621447 ps
CPU time 0.68 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206184 kb
Host smart-d5672291-8d36-4123-93e5-c7f811d893a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=807492797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.807492797
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1344306727
Short name T485
Test name
Test status
Simulation time 3464397465 ps
CPU time 4.19 seconds
Started Jul 04 06:12:05 PM PDT 24
Finished Jul 04 06:12:10 PM PDT 24
Peak memory 206156 kb
Host smart-dec40dd5-84f4-40e1-93f6-2363e18e0db6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1344306727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.1344306727
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3941928477
Short name T1908
Test name
Test status
Simulation time 13411401715 ps
CPU time 11.99 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:13 PM PDT 24
Peak memory 206268 kb
Host smart-e6f20458-aa64-45e2-8c1e-d195dbc92a24
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3941928477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3941928477
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1218176238
Short name T1881
Test name
Test status
Simulation time 23384420429 ps
CPU time 27.96 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:27 PM PDT 24
Peak memory 206284 kb
Host smart-a71c2190-8924-4fdc-a021-1cd36b2de295
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1218176238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1218176238
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3089477279
Short name T1610
Test name
Test status
Simulation time 159070010 ps
CPU time 0.81 seconds
Started Jul 04 06:11:59 PM PDT 24
Finished Jul 04 06:12:00 PM PDT 24
Peak memory 206172 kb
Host smart-36cf8a3d-ca31-4a64-8a8a-7c5e6b3c929f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30894
77279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3089477279
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.4676672
Short name T1195
Test name
Test status
Simulation time 145192814 ps
CPU time 0.82 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:02 PM PDT 24
Peak memory 206208 kb
Host smart-de583d91-e52c-4dc3-b9ae-1fb6e516ce9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46766
72 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.4676672
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3635644969
Short name T398
Test name
Test status
Simulation time 322938852 ps
CPU time 1.19 seconds
Started Jul 04 06:12:00 PM PDT 24
Finished Jul 04 06:12:01 PM PDT 24
Peak memory 206164 kb
Host smart-f7c6afa2-1e7d-41fd-bcb4-05ecdf758334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36356
44969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3635644969
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1296708752
Short name T162
Test name
Test status
Simulation time 760003178 ps
CPU time 1.84 seconds
Started Jul 04 06:12:03 PM PDT 24
Finished Jul 04 06:12:05 PM PDT 24
Peak memory 206460 kb
Host smart-c078f253-7ac4-4fb4-b7c3-8c427fb7f64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12967
08752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1296708752
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1795198456
Short name T1263
Test name
Test status
Simulation time 17435136570 ps
CPU time 30.93 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:33 PM PDT 24
Peak memory 206512 kb
Host smart-13d8b034-058b-4886-a216-16e110d0dda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17951
98456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1795198456
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1064147909
Short name T1175
Test name
Test status
Simulation time 371022230 ps
CPU time 1.25 seconds
Started Jul 04 06:12:02 PM PDT 24
Finished Jul 04 06:12:04 PM PDT 24
Peak memory 206212 kb
Host smart-001ede9d-f6f4-45d8-a8f2-80890b49a263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
47909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1064147909
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1567350697
Short name T892
Test name
Test status
Simulation time 138434822 ps
CPU time 0.82 seconds
Started Jul 04 06:12:01 PM PDT 24
Finished Jul 04 06:12:02 PM PDT 24
Peak memory 206144 kb
Host smart-217c3a9e-de99-443e-a121-3515bd0615e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
50697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1567350697
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4033382761
Short name T1562
Test name
Test status
Simulation time 50399153 ps
CPU time 0.68 seconds
Started Jul 04 06:12:06 PM PDT 24
Finished Jul 04 06:12:07 PM PDT 24
Peak memory 206168 kb
Host smart-3fada832-1c16-42f4-b17a-edb0094e562d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333
82761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4033382761
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.670825831
Short name T384
Test name
Test status
Simulation time 912333104 ps
CPU time 2.25 seconds
Started Jul 04 06:12:08 PM PDT 24
Finished Jul 04 06:12:10 PM PDT 24
Peak memory 206368 kb
Host smart-427722c0-d943-4996-82d5-709627430cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67082
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.670825831
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3051264640
Short name T691
Test name
Test status
Simulation time 210895359 ps
CPU time 1.29 seconds
Started Jul 04 06:12:10 PM PDT 24
Finished Jul 04 06:12:12 PM PDT 24
Peak memory 206352 kb
Host smart-e4b4792b-1684-498e-afa5-cc6fd97e957b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30512
64640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3051264640
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3337619500
Short name T2087
Test name
Test status
Simulation time 193742750 ps
CPU time 0.86 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206196 kb
Host smart-7d25a418-fd5f-4dc8-b09d-d2421e39a7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33376
19500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3337619500
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.440986186
Short name T1896
Test name
Test status
Simulation time 139542341 ps
CPU time 0.77 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:16 PM PDT 24
Peak memory 206208 kb
Host smart-6f378e47-135a-4f59-876f-e985bc98c9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44098
6186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.440986186
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3470866035
Short name T712
Test name
Test status
Simulation time 218372804 ps
CPU time 0.9 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:15 PM PDT 24
Peak memory 206212 kb
Host smart-35d275cb-fb74-4060-939f-188fa5ce2b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
66035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3470866035
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2810467090
Short name T105
Test name
Test status
Simulation time 9180027654 ps
CPU time 66.91 seconds
Started Jul 04 06:12:11 PM PDT 24
Finished Jul 04 06:13:18 PM PDT 24
Peak memory 206484 kb
Host smart-5c95bcd9-cee9-4e45-905b-a3db85e50967
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2810467090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2810467090
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1616582285
Short name T1013
Test name
Test status
Simulation time 294253912 ps
CPU time 0.96 seconds
Started Jul 04 06:12:08 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206212 kb
Host smart-e795697c-af81-4268-a5b0-e99941f12865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16165
82285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1616582285
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.249524437
Short name T645
Test name
Test status
Simulation time 23307004949 ps
CPU time 21.84 seconds
Started Jul 04 06:12:07 PM PDT 24
Finished Jul 04 06:12:29 PM PDT 24
Peak memory 206256 kb
Host smart-2c8dbb64-bd47-4f69-929d-d17be2d4783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
4437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.249524437
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2635643063
Short name T1793
Test name
Test status
Simulation time 3272997800 ps
CPU time 3.77 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206248 kb
Host smart-4a1320ba-9585-4a5e-8eb3-1b05f8b9d1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356
43063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2635643063
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3716598512
Short name T2436
Test name
Test status
Simulation time 9058011520 ps
CPU time 82.82 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:13:37 PM PDT 24
Peak memory 206460 kb
Host smart-be3f636d-56ad-4e6d-ae8c-f4f20563731f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37165
98512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3716598512
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.95080627
Short name T2653
Test name
Test status
Simulation time 5877662163 ps
CPU time 56.14 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:13:13 PM PDT 24
Peak memory 206524 kb
Host smart-d0af3f1e-231e-4932-b82d-bc3406e51109
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=95080627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.95080627
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1041339086
Short name T2412
Test name
Test status
Simulation time 249869065 ps
CPU time 0.92 seconds
Started Jul 04 06:12:08 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206192 kb
Host smart-52d63b8d-c526-4ae6-a00e-8424685141ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1041339086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1041339086
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.754704384
Short name T1107
Test name
Test status
Simulation time 197716011 ps
CPU time 1.07 seconds
Started Jul 04 06:12:10 PM PDT 24
Finished Jul 04 06:12:12 PM PDT 24
Peak memory 206180 kb
Host smart-4007cd84-866e-4cf4-bc59-53996da8c267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75470
4384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.754704384
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1588526147
Short name T346
Test name
Test status
Simulation time 5202627533 ps
CPU time 140.38 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206408 kb
Host smart-bc9930eb-9eee-44ff-a735-ed0b446e3800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15885
26147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1588526147
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3225878211
Short name T2280
Test name
Test status
Simulation time 4671942480 ps
CPU time 135.18 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:14:30 PM PDT 24
Peak memory 206396 kb
Host smart-c369ef35-d52d-47c8-9029-6fad91c0e73e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3225878211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3225878211
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.98789248
Short name T911
Test name
Test status
Simulation time 172833563 ps
CPU time 0.81 seconds
Started Jul 04 06:12:08 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206176 kb
Host smart-0f9f7953-85f3-4d0b-9919-288ec5b56add
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=98789248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.98789248
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2551490663
Short name T2113
Test name
Test status
Simulation time 139319746 ps
CPU time 0.82 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206192 kb
Host smart-696fd412-dc28-410d-900f-2ee296cf03cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514
90663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2551490663
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.201361557
Short name T788
Test name
Test status
Simulation time 176170665 ps
CPU time 0.79 seconds
Started Jul 04 06:12:07 PM PDT 24
Finished Jul 04 06:12:08 PM PDT 24
Peak memory 206108 kb
Host smart-4d94216a-67ae-471d-8682-0121c674e4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20136
1557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.201361557
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1966792471
Short name T760
Test name
Test status
Simulation time 188997456 ps
CPU time 0.82 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:16 PM PDT 24
Peak memory 206200 kb
Host smart-2f56ccf7-c717-4147-a2dd-22fe8da8e6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19667
92471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1966792471
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2939952918
Short name T859
Test name
Test status
Simulation time 174226551 ps
CPU time 0.81 seconds
Started Jul 04 06:12:13 PM PDT 24
Finished Jul 04 06:12:14 PM PDT 24
Peak memory 206220 kb
Host smart-b3b6dd03-6115-4768-bf50-ea2c95efd7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29399
52918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2939952918
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.740430395
Short name T1222
Test name
Test status
Simulation time 148552008 ps
CPU time 0.8 seconds
Started Jul 04 06:12:07 PM PDT 24
Finished Jul 04 06:12:08 PM PDT 24
Peak memory 206112 kb
Host smart-630d4352-9329-4cbf-b856-10bad95d3730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74043
0395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.740430395
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3355534274
Short name T1662
Test name
Test status
Simulation time 205874260 ps
CPU time 0.92 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206184 kb
Host smart-71a2e3d3-586d-41c6-8fca-c8ee010b0465
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3355534274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3355534274
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3017646341
Short name T604
Test name
Test status
Simulation time 201320189 ps
CPU time 0.8 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206176 kb
Host smart-42c4c043-b2f6-4be5-acb3-10a2539c4945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30176
46341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3017646341
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1823622539
Short name T1529
Test name
Test status
Simulation time 33185260 ps
CPU time 0.68 seconds
Started Jul 04 06:12:07 PM PDT 24
Finished Jul 04 06:12:08 PM PDT 24
Peak memory 206200 kb
Host smart-a47b2e9d-7106-40aa-a02f-b82d056ac46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
22539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1823622539
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2960974521
Short name T1843
Test name
Test status
Simulation time 11356969974 ps
CPU time 25.2 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:12:45 PM PDT 24
Peak memory 206500 kb
Host smart-aaac8164-2264-40bf-a88d-92b2a83e9272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29609
74521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2960974521
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1925610109
Short name T2037
Test name
Test status
Simulation time 180488922 ps
CPU time 0.84 seconds
Started Jul 04 06:12:07 PM PDT 24
Finished Jul 04 06:12:08 PM PDT 24
Peak memory 206232 kb
Host smart-13e54dd3-024d-4309-a3da-f37bc6edf96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
10109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1925610109
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.110733566
Short name T2206
Test name
Test status
Simulation time 222502424 ps
CPU time 0.86 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206192 kb
Host smart-fd61cd1d-263d-45c6-b7a8-eda946ddeee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11073
3566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.110733566
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.818713295
Short name T2315
Test name
Test status
Simulation time 224026688 ps
CPU time 0.92 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206212 kb
Host smart-9d160a5d-a9b5-4d04-aca9-d57dc86520b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81871
3295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.818713295
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3721145125
Short name T631
Test name
Test status
Simulation time 169478460 ps
CPU time 0.81 seconds
Started Jul 04 06:12:08 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206188 kb
Host smart-49ccd9dd-da23-4323-9e24-05a5a2121672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37211
45125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3721145125
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2072176278
Short name T589
Test name
Test status
Simulation time 133774206 ps
CPU time 0.8 seconds
Started Jul 04 06:12:09 PM PDT 24
Finished Jul 04 06:12:09 PM PDT 24
Peak memory 206192 kb
Host smart-4ea613b0-2982-4089-83fe-b70645181321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
76278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2072176278
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2582019094
Short name T2489
Test name
Test status
Simulation time 157116319 ps
CPU time 0.83 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:16 PM PDT 24
Peak memory 206156 kb
Host smart-eac837c6-28fa-400c-b7a4-e8007762c651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
19094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2582019094
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.61720198
Short name T99
Test name
Test status
Simulation time 152985832 ps
CPU time 0.72 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206200 kb
Host smart-696124a1-794f-4f34-8523-d349e0aac78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61720
198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.61720198
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3524555826
Short name T801
Test name
Test status
Simulation time 303931634 ps
CPU time 1.05 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:12:20 PM PDT 24
Peak memory 206212 kb
Host smart-86c72807-11ee-4f0d-91bc-5bc1589333da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245
55826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3524555826
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1657608469
Short name T2692
Test name
Test status
Simulation time 5985774434 ps
CPU time 42.64 seconds
Started Jul 04 06:12:24 PM PDT 24
Finished Jul 04 06:13:07 PM PDT 24
Peak memory 206512 kb
Host smart-5a973fd2-f19c-4e09-88af-fef71eb88d7e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1657608469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1657608469
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1010303320
Short name T572
Test name
Test status
Simulation time 177254063 ps
CPU time 0.81 seconds
Started Jul 04 06:12:24 PM PDT 24
Finished Jul 04 06:12:25 PM PDT 24
Peak memory 206200 kb
Host smart-531b0c08-27dc-4508-b7c1-eedac42109b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
03320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1010303320
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2291077762
Short name T1304
Test name
Test status
Simulation time 209895236 ps
CPU time 0.8 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206156 kb
Host smart-d3dc11ae-3a8b-48c5-8894-e76c424b4b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22910
77762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2291077762
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.2191256263
Short name T2110
Test name
Test status
Simulation time 464411281 ps
CPU time 1.25 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206176 kb
Host smart-289670b0-3237-4fbe-8a36-bfd4ec87a2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21912
56263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.2191256263
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2386593625
Short name T1733
Test name
Test status
Simulation time 6904818683 ps
CPU time 193.44 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:15:33 PM PDT 24
Peak memory 206520 kb
Host smart-616bb468-bebe-4b47-b616-76acfca076f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23865
93625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2386593625
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2364826402
Short name T2253
Test name
Test status
Simulation time 50828552 ps
CPU time 0.65 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206268 kb
Host smart-9456f599-1bff-469c-8bf7-28ff2873f9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2364826402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2364826402
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.802871953
Short name T219
Test name
Test status
Simulation time 3915349782 ps
CPU time 4.36 seconds
Started Jul 04 06:12:24 PM PDT 24
Finished Jul 04 06:12:28 PM PDT 24
Peak memory 206272 kb
Host smart-5c403bfd-2546-484e-954c-056c09489a0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=802871953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.802871953
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3227197328
Short name T1578
Test name
Test status
Simulation time 13318421665 ps
CPU time 12.76 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:35 PM PDT 24
Peak memory 206272 kb
Host smart-68d6b59e-9e13-4451-8fb1-14d302447915
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3227197328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3227197328
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2827257345
Short name T497
Test name
Test status
Simulation time 23397740671 ps
CPU time 22.67 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206468 kb
Host smart-6fd59806-8351-4b0a-b3d3-3b5fca744d0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2827257345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2827257345
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1140118833
Short name T388
Test name
Test status
Simulation time 175460643 ps
CPU time 0.8 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206224 kb
Host smart-c74ed362-41b6-45d4-991c-6cae21343f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11401
18833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1140118833
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.610597865
Short name T402
Test name
Test status
Simulation time 169615845 ps
CPU time 0.8 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206184 kb
Host smart-108fb49e-4504-480e-9589-affff41515b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61059
7865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.610597865
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.4179820666
Short name T115
Test name
Test status
Simulation time 279961954 ps
CPU time 1.05 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206176 kb
Host smart-66976de1-0d7e-43d0-bcf9-da10c4660a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
20666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.4179820666
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3754986525
Short name T1231
Test name
Test status
Simulation time 386081569 ps
CPU time 1.19 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206124 kb
Host smart-7b51baf1-48f7-4113-983d-8d2d4b2b6941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
86525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3754986525
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.440570346
Short name T1910
Test name
Test status
Simulation time 19583482649 ps
CPU time 35.16 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:12:53 PM PDT 24
Peak memory 206488 kb
Host smart-e66abf6a-af51-484e-889e-ac1e89605ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44057
0346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.440570346
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3255590468
Short name T1288
Test name
Test status
Simulation time 471688894 ps
CPU time 1.35 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206204 kb
Host smart-fef1851c-18a1-43e1-b548-4096944f14ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32555
90468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3255590468
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3598902624
Short name T2693
Test name
Test status
Simulation time 143145230 ps
CPU time 0.78 seconds
Started Jul 04 06:12:23 PM PDT 24
Finished Jul 04 06:12:24 PM PDT 24
Peak memory 206196 kb
Host smart-82002707-10d7-4cf8-896a-43e62d51d6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35989
02624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3598902624
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1533261813
Short name T590
Test name
Test status
Simulation time 36829826 ps
CPU time 0.65 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:29 PM PDT 24
Peak memory 206172 kb
Host smart-e5deb2d2-aed0-4936-ac33-0ee213341a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15332
61813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1533261813
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1918202894
Short name T831
Test name
Test status
Simulation time 848444486 ps
CPU time 2.27 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206412 kb
Host smart-f5ffe050-975a-46a1-a7c8-62dc7f57da1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182
02894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1918202894
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3206520508
Short name T2082
Test name
Test status
Simulation time 222185828 ps
CPU time 1.99 seconds
Started Jul 04 06:12:12 PM PDT 24
Finished Jul 04 06:12:14 PM PDT 24
Peak memory 206444 kb
Host smart-580b0778-1755-4020-ac8d-90d14900e2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
20508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3206520508
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3658318390
Short name T1894
Test name
Test status
Simulation time 268029441 ps
CPU time 0.96 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206164 kb
Host smart-92cede3c-464b-4681-8cdf-52455b7e995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36583
18390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3658318390
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2189980074
Short name T416
Test name
Test status
Simulation time 181003742 ps
CPU time 0.76 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206208 kb
Host smart-5332b85e-81f3-4273-8186-100f1a661005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21899
80074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2189980074
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.887370576
Short name T2477
Test name
Test status
Simulation time 197925358 ps
CPU time 0.84 seconds
Started Jul 04 06:12:23 PM PDT 24
Finished Jul 04 06:12:24 PM PDT 24
Peak memory 206184 kb
Host smart-96bc9041-cebc-49b9-bf11-d30af37cbb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88737
0576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.887370576
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1582321426
Short name T1783
Test name
Test status
Simulation time 5433641575 ps
CPU time 146.2 seconds
Started Jul 04 06:12:15 PM PDT 24
Finished Jul 04 06:14:42 PM PDT 24
Peak memory 206556 kb
Host smart-aad32b8b-d163-4dae-a9ae-ae17e780aab2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1582321426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1582321426
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1137437000
Short name T2217
Test name
Test status
Simulation time 155582118 ps
CPU time 0.88 seconds
Started Jul 04 06:12:16 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206188 kb
Host smart-ca84a2cd-a1a0-4def-b836-6d7c0c014870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11374
37000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1137437000
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3196200454
Short name T1387
Test name
Test status
Simulation time 23262524632 ps
CPU time 23.7 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206276 kb
Host smart-a57bed86-7be5-4b55-8edc-808d4e9abf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31962
00454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3196200454
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1964563490
Short name T2028
Test name
Test status
Simulation time 3329354408 ps
CPU time 4.65 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206276 kb
Host smart-e33c4603-d1bf-4a19-8cf7-9fa1214ea650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19645
63490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1964563490
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.1822063066
Short name T2633
Test name
Test status
Simulation time 8019247782 ps
CPU time 77.69 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206496 kb
Host smart-a0e3b54b-af48-4bc5-905e-843048a47444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18220
63066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.1822063066
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3741188085
Short name T1441
Test name
Test status
Simulation time 4521609323 ps
CPU time 45.07 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206664 kb
Host smart-8eb1b43a-6d71-44e4-a317-616a57222149
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3741188085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3741188085
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3782362111
Short name T491
Test name
Test status
Simulation time 248228495 ps
CPU time 0.92 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206224 kb
Host smart-b9aa27b0-d9d5-47bd-a427-bc6e11f8fc17
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3782362111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3782362111
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3341274103
Short name T1219
Test name
Test status
Simulation time 184584638 ps
CPU time 0.85 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206188 kb
Host smart-aa2ad4a0-6873-4cd7-8a7b-b65a505d7567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33412
74103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3341274103
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1905255905
Short name T1773
Test name
Test status
Simulation time 3196322476 ps
CPU time 28.58 seconds
Started Jul 04 06:12:23 PM PDT 24
Finished Jul 04 06:12:52 PM PDT 24
Peak memory 206496 kb
Host smart-6789e856-e07a-486d-a02a-308b39cfb33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19052
55905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1905255905
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.500940979
Short name T2356
Test name
Test status
Simulation time 5839473701 ps
CPU time 158.37 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:14:59 PM PDT 24
Peak memory 206508 kb
Host smart-18174544-e687-44cd-b621-a8ef6bfbc86a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=500940979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.500940979
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3962652862
Short name T2180
Test name
Test status
Simulation time 164667539 ps
CPU time 0.78 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206408 kb
Host smart-5f98c513-28bb-4edd-bd67-f72080410853
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3962652862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3962652862
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3667242351
Short name T391
Test name
Test status
Simulation time 178766202 ps
CPU time 0.78 seconds
Started Jul 04 06:12:16 PM PDT 24
Finished Jul 04 06:12:17 PM PDT 24
Peak memory 206164 kb
Host smart-bacc409d-1f3b-48c1-80cb-77a7ef63591d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36672
42351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3667242351
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2718494855
Short name T133
Test name
Test status
Simulation time 207272332 ps
CPU time 0.89 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206224 kb
Host smart-807d557d-1793-4939-b4ad-fa5decced1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184
94855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2718494855
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.51789077
Short name T1830
Test name
Test status
Simulation time 166645755 ps
CPU time 0.95 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:19 PM PDT 24
Peak memory 206200 kb
Host smart-99f4936e-5a59-4021-8d0b-778b877d2c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51789
077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.51789077
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3896859883
Short name T2416
Test name
Test status
Simulation time 176437839 ps
CPU time 0.8 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:15 PM PDT 24
Peak memory 206176 kb
Host smart-94c3dd18-3f18-4906-abd5-a386c966795c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
59883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3896859883
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3307444505
Short name T1088
Test name
Test status
Simulation time 193992132 ps
CPU time 0.85 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206168 kb
Host smart-a6eff281-8389-45c0-b438-559b3120cc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33074
44505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3307444505
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2002813137
Short name T172
Test name
Test status
Simulation time 150338663 ps
CPU time 0.78 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:12:20 PM PDT 24
Peak memory 206188 kb
Host smart-f16b0cae-62d7-49e1-9331-ec109854c065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
13137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2002813137
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3515526343
Short name T1043
Test name
Test status
Simulation time 223433052 ps
CPU time 0.95 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:15 PM PDT 24
Peak memory 206228 kb
Host smart-a23922ff-e23a-4258-87f5-73aa9ff8cb44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3515526343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3515526343
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.855347388
Short name T2171
Test name
Test status
Simulation time 140938383 ps
CPU time 0.77 seconds
Started Jul 04 06:12:14 PM PDT 24
Finished Jul 04 06:12:15 PM PDT 24
Peak memory 206168 kb
Host smart-fba7ae36-d9ec-4931-9fb4-e27c8cfda305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85534
7388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.855347388
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1526797672
Short name T272
Test name
Test status
Simulation time 10907103301 ps
CPU time 26.71 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:48 PM PDT 24
Peak memory 206504 kb
Host smart-4da9f302-641a-44ad-9a70-cf45e6ad8798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15267
97672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1526797672
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2596660769
Short name T499
Test name
Test status
Simulation time 181022877 ps
CPU time 0.8 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206212 kb
Host smart-6cccb0ed-a1cb-44be-8e51-66ab3e85b62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25966
60769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2596660769
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3691824255
Short name T740
Test name
Test status
Simulation time 222352756 ps
CPU time 0.88 seconds
Started Jul 04 06:12:17 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206176 kb
Host smart-5046a103-2957-4388-b3fe-a48e1a1be510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918
24255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3691824255
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.911199373
Short name T1554
Test name
Test status
Simulation time 259021529 ps
CPU time 0.94 seconds
Started Jul 04 06:12:16 PM PDT 24
Finished Jul 04 06:12:18 PM PDT 24
Peak memory 206416 kb
Host smart-8ca0efea-76f3-4610-b799-0147d12725e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91119
9373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.911199373
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.4106352786
Short name T2263
Test name
Test status
Simulation time 160485232 ps
CPU time 0.83 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206196 kb
Host smart-1a0d6d42-b9bf-4cbe-aa9c-9bda0bccd6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41063
52786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.4106352786
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.623674127
Short name T2042
Test name
Test status
Simulation time 133885333 ps
CPU time 0.78 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206168 kb
Host smart-9ab8a38e-7850-4c79-a951-4e153911fe5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62367
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.623674127
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.799890821
Short name T2073
Test name
Test status
Simulation time 147811683 ps
CPU time 0.77 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:12:20 PM PDT 24
Peak memory 206140 kb
Host smart-06a8752e-284f-4b53-912e-eac9cd0a0967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79989
0821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.799890821
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2475353226
Short name T2009
Test name
Test status
Simulation time 146652894 ps
CPU time 0.86 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206204 kb
Host smart-958b7415-ee8e-4602-a6af-ea852d2d9a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24753
53226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2475353226
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3694901978
Short name T714
Test name
Test status
Simulation time 178779023 ps
CPU time 0.91 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206180 kb
Host smart-ed686cfc-8503-430e-94b1-51e5a73489c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36949
01978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3694901978
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3014871969
Short name T458
Test name
Test status
Simulation time 4079477913 ps
CPU time 112.77 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:14:12 PM PDT 24
Peak memory 206532 kb
Host smart-2973c3ec-c231-486c-9477-59e3113f5f02
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3014871969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3014871969
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.910048364
Short name T1173
Test name
Test status
Simulation time 156355437 ps
CPU time 0.82 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206176 kb
Host smart-deb096be-d4fb-4482-b8e1-3feeaf4ceaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91004
8364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.910048364
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.584614694
Short name T1028
Test name
Test status
Simulation time 181684410 ps
CPU time 0.85 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206196 kb
Host smart-1ccfe746-29f3-47fe-9ac7-e8d8dd2a0191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58461
4694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.584614694
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1141208713
Short name T1186
Test name
Test status
Simulation time 207091008 ps
CPU time 0.86 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206188 kb
Host smart-8375496f-ef15-464b-8e92-46f2a697ac42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11412
08713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1141208713
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1878258865
Short name T1286
Test name
Test status
Simulation time 5138460798 ps
CPU time 53.34 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:13:14 PM PDT 24
Peak memory 206524 kb
Host smart-8de27677-ae39-4e79-85c2-1de17ac6f4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18782
58865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1878258865
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2091055858
Short name T1858
Test name
Test status
Simulation time 36897747 ps
CPU time 0.72 seconds
Started Jul 04 06:12:32 PM PDT 24
Finished Jul 04 06:12:33 PM PDT 24
Peak memory 206256 kb
Host smart-888a1ed7-4617-4d91-bb8f-0340a167496d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2091055858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2091055858
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.74254371
Short name T2240
Test name
Test status
Simulation time 4240224056 ps
CPU time 4.84 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:27 PM PDT 24
Peak memory 206524 kb
Host smart-8e0e3a03-8a6b-458a-a03a-6d4b26e95093
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=74254371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.74254371
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2834958897
Short name T906
Test name
Test status
Simulation time 13457873225 ps
CPU time 13.19 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:34 PM PDT 24
Peak memory 206252 kb
Host smart-266b8f88-94a9-4b42-8a9f-3a6dc12301e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2834958897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2834958897
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.4068796078
Short name T2647
Test name
Test status
Simulation time 23331078973 ps
CPU time 25.79 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:48 PM PDT 24
Peak memory 206532 kb
Host smart-3af100ba-c1aa-4626-b3f0-bf0fe61a2c61
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4068796078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.4068796078
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.221986616
Short name T2484
Test name
Test status
Simulation time 221909630 ps
CPU time 0.88 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206224 kb
Host smart-e2e52014-5516-46ce-b1bd-d9601984015f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22198
6616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.221986616
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.220708138
Short name T1677
Test name
Test status
Simulation time 193470532 ps
CPU time 0.82 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206176 kb
Host smart-15ca6abc-d494-4743-b96d-cbae993ec938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22070
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.220708138
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.48436025
Short name T2390
Test name
Test status
Simulation time 459703829 ps
CPU time 1.5 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:24 PM PDT 24
Peak memory 206416 kb
Host smart-237d91ff-9d63-414c-849d-12909091c9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48436
025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.48436025
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3090815359
Short name T1344
Test name
Test status
Simulation time 932055277 ps
CPU time 2.34 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206460 kb
Host smart-8b43263e-cc08-4984-b5b1-7964ef6e50d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30908
15359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3090815359
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3040585652
Short name T1297
Test name
Test status
Simulation time 19231618131 ps
CPU time 36.07 seconds
Started Jul 04 06:12:18 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206528 kb
Host smart-d99b2bfd-ca5a-43ea-b808-bc687b2c8393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30405
85652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3040585652
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3303369969
Short name T1808
Test name
Test status
Simulation time 392250342 ps
CPU time 1.25 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206172 kb
Host smart-48f2a33a-ad4e-4c03-a0e2-0167fa337a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33033
69969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3303369969
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1950712979
Short name T1438
Test name
Test status
Simulation time 137220087 ps
CPU time 0.76 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206212 kb
Host smart-f017ff13-6264-4a4c-b024-2dc62b9767a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19507
12979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1950712979
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.329577607
Short name T392
Test name
Test status
Simulation time 44987480 ps
CPU time 0.7 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206172 kb
Host smart-0f88c5cb-36cd-4ebb-887c-da37346a0d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32957
7607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.329577607
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3105093336
Short name T1873
Test name
Test status
Simulation time 929801724 ps
CPU time 2.21 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206420 kb
Host smart-a0595321-417d-4d02-ac5a-ba43ee8390dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31050
93336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3105093336
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3194077509
Short name T907
Test name
Test status
Simulation time 201518578 ps
CPU time 1.97 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:24 PM PDT 24
Peak memory 206448 kb
Host smart-52c95ce6-25fc-48cc-aebb-683533e612b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31940
77509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3194077509
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.986814166
Short name T2289
Test name
Test status
Simulation time 218215515 ps
CPU time 0.94 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:24 PM PDT 24
Peak memory 206160 kb
Host smart-0b132c1f-039c-40aa-9aa8-63748ee6460d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98681
4166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.986814166
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2675437526
Short name T31
Test name
Test status
Simulation time 163983798 ps
CPU time 0.82 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 206164 kb
Host smart-568877e5-ac02-494e-ab8b-c54f4d03041f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
37526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2675437526
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2527452697
Short name T2447
Test name
Test status
Simulation time 232719931 ps
CPU time 0.98 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206208 kb
Host smart-19016083-b95c-46a4-a5ea-af2076443122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
52697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2527452697
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.470217366
Short name T1061
Test name
Test status
Simulation time 5677751266 ps
CPU time 41.57 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:13:03 PM PDT 24
Peak memory 206476 kb
Host smart-b8505645-3970-4846-b6bf-3ac97689ff05
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=470217366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.470217366
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1726486063
Short name T2143
Test name
Test status
Simulation time 257495042 ps
CPU time 0.91 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:22 PM PDT 24
Peak memory 206236 kb
Host smart-01e1e61a-92b5-4995-88b5-8f4259fb695e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17264
86063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1726486063
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3022146926
Short name T656
Test name
Test status
Simulation time 23349827717 ps
CPU time 23.63 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:45 PM PDT 24
Peak memory 206188 kb
Host smart-cfdafe5a-f53a-4907-936f-b401a81ce806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30221
46926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3022146926
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1595807262
Short name T2467
Test name
Test status
Simulation time 3310943298 ps
CPU time 3.86 seconds
Started Jul 04 06:12:22 PM PDT 24
Finished Jul 04 06:12:26 PM PDT 24
Peak memory 206260 kb
Host smart-c01b6ba5-69f5-477e-a7bb-044d1104166e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15958
07262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1595807262
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2273064408
Short name T779
Test name
Test status
Simulation time 7095750529 ps
CPU time 202.8 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206548 kb
Host smart-cc7c4060-7b77-48d7-a02e-7578b0a3f4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22730
64408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2273064408
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3238047807
Short name T2598
Test name
Test status
Simulation time 5368184054 ps
CPU time 51.64 seconds
Started Jul 04 06:12:20 PM PDT 24
Finished Jul 04 06:13:12 PM PDT 24
Peak memory 206500 kb
Host smart-1c317305-35fe-4f9c-853c-ce0231136406
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3238047807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3238047807
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2354257425
Short name T2445
Test name
Test status
Simulation time 235872843 ps
CPU time 0.87 seconds
Started Jul 04 06:12:19 PM PDT 24
Finished Jul 04 06:12:20 PM PDT 24
Peak memory 206228 kb
Host smart-c15778cd-f6e8-4706-be89-3659bd9b17bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2354257425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2354257425
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4081509716
Short name T1623
Test name
Test status
Simulation time 195717694 ps
CPU time 0.88 seconds
Started Jul 04 06:12:21 PM PDT 24
Finished Jul 04 06:12:23 PM PDT 24
Peak memory 206180 kb
Host smart-3166cdc1-ce03-47d5-98a1-952a684b9ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40815
09716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4081509716
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.196153922
Short name T789
Test name
Test status
Simulation time 7177249022 ps
CPU time 50.48 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:13:19 PM PDT 24
Peak memory 206452 kb
Host smart-a00e0c82-01dd-4f3a-9022-f8ac491214e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
3922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.196153922
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1170904567
Short name T2411
Test name
Test status
Simulation time 3671513041 ps
CPU time 26.61 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206512 kb
Host smart-910a52f1-3f6c-4b58-98d4-11faa884d438
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1170904567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1170904567
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.2778595243
Short name T1611
Test name
Test status
Simulation time 160835141 ps
CPU time 0.81 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:29 PM PDT 24
Peak memory 206180 kb
Host smart-8aa0ceed-126b-4fce-8397-8d6f43502463
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2778595243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2778595243
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1587089198
Short name T1482
Test name
Test status
Simulation time 159680947 ps
CPU time 0.81 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:29 PM PDT 24
Peak memory 206124 kb
Host smart-859c1f78-d212-448c-8073-579f65ca8fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
89198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1587089198
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1635315265
Short name T136
Test name
Test status
Simulation time 215096010 ps
CPU time 0.86 seconds
Started Jul 04 06:12:27 PM PDT 24
Finished Jul 04 06:12:28 PM PDT 24
Peak memory 206212 kb
Host smart-c83f7621-803e-4456-b00f-7fa1c0af47cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16353
15265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1635315265
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1981792770
Short name T1055
Test name
Test status
Simulation time 214758415 ps
CPU time 0.99 seconds
Started Jul 04 06:12:31 PM PDT 24
Finished Jul 04 06:12:32 PM PDT 24
Peak memory 206196 kb
Host smart-5449c122-c141-416b-9280-5abf22aa3baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19817
92770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1981792770
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2124732831
Short name T426
Test name
Test status
Simulation time 179392551 ps
CPU time 0.85 seconds
Started Jul 04 06:12:33 PM PDT 24
Finished Jul 04 06:12:34 PM PDT 24
Peak memory 206168 kb
Host smart-182aabbb-3e68-4f8b-93d3-5a2a7973e755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
32831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2124732831
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1544624649
Short name T2346
Test name
Test status
Simulation time 170319500 ps
CPU time 0.78 seconds
Started Jul 04 06:12:30 PM PDT 24
Finished Jul 04 06:12:30 PM PDT 24
Peak memory 206196 kb
Host smart-9d2e46b8-1a99-4cea-8eba-48d56df3c6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15446
24649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1544624649
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2198254199
Short name T187
Test name
Test status
Simulation time 152851389 ps
CPU time 0.78 seconds
Started Jul 04 06:12:35 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206196 kb
Host smart-23af7fe8-afa7-4629-86f6-e220fb262ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21982
54199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2198254199
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.3346565903
Short name T2194
Test name
Test status
Simulation time 191455559 ps
CPU time 0.85 seconds
Started Jul 04 06:12:27 PM PDT 24
Finished Jul 04 06:12:28 PM PDT 24
Peak memory 206184 kb
Host smart-927f7aab-d657-4f67-b531-e31d6775e882
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3346565903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.3346565903
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2827511738
Short name T2457
Test name
Test status
Simulation time 152363327 ps
CPU time 0.75 seconds
Started Jul 04 06:12:31 PM PDT 24
Finished Jul 04 06:12:32 PM PDT 24
Peak memory 206172 kb
Host smart-8b895d8f-d044-4783-b3ac-d0dbe379aeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
11738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2827511738
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2355442577
Short name T2549
Test name
Test status
Simulation time 51658874 ps
CPU time 0.66 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:29 PM PDT 24
Peak memory 206200 kb
Host smart-33a38dbf-4974-4adc-bcc4-fe79985e1bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
42577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2355442577
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3579059154
Short name T87
Test name
Test status
Simulation time 12686382101 ps
CPU time 35.29 seconds
Started Jul 04 06:12:29 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206472 kb
Host smart-196bebee-a56a-4b87-a74c-6c208c19db25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35790
59154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3579059154
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.652568374
Short name T2572
Test name
Test status
Simulation time 162981685 ps
CPU time 0.76 seconds
Started Jul 04 06:12:30 PM PDT 24
Finished Jul 04 06:12:31 PM PDT 24
Peak memory 206200 kb
Host smart-c06463b9-671e-4035-af07-827e89578e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65256
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.652568374
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.201682209
Short name T519
Test name
Test status
Simulation time 198020624 ps
CPU time 0.86 seconds
Started Jul 04 06:12:29 PM PDT 24
Finished Jul 04 06:12:30 PM PDT 24
Peak memory 206188 kb
Host smart-db989493-1524-40bf-b4eb-fa5194853ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20168
2209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.201682209
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.4225611004
Short name T533
Test name
Test status
Simulation time 237589936 ps
CPU time 0.91 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:30 PM PDT 24
Peak memory 206212 kb
Host smart-7c31e21a-9f33-44cb-a21f-717a9099afe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256
11004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.4225611004
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1410270122
Short name T471
Test name
Test status
Simulation time 169103493 ps
CPU time 0.82 seconds
Started Jul 04 06:12:29 PM PDT 24
Finished Jul 04 06:12:30 PM PDT 24
Peak memory 206212 kb
Host smart-a7502b6b-e859-4a67-9b4f-dfb697fabe47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14102
70122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1410270122
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3468536156
Short name T2210
Test name
Test status
Simulation time 169849544 ps
CPU time 0.79 seconds
Started Jul 04 06:12:28 PM PDT 24
Finished Jul 04 06:12:29 PM PDT 24
Peak memory 206172 kb
Host smart-44bfb9da-9908-4282-b595-248e239b7067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34685
36156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3468536156
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1070917606
Short name T1160
Test name
Test status
Simulation time 147502138 ps
CPU time 0.78 seconds
Started Jul 04 06:12:32 PM PDT 24
Finished Jul 04 06:12:33 PM PDT 24
Peak memory 206192 kb
Host smart-de05c528-54a6-4de8-a698-d86b2fef43ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10709
17606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1070917606
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1202405293
Short name T657
Test name
Test status
Simulation time 153922620 ps
CPU time 0.78 seconds
Started Jul 04 06:12:35 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206200 kb
Host smart-c459a76c-8702-432c-a511-a690ec58a6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024
05293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1202405293
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.462331276
Short name T1850
Test name
Test status
Simulation time 190857877 ps
CPU time 0.88 seconds
Started Jul 04 06:12:37 PM PDT 24
Finished Jul 04 06:12:38 PM PDT 24
Peak memory 206164 kb
Host smart-d556011c-f532-416c-b0e3-e613523705bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46233
1276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.462331276
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.454598531
Short name T2108
Test name
Test status
Simulation time 4296343740 ps
CPU time 118.65 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:14:33 PM PDT 24
Peak memory 206528 kb
Host smart-034b4d12-aa3f-44ea-a318-eea60a5c8c72
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=454598531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.454598531
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.942357496
Short name T2483
Test name
Test status
Simulation time 165508182 ps
CPU time 0.8 seconds
Started Jul 04 06:12:43 PM PDT 24
Finished Jul 04 06:12:44 PM PDT 24
Peak memory 206156 kb
Host smart-a02c0542-d2ea-46de-baf3-88ae46209802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94235
7496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.942357496
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3479511525
Short name T415
Test name
Test status
Simulation time 206983126 ps
CPU time 0.81 seconds
Started Jul 04 06:12:37 PM PDT 24
Finished Jul 04 06:12:38 PM PDT 24
Peak memory 206208 kb
Host smart-b580ec47-b459-4c3f-89c3-531013016860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34795
11525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3479511525
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3700974131
Short name T1852
Test name
Test status
Simulation time 1392497967 ps
CPU time 3.21 seconds
Started Jul 04 06:12:38 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206456 kb
Host smart-42b432d8-7645-478f-b746-f6318c569723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37009
74131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3700974131
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.896544441
Short name T2383
Test name
Test status
Simulation time 7685998508 ps
CPU time 205.83 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:16:02 PM PDT 24
Peak memory 206476 kb
Host smart-c5ac68b6-106c-43c2-a776-438638a00627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89654
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.896544441
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3202331153
Short name T1310
Test name
Test status
Simulation time 64656905 ps
CPU time 0.68 seconds
Started Jul 04 06:12:47 PM PDT 24
Finished Jul 04 06:12:48 PM PDT 24
Peak memory 206252 kb
Host smart-f618a783-fce7-4b18-ae46-31fe02839c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3202331153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3202331153
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1414907489
Short name T1242
Test name
Test status
Simulation time 3843777533 ps
CPU time 4.4 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206452 kb
Host smart-8328430d-6871-406f-954c-a34c00438e44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1414907489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1414907489
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2554167781
Short name T2573
Test name
Test status
Simulation time 13327080229 ps
CPU time 12.2 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:12:47 PM PDT 24
Peak memory 206236 kb
Host smart-749cfe28-3fbd-4730-bc78-a684362de1f6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2554167781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2554167781
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3204944502
Short name T1223
Test name
Test status
Simulation time 23377108421 ps
CPU time 27.45 seconds
Started Jul 04 06:12:39 PM PDT 24
Finished Jul 04 06:13:07 PM PDT 24
Peak memory 206228 kb
Host smart-1ab1b221-d91b-43cc-b962-cd989ab1c192
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3204944502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3204944502
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2787668650
Short name T759
Test name
Test status
Simulation time 187078896 ps
CPU time 0.81 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:12:37 PM PDT 24
Peak memory 206200 kb
Host smart-95f43304-2fd3-466d-bff0-eb8d955b64fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27876
68650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2787668650
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2689491083
Short name T2332
Test name
Test status
Simulation time 173378554 ps
CPU time 0.8 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:12:37 PM PDT 24
Peak memory 206188 kb
Host smart-c85e0ba7-e240-4227-9cf7-d30e5cc1689c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
91083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2689491083
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1752811904
Short name T185
Test name
Test status
Simulation time 252828740 ps
CPU time 1 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:12:38 PM PDT 24
Peak memory 206212 kb
Host smart-fd92ed1e-c6aa-402c-92e3-8efcb827b459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
11904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1752811904
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1801715983
Short name T643
Test name
Test status
Simulation time 1015065920 ps
CPU time 2.32 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206396 kb
Host smart-25c889d7-5734-4d63-89aa-2fe115bad72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18017
15983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1801715983
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3309338252
Short name T1587
Test name
Test status
Simulation time 13357824062 ps
CPU time 25.6 seconds
Started Jul 04 06:12:38 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206528 kb
Host smart-fca0f2ac-e053-4c58-be2b-9bcc6cd27fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
38252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3309338252
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.703230489
Short name T1309
Test name
Test status
Simulation time 381056708 ps
CPU time 1.14 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:12:38 PM PDT 24
Peak memory 206152 kb
Host smart-69a2209f-a072-472f-8b50-72f72e1117e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70323
0489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.703230489
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2214368313
Short name T721
Test name
Test status
Simulation time 140535415 ps
CPU time 0.77 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:12:35 PM PDT 24
Peak memory 206216 kb
Host smart-ced37404-cd38-4d55-a8ce-d15e4c5bb08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22143
68313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2214368313
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2678865322
Short name T355
Test name
Test status
Simulation time 51648811 ps
CPU time 0.77 seconds
Started Jul 04 06:12:35 PM PDT 24
Finished Jul 04 06:12:37 PM PDT 24
Peak memory 206144 kb
Host smart-2f4c6267-3542-4054-ae6e-365ff73c0541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26788
65322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2678865322
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2503132023
Short name T1116
Test name
Test status
Simulation time 751123843 ps
CPU time 1.91 seconds
Started Jul 04 06:12:33 PM PDT 24
Finished Jul 04 06:12:35 PM PDT 24
Peak memory 206368 kb
Host smart-c5cbf83c-11fc-4591-9d90-15c64adece85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
32023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2503132023
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2055570525
Short name T770
Test name
Test status
Simulation time 170575479 ps
CPU time 1.31 seconds
Started Jul 04 06:12:35 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206392 kb
Host smart-d66f3254-da92-46a3-b1b5-5a3ba181b8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20555
70525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2055570525
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1112113067
Short name T2322
Test name
Test status
Simulation time 176358922 ps
CPU time 0.79 seconds
Started Jul 04 06:12:38 PM PDT 24
Finished Jul 04 06:12:39 PM PDT 24
Peak memory 206192 kb
Host smart-963440df-2dad-4790-9f65-3af0ee50c0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11121
13067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1112113067
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2689572751
Short name T2283
Test name
Test status
Simulation time 133231894 ps
CPU time 0.77 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206168 kb
Host smart-01592112-7018-46eb-a366-7efcac065809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26895
72751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2689572751
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1238797353
Short name T2382
Test name
Test status
Simulation time 181946387 ps
CPU time 0.83 seconds
Started Jul 04 06:12:35 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206196 kb
Host smart-84bdd79c-475f-499b-b482-e169342f5f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12387
97353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1238797353
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.996149461
Short name T19
Test name
Test status
Simulation time 7499786258 ps
CPU time 72.78 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:13:50 PM PDT 24
Peak memory 206528 kb
Host smart-b3f70b5c-1aec-4906-be9b-cb3b74229a6e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=996149461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.996149461
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2964986407
Short name T1307
Test name
Test status
Simulation time 223579537 ps
CPU time 0.9 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:12:36 PM PDT 24
Peak memory 206208 kb
Host smart-6f188253-d001-45ff-9086-77cf74159ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29649
86407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2964986407
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2077559848
Short name T647
Test name
Test status
Simulation time 23303123109 ps
CPU time 22.61 seconds
Started Jul 04 06:12:35 PM PDT 24
Finished Jul 04 06:12:58 PM PDT 24
Peak memory 206236 kb
Host smart-5133ecae-eb12-4947-bfb2-a286a6ad49e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20775
59848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2077559848
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2892096538
Short name T672
Test name
Test status
Simulation time 3257250919 ps
CPU time 3.78 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:12:40 PM PDT 24
Peak memory 206232 kb
Host smart-b9ec3637-9e93-4ebf-918a-8b00a4f32db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28920
96538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2892096538
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3276276080
Short name T504
Test name
Test status
Simulation time 6175338217 ps
CPU time 173.6 seconds
Started Jul 04 06:12:34 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206528 kb
Host smart-d90135c6-0000-4524-ad71-e07d3f2588fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
76080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3276276080
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3580387074
Short name T83
Test name
Test status
Simulation time 4275201116 ps
CPU time 41.86 seconds
Started Jul 04 06:12:36 PM PDT 24
Finished Jul 04 06:13:18 PM PDT 24
Peak memory 206420 kb
Host smart-1fb8f2ba-fcd4-4a97-acc9-c4bb527fe38a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3580387074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3580387074
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1804539281
Short name T1241
Test name
Test status
Simulation time 241396083 ps
CPU time 0.92 seconds
Started Jul 04 06:12:37 PM PDT 24
Finished Jul 04 06:12:38 PM PDT 24
Peak memory 206188 kb
Host smart-e6e4722c-a2a3-4d1f-9e8c-f8f244f975f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1804539281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1804539281
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2420648055
Short name T1249
Test name
Test status
Simulation time 192465949 ps
CPU time 0.84 seconds
Started Jul 04 06:12:40 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206124 kb
Host smart-2c035e1b-3341-498c-b058-a2a8f2f4ce44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24206
48055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2420648055
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1772348415
Short name T1278
Test name
Test status
Simulation time 5024183215 ps
CPU time 49.13 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:13:32 PM PDT 24
Peak memory 206440 kb
Host smart-4fb48466-7053-4dfc-b218-cd5a6cf3ab5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17723
48415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1772348415
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1023409501
Short name T2393
Test name
Test status
Simulation time 3862410654 ps
CPU time 29 seconds
Started Jul 04 06:12:43 PM PDT 24
Finished Jul 04 06:13:12 PM PDT 24
Peak memory 206348 kb
Host smart-ee91494d-6a7b-4193-ac28-c9f6b2e44710
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1023409501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1023409501
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3992436087
Short name T1889
Test name
Test status
Simulation time 239890435 ps
CPU time 0.89 seconds
Started Jul 04 06:12:39 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206180 kb
Host smart-dbf435cb-bfc3-41bc-be58-b3835ebc5f23
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3992436087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3992436087
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.879387420
Short name T1799
Test name
Test status
Simulation time 191275279 ps
CPU time 0.8 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206180 kb
Host smart-6fcbdd28-a2d6-435e-ab7c-869e0ec6aeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87938
7420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.879387420
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3436302939
Short name T125
Test name
Test status
Simulation time 209097712 ps
CPU time 0.86 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206208 kb
Host smart-191336f3-3eab-4169-b6df-f68d307c2243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
02939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3436302939
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2942038403
Short name T2314
Test name
Test status
Simulation time 183179295 ps
CPU time 0.91 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206236 kb
Host smart-a1788fb8-51c0-4075-acdc-26fb61fa6eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
38403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2942038403
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2733170544
Short name T1804
Test name
Test status
Simulation time 196965519 ps
CPU time 0.86 seconds
Started Jul 04 06:12:41 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206208 kb
Host smart-98c27c44-284c-4153-a236-0fe83f0940e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
70544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2733170544
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1696885110
Short name T719
Test name
Test status
Simulation time 191488862 ps
CPU time 0.8 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206168 kb
Host smart-147dc6c9-6781-4494-9c88-7d5585593b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16968
85110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1696885110
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3964516052
Short name T2379
Test name
Test status
Simulation time 169870709 ps
CPU time 0.79 seconds
Started Jul 04 06:12:47 PM PDT 24
Finished Jul 04 06:12:48 PM PDT 24
Peak memory 206116 kb
Host smart-5eed54ea-aa05-405d-b17b-5f28e0e07d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39645
16052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3964516052
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3768039285
Short name T2330
Test name
Test status
Simulation time 205643370 ps
CPU time 0.91 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206168 kb
Host smart-33e0cf7b-0ba8-4d9f-b13e-bc139ab0c830
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3768039285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3768039285
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.488288321
Short name T829
Test name
Test status
Simulation time 140748690 ps
CPU time 0.76 seconds
Started Jul 04 06:12:44 PM PDT 24
Finished Jul 04 06:12:45 PM PDT 24
Peak memory 206180 kb
Host smart-390ea250-4645-4b92-bc4f-b1166845d40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48828
8321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.488288321
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2414087879
Short name T1478
Test name
Test status
Simulation time 37308890 ps
CPU time 0.66 seconds
Started Jul 04 06:12:41 PM PDT 24
Finished Jul 04 06:12:42 PM PDT 24
Peak memory 206168 kb
Host smart-8b030e33-574f-4c64-8f0a-282566a11803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24140
87879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2414087879
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2905818184
Short name T263
Test name
Test status
Simulation time 23623872102 ps
CPU time 57.45 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206464 kb
Host smart-aec85d57-48ee-4dbf-80bd-a5f4aaf34c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
18184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2905818184
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1528791254
Short name T2075
Test name
Test status
Simulation time 170824010 ps
CPU time 0.81 seconds
Started Jul 04 06:12:40 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206200 kb
Host smart-83216836-57b1-4edc-86c4-a9362880d313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15287
91254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1528791254
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3789786152
Short name T1875
Test name
Test status
Simulation time 206781483 ps
CPU time 0.92 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206192 kb
Host smart-9be717b3-4ebc-4488-8d6c-4fc80cb23933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37897
86152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3789786152
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1676813367
Short name T335
Test name
Test status
Simulation time 239152295 ps
CPU time 0.91 seconds
Started Jul 04 06:12:40 PM PDT 24
Finished Jul 04 06:12:42 PM PDT 24
Peak memory 206192 kb
Host smart-9841e1bb-5cea-482c-a94f-cd30f4a365b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
13367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1676813367
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2593181136
Short name T1853
Test name
Test status
Simulation time 193217370 ps
CPU time 0.82 seconds
Started Jul 04 06:12:43 PM PDT 24
Finished Jul 04 06:12:44 PM PDT 24
Peak memory 206200 kb
Host smart-2e206570-1a3c-4d72-ab6d-87128f7fbbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25931
81136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2593181136
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.789341649
Short name T1650
Test name
Test status
Simulation time 217086415 ps
CPU time 0.82 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206176 kb
Host smart-11ba3c14-d0d1-4f44-bd37-1fb271e61b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78934
1649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.789341649
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3585064567
Short name T2584
Test name
Test status
Simulation time 145168314 ps
CPU time 0.79 seconds
Started Jul 04 06:12:47 PM PDT 24
Finished Jul 04 06:12:48 PM PDT 24
Peak memory 206200 kb
Host smart-04f91c20-86ee-4140-bcf3-6783d5c6be9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35850
64567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3585064567
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2559914368
Short name T708
Test name
Test status
Simulation time 152004189 ps
CPU time 0.8 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:12:43 PM PDT 24
Peak memory 206200 kb
Host smart-d159dbf7-c410-4d14-ae6f-f1bfdbc173d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25599
14368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2559914368
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1337155615
Short name T933
Test name
Test status
Simulation time 241781675 ps
CPU time 1 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206232 kb
Host smart-0f946796-be0a-45bd-b754-f32f34b9fc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13371
55615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1337155615
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1664663674
Short name T554
Test name
Test status
Simulation time 4285381549 ps
CPU time 115.99 seconds
Started Jul 04 06:12:43 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206552 kb
Host smart-1272d727-199a-4e3b-b16c-54c2a8c71148
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1664663674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1664663674
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3474654885
Short name T2209
Test name
Test status
Simulation time 180560814 ps
CPU time 0.88 seconds
Started Jul 04 06:12:41 PM PDT 24
Finished Jul 04 06:12:42 PM PDT 24
Peak memory 206196 kb
Host smart-0adb632d-332e-4a73-803e-f6121be759c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34746
54885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3474654885
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2677894225
Short name T629
Test name
Test status
Simulation time 153319393 ps
CPU time 0.79 seconds
Started Jul 04 06:12:40 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206224 kb
Host smart-a356a0c1-b8d1-4bf3-9152-6b06dd0b8d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778
94225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2677894225
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2136288400
Short name T1864
Test name
Test status
Simulation time 439087710 ps
CPU time 1.28 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:12:44 PM PDT 24
Peak memory 206164 kb
Host smart-cb109301-98cf-470a-ab2d-ae3ca4272ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
88400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2136288400
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.663430062
Short name T1841
Test name
Test status
Simulation time 7056132610 ps
CPU time 198.88 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:16:01 PM PDT 24
Peak memory 206520 kb
Host smart-87cec664-da1e-434c-a0e1-a347febdd43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66343
0062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.663430062
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.545417054
Short name T503
Test name
Test status
Simulation time 35035341 ps
CPU time 0.66 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206124 kb
Host smart-bad6d66e-dad8-4b27-9d9a-be3b598e59cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=545417054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.545417054
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3656980170
Short name T1869
Test name
Test status
Simulation time 4363315499 ps
CPU time 4.75 seconds
Started Jul 04 06:12:47 PM PDT 24
Finished Jul 04 06:12:52 PM PDT 24
Peak memory 206516 kb
Host smart-b2d6c806-928f-4fd3-a186-aa43a0e3426f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3656980170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3656980170
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3312632411
Short name T224
Test name
Test status
Simulation time 13302999864 ps
CPU time 14.05 seconds
Started Jul 04 06:12:40 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206276 kb
Host smart-661db8d2-713f-4413-b096-ae517e0feec2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3312632411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3312632411
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.4275384695
Short name T1405
Test name
Test status
Simulation time 23310539872 ps
CPU time 26.05 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206268 kb
Host smart-adba4915-6861-4455-b602-c85290709e7e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4275384695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.4275384695
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3252583426
Short name T2496
Test name
Test status
Simulation time 182611085 ps
CPU time 0.88 seconds
Started Jul 04 06:12:43 PM PDT 24
Finished Jul 04 06:12:44 PM PDT 24
Peak memory 206052 kb
Host smart-d8635b2c-acd7-4cb9-8b54-e9affe295df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
83426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3252583426
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3541046673
Short name T1168
Test name
Test status
Simulation time 147173681 ps
CPU time 0.75 seconds
Started Jul 04 06:12:40 PM PDT 24
Finished Jul 04 06:12:41 PM PDT 24
Peak memory 206136 kb
Host smart-8f1b543e-8eb6-463e-9b5f-8cc6a699d9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
46673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3541046673
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3373869244
Short name T1324
Test name
Test status
Simulation time 157912235 ps
CPU time 0.8 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206112 kb
Host smart-88d7ac15-26c2-4c73-b268-67b32fccf0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
69244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3373869244
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2987489156
Short name T176
Test name
Test status
Simulation time 579739843 ps
CPU time 1.36 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206208 kb
Host smart-994901a5-936c-4621-9beb-fff6c25e5732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29874
89156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2987489156
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2403871028
Short name T92
Test name
Test status
Simulation time 14304577666 ps
CPU time 27.87 seconds
Started Jul 04 06:12:42 PM PDT 24
Finished Jul 04 06:13:10 PM PDT 24
Peak memory 206504 kb
Host smart-b6593f93-25ea-4ab9-a4c7-76af434c5d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24038
71028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2403871028
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1241021337
Short name T1512
Test name
Test status
Simulation time 352936799 ps
CPU time 1.19 seconds
Started Jul 04 06:12:41 PM PDT 24
Finished Jul 04 06:12:42 PM PDT 24
Peak memory 206180 kb
Host smart-dbc053db-a5fc-4da1-bb28-3468d3075a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12410
21337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1241021337
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2638841711
Short name T2228
Test name
Test status
Simulation time 150993112 ps
CPU time 0.77 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206176 kb
Host smart-f2f660ac-f546-4d67-933e-8e542d87bbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26388
41711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2638841711
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2806225993
Short name T2305
Test name
Test status
Simulation time 38814004 ps
CPU time 0.66 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206144 kb
Host smart-2b241645-e48e-498f-ae5e-de11a714c78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28062
25993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2806225993
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1096186000
Short name T937
Test name
Test status
Simulation time 1128513507 ps
CPU time 2.43 seconds
Started Jul 04 06:12:52 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206408 kb
Host smart-be5e2743-e7bc-4964-8029-bdbe82b00fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961
86000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1096186000
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.582090380
Short name T2056
Test name
Test status
Simulation time 323745253 ps
CPU time 2.21 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:12:52 PM PDT 24
Peak memory 206412 kb
Host smart-55a404f3-fa46-4bc5-bce0-fb0601008910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58209
0380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.582090380
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1329958388
Short name T1711
Test name
Test status
Simulation time 201664949 ps
CPU time 0.86 seconds
Started Jul 04 06:12:52 PM PDT 24
Finished Jul 04 06:12:53 PM PDT 24
Peak memory 206160 kb
Host smart-b88a7180-95a0-4b0e-b90d-3dc383b00815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
58388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1329958388
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.435806545
Short name T1705
Test name
Test status
Simulation time 140592358 ps
CPU time 0.75 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206184 kb
Host smart-e639a539-fe91-4bd7-9c97-99417d4898f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43580
6545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.435806545
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.543545147
Short name T2154
Test name
Test status
Simulation time 182661005 ps
CPU time 0.85 seconds
Started Jul 04 06:12:52 PM PDT 24
Finished Jul 04 06:12:53 PM PDT 24
Peak memory 206208 kb
Host smart-7ab25e5c-e3ce-43d0-bdc4-eed6e8cd4a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54354
5147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.543545147
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1774762492
Short name T2407
Test name
Test status
Simulation time 9702851419 ps
CPU time 267.44 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 206488 kb
Host smart-ec37046d-e347-43bf-b10d-3ed0cff35ee1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774762492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1774762492
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3221365919
Short name T448
Test name
Test status
Simulation time 175730895 ps
CPU time 0.79 seconds
Started Jul 04 06:12:51 PM PDT 24
Finished Jul 04 06:12:51 PM PDT 24
Peak memory 206216 kb
Host smart-6936bad7-ac42-4d5f-b2f2-954c9b162702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
65919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3221365919
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.28262841
Short name T2619
Test name
Test status
Simulation time 23348238956 ps
CPU time 24.88 seconds
Started Jul 04 06:12:51 PM PDT 24
Finished Jul 04 06:13:17 PM PDT 24
Peak memory 206220 kb
Host smart-bce8df52-e2fc-467d-99f9-3e275883a40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28262
841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.28262841
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2076083246
Short name T235
Test name
Test status
Simulation time 3297431219 ps
CPU time 3.76 seconds
Started Jul 04 06:12:51 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206284 kb
Host smart-19eb94f5-288d-49bc-9d05-17afde90f57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20760
83246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2076083246
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1234312748
Short name T2270
Test name
Test status
Simulation time 9580956725 ps
CPU time 71.57 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206532 kb
Host smart-5d407a62-3d5b-44c4-adaa-c3ed42f664d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12343
12748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1234312748
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3772080936
Short name T1042
Test name
Test status
Simulation time 4803033301 ps
CPU time 135.09 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206464 kb
Host smart-7c0f8d15-de01-48c3-afec-67bf141859ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3772080936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3772080936
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.723357828
Short name T2131
Test name
Test status
Simulation time 252488830 ps
CPU time 0.93 seconds
Started Jul 04 06:12:50 PM PDT 24
Finished Jul 04 06:12:52 PM PDT 24
Peak memory 206212 kb
Host smart-4bde4793-f454-48c8-a732-8bbe9ac5ff1f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=723357828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.723357828
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.4159734852
Short name T354
Test name
Test status
Simulation time 188419986 ps
CPU time 0.88 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206156 kb
Host smart-4c3c0f1e-d3c4-4f3e-8fb6-90193dff6af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
34852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.4159734852
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3541066499
Short name T1732
Test name
Test status
Simulation time 4630978825 ps
CPU time 131.38 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:15:07 PM PDT 24
Peak memory 206476 kb
Host smart-55eb7a22-61cc-4700-abcf-95c768638352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
66499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3541066499
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.195329988
Short name T1743
Test name
Test status
Simulation time 3866848394 ps
CPU time 36.08 seconds
Started Jul 04 06:12:48 PM PDT 24
Finished Jul 04 06:13:25 PM PDT 24
Peak memory 206440 kb
Host smart-df7243ee-d91f-4132-b251-8984af22efb1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=195329988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.195329988
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.3747592423
Short name T2251
Test name
Test status
Simulation time 189466195 ps
CPU time 0.88 seconds
Started Jul 04 06:12:50 PM PDT 24
Finished Jul 04 06:12:52 PM PDT 24
Peak memory 206212 kb
Host smart-43cacc5c-6f9f-4b35-8b51-50f9adf0c41b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3747592423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3747592423
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2870536634
Short name T322
Test name
Test status
Simulation time 187069485 ps
CPU time 0.81 seconds
Started Jul 04 06:12:52 PM PDT 24
Finished Jul 04 06:12:53 PM PDT 24
Peak memory 206176 kb
Host smart-5de2005f-fd01-4301-a27b-0d644bf6b2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705
36634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2870536634
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2174841223
Short name T134
Test name
Test status
Simulation time 159520631 ps
CPU time 0.83 seconds
Started Jul 04 06:12:51 PM PDT 24
Finished Jul 04 06:12:52 PM PDT 24
Peak memory 206224 kb
Host smart-df3228b6-b2b9-4245-9bc5-0b3a3c6375ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
41223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2174841223
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3373109087
Short name T523
Test name
Test status
Simulation time 215207146 ps
CPU time 0.9 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206216 kb
Host smart-ea6e7d0f-4369-493c-828f-3c360bff7c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
09087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3373109087
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2036213615
Short name T1151
Test name
Test status
Simulation time 187626809 ps
CPU time 0.83 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206216 kb
Host smart-9a526c4e-f252-42bd-8be7-d4cac0d88568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20362
13615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2036213615
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3109013918
Short name T1035
Test name
Test status
Simulation time 193208497 ps
CPU time 0.8 seconds
Started Jul 04 06:12:49 PM PDT 24
Finished Jul 04 06:12:50 PM PDT 24
Peak memory 206208 kb
Host smart-df1f4220-5c02-4079-b218-98f78e577a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31090
13918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3109013918
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3360727673
Short name T2469
Test name
Test status
Simulation time 152070355 ps
CPU time 0.86 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206112 kb
Host smart-aede27be-36c9-4148-a794-8cad6cb2a8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
27673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3360727673
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.340857620
Short name T1397
Test name
Test status
Simulation time 248418416 ps
CPU time 0.99 seconds
Started Jul 04 06:12:58 PM PDT 24
Finished Jul 04 06:13:00 PM PDT 24
Peak memory 206192 kb
Host smart-ebd400ce-c7b8-43c4-bf51-1f5c3e169dc8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=340857620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.340857620
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3043766644
Short name T955
Test name
Test status
Simulation time 172403310 ps
CPU time 0.81 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206136 kb
Host smart-8ec192b9-c368-4cfc-bd2d-b998bbfb4604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30437
66644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3043766644
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2316298573
Short name T1031
Test name
Test status
Simulation time 37074365 ps
CPU time 0.64 seconds
Started Jul 04 06:12:59 PM PDT 24
Finished Jul 04 06:13:00 PM PDT 24
Peak memory 206152 kb
Host smart-7ba43a21-2630-477f-89f0-9e6f1407cc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
98573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2316298573
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1337742200
Short name T274
Test name
Test status
Simulation time 21398958450 ps
CPU time 47.2 seconds
Started Jul 04 06:12:54 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206572 kb
Host smart-7eb7208d-68da-4a90-b093-77e3f293c56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13377
42200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1337742200
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1678276354
Short name T2214
Test name
Test status
Simulation time 186435159 ps
CPU time 0.86 seconds
Started Jul 04 06:12:52 PM PDT 24
Finished Jul 04 06:12:54 PM PDT 24
Peak memory 206176 kb
Host smart-0f105dda-50ae-404b-ac54-f12e1bce7356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
76354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1678276354
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1243463198
Short name T2247
Test name
Test status
Simulation time 183437705 ps
CPU time 0.83 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:12:58 PM PDT 24
Peak memory 206176 kb
Host smart-c09d9e8f-6983-41b1-a8cf-a3577f75f157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
63198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1243463198
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3225958628
Short name T1215
Test name
Test status
Simulation time 195095666 ps
CPU time 0.86 seconds
Started Jul 04 06:12:54 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206212 kb
Host smart-e32396bf-de07-4456-9376-0bc4049636ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
58628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3225958628
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.674433316
Short name T860
Test name
Test status
Simulation time 140194434 ps
CPU time 0.84 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206124 kb
Host smart-9acf7079-e2a4-4b1a-941d-131f391e7df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67443
3316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.674433316
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1039040631
Short name T1781
Test name
Test status
Simulation time 172456693 ps
CPU time 0.84 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206220 kb
Host smart-2487eebf-0ceb-4ffd-b248-ca9b69ed23d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10390
40631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1039040631
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3213001111
Short name T2321
Test name
Test status
Simulation time 150633466 ps
CPU time 0.74 seconds
Started Jul 04 06:12:53 PM PDT 24
Finished Jul 04 06:12:54 PM PDT 24
Peak memory 206216 kb
Host smart-c82ecba2-3bad-4619-9a76-c4a8245cb7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32130
01111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3213001111
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1156732861
Short name T754
Test name
Test status
Simulation time 146596142 ps
CPU time 0.79 seconds
Started Jul 04 06:12:53 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206220 kb
Host smart-be4cd3dd-dc3d-4076-a26d-d8fddc9a06b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11567
32861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1156732861
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.690543107
Short name T156
Test name
Test status
Simulation time 252923717 ps
CPU time 1.06 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 206180 kb
Host smart-a8f7e8b8-698f-474e-b180-7a7fd53b4e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69054
3107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.690543107
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2452153168
Short name T1083
Test name
Test status
Simulation time 4996624003 ps
CPU time 127.77 seconds
Started Jul 04 06:12:59 PM PDT 24
Finished Jul 04 06:15:07 PM PDT 24
Peak memory 206476 kb
Host smart-d17f6423-24d3-408f-b65e-1310583bfec6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2452153168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2452153168
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1805962358
Short name T1480
Test name
Test status
Simulation time 214342819 ps
CPU time 0.85 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 206188 kb
Host smart-b6930887-e7b5-4763-a6fa-e88b051eb6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18059
62358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1805962358
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2130529845
Short name T1602
Test name
Test status
Simulation time 175521376 ps
CPU time 0.8 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206212 kb
Host smart-e44451cc-f20b-46f7-83cd-fc5e9ab027d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21305
29845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2130529845
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.701737695
Short name T2511
Test name
Test status
Simulation time 1250663644 ps
CPU time 2.53 seconds
Started Jul 04 06:12:54 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206596 kb
Host smart-22dc4c13-2908-4170-a9ee-a45417d51c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70173
7695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.701737695
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.868236496
Short name T1384
Test name
Test status
Simulation time 3730329889 ps
CPU time 102.42 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206544 kb
Host smart-b84e37ce-424e-4914-a62c-01cc71db6272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86823
6496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.868236496
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.678614221
Short name T2586
Test name
Test status
Simulation time 54908330 ps
CPU time 0.71 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206252 kb
Host smart-491e55b4-331d-47c5-8bcb-25e23207a305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=678614221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.678614221
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.4028622262
Short name T580
Test name
Test status
Simulation time 3338513177 ps
CPU time 4.52 seconds
Started Jul 04 06:12:53 PM PDT 24
Finished Jul 04 06:12:58 PM PDT 24
Peak memory 206264 kb
Host smart-f5499e69-6c3d-42d8-bef7-0313d32bb332
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4028622262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.4028622262
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2515802475
Short name T2188
Test name
Test status
Simulation time 13301904842 ps
CPU time 12.39 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206428 kb
Host smart-a23b4082-8726-40b0-a7db-b42327cd32fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2515802475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2515802475
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.704029009
Short name T1429
Test name
Test status
Simulation time 23351873346 ps
CPU time 24.53 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:13:20 PM PDT 24
Peak memory 206276 kb
Host smart-672beebc-3403-4e6e-908c-b7eff0306200
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=704029009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.704029009
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.419163024
Short name T683
Test name
Test status
Simulation time 182288848 ps
CPU time 0.8 seconds
Started Jul 04 06:12:59 PM PDT 24
Finished Jul 04 06:13:00 PM PDT 24
Peak memory 206156 kb
Host smart-e682eee6-458a-4d2d-87c9-d156fdcf4b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916
3024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.419163024
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3247351497
Short name T2539
Test name
Test status
Simulation time 174662184 ps
CPU time 0.78 seconds
Started Jul 04 06:12:54 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206416 kb
Host smart-c69a4010-bacd-409a-a572-adfb3d402322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
51497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3247351497
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3537506347
Short name T167
Test name
Test status
Simulation time 285364558 ps
CPU time 1.04 seconds
Started Jul 04 06:12:54 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206212 kb
Host smart-870be3e8-450d-4ae7-9dde-0b7af56ceb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
06347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3537506347
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.751413587
Short name T1082
Test name
Test status
Simulation time 255720431 ps
CPU time 0.87 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 206176 kb
Host smart-a8b7d6b3-9433-4be3-aa67-4afabfc3a28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75141
3587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.751413587
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.152128394
Short name T1109
Test name
Test status
Simulation time 12003440102 ps
CPU time 20.03 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:24 PM PDT 24
Peak memory 206464 kb
Host smart-ad7bd540-dc34-4bd9-95fe-0eca6d0b13f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
8394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.152128394
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2202530680
Short name T1919
Test name
Test status
Simulation time 408255017 ps
CPU time 1.24 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 206164 kb
Host smart-e7feb0d3-eb3c-4174-9f8f-4b6313c8b91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
30680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2202530680
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.36253648
Short name T815
Test name
Test status
Simulation time 174420380 ps
CPU time 0.78 seconds
Started Jul 04 06:12:54 PM PDT 24
Finished Jul 04 06:12:55 PM PDT 24
Peak memory 206204 kb
Host smart-ee6e164b-8f40-433f-900c-5e9495c39f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36253
648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.36253648
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3406613139
Short name T1056
Test name
Test status
Simulation time 71650433 ps
CPU time 0.7 seconds
Started Jul 04 06:13:04 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206184 kb
Host smart-01ccaced-f8d7-45d9-8add-8c1e3b1ecf4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34066
13139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3406613139
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1009498570
Short name T713
Test name
Test status
Simulation time 814890692 ps
CPU time 2.18 seconds
Started Jul 04 06:12:53 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206368 kb
Host smart-4449d8ca-2eec-4b85-a73f-b09aec29c79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10094
98570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1009498570
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2714464651
Short name T1903
Test name
Test status
Simulation time 420420135 ps
CPU time 2.51 seconds
Started Jul 04 06:12:59 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206400 kb
Host smart-6f111bb6-21d1-4e7c-8d54-a79a4aa5dcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27144
64651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2714464651
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3851952517
Short name T435
Test name
Test status
Simulation time 236808674 ps
CPU time 0.93 seconds
Started Jul 04 06:13:04 PM PDT 24
Finished Jul 04 06:13:06 PM PDT 24
Peak memory 206188 kb
Host smart-ccd4b6a9-e979-4f4f-a943-18d22e6c8966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
52517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3851952517
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2625497777
Short name T692
Test name
Test status
Simulation time 143120997 ps
CPU time 0.77 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 206192 kb
Host smart-3e7bc0d8-9276-4bf4-bab0-f2ca74c75f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26254
97777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2625497777
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1628415152
Short name T265
Test name
Test status
Simulation time 218853932 ps
CPU time 0.98 seconds
Started Jul 04 06:12:58 PM PDT 24
Finished Jul 04 06:13:00 PM PDT 24
Peak memory 206108 kb
Host smart-e0d86b1c-81a0-4605-a39a-f6856db71324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
15152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1628415152
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.213550792
Short name T2302
Test name
Test status
Simulation time 232773242 ps
CPU time 0.87 seconds
Started Jul 04 06:12:59 PM PDT 24
Finished Jul 04 06:13:00 PM PDT 24
Peak memory 206156 kb
Host smart-28020c58-8d38-4777-8f93-4e8666642789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21355
0792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.213550792
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1628162951
Short name T1741
Test name
Test status
Simulation time 23320934205 ps
CPU time 22.65 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:13:19 PM PDT 24
Peak memory 206240 kb
Host smart-79f8b907-3c8a-420c-afaf-f02b528bcf89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
62951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1628162951
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.494903445
Short name T2676
Test name
Test status
Simulation time 3330893082 ps
CPU time 3.96 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:59 PM PDT 24
Peak memory 206260 kb
Host smart-b053d3e5-911e-4d73-85b3-c40267d79b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49490
3445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.494903445
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2139561040
Short name T246
Test name
Test status
Simulation time 11336890231 ps
CPU time 322.55 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 206504 kb
Host smart-f33f0703-70ae-4e1f-97d1-a30158d92b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21395
61040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2139561040
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1180556461
Short name T2551
Test name
Test status
Simulation time 4055228523 ps
CPU time 112.9 seconds
Started Jul 04 06:12:56 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206432 kb
Host smart-067da607-b864-4c29-8762-ce720862459e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1180556461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1180556461
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1799031237
Short name T2590
Test name
Test status
Simulation time 274488232 ps
CPU time 0.94 seconds
Started Jul 04 06:12:58 PM PDT 24
Finished Jul 04 06:12:59 PM PDT 24
Peak memory 206204 kb
Host smart-464c8788-a6f8-4e22-9956-cc89b56247c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1799031237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1799031237
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2276730237
Short name T1499
Test name
Test status
Simulation time 187252029 ps
CPU time 0.89 seconds
Started Jul 04 06:12:55 PM PDT 24
Finished Jul 04 06:12:56 PM PDT 24
Peak memory 206144 kb
Host smart-868763b1-4fbf-4a80-abc7-ba3f82e23926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
30237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2276730237
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3533284165
Short name T1016
Test name
Test status
Simulation time 4707815171 ps
CPU time 34.49 seconds
Started Jul 04 06:12:58 PM PDT 24
Finished Jul 04 06:13:33 PM PDT 24
Peak memory 206440 kb
Host smart-3640c537-9e35-402f-8851-b306281a219a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
84165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3533284165
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2319397591
Short name T2031
Test name
Test status
Simulation time 4638960659 ps
CPU time 44.98 seconds
Started Jul 04 06:12:57 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206356 kb
Host smart-c70f0f43-9d83-4a5b-ba51-70e18daf77a0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2319397591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2319397591
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1987910515
Short name T1437
Test name
Test status
Simulation time 160331323 ps
CPU time 0.8 seconds
Started Jul 04 06:12:58 PM PDT 24
Finished Jul 04 06:13:00 PM PDT 24
Peak memory 206204 kb
Host smart-15cea184-7f19-4933-9b14-9c7ac5d20281
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1987910515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1987910515
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.15417220
Short name T2540
Test name
Test status
Simulation time 145649001 ps
CPU time 0.75 seconds
Started Jul 04 06:12:53 PM PDT 24
Finished Jul 04 06:12:54 PM PDT 24
Peak memory 206220 kb
Host smart-24ccfc0e-4d0d-430c-aa8f-d9f7870627aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15417
220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.15417220
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3050904486
Short name T2125
Test name
Test status
Simulation time 210401211 ps
CPU time 0.88 seconds
Started Jul 04 06:12:57 PM PDT 24
Finished Jul 04 06:12:58 PM PDT 24
Peak memory 206196 kb
Host smart-e93a0464-3d6f-48bd-8398-3f1ea1407308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30509
04486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3050904486
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.806020697
Short name T2136
Test name
Test status
Simulation time 208043839 ps
CPU time 0.92 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206188 kb
Host smart-2b847082-8ed0-4a9d-9837-d1633f402211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80602
0697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.806020697
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2668952031
Short name T959
Test name
Test status
Simulation time 172961307 ps
CPU time 0.96 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206208 kb
Host smart-57e8cbcb-bf93-439c-b25b-87c2cb5af47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26689
52031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2668952031
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3427540088
Short name T2238
Test name
Test status
Simulation time 197509040 ps
CPU time 0.81 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:03 PM PDT 24
Peak memory 206196 kb
Host smart-1900d087-28fa-4695-82a7-d1b163acb182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
40088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3427540088
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3172441829
Short name T178
Test name
Test status
Simulation time 162101563 ps
CPU time 0.83 seconds
Started Jul 04 06:13:04 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206192 kb
Host smart-54c30631-b59e-4253-beae-a23107d20e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
41829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3172441829
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3175490004
Short name T2596
Test name
Test status
Simulation time 209121014 ps
CPU time 0.99 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206204 kb
Host smart-9ee33ac4-d275-4cc6-97f2-98273d1e2261
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3175490004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3175490004
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.891037958
Short name T1019
Test name
Test status
Simulation time 165755590 ps
CPU time 0.75 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206160 kb
Host smart-c47f2445-7210-4208-9a25-9a21a8192449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89103
7958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.891037958
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1115476688
Short name T1445
Test name
Test status
Simulation time 78048519 ps
CPU time 0.73 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206204 kb
Host smart-841bb688-1fb5-40c3-976a-11df127851e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11154
76688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1115476688
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3669931501
Short name T1391
Test name
Test status
Simulation time 18479290898 ps
CPU time 40.92 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206544 kb
Host smart-c2a47ebd-85e0-4fb7-a60e-ef11830511cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36699
31501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3669931501
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3412193132
Short name T305
Test name
Test status
Simulation time 157768148 ps
CPU time 0.83 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206192 kb
Host smart-82c07843-74e4-4fc6-aeb8-51d77b228883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34121
93132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3412193132
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1874127638
Short name T422
Test name
Test status
Simulation time 287310246 ps
CPU time 1 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:03 PM PDT 24
Peak memory 206188 kb
Host smart-d261456e-dc19-42db-83a6-af907066ea36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18741
27638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1874127638
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.240479015
Short name T431
Test name
Test status
Simulation time 226284321 ps
CPU time 0.91 seconds
Started Jul 04 06:13:04 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206180 kb
Host smart-ca20dbaf-ae99-4034-92e0-2fb6c6b59177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24047
9015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.240479015
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.4140999461
Short name T679
Test name
Test status
Simulation time 154430336 ps
CPU time 0.82 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206196 kb
Host smart-35e3b9d4-3aff-4ff6-ba2b-2612fd586255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
99461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.4140999461
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1216338279
Short name T89
Test name
Test status
Simulation time 142630831 ps
CPU time 0.78 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206172 kb
Host smart-74c8f897-9117-4184-a13e-e8a5edfa4f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12163
38279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1216338279
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.281262404
Short name T670
Test name
Test status
Simulation time 178421990 ps
CPU time 0.83 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206184 kb
Host smart-ba7c8970-6225-4932-81a8-8756f2e27853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28126
2404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.281262404
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.4112439050
Short name T2140
Test name
Test status
Simulation time 150119886 ps
CPU time 0.82 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206124 kb
Host smart-253881c5-f193-41cc-bcf5-c23ec4c2700e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41124
39050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.4112439050
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2758431540
Short name T2608
Test name
Test status
Simulation time 288899487 ps
CPU time 0.96 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:05 PM PDT 24
Peak memory 206208 kb
Host smart-6735e0a4-9092-4d9a-95dc-3d17bf546bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27584
31540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2758431540
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3702711486
Short name T752
Test name
Test status
Simulation time 6120321629 ps
CPU time 165.17 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:15:46 PM PDT 24
Peak memory 206532 kb
Host smart-aba6eee0-13dd-406c-b4c5-ed8afaa59eda
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3702711486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3702711486
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1534431072
Short name T1515
Test name
Test status
Simulation time 175469131 ps
CPU time 0.79 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206108 kb
Host smart-0e2881ef-8876-46ee-927a-a93e33623a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15344
31072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1534431072
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1435606782
Short name T405
Test name
Test status
Simulation time 156892588 ps
CPU time 0.84 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206208 kb
Host smart-28128105-d01c-45a0-83cc-e39a1d7beaeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14356
06782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1435606782
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.3952608436
Short name T1465
Test name
Test status
Simulation time 453822464 ps
CPU time 1.36 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206216 kb
Host smart-a55f54df-415f-41fb-a9a6-72f9943582ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
08436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3952608436
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.616673656
Short name T1495
Test name
Test status
Simulation time 4420039761 ps
CPU time 119.57 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:15:00 PM PDT 24
Peak memory 206488 kb
Host smart-f5fa16b2-3754-42dc-84b9-10d9fa022075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61667
3656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.616673656
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1608127807
Short name T2396
Test name
Test status
Simulation time 41928571 ps
CPU time 0.68 seconds
Started Jul 04 06:06:52 PM PDT 24
Finished Jul 04 06:06:52 PM PDT 24
Peak memory 205856 kb
Host smart-cb69b02b-0f70-44e2-a4d7-e3459d2c628a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1608127807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1608127807
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3415876694
Short name T2047
Test name
Test status
Simulation time 3457927289 ps
CPU time 4 seconds
Started Jul 04 06:06:18 PM PDT 24
Finished Jul 04 06:06:23 PM PDT 24
Peak memory 206240 kb
Host smart-8203d6c1-3430-4888-ad9e-2506c3ab6eb9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3415876694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3415876694
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4169122963
Short name T1126
Test name
Test status
Simulation time 13524044195 ps
CPU time 12.82 seconds
Started Jul 04 06:06:22 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 206428 kb
Host smart-e72f09fb-5329-43fc-bb0d-1a02e1967afe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4169122963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4169122963
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3141125045
Short name T1524
Test name
Test status
Simulation time 23327691507 ps
CPU time 24.73 seconds
Started Jul 04 06:06:19 PM PDT 24
Finished Jul 04 06:06:44 PM PDT 24
Peak memory 206456 kb
Host smart-c94c20b0-444b-4f9e-831d-37e258abea04
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3141125045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3141125045
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2746574553
Short name T2657
Test name
Test status
Simulation time 165010305 ps
CPU time 0.81 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:06:27 PM PDT 24
Peak memory 206204 kb
Host smart-05e71446-d7cf-41be-b20f-a5e9554f1b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
74553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2746574553
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2463426737
Short name T52
Test name
Test status
Simulation time 203253022 ps
CPU time 0.9 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:06:27 PM PDT 24
Peak memory 206144 kb
Host smart-6de40cfe-c85a-4d00-a33d-d6b45bcc97c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
26737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2463426737
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2660965035
Short name T68
Test name
Test status
Simulation time 150166258 ps
CPU time 0.79 seconds
Started Jul 04 06:06:25 PM PDT 24
Finished Jul 04 06:06:26 PM PDT 24
Peak memory 206120 kb
Host smart-b27a7039-6982-474c-af2a-203bfe30d7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609
65035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2660965035
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2919040697
Short name T1410
Test name
Test status
Simulation time 157631878 ps
CPU time 0.77 seconds
Started Jul 04 06:06:28 PM PDT 24
Finished Jul 04 06:06:29 PM PDT 24
Peak memory 206172 kb
Host smart-fbd5285f-de8d-436c-a670-8aa1be6fd587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29190
40697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2919040697
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1803505613
Short name T601
Test name
Test status
Simulation time 324628061 ps
CPU time 1.15 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:06:27 PM PDT 24
Peak memory 206204 kb
Host smart-b7cf3589-4a93-4b28-8b47-2c1f0c2d4d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18035
05613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1803505613
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1440901380
Short name T1978
Test name
Test status
Simulation time 821387555 ps
CPU time 1.76 seconds
Started Jul 04 06:06:24 PM PDT 24
Finished Jul 04 06:06:27 PM PDT 24
Peak memory 206492 kb
Host smart-b2ba2b9c-91a3-47d4-8c33-12af69855080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14409
01380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1440901380
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.4191820202
Short name T2020
Test name
Test status
Simulation time 16245858268 ps
CPU time 28.29 seconds
Started Jul 04 06:06:27 PM PDT 24
Finished Jul 04 06:06:55 PM PDT 24
Peak memory 206500 kb
Host smart-0a212a02-5798-4cf1-8dba-9b6f53e7de44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41918
20202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.4191820202
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.825165829
Short name T1149
Test name
Test status
Simulation time 397319740 ps
CPU time 1.28 seconds
Started Jul 04 06:06:27 PM PDT 24
Finished Jul 04 06:06:28 PM PDT 24
Peak memory 206184 kb
Host smart-89003534-1ed8-4586-9759-1caee6117674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82516
5829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.825165829
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2053349047
Short name T630
Test name
Test status
Simulation time 137733452 ps
CPU time 0.75 seconds
Started Jul 04 06:06:25 PM PDT 24
Finished Jul 04 06:06:26 PM PDT 24
Peak memory 206208 kb
Host smart-54b31855-536d-42b7-9527-8c9d3dd2d6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20533
49047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2053349047
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3696166278
Short name T973
Test name
Test status
Simulation time 31160095 ps
CPU time 0.65 seconds
Started Jul 04 06:06:24 PM PDT 24
Finished Jul 04 06:06:25 PM PDT 24
Peak memory 206188 kb
Host smart-4fa5e28f-b33b-4d3b-b46e-db09e5d9dab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
66278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3696166278
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1527781923
Short name T1831
Test name
Test status
Simulation time 743196675 ps
CPU time 1.93 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:06:28 PM PDT 24
Peak memory 206452 kb
Host smart-a94624fd-7576-4b22-ad6f-3a85182f2f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
81923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1527781923
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1756677353
Short name T1997
Test name
Test status
Simulation time 229535627 ps
CPU time 2.14 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:06:28 PM PDT 24
Peak memory 206416 kb
Host smart-2a172e00-f266-4012-a562-d4fc946a5322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17566
77353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1756677353
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.4098204699
Short name T662
Test name
Test status
Simulation time 106219266195 ps
CPU time 143.77 seconds
Started Jul 04 06:06:25 PM PDT 24
Finished Jul 04 06:08:49 PM PDT 24
Peak memory 206492 kb
Host smart-9710dfe2-ce8d-437c-b8eb-25aa3813612a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4098204699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.4098204699
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.4188114052
Short name T1114
Test name
Test status
Simulation time 108091606925 ps
CPU time 142.19 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:08:49 PM PDT 24
Peak memory 206460 kb
Host smart-8819a9e6-f874-4710-8b21-e815caa48cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188114052 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.4188114052
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2298546273
Short name T1628
Test name
Test status
Simulation time 116090257180 ps
CPU time 150.27 seconds
Started Jul 04 06:06:25 PM PDT 24
Finished Jul 04 06:08:56 PM PDT 24
Peak memory 206452 kb
Host smart-08e96b37-6aae-4ef0-896a-c19d54ff8186
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2298546273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2298546273
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.167495618
Short name T1544
Test name
Test status
Simulation time 88216386556 ps
CPU time 120.55 seconds
Started Jul 04 06:06:25 PM PDT 24
Finished Jul 04 06:08:25 PM PDT 24
Peak memory 206404 kb
Host smart-8f59c3b3-c239-471c-8da0-9fe5ec0da702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167495618 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.167495618
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.4103409992
Short name T2652
Test name
Test status
Simulation time 102174161426 ps
CPU time 151.71 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206408 kb
Host smart-769028f7-7db7-4f81-9afd-31e916a4ee09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41034
09992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.4103409992
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2253457819
Short name T1182
Test name
Test status
Simulation time 219573027 ps
CPU time 0.88 seconds
Started Jul 04 06:06:26 PM PDT 24
Finished Jul 04 06:06:27 PM PDT 24
Peak memory 206208 kb
Host smart-e5e37178-1c47-4e84-9c23-58b88cd9c5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534
57819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2253457819
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3178071033
Short name T2363
Test name
Test status
Simulation time 182811475 ps
CPU time 0.79 seconds
Started Jul 04 06:06:32 PM PDT 24
Finished Jul 04 06:06:33 PM PDT 24
Peak memory 206196 kb
Host smart-8f66c97b-7fda-4baa-90d4-30c2f09e032f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31780
71033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3178071033
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1355195005
Short name T1139
Test name
Test status
Simulation time 223879500 ps
CPU time 0.9 seconds
Started Jul 04 06:06:34 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 206140 kb
Host smart-83604a43-66f7-4224-989e-e78d1d2e6e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
95005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1355195005
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1370383755
Short name T2189
Test name
Test status
Simulation time 180293115 ps
CPU time 0.84 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206164 kb
Host smart-bac16072-f26d-4709-b8c8-2a67d7061556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13703
83755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1370383755
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3508593726
Short name T989
Test name
Test status
Simulation time 23270787533 ps
CPU time 26.05 seconds
Started Jul 04 06:06:32 PM PDT 24
Finished Jul 04 06:06:58 PM PDT 24
Peak memory 206240 kb
Host smart-8caa5ea9-a619-4589-b746-2f4ce56272aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
93726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3508593726
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1601645888
Short name T2268
Test name
Test status
Simulation time 3281083747 ps
CPU time 3.72 seconds
Started Jul 04 06:06:32 PM PDT 24
Finished Jul 04 06:06:36 PM PDT 24
Peak memory 206276 kb
Host smart-dc8e2394-4903-48b9-8cf7-5007ace0b3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16016
45888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1601645888
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1662973512
Short name T2277
Test name
Test status
Simulation time 9235867798 ps
CPU time 77.82 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:07:51 PM PDT 24
Peak memory 206536 kb
Host smart-0c0309af-d090-4bfd-afeb-3e8d96226467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
73512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1662973512
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1549145454
Short name T1449
Test name
Test status
Simulation time 7052422572 ps
CPU time 49.54 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:07:23 PM PDT 24
Peak memory 206452 kb
Host smart-4b00639c-398b-4001-b69c-ba6e7d2fc7b6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1549145454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1549145454
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2538370470
Short name T2629
Test name
Test status
Simulation time 287195112 ps
CPU time 0.99 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206188 kb
Host smart-e2ac4dcd-660f-41c8-83a3-f5b66d20764e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2538370470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2538370470
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.662347166
Short name T548
Test name
Test status
Simulation time 201865029 ps
CPU time 0.89 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206180 kb
Host smart-03927692-2bce-4fb0-9daa-f7d6529ca809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66234
7166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.662347166
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1263473519
Short name T1892
Test name
Test status
Simulation time 5880243860 ps
CPU time 167.15 seconds
Started Jul 04 06:06:32 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206492 kb
Host smart-01c3ae79-be89-4171-8934-cf618b7bb372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12634
73519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1263473519
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1377524197
Short name T2208
Test name
Test status
Simulation time 4740977818 ps
CPU time 132.21 seconds
Started Jul 04 06:06:32 PM PDT 24
Finished Jul 04 06:08:44 PM PDT 24
Peak memory 206472 kb
Host smart-3dd1ed0e-0a05-4d66-bb93-db8c8fc4c145
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1377524197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1377524197
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2131492034
Short name T821
Test name
Test status
Simulation time 166881486 ps
CPU time 0.82 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206212 kb
Host smart-e6a1a33d-eeac-45b7-aa3d-ff9e625201c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2131492034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2131492034
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1382925536
Short name T2198
Test name
Test status
Simulation time 145285498 ps
CPU time 0.82 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206196 kb
Host smart-9e7ce015-081b-4133-99f4-88d00eef95a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
25536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1382925536
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3260985120
Short name T1938
Test name
Test status
Simulation time 259290038 ps
CPU time 0.91 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206192 kb
Host smart-5ba35162-0abc-42d4-b5ed-854071998e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32609
85120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3260985120
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.972393951
Short name T102
Test name
Test status
Simulation time 156202186 ps
CPU time 0.79 seconds
Started Jul 04 06:06:33 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 206204 kb
Host smart-c997720f-d122-4d5a-844b-8de772486768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97239
3951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.972393951
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2120856495
Short name T2036
Test name
Test status
Simulation time 196388383 ps
CPU time 0.84 seconds
Started Jul 04 06:06:34 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 206164 kb
Host smart-41a24d96-0472-4d5d-8233-e97226b4c382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208
56495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2120856495
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.879895199
Short name T2023
Test name
Test status
Simulation time 174493780 ps
CPU time 0.83 seconds
Started Jul 04 06:06:34 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 206140 kb
Host smart-f11add78-6188-4426-8e8f-ca865c56acbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87989
5199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.879895199
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3611494278
Short name T1084
Test name
Test status
Simulation time 226910216 ps
CPU time 0.9 seconds
Started Jul 04 06:06:41 PM PDT 24
Finished Jul 04 06:06:42 PM PDT 24
Peak memory 206208 kb
Host smart-f93d2fe7-69cb-4db6-8a6a-d519317e4aac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3611494278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3611494278
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2405189989
Short name T49
Test name
Test status
Simulation time 201668170 ps
CPU time 0.88 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:06:41 PM PDT 24
Peak memory 206192 kb
Host smart-97bc3be9-8399-4aa7-b15a-bc7cff7809f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24051
89989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2405189989
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.118590695
Short name T2532
Test name
Test status
Simulation time 152633084 ps
CPU time 0.81 seconds
Started Jul 04 06:06:39 PM PDT 24
Finished Jul 04 06:06:40 PM PDT 24
Peak memory 206176 kb
Host smart-7d9e081b-ba8d-4002-a101-3fd5fa7a3525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11859
0695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.118590695
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1703424896
Short name T967
Test name
Test status
Simulation time 66847994 ps
CPU time 0.69 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:06:41 PM PDT 24
Peak memory 206164 kb
Host smart-6d859905-948d-44cb-ac6c-59228131ad3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
24896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1703424896
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.918898802
Short name T2591
Test name
Test status
Simulation time 9500383348 ps
CPU time 21.58 seconds
Started Jul 04 06:06:39 PM PDT 24
Finished Jul 04 06:07:01 PM PDT 24
Peak memory 206552 kb
Host smart-6ae2ab69-ee6e-494b-8264-89f060bbfce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91889
8802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.918898802
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3656880479
Short name T974
Test name
Test status
Simulation time 186555505 ps
CPU time 0.88 seconds
Started Jul 04 06:06:39 PM PDT 24
Finished Jul 04 06:06:40 PM PDT 24
Peak memory 206192 kb
Host smart-6bb7fd7c-46c6-4a0d-9faa-5a89cb881b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36568
80479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3656880479
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2375737174
Short name T1179
Test name
Test status
Simulation time 255073654 ps
CPU time 0.87 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:06:41 PM PDT 24
Peak memory 206180 kb
Host smart-48691428-2d9d-4f65-b52c-7d0701517305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
37174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2375737174
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1975023052
Short name T2187
Test name
Test status
Simulation time 6988609116 ps
CPU time 81.73 seconds
Started Jul 04 06:06:38 PM PDT 24
Finished Jul 04 06:08:00 PM PDT 24
Peak memory 206560 kb
Host smart-8d5f011d-3fff-4c91-bc7f-de2170c23b22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1975023052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1975023052
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.373019063
Short name T1622
Test name
Test status
Simulation time 10004314080 ps
CPU time 241.97 seconds
Started Jul 04 06:06:38 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206560 kb
Host smart-cc61a0d1-ffd1-4718-9ba4-eded0082b061
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=373019063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.373019063
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.4101440157
Short name T655
Test name
Test status
Simulation time 16233813086 ps
CPU time 92.85 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:08:13 PM PDT 24
Peak memory 206428 kb
Host smart-f1651e0a-52d9-47b9-b75a-c017cdb803ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4101440157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.4101440157
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1557007030
Short name T466
Test name
Test status
Simulation time 266107476 ps
CPU time 1 seconds
Started Jul 04 06:06:41 PM PDT 24
Finished Jul 04 06:06:42 PM PDT 24
Peak memory 206180 kb
Host smart-d2fa0061-bcbe-47f9-9003-08d6e8529bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15570
07030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1557007030
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2323110298
Short name T2344
Test name
Test status
Simulation time 157721994 ps
CPU time 0.8 seconds
Started Jul 04 06:06:41 PM PDT 24
Finished Jul 04 06:06:42 PM PDT 24
Peak memory 206200 kb
Host smart-7cfc5075-c26e-48fd-bd6b-25818c75f5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
10298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2323110298
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.559951693
Short name T2375
Test name
Test status
Simulation time 164284461 ps
CPU time 0.76 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:06:41 PM PDT 24
Peak memory 206180 kb
Host smart-8b4a0301-6d20-47ac-95ac-78dcdbe8538f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55995
1693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.559951693
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3601905695
Short name T79
Test name
Test status
Simulation time 163167414 ps
CPU time 0.77 seconds
Started Jul 04 06:06:41 PM PDT 24
Finished Jul 04 06:06:42 PM PDT 24
Peak memory 206144 kb
Host smart-f9f12b19-0dd6-4bf4-be26-94a8fe65c3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
05695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3601905695
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2602564629
Short name T230
Test name
Test status
Simulation time 396343338 ps
CPU time 1.29 seconds
Started Jul 04 06:06:50 PM PDT 24
Finished Jul 04 06:06:51 PM PDT 24
Peak memory 224076 kb
Host smart-81ecd496-2376-4a50-98a4-423ccb94000c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2602564629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2602564629
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1138574330
Short name T56
Test name
Test status
Simulation time 438357760 ps
CPU time 1.35 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:06:42 PM PDT 24
Peak memory 206212 kb
Host smart-cb75fd0b-200e-4b39-9ae6-0495b1c585e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
74330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1138574330
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3651674220
Short name T1749
Test name
Test status
Simulation time 240258395 ps
CPU time 0.92 seconds
Started Jul 04 06:06:40 PM PDT 24
Finished Jul 04 06:06:41 PM PDT 24
Peak memory 206192 kb
Host smart-1e5e8fa7-bee5-48e9-80b0-7419dfce4323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36516
74220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3651674220
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3050740002
Short name T1328
Test name
Test status
Simulation time 164057510 ps
CPU time 0.78 seconds
Started Jul 04 06:06:50 PM PDT 24
Finished Jul 04 06:06:51 PM PDT 24
Peak memory 206208 kb
Host smart-6c8c869f-3a4e-4b83-9c02-7cef78eca187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30507
40002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3050740002
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.809932527
Short name T1985
Test name
Test status
Simulation time 152565668 ps
CPU time 0.8 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:06:49 PM PDT 24
Peak memory 206220 kb
Host smart-3465e122-6dd3-49d8-8b98-ec9b084fc869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80993
2527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.809932527
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2596909636
Short name T2055
Test name
Test status
Simulation time 201297266 ps
CPU time 0.94 seconds
Started Jul 04 06:06:49 PM PDT 24
Finished Jul 04 06:06:50 PM PDT 24
Peak memory 206224 kb
Host smart-fb3479ce-ec5b-4508-a103-c15dabaa7980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25969
09636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2596909636
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3098798317
Short name T2377
Test name
Test status
Simulation time 4468390950 ps
CPU time 43.37 seconds
Started Jul 04 06:06:49 PM PDT 24
Finished Jul 04 06:07:33 PM PDT 24
Peak memory 206484 kb
Host smart-a1e24a29-6a84-44c7-bc49-e444b15d7c53
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3098798317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3098798317
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2626020886
Short name T2064
Test name
Test status
Simulation time 162354592 ps
CPU time 0.87 seconds
Started Jul 04 06:06:50 PM PDT 24
Finished Jul 04 06:06:51 PM PDT 24
Peak memory 206172 kb
Host smart-855fda3f-1c89-4779-8d99-d2a6e03cc74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
20886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2626020886
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3085734847
Short name T2569
Test name
Test status
Simulation time 230913610 ps
CPU time 0.91 seconds
Started Jul 04 06:06:51 PM PDT 24
Finished Jul 04 06:06:52 PM PDT 24
Peak memory 206164 kb
Host smart-eedf6da9-bdba-4c43-b023-b12a0d9b5d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
34847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3085734847
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.4191842773
Short name T82
Test name
Test status
Simulation time 277162718 ps
CPU time 0.98 seconds
Started Jul 04 06:06:49 PM PDT 24
Finished Jul 04 06:06:50 PM PDT 24
Peak memory 206208 kb
Host smart-37aaccdb-0802-45a8-90ee-48c51a1404f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41918
42773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.4191842773
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3184851840
Short name T2118
Test name
Test status
Simulation time 4785939246 ps
CPU time 137.46 seconds
Started Jul 04 06:06:49 PM PDT 24
Finished Jul 04 06:09:07 PM PDT 24
Peak memory 206524 kb
Host smart-d41914b4-55fe-4900-933c-52e0a6e96f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31848
51840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3184851840
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.1202540951
Short name T1174
Test name
Test status
Simulation time 46236437 ps
CPU time 0.72 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206228 kb
Host smart-70b052b6-fe9a-40dd-946a-611041ea4b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1202540951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1202540951
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2569884272
Short name T2102
Test name
Test status
Simulation time 4311483598 ps
CPU time 5.03 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:07 PM PDT 24
Peak memory 206264 kb
Host smart-55c67bc4-8db5-4a63-aa79-ead9941fc296
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2569884272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2569884272
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2492394380
Short name T443
Test name
Test status
Simulation time 13323971600 ps
CPU time 14.74 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206260 kb
Host smart-415672dc-4997-436b-a32c-54e5b6846eed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2492394380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2492394380
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2298824812
Short name T414
Test name
Test status
Simulation time 23341443691 ps
CPU time 22.97 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:24 PM PDT 24
Peak memory 206196 kb
Host smart-cf136f0b-da05-4435-a7c7-34b2fdf7fe14
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2298824812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.2298824812
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3744395001
Short name T733
Test name
Test status
Simulation time 178433556 ps
CPU time 0.81 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206172 kb
Host smart-a2c3d6bd-2bb0-4026-8dd2-171b82cec597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37443
95001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3744395001
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2908044296
Short name T1022
Test name
Test status
Simulation time 151936170 ps
CPU time 0.82 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:02 PM PDT 24
Peak memory 206232 kb
Host smart-a3ac9035-32a8-46c3-a468-ee48499076b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29080
44296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2908044296
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3684070892
Short name T2348
Test name
Test status
Simulation time 424359895 ps
CPU time 1.47 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:03 PM PDT 24
Peak memory 206192 kb
Host smart-27893b0f-b8f5-498e-890a-c76ae5435635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
70892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3684070892
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3431632061
Short name T1240
Test name
Test status
Simulation time 1322253321 ps
CPU time 2.79 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:06 PM PDT 24
Peak memory 206460 kb
Host smart-64ffc8b5-07a5-4789-b463-058c4cabb49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34316
32061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3431632061
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1457057395
Short name T2342
Test name
Test status
Simulation time 22120411816 ps
CPU time 44.97 seconds
Started Jul 04 06:13:04 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206432 kb
Host smart-e554aafc-b55b-4032-aec2-a79e6b02f1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14570
57395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1457057395
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1421897816
Short name T2177
Test name
Test status
Simulation time 508275052 ps
CPU time 1.41 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206192 kb
Host smart-779f514d-d4e5-4201-95c0-fa6ea0e2566a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
97816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1421897816
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_enable.160846485
Short name T1810
Test name
Test status
Simulation time 51285857 ps
CPU time 0.71 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206192 kb
Host smart-f9057086-4689-4482-8d28-d6961e789bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
6485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.160846485
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3796976795
Short name T2448
Test name
Test status
Simulation time 902700022 ps
CPU time 1.96 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206356 kb
Host smart-e65074d1-6d2b-4194-938f-7c50794950e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37969
76795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3796976795
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1271626264
Short name T1675
Test name
Test status
Simulation time 306919395 ps
CPU time 2.36 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206400 kb
Host smart-5069c0f9-48b3-42d2-b256-befb6398b8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
26264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1271626264
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4198870207
Short name T2515
Test name
Test status
Simulation time 231891959 ps
CPU time 0.93 seconds
Started Jul 04 06:13:01 PM PDT 24
Finished Jul 04 06:13:03 PM PDT 24
Peak memory 206156 kb
Host smart-5622e870-49cd-49a7-aa6a-704c35cf3ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41988
70207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4198870207
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1012237602
Short name T1958
Test name
Test status
Simulation time 146792190 ps
CPU time 0.83 seconds
Started Jul 04 06:13:00 PM PDT 24
Finished Jul 04 06:13:01 PM PDT 24
Peak memory 206208 kb
Host smart-800a2177-2e22-4897-8d67-6b29101cccc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122
37602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1012237602
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2350627744
Short name T2391
Test name
Test status
Simulation time 221482441 ps
CPU time 0.92 seconds
Started Jul 04 06:13:03 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206204 kb
Host smart-8feac61e-1223-4866-98cb-63487e3fa756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
27744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2350627744
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2364567241
Short name T2553
Test name
Test status
Simulation time 190401433 ps
CPU time 0.79 seconds
Started Jul 04 06:13:02 PM PDT 24
Finished Jul 04 06:13:04 PM PDT 24
Peak memory 206200 kb
Host smart-e7109863-d47e-496d-a5ae-ab4ade77ffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
67241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2364567241
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3840134468
Short name T2466
Test name
Test status
Simulation time 23262770194 ps
CPU time 20.83 seconds
Started Jul 04 06:13:06 PM PDT 24
Finished Jul 04 06:13:27 PM PDT 24
Peak memory 206236 kb
Host smart-f47edc51-8805-493f-a659-4f8224d70d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38401
34468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3840134468
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.735100603
Short name T1761
Test name
Test status
Simulation time 3333518486 ps
CPU time 3.98 seconds
Started Jul 04 06:13:05 PM PDT 24
Finished Jul 04 06:13:10 PM PDT 24
Peak memory 206272 kb
Host smart-fa0398bb-2762-4d6c-8f58-a6100dd59781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73510
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.735100603
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1497892549
Short name T1692
Test name
Test status
Simulation time 8779637607 ps
CPU time 243.76 seconds
Started Jul 04 06:13:06 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 206524 kb
Host smart-838af23f-a403-494c-a65b-69cc76a03750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14978
92549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1497892549
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.119999063
Short name T1548
Test name
Test status
Simulation time 3851153539 ps
CPU time 102.3 seconds
Started Jul 04 06:13:08 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206464 kb
Host smart-1bf1129d-22b5-4abb-93e6-ac56e185f364
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=119999063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.119999063
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2485235315
Short name T517
Test name
Test status
Simulation time 253442070 ps
CPU time 0.93 seconds
Started Jul 04 06:13:06 PM PDT 24
Finished Jul 04 06:13:07 PM PDT 24
Peak memory 206204 kb
Host smart-046fb353-f15b-4acc-8a8c-a2fcd25a017c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2485235315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2485235315
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3694436871
Short name T710
Test name
Test status
Simulation time 188108784 ps
CPU time 0.88 seconds
Started Jul 04 06:13:08 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206172 kb
Host smart-bbac83e5-3b7e-480c-99a0-58c28f3cad87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36944
36871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3694436871
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1707237469
Short name T726
Test name
Test status
Simulation time 4403352657 ps
CPU time 114.48 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:15:07 PM PDT 24
Peak memory 206392 kb
Host smart-cc0ad150-c6f8-4a8c-86db-650e131068d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17072
37469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1707237469
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.212339494
Short name T2313
Test name
Test status
Simulation time 4325905115 ps
CPU time 120.85 seconds
Started Jul 04 06:13:07 PM PDT 24
Finished Jul 04 06:15:08 PM PDT 24
Peak memory 206452 kb
Host smart-0c78d3c2-ecac-451f-b277-0c731490fc74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=212339494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.212339494
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3637904655
Short name T2699
Test name
Test status
Simulation time 155034400 ps
CPU time 0.81 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:13:14 PM PDT 24
Peak memory 206192 kb
Host smart-d53ff59e-61af-4c2e-ba79-858170a96abf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3637904655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3637904655
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1094348789
Short name T1605
Test name
Test status
Simulation time 193986245 ps
CPU time 0.85 seconds
Started Jul 04 06:13:07 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206172 kb
Host smart-5b337c54-5dae-4cb5-8fff-da74636f901f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
48789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1094348789
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.752660207
Short name T101
Test name
Test status
Simulation time 176513750 ps
CPU time 0.86 seconds
Started Jul 04 06:13:12 PM PDT 24
Finished Jul 04 06:13:13 PM PDT 24
Peak memory 206176 kb
Host smart-2556ecd6-de82-42d5-8a85-a6723bfd69fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75266
0207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.752660207
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2084725417
Short name T2664
Test name
Test status
Simulation time 175284583 ps
CPU time 0.81 seconds
Started Jul 04 06:13:08 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206196 kb
Host smart-762a03a4-3289-4f38-93ee-bda260834caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20847
25417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2084725417
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.715607482
Short name T2574
Test name
Test status
Simulation time 183345975 ps
CPU time 0.9 seconds
Started Jul 04 06:13:08 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206208 kb
Host smart-17cdeea6-ac88-488a-9204-6a340c01b45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71560
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.715607482
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1234608746
Short name T182
Test name
Test status
Simulation time 150146857 ps
CPU time 0.76 seconds
Started Jul 04 06:13:09 PM PDT 24
Finished Jul 04 06:13:10 PM PDT 24
Peak memory 206188 kb
Host smart-2f3013e3-63f5-4739-8910-a6f78cf79797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346
08746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1234608746
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1132987077
Short name T2571
Test name
Test status
Simulation time 216440626 ps
CPU time 0.89 seconds
Started Jul 04 06:13:09 PM PDT 24
Finished Jul 04 06:13:10 PM PDT 24
Peak memory 206212 kb
Host smart-e9a83535-abfa-463a-9770-0976958bebf7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1132987077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1132987077
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.845202956
Short name T2290
Test name
Test status
Simulation time 151293608 ps
CPU time 0.81 seconds
Started Jul 04 06:13:08 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206156 kb
Host smart-e62e4a85-ac95-4199-9cc0-a96690873a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84520
2956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.845202956
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1363561116
Short name T944
Test name
Test status
Simulation time 37653283 ps
CPU time 0.66 seconds
Started Jul 04 06:13:12 PM PDT 24
Finished Jul 04 06:13:13 PM PDT 24
Peak memory 206156 kb
Host smart-797dd5fc-6013-4ac4-9b28-dec92a4db65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13635
61116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1363561116
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1391222022
Short name T659
Test name
Test status
Simulation time 9623697825 ps
CPU time 20.01 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:13:33 PM PDT 24
Peak memory 206420 kb
Host smart-47c01eee-614d-41ab-aba9-0f24f77df8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13912
22022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1391222022
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1850121391
Short name T2684
Test name
Test status
Simulation time 186769500 ps
CPU time 0.81 seconds
Started Jul 04 06:13:07 PM PDT 24
Finished Jul 04 06:13:08 PM PDT 24
Peak memory 206196 kb
Host smart-aa1a9584-50bf-45d1-875a-45fe3d3dfe11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
21391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1850121391
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1851996380
Short name T369
Test name
Test status
Simulation time 188430031 ps
CPU time 0.85 seconds
Started Jul 04 06:13:12 PM PDT 24
Finished Jul 04 06:13:13 PM PDT 24
Peak memory 206164 kb
Host smart-8de1b25c-f2df-4778-b30f-a308c7fe16f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18519
96380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1851996380
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1698161500
Short name T1128
Test name
Test status
Simulation time 203717589 ps
CPU time 0.89 seconds
Started Jul 04 06:13:07 PM PDT 24
Finished Jul 04 06:13:09 PM PDT 24
Peak memory 206176 kb
Host smart-fe97ab6f-e492-4a16-b291-b4541fca43a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16981
61500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1698161500
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.142955617
Short name T1032
Test name
Test status
Simulation time 178493440 ps
CPU time 0.82 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:13:14 PM PDT 24
Peak memory 206196 kb
Host smart-f2a3bc27-c6b9-4918-9e6f-cc100366bb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14295
5617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.142955617
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3541796152
Short name T1710
Test name
Test status
Simulation time 189120288 ps
CPU time 0.85 seconds
Started Jul 04 06:13:12 PM PDT 24
Finished Jul 04 06:13:13 PM PDT 24
Peak memory 206160 kb
Host smart-d224aa9f-ee85-45eb-8efc-e637878e30e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
96152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3541796152
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2221180222
Short name T1679
Test name
Test status
Simulation time 154655487 ps
CPU time 0.74 seconds
Started Jul 04 06:13:18 PM PDT 24
Finished Jul 04 06:13:19 PM PDT 24
Peak memory 206208 kb
Host smart-15cc24c9-900f-43d6-8245-1fbe7f69b053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22211
80222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2221180222
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2849689757
Short name T2681
Test name
Test status
Simulation time 181988261 ps
CPU time 0.82 seconds
Started Jul 04 06:13:16 PM PDT 24
Finished Jul 04 06:13:17 PM PDT 24
Peak memory 206168 kb
Host smart-d3e88d7b-7f15-4f49-887c-8054a9662247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
89757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2849689757
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2794569034
Short name T2062
Test name
Test status
Simulation time 241934857 ps
CPU time 0.97 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206188 kb
Host smart-048f800a-15a5-467d-a88c-0c6039be0917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27945
69034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2794569034
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.3839608328
Short name T1827
Test name
Test status
Simulation time 6243439014 ps
CPU time 167.82 seconds
Started Jul 04 06:13:14 PM PDT 24
Finished Jul 04 06:16:02 PM PDT 24
Peak memory 206520 kb
Host smart-92d9ec26-0db6-44bf-a0e2-bd55203e468e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3839608328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.3839608328
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1443475012
Short name T1485
Test name
Test status
Simulation time 208220004 ps
CPU time 0.84 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206164 kb
Host smart-fc434c88-f657-42aa-a0ae-d9beebd01944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
75012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1443475012
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3999732645
Short name T1190
Test name
Test status
Simulation time 146124079 ps
CPU time 0.83 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:13:14 PM PDT 24
Peak memory 206236 kb
Host smart-c17cdbe3-756f-4ce6-b67e-fedec699cded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39997
32645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3999732645
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1167548565
Short name T1695
Test name
Test status
Simulation time 1102119828 ps
CPU time 2.63 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:18 PM PDT 24
Peak memory 206456 kb
Host smart-411274fe-2cd0-4c05-994e-5642ec023aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11675
48565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1167548565
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.4097091928
Short name T2015
Test name
Test status
Simulation time 4197466982 ps
CPU time 42.25 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:57 PM PDT 24
Peak memory 206396 kb
Host smart-c2078542-fd70-48da-bc1a-4eeed62d7d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40970
91928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.4097091928
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.876630306
Short name T841
Test name
Test status
Simulation time 48451122 ps
CPU time 0.72 seconds
Started Jul 04 06:13:26 PM PDT 24
Finished Jul 04 06:13:27 PM PDT 24
Peak memory 206280 kb
Host smart-2bc2a88c-4f46-4254-87b2-8593d6eb1baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=876630306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.876630306
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2431225902
Short name T484
Test name
Test status
Simulation time 3852377668 ps
CPU time 5.24 seconds
Started Jul 04 06:13:14 PM PDT 24
Finished Jul 04 06:13:20 PM PDT 24
Peak memory 206456 kb
Host smart-dc484831-f349-4de5-9992-3e3d598a5346
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2431225902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2431225902
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3644270603
Short name T887
Test name
Test status
Simulation time 13349762809 ps
CPU time 12.67 seconds
Started Jul 04 06:13:18 PM PDT 24
Finished Jul 04 06:13:31 PM PDT 24
Peak memory 206192 kb
Host smart-307cd112-fcfc-4e28-b6b5-e52e1d1c931d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3644270603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3644270603
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3080365587
Short name T905
Test name
Test status
Simulation time 23341642887 ps
CPU time 23.55 seconds
Started Jul 04 06:13:11 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206236 kb
Host smart-673e756d-c749-4b08-b740-69ad0613a8e8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3080365587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3080365587
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3749268894
Short name T964
Test name
Test status
Simulation time 145937372 ps
CPU time 0.76 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:15 PM PDT 24
Peak memory 206140 kb
Host smart-746a995d-7703-4570-bf0c-986a87da8f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37492
68894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3749268894
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3566614553
Short name T65
Test name
Test status
Simulation time 146675740 ps
CPU time 0.75 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206212 kb
Host smart-5d226e69-3543-4402-b0e0-dada9515edae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35666
14553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3566614553
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1533665771
Short name T2455
Test name
Test status
Simulation time 150793379 ps
CPU time 0.9 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206196 kb
Host smart-6ec2a782-8841-426e-ab59-7b4a40f7f8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336
65771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1533665771
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.4292473758
Short name T1988
Test name
Test status
Simulation time 1454170090 ps
CPU time 3.24 seconds
Started Jul 04 06:13:13 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206380 kb
Host smart-f2446f1e-b5b7-4a34-b99e-9869b063c174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924
73758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.4292473758
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1686982808
Short name T1966
Test name
Test status
Simulation time 17969099401 ps
CPU time 34.64 seconds
Started Jul 04 06:13:18 PM PDT 24
Finished Jul 04 06:13:53 PM PDT 24
Peak memory 206444 kb
Host smart-75afb8c4-7fb4-4327-a15f-64e7172f1f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
82808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1686982808
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.1764726301
Short name T509
Test name
Test status
Simulation time 353796655 ps
CPU time 1.29 seconds
Started Jul 04 06:13:14 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206176 kb
Host smart-18e15780-e3cf-4318-ae2c-9f3bb87389a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17647
26301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.1764726301
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.638555457
Short name T41
Test name
Test status
Simulation time 157071465 ps
CPU time 0.76 seconds
Started Jul 04 06:13:16 PM PDT 24
Finished Jul 04 06:13:17 PM PDT 24
Peak memory 206160 kb
Host smart-ff3dbbb1-deb5-46eb-818c-b62eb55801a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63855
5457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.638555457
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3274248895
Short name T2276
Test name
Test status
Simulation time 39526981 ps
CPU time 0.68 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206164 kb
Host smart-778773ca-7b22-484c-98ee-2f39f93d715a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32742
48895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3274248895
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3551376782
Short name T362
Test name
Test status
Simulation time 926443908 ps
CPU time 2.09 seconds
Started Jul 04 06:13:14 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206388 kb
Host smart-38523cf8-2143-4724-82df-24b80adc65fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35513
76782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3551376782
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.480228832
Short name T1362
Test name
Test status
Simulation time 290474630 ps
CPU time 2.15 seconds
Started Jul 04 06:13:14 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206436 kb
Host smart-a6b44f39-6db5-46be-ac29-593d57bd5d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48022
8832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.480228832
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3963395673
Short name T119
Test name
Test status
Simulation time 242106589 ps
CPU time 0.92 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206196 kb
Host smart-1e119b92-8949-4997-8431-39d4440c49c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
95673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3963395673
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3712949321
Short name T1615
Test name
Test status
Simulation time 139907301 ps
CPU time 0.79 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:13:16 PM PDT 24
Peak memory 206204 kb
Host smart-d0aea39b-0211-451e-bed1-7132138d4040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37129
49321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3712949321
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.28907436
Short name T1188
Test name
Test status
Simulation time 198986230 ps
CPU time 0.91 seconds
Started Jul 04 06:13:14 PM PDT 24
Finished Jul 04 06:13:15 PM PDT 24
Peak memory 206208 kb
Host smart-29102c43-7a1f-4aa0-9f7b-1b28fb1904fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28907
436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.28907436
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.824276834
Short name T1959
Test name
Test status
Simulation time 9012931139 ps
CPU time 62.65 seconds
Started Jul 04 06:13:15 PM PDT 24
Finished Jul 04 06:14:18 PM PDT 24
Peak memory 206520 kb
Host smart-7786743d-b3f0-4010-90a2-10642875a469
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=824276834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.824276834
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1774206166
Short name T1798
Test name
Test status
Simulation time 165420303 ps
CPU time 0.83 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:13:22 PM PDT 24
Peak memory 206188 kb
Host smart-d18127ae-79e4-429c-903b-c42a72e48c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17742
06166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1774206166
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3871233907
Short name T1751
Test name
Test status
Simulation time 23278745450 ps
CPU time 28.51 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206288 kb
Host smart-29f5870f-b533-40bb-ae80-421727b9bd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
33907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3871233907
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2874705525
Short name T2548
Test name
Test status
Simulation time 3298103884 ps
CPU time 3.99 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:13:25 PM PDT 24
Peak memory 206260 kb
Host smart-0b2e65e1-d703-4063-afad-2ea364af37c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
05525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2874705525
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3351975233
Short name T2660
Test name
Test status
Simulation time 11280633390 ps
CPU time 111.84 seconds
Started Jul 04 06:13:24 PM PDT 24
Finished Jul 04 06:15:17 PM PDT 24
Peak memory 206568 kb
Host smart-3642f7cc-eb35-43e8-8c14-ec817304ccf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33519
75233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3351975233
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1625573831
Short name T1947
Test name
Test status
Simulation time 5093256121 ps
CPU time 143.64 seconds
Started Jul 04 06:13:22 PM PDT 24
Finished Jul 04 06:15:46 PM PDT 24
Peak memory 206440 kb
Host smart-2d749fb8-765f-4c86-a0b3-a933cebb4cfc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1625573831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1625573831
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1291623966
Short name T1855
Test name
Test status
Simulation time 233823790 ps
CPU time 0.88 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206212 kb
Host smart-d32a652f-ddcc-4019-9fff-0c211a1688d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1291623966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1291623966
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.944293475
Short name T2186
Test name
Test status
Simulation time 189177278 ps
CPU time 0.9 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:13:22 PM PDT 24
Peak memory 206132 kb
Host smart-66662ef3-4d77-40ea-8a7d-3bf7c5a4d2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94429
3475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.944293475
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1136152522
Short name T1021
Test name
Test status
Simulation time 6107928053 ps
CPU time 60.32 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:14:22 PM PDT 24
Peak memory 206492 kb
Host smart-5953bbf1-74e8-4d8b-ad5b-2d0999c65ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
52522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1136152522
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3411873633
Short name T999
Test name
Test status
Simulation time 5566172100 ps
CPU time 154.22 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:15:54 PM PDT 24
Peak memory 206420 kb
Host smart-e1889928-97d7-452d-90fe-a38bfb96af51
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3411873633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3411873633
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2570606146
Short name T2485
Test name
Test status
Simulation time 163254155 ps
CPU time 0.82 seconds
Started Jul 04 06:13:24 PM PDT 24
Finished Jul 04 06:13:25 PM PDT 24
Peak memory 206212 kb
Host smart-cf22358c-e4e5-4204-8946-554b0094ca6c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2570606146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2570606146
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3875421653
Short name T1251
Test name
Test status
Simulation time 152642700 ps
CPU time 0.81 seconds
Started Jul 04 06:13:22 PM PDT 24
Finished Jul 04 06:13:23 PM PDT 24
Peak memory 206184 kb
Host smart-e8f27e13-96a7-4147-8685-fd0c5e5e6c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
21653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3875421653
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2423612116
Short name T1462
Test name
Test status
Simulation time 187274664 ps
CPU time 0.87 seconds
Started Jul 04 06:13:18 PM PDT 24
Finished Jul 04 06:13:19 PM PDT 24
Peak memory 206224 kb
Host smart-b8ab4dac-6c51-437e-bfeb-527028292d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24236
12116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2423612116
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4100308623
Short name T577
Test name
Test status
Simulation time 177596693 ps
CPU time 0.81 seconds
Started Jul 04 06:13:22 PM PDT 24
Finished Jul 04 06:13:23 PM PDT 24
Peak memory 206176 kb
Host smart-c3b82cea-8b74-4847-bc9d-3c4505f1a5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41003
08623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4100308623
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1283422369
Short name T897
Test name
Test status
Simulation time 174837566 ps
CPU time 0.83 seconds
Started Jul 04 06:13:25 PM PDT 24
Finished Jul 04 06:13:26 PM PDT 24
Peak memory 206148 kb
Host smart-5a60427d-16ae-4d9f-b3f9-55a466cece68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12834
22369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1283422369
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3879253718
Short name T1059
Test name
Test status
Simulation time 150118848 ps
CPU time 0.77 seconds
Started Jul 04 06:13:24 PM PDT 24
Finished Jul 04 06:13:25 PM PDT 24
Peak memory 206192 kb
Host smart-1af3595f-5cfa-4cec-beec-e78ecc4cae18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38792
53718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3879253718
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.4103455916
Short name T433
Test name
Test status
Simulation time 200708611 ps
CPU time 0.86 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206148 kb
Host smart-e5befbfe-b6d9-4fcc-8ee7-5debfc29d9b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4103455916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.4103455916
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3499290886
Short name T212
Test name
Test status
Simulation time 199647797 ps
CPU time 0.81 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206160 kb
Host smart-212c6d96-a137-4702-ad21-aa2dd5442c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34992
90886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3499290886
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3160433496
Short name T1972
Test name
Test status
Simulation time 38831777 ps
CPU time 0.65 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:13:22 PM PDT 24
Peak memory 206184 kb
Host smart-6c121112-d89e-40e0-9e88-6f2d468d90ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31604
33496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3160433496
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1553131267
Short name T1629
Test name
Test status
Simulation time 19945492499 ps
CPU time 46.14 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206556 kb
Host smart-98486c6b-ebe2-412a-87db-64a124692d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
31267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1553131267
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1826390303
Short name T507
Test name
Test status
Simulation time 179433731 ps
CPU time 0.81 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:13:22 PM PDT 24
Peak memory 206168 kb
Host smart-cfeba58f-a4d0-4837-80d5-8e34f22093a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
90303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1826390303
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2461167977
Short name T1181
Test name
Test status
Simulation time 217909723 ps
CPU time 0.91 seconds
Started Jul 04 06:13:22 PM PDT 24
Finished Jul 04 06:13:23 PM PDT 24
Peak memory 206124 kb
Host smart-6231f3cc-7cc6-4721-9829-35ae18f60dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24611
67977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2461167977
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.4214898080
Short name T2476
Test name
Test status
Simulation time 258522221 ps
CPU time 0.93 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206180 kb
Host smart-92e73684-5923-455b-9f81-da54ae4f4f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42148
98080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.4214898080
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1026718561
Short name T1926
Test name
Test status
Simulation time 193782915 ps
CPU time 0.89 seconds
Started Jul 04 06:13:21 PM PDT 24
Finished Jul 04 06:13:22 PM PDT 24
Peak memory 206200 kb
Host smart-7e56779e-b564-46c2-939d-3551632f23a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
18561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1026718561
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2501965169
Short name T928
Test name
Test status
Simulation time 170257639 ps
CPU time 0.81 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206208 kb
Host smart-af7d0aee-1477-4756-99a9-a70eb1c44f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
65169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2501965169
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.741435329
Short name T429
Test name
Test status
Simulation time 218653784 ps
CPU time 0.89 seconds
Started Jul 04 06:13:25 PM PDT 24
Finished Jul 04 06:13:26 PM PDT 24
Peak memory 206144 kb
Host smart-ac658771-1ac7-4d77-b390-bb0b702dde93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74143
5329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.741435329
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3232164820
Short name T1612
Test name
Test status
Simulation time 146969238 ps
CPU time 0.78 seconds
Started Jul 04 06:13:18 PM PDT 24
Finished Jul 04 06:13:19 PM PDT 24
Peak memory 206176 kb
Host smart-a79c1b58-7a9f-4cbd-a6ff-15ed919f65a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32321
64820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3232164820
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2863439458
Short name T1756
Test name
Test status
Simulation time 258446920 ps
CPU time 1.07 seconds
Started Jul 04 06:13:20 PM PDT 24
Finished Jul 04 06:13:21 PM PDT 24
Peak memory 206172 kb
Host smart-16cc273a-6cd3-4e54-ab88-2bf18623b839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28634
39458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2863439458
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2439251382
Short name T1422
Test name
Test status
Simulation time 4245983501 ps
CPU time 40.98 seconds
Started Jul 04 06:13:19 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206464 kb
Host smart-e6895e4b-c3ec-4764-a927-2cff5611981e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2439251382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2439251382
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1031326123
Short name T2418
Test name
Test status
Simulation time 181862204 ps
CPU time 0.86 seconds
Started Jul 04 06:13:22 PM PDT 24
Finished Jul 04 06:13:23 PM PDT 24
Peak memory 206204 kb
Host smart-2dd8eeea-d327-4872-90fb-9faffad64cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10313
26123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1031326123
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1346016082
Short name T1923
Test name
Test status
Simulation time 178558540 ps
CPU time 0.81 seconds
Started Jul 04 06:13:28 PM PDT 24
Finished Jul 04 06:13:29 PM PDT 24
Peak memory 206200 kb
Host smart-00db01da-5537-420b-ba4e-797d3123abe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13460
16082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1346016082
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2290051219
Short name T1812
Test name
Test status
Simulation time 724403152 ps
CPU time 1.68 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:29 PM PDT 24
Peak memory 206408 kb
Host smart-a9e3ab89-2b1f-4668-9e44-5d77d27c75c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22900
51219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2290051219
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.599567251
Short name T1077
Test name
Test status
Simulation time 4847587267 ps
CPU time 46.91 seconds
Started Jul 04 06:13:26 PM PDT 24
Finished Jul 04 06:14:14 PM PDT 24
Peak memory 206416 kb
Host smart-d90c33c6-80a9-455c-ad4c-a7d2b082b9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59956
7251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.599567251
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.372574815
Short name T1333
Test name
Test status
Simulation time 71091586 ps
CPU time 0.68 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:33 PM PDT 24
Peak memory 206260 kb
Host smart-303acb3c-8169-4b8c-91c9-076eef0a1c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=372574815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.372574815
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.454397293
Short name T12
Test name
Test status
Simulation time 3887667861 ps
CPU time 4.26 seconds
Started Jul 04 06:13:26 PM PDT 24
Finished Jul 04 06:13:31 PM PDT 24
Peak memory 206272 kb
Host smart-a2a28bfe-b4f4-40e5-8c63-34ce9d023a94
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=454397293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.454397293
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.866441487
Short name T1071
Test name
Test status
Simulation time 13351910344 ps
CPU time 11.98 seconds
Started Jul 04 06:13:25 PM PDT 24
Finished Jul 04 06:13:37 PM PDT 24
Peak memory 206544 kb
Host smart-1daa6387-9b95-44f0-a66e-15c1b0c53169
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=866441487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.866441487
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2702244575
Short name T2392
Test name
Test status
Simulation time 23358041266 ps
CPU time 23.38 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:50 PM PDT 24
Peak memory 206260 kb
Host smart-9d307d23-6935-47c1-a399-9bc3e8c469bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2702244575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2702244575
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1157583924
Short name T2687
Test name
Test status
Simulation time 208383064 ps
CPU time 0.87 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:28 PM PDT 24
Peak memory 206208 kb
Host smart-ac0416e6-1318-47b0-88b1-f55f835570c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11575
83924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1157583924
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.605472029
Short name T64
Test name
Test status
Simulation time 151343287 ps
CPU time 0.82 seconds
Started Jul 04 06:13:30 PM PDT 24
Finished Jul 04 06:13:31 PM PDT 24
Peak memory 206168 kb
Host smart-50c19a9a-2a57-4e23-a374-a9f11cc82d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60547
2029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.605472029
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.583420800
Short name T190
Test name
Test status
Simulation time 295730961 ps
CPU time 1.12 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:28 PM PDT 24
Peak memory 206192 kb
Host smart-08fa6d30-296e-425a-98a1-e2c11c5d14c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58342
0800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.583420800
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2713518998
Short name T1023
Test name
Test status
Simulation time 586581163 ps
CPU time 1.61 seconds
Started Jul 04 06:13:26 PM PDT 24
Finished Jul 04 06:13:28 PM PDT 24
Peak memory 206132 kb
Host smart-51564dc7-a806-4f65-8e98-91cc80f1c037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27135
18998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2713518998
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3773323817
Short name T1395
Test name
Test status
Simulation time 10974305632 ps
CPU time 26.32 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206452 kb
Host smart-feed7c21-84a0-489c-9aad-923054342262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
23817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3773323817
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2464060142
Short name T1930
Test name
Test status
Simulation time 472514359 ps
CPU time 1.39 seconds
Started Jul 04 06:13:29 PM PDT 24
Finished Jul 04 06:13:30 PM PDT 24
Peak memory 206200 kb
Host smart-4f67a471-2ac2-4ded-8189-e5faa2910aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24640
60142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2464060142
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1939401286
Short name T2645
Test name
Test status
Simulation time 152098083 ps
CPU time 0.77 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:34 PM PDT 24
Peak memory 206160 kb
Host smart-ff743d42-33d8-487d-8ee8-069accf054b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
01286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1939401286
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2208131017
Short name T1617
Test name
Test status
Simulation time 44421205 ps
CPU time 0.68 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:28 PM PDT 24
Peak memory 206176 kb
Host smart-970466e8-cd90-40ba-a765-2eb74a6b2daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22081
31017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2208131017
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3598237815
Short name T232
Test name
Test status
Simulation time 1017773028 ps
CPU time 2.4 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:30 PM PDT 24
Peak memory 206396 kb
Host smart-1ff1d996-a80c-4922-a04a-3a8135550e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35982
37815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3598237815
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3372850236
Short name T546
Test name
Test status
Simulation time 208124997 ps
CPU time 1.36 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206348 kb
Host smart-bad70be9-d27b-4b1c-b476-65c3efada869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33728
50236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3372850236
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.32531639
Short name T2184
Test name
Test status
Simulation time 226080843 ps
CPU time 0.9 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:28 PM PDT 24
Peak memory 206172 kb
Host smart-0d2449c3-5aa2-4c44-a104-d72444dd7b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32531
639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.32531639
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1689681016
Short name T687
Test name
Test status
Simulation time 151295436 ps
CPU time 0.78 seconds
Started Jul 04 06:13:28 PM PDT 24
Finished Jul 04 06:13:29 PM PDT 24
Peak memory 206196 kb
Host smart-19d36c73-c2c8-49a6-b6b1-bc3fc2f5a570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
81016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1689681016
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.4244864036
Short name T1271
Test name
Test status
Simulation time 153030663 ps
CPU time 0.79 seconds
Started Jul 04 06:13:29 PM PDT 24
Finished Jul 04 06:13:30 PM PDT 24
Peak memory 206212 kb
Host smart-cbbb75df-4c35-4e87-84e9-de25b4b4845e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42448
64036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.4244864036
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1647170025
Short name T743
Test name
Test status
Simulation time 159736770 ps
CPU time 0.8 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206156 kb
Host smart-4f0d52f1-c83f-4ebc-b1ac-eed3f87d204d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16471
70025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1647170025
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.866266717
Short name T207
Test name
Test status
Simulation time 23363714079 ps
CPU time 25.51 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206220 kb
Host smart-b2d8f12f-75ee-4761-8a0d-ee8db01fbdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86626
6717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.866266717
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2803819119
Short name T2071
Test name
Test status
Simulation time 3372068133 ps
CPU time 3.88 seconds
Started Jul 04 06:13:26 PM PDT 24
Finished Jul 04 06:13:30 PM PDT 24
Peak memory 206240 kb
Host smart-38c956d4-3adf-4d7c-bb0e-dcbe63da5683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28038
19119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2803819119
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2150395850
Short name T368
Test name
Test status
Simulation time 10004848742 ps
CPU time 70.5 seconds
Started Jul 04 06:13:28 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206472 kb
Host smart-dc56922f-a772-449e-99ce-af90ec4423e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
95850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2150395850
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3561376855
Short name T753
Test name
Test status
Simulation time 5605149301 ps
CPU time 53.49 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:14:21 PM PDT 24
Peak memory 206512 kb
Host smart-459fc5f7-201a-47e3-8386-09c7e408b5d2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3561376855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3561376855
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1270180496
Short name T2287
Test name
Test status
Simulation time 245216178 ps
CPU time 0.9 seconds
Started Jul 04 06:13:27 PM PDT 24
Finished Jul 04 06:13:28 PM PDT 24
Peak memory 206128 kb
Host smart-45b49793-f39b-47c5-956b-ccd3f28b4e4e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1270180496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1270180496
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.433651448
Short name T608
Test name
Test status
Simulation time 223174289 ps
CPU time 0.89 seconds
Started Jul 04 06:13:26 PM PDT 24
Finished Jul 04 06:13:27 PM PDT 24
Peak memory 206216 kb
Host smart-aebb662c-ad94-4522-99ee-9b6be6a401ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43365
1448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.433651448
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.261591654
Short name T412
Test name
Test status
Simulation time 3127655258 ps
CPU time 29.53 seconds
Started Jul 04 06:13:37 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206496 kb
Host smart-83a57e31-4dc2-4063-8c40-d32d121c85c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26159
1654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.261591654
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.858391712
Short name T711
Test name
Test status
Simulation time 6928548645 ps
CPU time 54.89 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206464 kb
Host smart-ef9457b2-05a6-44dc-b573-32e34b2ad3b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=858391712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.858391712
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3476225825
Short name T667
Test name
Test status
Simulation time 150251886 ps
CPU time 0.8 seconds
Started Jul 04 06:13:36 PM PDT 24
Finished Jul 04 06:13:37 PM PDT 24
Peak memory 206192 kb
Host smart-296ce7c1-1840-4894-8813-8a6f58b4aaf1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3476225825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3476225825
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.4050926424
Short name T1444
Test name
Test status
Simulation time 156579208 ps
CPU time 0.74 seconds
Started Jul 04 06:13:31 PM PDT 24
Finished Jul 04 06:13:32 PM PDT 24
Peak memory 206192 kb
Host smart-3deae5dd-ae3b-4c35-bd54-717c973e706e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40509
26424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.4050926424
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2838581068
Short name T147
Test name
Test status
Simulation time 184554150 ps
CPU time 0.81 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:34 PM PDT 24
Peak memory 206208 kb
Host smart-ec887fd1-acdd-49c8-b06c-fb848bdec0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
81068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2838581068
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.514009815
Short name T1973
Test name
Test status
Simulation time 152486867 ps
CPU time 0.86 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:37 PM PDT 24
Peak memory 206176 kb
Host smart-1768f810-6b9b-4b22-b19b-87465829d2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51400
9815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.514009815
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1170369919
Short name T1507
Test name
Test status
Simulation time 214124965 ps
CPU time 0.87 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:34 PM PDT 24
Peak memory 206180 kb
Host smart-a800a5d3-52f9-42f0-90b5-03e489851637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11703
69919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1170369919
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.380055003
Short name T586
Test name
Test status
Simulation time 171408673 ps
CPU time 0.82 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206208 kb
Host smart-d3aef07f-86bf-4fe9-843a-6b7bb309dbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38005
5003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.380055003
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3026396073
Short name T2168
Test name
Test status
Simulation time 155634239 ps
CPU time 0.82 seconds
Started Jul 04 06:13:38 PM PDT 24
Finished Jul 04 06:13:39 PM PDT 24
Peak memory 206204 kb
Host smart-aceab5af-94cc-4f01-a7fc-4861eab7207a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30263
96073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3026396073
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2654519124
Short name T962
Test name
Test status
Simulation time 237457330 ps
CPU time 0.96 seconds
Started Jul 04 06:13:37 PM PDT 24
Finished Jul 04 06:13:39 PM PDT 24
Peak memory 206232 kb
Host smart-a3fe3c2f-7cdf-46b5-beac-94a4bb6ec067
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2654519124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2654519124
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3756946085
Short name T403
Test name
Test status
Simulation time 152254739 ps
CPU time 0.76 seconds
Started Jul 04 06:13:31 PM PDT 24
Finished Jul 04 06:13:32 PM PDT 24
Peak memory 206204 kb
Host smart-4274c009-bd9d-4774-9378-c9f95abd8b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37569
46085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3756946085
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1924353535
Short name T1569
Test name
Test status
Simulation time 36399262 ps
CPU time 0.65 seconds
Started Jul 04 06:13:37 PM PDT 24
Finished Jul 04 06:13:38 PM PDT 24
Peak memory 206204 kb
Host smart-55e7cce1-ee56-47ae-8206-c979ec192143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
53535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1924353535
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1092493253
Short name T1415
Test name
Test status
Simulation time 22363898294 ps
CPU time 50.71 seconds
Started Jul 04 06:13:36 PM PDT 24
Finished Jul 04 06:14:27 PM PDT 24
Peak memory 206508 kb
Host smart-201ece7e-09e4-4a7b-b8a4-c272699439b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10924
93253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1092493253
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2973620109
Short name T2241
Test name
Test status
Simulation time 236366289 ps
CPU time 0.9 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206128 kb
Host smart-081ef5f2-27df-4515-ac87-5d229b0dbaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29736
20109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2973620109
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1779746391
Short name T1604
Test name
Test status
Simulation time 261889595 ps
CPU time 0.87 seconds
Started Jul 04 06:13:31 PM PDT 24
Finished Jul 04 06:13:32 PM PDT 24
Peak memory 206180 kb
Host smart-c4f5c223-024f-4c3a-84fa-3205eceb190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
46391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1779746391
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3589413553
Short name T2514
Test name
Test status
Simulation time 213954448 ps
CPU time 0.83 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206216 kb
Host smart-4e4314b5-1210-48cc-be18-54f3c49e6778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35894
13553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3589413553
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1823681361
Short name T1117
Test name
Test status
Simulation time 205303020 ps
CPU time 0.83 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206220 kb
Host smart-a3496d5d-2f09-4af5-ac08-62bc63676001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
81361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1823681361
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3656358419
Short name T799
Test name
Test status
Simulation time 172695577 ps
CPU time 0.8 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:34 PM PDT 24
Peak memory 206192 kb
Host smart-66536730-1d2e-44a2-8e2d-8a7f31121551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36563
58419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3656358419
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3774780080
Short name T2460
Test name
Test status
Simulation time 163705023 ps
CPU time 0.87 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206176 kb
Host smart-32169d9d-19fe-4211-bd32-0cc8f9bd70a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37747
80080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3774780080
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1009999660
Short name T2426
Test name
Test status
Simulation time 197373867 ps
CPU time 0.83 seconds
Started Jul 04 06:13:31 PM PDT 24
Finished Jul 04 06:13:32 PM PDT 24
Peak memory 206160 kb
Host smart-5fe2830e-ce0b-40f3-a9b3-bb4188f33edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10099
99660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1009999660
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1545107008
Short name T1349
Test name
Test status
Simulation time 247567123 ps
CPU time 0.97 seconds
Started Jul 04 06:13:32 PM PDT 24
Finished Jul 04 06:13:33 PM PDT 24
Peak memory 206176 kb
Host smart-b3f130c2-1e6c-442b-9701-04c2572128d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15451
07008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1545107008
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2989576592
Short name T238
Test name
Test status
Simulation time 4000074791 ps
CPU time 115.65 seconds
Started Jul 04 06:13:32 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206500 kb
Host smart-c8c6723e-99da-4621-a8df-a8b79d6d4415
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2989576592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2989576592
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3622287336
Short name T1436
Test name
Test status
Simulation time 238384381 ps
CPU time 0.88 seconds
Started Jul 04 06:13:37 PM PDT 24
Finished Jul 04 06:13:38 PM PDT 24
Peak memory 206216 kb
Host smart-bd0ea16b-86b3-4930-a4c3-33f926e58f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36222
87336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3622287336
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1476241444
Short name T2134
Test name
Test status
Simulation time 196048406 ps
CPU time 0.88 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206180 kb
Host smart-4735d7b6-d4e1-4683-b92f-53a6b6b5c8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14762
41444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1476241444
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1972593557
Short name T2621
Test name
Test status
Simulation time 943859495 ps
CPU time 1.96 seconds
Started Jul 04 06:13:31 PM PDT 24
Finished Jul 04 06:13:34 PM PDT 24
Peak memory 206460 kb
Host smart-cb518509-03b6-4194-a1a0-f696dc041e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
93557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1972593557
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1285921193
Short name T637
Test name
Test status
Simulation time 5392950762 ps
CPU time 50.32 seconds
Started Jul 04 06:13:38 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206448 kb
Host smart-8978a86e-a864-447b-988e-8142a6afce9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12859
21193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1285921193
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.362922823
Short name T1866
Test name
Test status
Simulation time 45979674 ps
CPU time 0.71 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206220 kb
Host smart-5fd565d0-432e-4ed7-a0e0-dd29189b9993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=362922823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.362922823
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1423289845
Short name T882
Test name
Test status
Simulation time 4074219231 ps
CPU time 4.55 seconds
Started Jul 04 06:13:37 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206544 kb
Host smart-ba5c4511-c587-4973-a60a-6f09b3dfbc44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1423289845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1423289845
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3499225706
Short name T1585
Test name
Test status
Simulation time 13365428380 ps
CPU time 14.95 seconds
Started Jul 04 06:13:38 PM PDT 24
Finished Jul 04 06:13:53 PM PDT 24
Peak memory 206520 kb
Host smart-44aaca56-abd6-488e-9869-18d9243b880b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3499225706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3499225706
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2731953896
Short name T909
Test name
Test status
Simulation time 23327956511 ps
CPU time 22.67 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:58 PM PDT 24
Peak memory 206364 kb
Host smart-c88398f3-728f-4711-94e6-41b6720b7f9c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2731953896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2731953896
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3351732853
Short name T1472
Test name
Test status
Simulation time 241721501 ps
CPU time 0.9 seconds
Started Jul 04 06:13:32 PM PDT 24
Finished Jul 04 06:13:33 PM PDT 24
Peak memory 206208 kb
Host smart-84d72ca9-7de3-4e15-871f-bec085e17f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33517
32853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3351732853
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2078426303
Short name T1645
Test name
Test status
Simulation time 175440840 ps
CPU time 0.76 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206132 kb
Host smart-e62f0851-0f85-42d3-a922-19e477ff5c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20784
26303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2078426303
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.921813480
Short name T1096
Test name
Test status
Simulation time 432012616 ps
CPU time 1.37 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206204 kb
Host smart-e0e180eb-c4f1-4161-ae41-88d3a00ebf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92181
3480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.921813480
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3519197168
Short name T1065
Test name
Test status
Simulation time 1261533234 ps
CPU time 2.92 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206408 kb
Host smart-e90b989e-382a-4538-8012-baba845b24a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
97168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3519197168
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2074272156
Short name T1846
Test name
Test status
Simulation time 17965835304 ps
CPU time 30.79 seconds
Started Jul 04 06:13:38 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206536 kb
Host smart-482675ef-d991-41e2-aa38-05dc4e786ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
72156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2074272156
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2100612058
Short name T2535
Test name
Test status
Simulation time 421325169 ps
CPU time 1.28 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206124 kb
Host smart-d90c146a-e00f-4b94-80e1-f6ac0f5ccef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
12058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2100612058
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2244052387
Short name T1809
Test name
Test status
Simulation time 228048884 ps
CPU time 0.85 seconds
Started Jul 04 06:13:32 PM PDT 24
Finished Jul 04 06:13:34 PM PDT 24
Peak memory 206212 kb
Host smart-59771b20-b8b0-45dd-b9a8-896e705b6451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
52387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2244052387
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2658705141
Short name T2084
Test name
Test status
Simulation time 42777546 ps
CPU time 0.68 seconds
Started Jul 04 06:13:37 PM PDT 24
Finished Jul 04 06:13:38 PM PDT 24
Peak memory 206192 kb
Host smart-75eee090-3e8c-4d1e-ae1d-4d9b5b21894e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26587
05141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2658705141
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1212352244
Short name T1239
Test name
Test status
Simulation time 837786160 ps
CPU time 1.98 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:38 PM PDT 24
Peak memory 206460 kb
Host smart-b3a1b1e3-38e7-4e66-88da-a709eab248ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12123
52244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1212352244
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1502486726
Short name T2403
Test name
Test status
Simulation time 201685231 ps
CPU time 1.95 seconds
Started Jul 04 06:13:38 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206428 kb
Host smart-8c582485-2ce4-4d9d-bdce-fe21d42a0fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15024
86726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1502486726
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4268082906
Short name T1943
Test name
Test status
Simulation time 163383505 ps
CPU time 0.8 seconds
Started Jul 04 06:13:34 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206164 kb
Host smart-a8492da3-502d-4059-a955-8c8a06516e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42680
82906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4268082906
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.4065923242
Short name T2335
Test name
Test status
Simulation time 142320558 ps
CPU time 0.75 seconds
Started Jul 04 06:13:35 PM PDT 24
Finished Jul 04 06:13:36 PM PDT 24
Peak memory 206176 kb
Host smart-3822209b-53ba-4878-9aa7-251d52c66aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40659
23242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.4065923242
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2569385664
Short name T47
Test name
Test status
Simulation time 176728578 ps
CPU time 0.95 seconds
Started Jul 04 06:13:33 PM PDT 24
Finished Jul 04 06:13:35 PM PDT 24
Peak memory 206212 kb
Host smart-8ab1b59b-c001-43e7-b34c-e85f7675c25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
85664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2569385664
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2555694888
Short name T537
Test name
Test status
Simulation time 212461302 ps
CPU time 0.94 seconds
Started Jul 04 06:13:40 PM PDT 24
Finished Jul 04 06:13:41 PM PDT 24
Peak memory 206184 kb
Host smart-389648be-1896-4c1e-be4f-44abaa1a59f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25556
94888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2555694888
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.952582244
Short name T1141
Test name
Test status
Simulation time 23344161095 ps
CPU time 21.51 seconds
Started Jul 04 06:13:46 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206240 kb
Host smart-e98e12b6-8891-4f5b-a8b1-4eecf09a55ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95258
2244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.952582244
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.4127210496
Short name T809
Test name
Test status
Simulation time 3294155739 ps
CPU time 3.66 seconds
Started Jul 04 06:13:40 PM PDT 24
Finished Jul 04 06:13:44 PM PDT 24
Peak memory 206296 kb
Host smart-ffeaf7fb-dae4-463b-8da6-aea01caf1652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41272
10496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.4127210496
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3511364426
Short name T1227
Test name
Test status
Simulation time 11074418495 ps
CPU time 298.24 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:18:44 PM PDT 24
Peak memory 206500 kb
Host smart-276ef17e-4486-4bd0-8abc-797b69c0d62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35113
64426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3511364426
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.667056149
Short name T701
Test name
Test status
Simulation time 3937932428 ps
CPU time 35.98 seconds
Started Jul 04 06:13:46 PM PDT 24
Finished Jul 04 06:14:22 PM PDT 24
Peak memory 206472 kb
Host smart-239f1406-b29f-4fe4-8482-f749e621332d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=667056149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.667056149
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2932250192
Short name T2371
Test name
Test status
Simulation time 243830492 ps
CPU time 0.91 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206208 kb
Host smart-e58f8f58-05f6-4266-a554-abea59af5229
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2932250192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2932250192
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3669461454
Short name T363
Test name
Test status
Simulation time 184121433 ps
CPU time 0.83 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206176 kb
Host smart-139393d2-67b2-4c57-8447-84e9e584593e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36694
61454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3669461454
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1682823029
Short name T1652
Test name
Test status
Simulation time 5562179733 ps
CPU time 156.68 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:16:16 PM PDT 24
Peak memory 206432 kb
Host smart-c112cc90-512c-434d-b603-0ba0f6bcdbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16828
23029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1682823029
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1320367097
Short name T154
Test name
Test status
Simulation time 2966827703 ps
CPU time 82 seconds
Started Jul 04 06:13:42 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206444 kb
Host smart-f225d320-5057-4a30-828c-ce1c39accd50
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1320367097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1320367097
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.834563527
Short name T2017
Test name
Test status
Simulation time 154387107 ps
CPU time 0.81 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206176 kb
Host smart-3d2b6087-0019-4770-8f40-16ba8236ed1a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=834563527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.834563527
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3528577181
Short name T1968
Test name
Test status
Simulation time 145855134 ps
CPU time 0.78 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206196 kb
Host smart-f32cd8b1-5786-4993-a236-97b063c80e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35285
77181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3528577181
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3765181055
Short name T145
Test name
Test status
Simulation time 177378860 ps
CPU time 0.82 seconds
Started Jul 04 06:13:36 PM PDT 24
Finished Jul 04 06:13:37 PM PDT 24
Peak memory 206212 kb
Host smart-42b96937-211f-459c-b2bf-f3235ca34f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37651
81055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3765181055
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2790770075
Short name T693
Test name
Test status
Simulation time 154592375 ps
CPU time 0.76 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206156 kb
Host smart-a7dda5f3-3751-4ea1-b6d9-3b848bb47bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27907
70075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2790770075
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3912045236
Short name T2463
Test name
Test status
Simulation time 184992759 ps
CPU time 0.87 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206224 kb
Host smart-9cacdaf6-29c6-43cc-800f-0cbb3a9d67a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120
45236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3912045236
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2097945859
Short name T2252
Test name
Test status
Simulation time 188346539 ps
CPU time 0.84 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206180 kb
Host smart-299e5969-7e27-4cb1-b219-c90445c4a67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20979
45859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2097945859
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2587937058
Short name T2401
Test name
Test status
Simulation time 151703036 ps
CPU time 0.78 seconds
Started Jul 04 06:13:44 PM PDT 24
Finished Jul 04 06:13:45 PM PDT 24
Peak memory 206164 kb
Host smart-c43bb894-2d7c-4c77-8981-755c87c9aaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
37058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2587937058
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.719275558
Short name T1176
Test name
Test status
Simulation time 250365719 ps
CPU time 1 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206220 kb
Host smart-29a9cbfa-19d1-4f2b-b85e-c460f65f65d0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=719275558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.719275558
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.4258479139
Short name T2616
Test name
Test status
Simulation time 148076313 ps
CPU time 0.78 seconds
Started Jul 04 06:13:42 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206184 kb
Host smart-a8410017-cc42-4dee-bd97-266a05afbdaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
79139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.4258479139
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2425315647
Short name T1932
Test name
Test status
Simulation time 93777768 ps
CPU time 0.71 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206192 kb
Host smart-d0fdb5bd-0d7b-4eae-b4ca-b17b6c5a3b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24253
15647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2425315647
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.822873258
Short name T233
Test name
Test status
Simulation time 12646000625 ps
CPU time 27.19 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206500 kb
Host smart-9cfd5b04-fe05-46f8-8edf-610a1e411b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82287
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.822873258
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2104228339
Short name T649
Test name
Test status
Simulation time 184111386 ps
CPU time 0.83 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206196 kb
Host smart-b77969f4-a7e9-40f6-a533-b6cb88e4ab8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
28339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2104228339
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1165644356
Short name T792
Test name
Test status
Simulation time 167613790 ps
CPU time 0.86 seconds
Started Jul 04 06:13:40 PM PDT 24
Finished Jul 04 06:13:41 PM PDT 24
Peak memory 206124 kb
Host smart-909355c6-41ce-41d9-b09d-9591f7703ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
44356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1165644356
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.267574142
Short name T267
Test name
Test status
Simulation time 182641703 ps
CPU time 0.8 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206140 kb
Host smart-3774bc1c-4605-4759-80fa-4101642a5844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26757
4142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.267574142
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.841641236
Short name T2219
Test name
Test status
Simulation time 187153494 ps
CPU time 0.85 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206176 kb
Host smart-d5947cbe-8969-462c-9c18-2ff61258311f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84164
1236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.841641236
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1170059904
Short name T2065
Test name
Test status
Simulation time 163949803 ps
CPU time 0.8 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206172 kb
Host smart-b3d0d7d8-1c56-408e-a498-23d95c85d664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11700
59904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1170059904
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.729603285
Short name T234
Test name
Test status
Simulation time 158463097 ps
CPU time 0.83 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:40 PM PDT 24
Peak memory 206124 kb
Host smart-8bc68134-b8e3-4233-aeae-f1c6ccccd286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72960
3285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.729603285
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3506547620
Short name T387
Test name
Test status
Simulation time 154707348 ps
CPU time 0.83 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206192 kb
Host smart-21159b4a-07c6-4f71-9271-6586cbe2295b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35065
47620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3506547620
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.351220189
Short name T1736
Test name
Test status
Simulation time 236244908 ps
CPU time 0.88 seconds
Started Jul 04 06:13:40 PM PDT 24
Finished Jul 04 06:13:41 PM PDT 24
Peak memory 206416 kb
Host smart-f7d419e5-0ded-4c5f-b53d-bbcb93b59718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122
0189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.351220189
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3766448103
Short name T1871
Test name
Test status
Simulation time 3545164292 ps
CPU time 98.33 seconds
Started Jul 04 06:13:49 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206508 kb
Host smart-3e948c44-1173-41d9-ab76-3d95dfd412e0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3766448103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3766448103
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1071837111
Short name T1660
Test name
Test status
Simulation time 222335898 ps
CPU time 0.83 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206108 kb
Host smart-a07791ce-e7a1-468a-b537-f71e81cdef89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10718
37111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1071837111
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1954136457
Short name T418
Test name
Test status
Simulation time 160792054 ps
CPU time 0.78 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:41 PM PDT 24
Peak memory 206200 kb
Host smart-85cab458-2058-4929-b8b4-5f47bac64157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19541
36457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1954136457
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2822123576
Short name T1625
Test name
Test status
Simulation time 1322091678 ps
CPU time 2.65 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:42 PM PDT 24
Peak memory 206352 kb
Host smart-ac573951-230a-4586-b472-5ff9e5ff98bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
23576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2822123576
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1183169323
Short name T2397
Test name
Test status
Simulation time 3110346314 ps
CPU time 22.47 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:14:04 PM PDT 24
Peak memory 206456 kb
Host smart-30bfd38b-5047-45b7-a7e3-80701bc89b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11831
69323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1183169323
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3425927871
Short name T1742
Test name
Test status
Simulation time 102695267 ps
CPU time 0.72 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206228 kb
Host smart-75c503e4-ad7a-48b1-833b-dc1449c5fdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3425927871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3425927871
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1496339883
Short name T1469
Test name
Test status
Simulation time 4377701295 ps
CPU time 5.06 seconds
Started Jul 04 06:13:39 PM PDT 24
Finished Jul 04 06:13:44 PM PDT 24
Peak memory 206468 kb
Host smart-31cbb030-3d30-490d-be68-7d1340795f47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1496339883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1496339883
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1372228280
Short name T1872
Test name
Test status
Simulation time 13351347470 ps
CPU time 14.76 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206264 kb
Host smart-c9a6d2f1-8cb9-40d0-8d60-4fd0876c5a50
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1372228280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1372228280
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2095261049
Short name T828
Test name
Test status
Simulation time 23322644963 ps
CPU time 23.37 seconds
Started Jul 04 06:13:49 PM PDT 24
Finished Jul 04 06:14:13 PM PDT 24
Peak memory 206480 kb
Host smart-1e605c45-6984-47be-9193-f4d3e93f594f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2095261049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.2095261049
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3156571963
Short name T1138
Test name
Test status
Simulation time 179893488 ps
CPU time 0.84 seconds
Started Jul 04 06:13:42 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206196 kb
Host smart-c4950ad4-9d5e-45c3-bef1-698922335ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31565
71963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3156571963
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1542975323
Short name T1971
Test name
Test status
Simulation time 153804515 ps
CPU time 0.8 seconds
Started Jul 04 06:13:40 PM PDT 24
Finished Jul 04 06:13:41 PM PDT 24
Peak memory 206192 kb
Host smart-37873e15-d7bf-45cb-b7c1-140a06eeca74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429
75323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1542975323
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3899400253
Short name T1542
Test name
Test status
Simulation time 395304123 ps
CPU time 1.27 seconds
Started Jul 04 06:13:40 PM PDT 24
Finished Jul 04 06:13:41 PM PDT 24
Peak memory 206412 kb
Host smart-b292b344-6c6d-4b51-9ce2-d49f3a6dfd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38994
00253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3899400253
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1722179352
Short name T2114
Test name
Test status
Simulation time 1423470760 ps
CPU time 3.23 seconds
Started Jul 04 06:13:42 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206428 kb
Host smart-18b4d278-4a79-4f3a-967c-71de110a7b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17221
79352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1722179352
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2432930863
Short name T2519
Test name
Test status
Simulation time 16488042093 ps
CPU time 30.47 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206512 kb
Host smart-acbdba6e-f094-4183-8317-66d28e1eeb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
30863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2432930863
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2707381223
Short name T1370
Test name
Test status
Simulation time 465058613 ps
CPU time 1.4 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206196 kb
Host smart-49c544b1-fbf8-4f48-912d-18aa234ab08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27073
81223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2707381223
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.4290487549
Short name T881
Test name
Test status
Simulation time 162385852 ps
CPU time 0.79 seconds
Started Jul 04 06:13:42 PM PDT 24
Finished Jul 04 06:13:43 PM PDT 24
Peak memory 206212 kb
Host smart-726007b9-1e5d-4474-a28b-6759287a3771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42904
87549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.4290487549
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.555073825
Short name T2086
Test name
Test status
Simulation time 42489375 ps
CPU time 0.67 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206216 kb
Host smart-b0a948fa-3d9a-4667-a9b5-1b1173dc7581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55507
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.555073825
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3656215774
Short name T1398
Test name
Test status
Simulation time 1016584498 ps
CPU time 2.25 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:13:44 PM PDT 24
Peak memory 206340 kb
Host smart-124a44c7-db95-43e7-ae5f-daef31ca9460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
15774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3656215774
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1046513226
Short name T1918
Test name
Test status
Simulation time 290424364 ps
CPU time 1.74 seconds
Started Jul 04 06:13:42 PM PDT 24
Finished Jul 04 06:13:44 PM PDT 24
Peak memory 206296 kb
Host smart-0ab62e0e-35a0-45f4-8193-878384944fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
13226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1046513226
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1734758206
Short name T2227
Test name
Test status
Simulation time 282421433 ps
CPU time 0.94 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206160 kb
Host smart-66b14e05-1558-4ee9-898b-f85ff944f1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17347
58206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1734758206
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.655881454
Short name T1018
Test name
Test status
Simulation time 139662391 ps
CPU time 0.84 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206204 kb
Host smart-c5887276-b16a-4d3c-a734-aeccdb6080eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65588
1454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.655881454
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1320043551
Short name T1417
Test name
Test status
Simulation time 257730398 ps
CPU time 0.93 seconds
Started Jul 04 06:13:47 PM PDT 24
Finished Jul 04 06:13:48 PM PDT 24
Peak memory 206204 kb
Host smart-fcdcaa66-7dea-442c-96ac-bca3619294fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13200
43551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1320043551
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.1910411906
Short name T1965
Test name
Test status
Simulation time 5072057197 ps
CPU time 142.58 seconds
Started Jul 04 06:13:41 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206540 kb
Host smart-e6f93d22-598f-4d7c-90d1-d43310b8addc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1910411906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.1910411906
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3624046284
Short name T751
Test name
Test status
Simulation time 152538155 ps
CPU time 0.78 seconds
Started Jul 04 06:13:49 PM PDT 24
Finished Jul 04 06:13:50 PM PDT 24
Peak memory 206180 kb
Host smart-e749766b-efde-46e8-9420-60ff5d9f251e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240
46284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3624046284
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.294996516
Short name T2420
Test name
Test status
Simulation time 23316440215 ps
CPU time 24.85 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:14:10 PM PDT 24
Peak memory 206268 kb
Host smart-c7a4a2c9-1c6a-4953-bba2-289a07256af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
6516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.294996516
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1454348816
Short name T1356
Test name
Test status
Simulation time 3274128077 ps
CPU time 3.95 seconds
Started Jul 04 06:13:49 PM PDT 24
Finished Jul 04 06:13:53 PM PDT 24
Peak memory 206224 kb
Host smart-7dc19f5b-e353-4331-b78c-c8c76df03a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14543
48816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1454348816
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3428673902
Short name T702
Test name
Test status
Simulation time 5948210675 ps
CPU time 45.7 seconds
Started Jul 04 06:13:46 PM PDT 24
Finished Jul 04 06:14:32 PM PDT 24
Peak memory 206532 kb
Host smart-60f052f7-f5de-4d13-a6cf-bab1d4398248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34286
73902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3428673902
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3704507996
Short name T777
Test name
Test status
Simulation time 4652793007 ps
CPU time 130.26 seconds
Started Jul 04 06:13:52 PM PDT 24
Finished Jul 04 06:16:03 PM PDT 24
Peak memory 206464 kb
Host smart-e0d276a8-b251-4603-ae99-dae315c9983b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3704507996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3704507996
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2972647410
Short name T781
Test name
Test status
Simulation time 244207146 ps
CPU time 0.96 seconds
Started Jul 04 06:13:52 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206212 kb
Host smart-ac6c2b1b-dfdb-4271-a459-5fb1e3309331
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2972647410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2972647410
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3707553773
Short name T2451
Test name
Test status
Simulation time 183481245 ps
CPU time 0.84 seconds
Started Jul 04 06:13:45 PM PDT 24
Finished Jul 04 06:13:46 PM PDT 24
Peak memory 206172 kb
Host smart-fb6a4772-5abf-401d-bd04-580324b74d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37075
53773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3707553773
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.591499025
Short name T1329
Test name
Test status
Simulation time 5658774417 ps
CPU time 43.07 seconds
Started Jul 04 06:13:49 PM PDT 24
Finished Jul 04 06:14:32 PM PDT 24
Peak memory 206436 kb
Host smart-e8a2544f-174e-4971-8e8f-1be85d6cbffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59149
9025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.591499025
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2672516776
Short name T600
Test name
Test status
Simulation time 6254637424 ps
CPU time 59.25 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:14:48 PM PDT 24
Peak memory 206480 kb
Host smart-26b90587-3f9a-4bf0-9cbc-ac07983800ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2672516776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2672516776
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2900611813
Short name T1418
Test name
Test status
Simulation time 152757373 ps
CPU time 0.78 seconds
Started Jul 04 06:13:47 PM PDT 24
Finished Jul 04 06:13:48 PM PDT 24
Peak memory 206172 kb
Host smart-400fdc3d-2d14-40f6-9906-82d578ff0348
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2900611813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2900611813
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3434484684
Short name T1608
Test name
Test status
Simulation time 139338836 ps
CPU time 0.73 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206188 kb
Host smart-52f0c5ee-9911-4fe7-9a06-85fa8d960227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34344
84684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3434484684
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.4222493858
Short name T140
Test name
Test status
Simulation time 166452482 ps
CPU time 0.82 seconds
Started Jul 04 06:13:46 PM PDT 24
Finished Jul 04 06:13:48 PM PDT 24
Peak memory 206144 kb
Host smart-3d13122a-6dec-4959-8615-0758aff94782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42224
93858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.4222493858
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1989718468
Short name T778
Test name
Test status
Simulation time 161427830 ps
CPU time 0.8 seconds
Started Jul 04 06:13:46 PM PDT 24
Finished Jul 04 06:13:47 PM PDT 24
Peak memory 206200 kb
Host smart-0600f515-6042-4b77-9149-2548a94480d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
18468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1989718468
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.789060811
Short name T1196
Test name
Test status
Simulation time 139593722 ps
CPU time 0.79 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206172 kb
Host smart-325b3049-91c7-457c-a846-8691dc4f23d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78906
0811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.789060811
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.4254512760
Short name T2150
Test name
Test status
Simulation time 159969572 ps
CPU time 0.75 seconds
Started Jul 04 06:13:47 PM PDT 24
Finished Jul 04 06:13:48 PM PDT 24
Peak memory 206204 kb
Host smart-c76f6d9f-a02b-41f5-be56-53037d000680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42545
12760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.4254512760
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2493813450
Short name T479
Test name
Test status
Simulation time 160456433 ps
CPU time 0.85 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206160 kb
Host smart-c453e25a-32c3-4ef5-a82a-ffd88bebac8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
13450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2493813450
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2433079674
Short name T2026
Test name
Test status
Simulation time 249881719 ps
CPU time 1.02 seconds
Started Jul 04 06:13:48 PM PDT 24
Finished Jul 04 06:13:49 PM PDT 24
Peak memory 206192 kb
Host smart-9a094213-5caf-4652-82d7-6fea54cbafb1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2433079674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2433079674
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.4138623019
Short name T450
Test name
Test status
Simulation time 162923490 ps
CPU time 0.75 seconds
Started Jul 04 06:13:46 PM PDT 24
Finished Jul 04 06:13:47 PM PDT 24
Peak memory 206204 kb
Host smart-7ee1e646-bdd2-46aa-bd07-d390f9e183bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41386
23019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.4138623019
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.264458235
Short name T39
Test name
Test status
Simulation time 39472095 ps
CPU time 0.67 seconds
Started Jul 04 06:13:49 PM PDT 24
Finished Jul 04 06:13:50 PM PDT 24
Peak memory 206200 kb
Host smart-00a83466-21c2-4905-a398-be7d73a74eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26445
8235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.264458235
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3203379922
Short name T1609
Test name
Test status
Simulation time 11255613165 ps
CPU time 23.18 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206512 kb
Host smart-497e81c5-ef02-4a2a-8e04-a8fd1ae9706e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32033
79922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3203379922
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.226484579
Short name T982
Test name
Test status
Simulation time 153758747 ps
CPU time 0.82 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:13:55 PM PDT 24
Peak memory 206208 kb
Host smart-35cc5280-74d2-4db2-830d-1e46ca434119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
4579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.226484579
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4282318865
Short name T2339
Test name
Test status
Simulation time 254332776 ps
CPU time 0.92 seconds
Started Jul 04 06:13:56 PM PDT 24
Finished Jul 04 06:13:57 PM PDT 24
Peak memory 206196 kb
Host smart-8c978d82-29b3-4012-a9cd-578911c0ca3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
18865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4282318865
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3453276616
Short name T1060
Test name
Test status
Simulation time 227193950 ps
CPU time 0.87 seconds
Started Jul 04 06:13:55 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206192 kb
Host smart-5b1c5803-0364-4b2f-bf41-57519d3f35e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
76616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3453276616
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2461884481
Short name T703
Test name
Test status
Simulation time 150676015 ps
CPU time 0.81 seconds
Started Jul 04 06:13:55 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206176 kb
Host smart-2ae46fb3-fbdc-4c41-9273-722cfe0d192c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24618
84481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2461884481
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3449117285
Short name T2074
Test name
Test status
Simulation time 148693926 ps
CPU time 0.75 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206160 kb
Host smart-0ce3a4d9-b149-4751-b78e-dc1e2521fecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
17285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3449117285
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3644999945
Short name T1989
Test name
Test status
Simulation time 187620985 ps
CPU time 0.79 seconds
Started Jul 04 06:13:55 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206188 kb
Host smart-72c5945c-3bdd-45d7-8a00-0843f180e623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
99945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3644999945
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1425132426
Short name T699
Test name
Test status
Simulation time 172319995 ps
CPU time 0.8 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206208 kb
Host smart-75a11a03-ce5e-4d12-89f8-47fb649d2760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
32426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1425132426
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2721799371
Short name T876
Test name
Test status
Simulation time 293180393 ps
CPU time 0.98 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206208 kb
Host smart-6a71216b-9c58-489e-81f9-719d12e98bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27217
99371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2721799371
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1568324959
Short name T2475
Test name
Test status
Simulation time 3809098502 ps
CPU time 26.63 seconds
Started Jul 04 06:13:57 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206504 kb
Host smart-2a7d4d8d-41fd-4224-8d96-502e08ebefd1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1568324959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1568324959
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2346346507
Short name T924
Test name
Test status
Simulation time 227777178 ps
CPU time 0.86 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206200 kb
Host smart-e5cd60f8-9abb-4bac-956c-71ca7fa9f05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
46507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2346346507
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.818435035
Short name T2415
Test name
Test status
Simulation time 178604625 ps
CPU time 0.84 seconds
Started Jul 04 06:13:52 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206132 kb
Host smart-849e4a56-08b7-4932-8446-9cc511d9aac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81843
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.818435035
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1649082483
Short name T1595
Test name
Test status
Simulation time 198568970 ps
CPU time 0.9 seconds
Started Jul 04 06:13:52 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206196 kb
Host smart-3bc31e9e-dd93-480e-acd8-e97cfc8846c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16490
82483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1649082483
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.479678659
Short name T332
Test name
Test status
Simulation time 4537145291 ps
CPU time 111.71 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206476 kb
Host smart-ad617bd2-bac7-4801-a777-2bb092b86190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47967
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.479678659
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.4011740940
Short name T1630
Test name
Test status
Simulation time 51441736 ps
CPU time 0.74 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206256 kb
Host smart-7b37a03d-881f-4b62-aa57-6bcca5663923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4011740940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.4011740940
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.26153371
Short name T1183
Test name
Test status
Simulation time 3712073036 ps
CPU time 4.98 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:13:58 PM PDT 24
Peak memory 206576 kb
Host smart-60c28267-9cb3-4450-8f72-aedf8ee686d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=26153371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.26153371
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3681170735
Short name T1814
Test name
Test status
Simulation time 13340090875 ps
CPU time 13.07 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206456 kb
Host smart-cda6f107-e456-41fd-b0bd-fdd98dae79ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3681170735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3681170735
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1479070809
Short name T879
Test name
Test status
Simulation time 155883153 ps
CPU time 0.77 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206212 kb
Host smart-4078bcd3-51b8-4bfa-97a1-37d2c7047719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14790
70809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1479070809
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.196232036
Short name T1038
Test name
Test status
Simulation time 182679110 ps
CPU time 0.9 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206164 kb
Host smart-0925d8f7-85b9-4346-af50-059c8043c6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19623
2036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.196232036
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2023368283
Short name T1693
Test name
Test status
Simulation time 408420082 ps
CPU time 1.39 seconds
Started Jul 04 06:13:55 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206212 kb
Host smart-0ad4406b-b5d4-4c0e-805d-4224cfe807a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20233
68283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2023368283
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1034270107
Short name T1690
Test name
Test status
Simulation time 685801046 ps
CPU time 1.79 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206404 kb
Host smart-06689b66-546b-4297-83d9-ee56ba3bd969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10342
70107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1034270107
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.555009268
Short name T2505
Test name
Test status
Simulation time 15158905847 ps
CPU time 30.27 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206520 kb
Host smart-9c648f78-48da-44c8-8985-d8bd02ce9c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55500
9268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.555009268
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1223054896
Short name T97
Test name
Test status
Simulation time 401285325 ps
CPU time 1.29 seconds
Started Jul 04 06:13:56 PM PDT 24
Finished Jul 04 06:13:57 PM PDT 24
Peak memory 206176 kb
Host smart-97d9d6e4-b2fb-46aa-8060-32afba817648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
54896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1223054896
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.312876192
Short name T2357
Test name
Test status
Simulation time 141094921 ps
CPU time 0.74 seconds
Started Jul 04 06:13:55 PM PDT 24
Finished Jul 04 06:13:56 PM PDT 24
Peak memory 206196 kb
Host smart-532c2e31-b6db-4659-89a8-b2e1ee6bb0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31287
6192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.312876192
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1236464414
Short name T2193
Test name
Test status
Simulation time 127450386 ps
CPU time 0.75 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:13:55 PM PDT 24
Peak memory 206160 kb
Host smart-11a2a80f-471e-4531-8596-cca54053621f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12364
64414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1236464414
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1904229658
Short name T511
Test name
Test status
Simulation time 765529940 ps
CPU time 1.96 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206408 kb
Host smart-6cf16181-7546-48af-88c1-c492aeaad91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19042
29658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1904229658
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1168249621
Short name T1477
Test name
Test status
Simulation time 297685120 ps
CPU time 2.07 seconds
Started Jul 04 06:13:57 PM PDT 24
Finished Jul 04 06:13:59 PM PDT 24
Peak memory 206360 kb
Host smart-c67135cd-70c8-4c37-9d23-9c536006fa79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
49621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1168249621
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.4257573458
Short name T374
Test name
Test status
Simulation time 190232681 ps
CPU time 0.9 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206200 kb
Host smart-9ce7887c-2366-43ab-b37f-63775012ad5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
73458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.4257573458
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2525547851
Short name T1458
Test name
Test status
Simulation time 160668128 ps
CPU time 0.8 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:13:55 PM PDT 24
Peak memory 206136 kb
Host smart-a0ca4807-4603-4613-89ca-e0e7d2372b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
47851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2525547851
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2600030270
Short name T1442
Test name
Test status
Simulation time 160554478 ps
CPU time 0.8 seconds
Started Jul 04 06:13:57 PM PDT 24
Finished Jul 04 06:13:59 PM PDT 24
Peak memory 206192 kb
Host smart-cf6fe0f8-9d0c-40b2-8293-f3c6d7c254c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26000
30270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2600030270
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.1966209221
Short name T1146
Test name
Test status
Simulation time 5061615939 ps
CPU time 48.89 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206484 kb
Host smart-1e607287-0590-4414-b482-3eaf4a407df5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1966209221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1966209221
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2022823865
Short name T2583
Test name
Test status
Simulation time 240935170 ps
CPU time 0.92 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206200 kb
Host smart-1d12408d-803b-4c64-9ee2-3da977603283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228
23865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2022823865
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.36945217
Short name T1101
Test name
Test status
Simulation time 23304229059 ps
CPU time 26.87 seconds
Started Jul 04 06:13:57 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206224 kb
Host smart-7fd3a5da-2a4e-4af3-ae60-440e61f39c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36945
217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.36945217
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.757034516
Short name T472
Test name
Test status
Simulation time 3281081047 ps
CPU time 3.67 seconds
Started Jul 04 06:13:55 PM PDT 24
Finished Jul 04 06:13:59 PM PDT 24
Peak memory 206272 kb
Host smart-d0eb616d-bb65-4836-895d-850bc2d0243c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75703
4516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.757034516
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.758742425
Short name T1571
Test name
Test status
Simulation time 7624087606 ps
CPU time 68.08 seconds
Started Jul 04 06:13:52 PM PDT 24
Finished Jul 04 06:15:00 PM PDT 24
Peak memory 206432 kb
Host smart-26534e25-9151-46ba-9b05-9b77463ba493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75874
2425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.758742425
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3767826195
Short name T2547
Test name
Test status
Simulation time 4500971695 ps
CPU time 43.33 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:44 PM PDT 24
Peak memory 206460 kb
Host smart-c01d67e7-e7ed-4f2f-ac5e-cf203f0cfdf3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3767826195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3767826195
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3753412434
Short name T1713
Test name
Test status
Simulation time 238562411 ps
CPU time 0.92 seconds
Started Jul 04 06:13:53 PM PDT 24
Finished Jul 04 06:13:54 PM PDT 24
Peak memory 206228 kb
Host smart-08a10d91-aba1-4bb0-b44d-a364ac658495
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3753412434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3753412434
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.120306293
Short name T1193
Test name
Test status
Simulation time 222469146 ps
CPU time 0.94 seconds
Started Jul 04 06:13:54 PM PDT 24
Finished Jul 04 06:13:55 PM PDT 24
Peak memory 206192 kb
Host smart-1c88ef59-84ae-4ce0-8e00-b3cfa536f4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12030
6293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.120306293
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2469189927
Short name T2677
Test name
Test status
Simulation time 5048916789 ps
CPU time 141.2 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:16:29 PM PDT 24
Peak memory 206456 kb
Host smart-50a8c87c-b1b9-4239-8c50-bdbd774fa9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24691
89927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2469189927
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.141358705
Short name T1649
Test name
Test status
Simulation time 3052161335 ps
CPU time 86.72 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206440 kb
Host smart-e5082cb4-ce3e-455d-a1db-6b00075c0390
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=141358705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.141358705
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.205906279
Short name T1197
Test name
Test status
Simulation time 220024721 ps
CPU time 0.87 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206212 kb
Host smart-c1ff74be-42a2-47a6-bcee-61d579e58d66
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=205906279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.205906279
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.433119676
Short name T2105
Test name
Test status
Simulation time 142177659 ps
CPU time 0.8 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206172 kb
Host smart-bdf7173d-64b8-4687-a94c-aff3d4a4c814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43311
9676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.433119676
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1326814672
Short name T1536
Test name
Test status
Simulation time 208915594 ps
CPU time 0.93 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:14:02 PM PDT 24
Peak memory 206212 kb
Host smart-dd8e45f9-54bd-46b0-b95f-ee29679b1953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13268
14672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1326814672
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1286371227
Short name T2546
Test name
Test status
Simulation time 153299806 ps
CPU time 0.79 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:14:02 PM PDT 24
Peak memory 206208 kb
Host smart-7dd5d3c6-82f9-45aa-922c-1282a1f2b455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863
71227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1286371227
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.4209114382
Short name T1270
Test name
Test status
Simulation time 152044178 ps
CPU time 0.8 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206224 kb
Host smart-194597a1-dd68-4bfe-a21b-717cc4952d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091
14382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.4209114382
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.54102562
Short name T1261
Test name
Test status
Simulation time 169295797 ps
CPU time 0.82 seconds
Started Jul 04 06:14:04 PM PDT 24
Finished Jul 04 06:14:05 PM PDT 24
Peak memory 206180 kb
Host smart-207e17c0-2021-4b16-b18b-6e9e2cc3ce67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54102
562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.54102562
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.238110802
Short name T2248
Test name
Test status
Simulation time 190445435 ps
CPU time 0.86 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:14:03 PM PDT 24
Peak memory 206168 kb
Host smart-52586b0e-bb5e-4f44-a7e3-64fb15642a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811
0802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.238110802
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1793069220
Short name T728
Test name
Test status
Simulation time 251370377 ps
CPU time 1.02 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:02 PM PDT 24
Peak memory 206220 kb
Host smart-d1f62728-3a1b-4955-bfa5-c2ab7043a288
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1793069220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1793069220
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1233795964
Short name T2211
Test name
Test status
Simulation time 144874756 ps
CPU time 0.78 seconds
Started Jul 04 06:14:05 PM PDT 24
Finished Jul 04 06:14:06 PM PDT 24
Peak memory 206104 kb
Host smart-306416a9-27ee-49b3-bb1d-c09703f77171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
95964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1233795964
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3195436793
Short name T2203
Test name
Test status
Simulation time 36421215 ps
CPU time 0.67 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:13:59 PM PDT 24
Peak memory 206140 kb
Host smart-7e68706a-66a4-4801-9a4f-9b66e240278a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31954
36793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3195436793
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1168283255
Short name T2423
Test name
Test status
Simulation time 8227500319 ps
CPU time 18.02 seconds
Started Jul 04 06:14:02 PM PDT 24
Finished Jul 04 06:14:20 PM PDT 24
Peak memory 206492 kb
Host smart-07243263-0336-4f56-ae1d-835550969a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
83255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1168283255
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1875311135
Short name T1518
Test name
Test status
Simulation time 192684328 ps
CPU time 0.87 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206172 kb
Host smart-d1dc089b-7cb4-43b2-9d3a-7f12b4eb444f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
11135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1875311135
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4048544931
Short name T2492
Test name
Test status
Simulation time 239210910 ps
CPU time 0.95 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:14:02 PM PDT 24
Peak memory 206128 kb
Host smart-41815792-1e78-410b-888a-a2e324ab4087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
44931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4048544931
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.3878795558
Short name T33
Test name
Test status
Simulation time 210986210 ps
CPU time 0.83 seconds
Started Jul 04 06:13:59 PM PDT 24
Finished Jul 04 06:14:00 PM PDT 24
Peak memory 206176 kb
Host smart-d0f37252-fae7-46da-b71f-0bee0dd1cefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38787
95558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.3878795558
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2196998202
Short name T325
Test name
Test status
Simulation time 166212455 ps
CPU time 0.81 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206176 kb
Host smart-19fe253b-b5cd-4f65-b10f-aee12f5f7709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21969
98202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2196998202
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.639857335
Short name T74
Test name
Test status
Simulation time 134572807 ps
CPU time 0.72 seconds
Started Jul 04 06:14:02 PM PDT 24
Finished Jul 04 06:14:03 PM PDT 24
Peak memory 206204 kb
Host smart-ef723ba8-2e59-4495-8746-239ae37da574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63985
7335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.639857335
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2507795927
Short name T2326
Test name
Test status
Simulation time 150216871 ps
CPU time 0.81 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:01 PM PDT 24
Peak memory 206208 kb
Host smart-01087e12-8c4f-411b-93f2-0e87024f5cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
95927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2507795927
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3954693257
Short name T1268
Test name
Test status
Simulation time 212773217 ps
CPU time 0.83 seconds
Started Jul 04 06:14:02 PM PDT 24
Finished Jul 04 06:14:03 PM PDT 24
Peak memory 206184 kb
Host smart-9b6c0a50-a4e0-4008-93a6-47bdca200abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546
93257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3954693257
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3573810420
Short name T2642
Test name
Test status
Simulation time 242836608 ps
CPU time 1.01 seconds
Started Jul 04 06:14:03 PM PDT 24
Finished Jul 04 06:14:04 PM PDT 24
Peak memory 206172 kb
Host smart-0bb8b1d2-85b7-42bd-a6d9-889e9652619b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738
10420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3573810420
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.382912331
Short name T689
Test name
Test status
Simulation time 4926481538 ps
CPU time 35.13 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:44 PM PDT 24
Peak memory 206512 kb
Host smart-1c826511-824b-43ba-ac9f-3f99277ecb9c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=382912331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.382912331
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3714364989
Short name T1424
Test name
Test status
Simulation time 191644030 ps
CPU time 0.94 seconds
Started Jul 04 06:14:02 PM PDT 24
Finished Jul 04 06:14:03 PM PDT 24
Peak memory 206168 kb
Host smart-f742271c-0b6c-4d6e-9a65-86de4b593342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37143
64989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3714364989
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2103984234
Short name T2129
Test name
Test status
Simulation time 145202719 ps
CPU time 0.79 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:14:02 PM PDT 24
Peak memory 206200 kb
Host smart-1e760de4-7b83-415a-981c-4a3e15336909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
84234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2103984234
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2076340801
Short name T1
Test name
Test status
Simulation time 1125113836 ps
CPU time 2.81 seconds
Started Jul 04 06:14:00 PM PDT 24
Finished Jul 04 06:14:03 PM PDT 24
Peak memory 206448 kb
Host smart-9828e64b-7161-4479-8f65-3f3630cecb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20763
40801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2076340801
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.276773104
Short name T2431
Test name
Test status
Simulation time 3148672812 ps
CPU time 30.99 seconds
Started Jul 04 06:14:01 PM PDT 24
Finished Jul 04 06:14:32 PM PDT 24
Peak memory 206488 kb
Host smart-fb1ed15c-fc08-4483-8cb2-eb5b2f2ab114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27677
3104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.276773104
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1977495949
Short name T2578
Test name
Test status
Simulation time 43637805 ps
CPU time 0.68 seconds
Started Jul 04 06:14:18 PM PDT 24
Finished Jul 04 06:14:19 PM PDT 24
Peak memory 206276 kb
Host smart-339bfafc-57b4-49c5-bba6-a9a49382df1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1977495949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1977495949
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2507546246
Short name T902
Test name
Test status
Simulation time 3878083512 ps
CPU time 5.73 seconds
Started Jul 04 06:14:02 PM PDT 24
Finished Jul 04 06:14:08 PM PDT 24
Peak memory 206536 kb
Host smart-0a8fc5b1-f4d9-49ee-b721-30fc4e6b3656
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2507546246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2507546246
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2268791799
Short name T2611
Test name
Test status
Simulation time 13340130820 ps
CPU time 11.4 seconds
Started Jul 04 06:14:09 PM PDT 24
Finished Jul 04 06:14:20 PM PDT 24
Peak memory 206460 kb
Host smart-dde40343-5e98-4a50-9e96-2e428516c828
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2268791799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2268791799
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.833741359
Short name T837
Test name
Test status
Simulation time 23350469030 ps
CPU time 24.36 seconds
Started Jul 04 06:14:09 PM PDT 24
Finished Jul 04 06:14:33 PM PDT 24
Peak memory 206188 kb
Host smart-2855c0b6-bdd8-4b09-bf98-b04c5d899da6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=833741359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.833741359
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1699169200
Short name T2170
Test name
Test status
Simulation time 159950263 ps
CPU time 0.81 seconds
Started Jul 04 06:14:06 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206188 kb
Host smart-848c2f5f-3175-412f-b153-3044e06b4148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16991
69200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1699169200
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3553499650
Short name T1942
Test name
Test status
Simulation time 153256919 ps
CPU time 0.77 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206196 kb
Host smart-54410593-d6f7-4372-be95-82934da1a72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35534
99650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3553499650
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3520921096
Short name T2604
Test name
Test status
Simulation time 316941360 ps
CPU time 1.1 seconds
Started Jul 04 06:14:09 PM PDT 24
Finished Jul 04 06:14:10 PM PDT 24
Peak memory 206172 kb
Host smart-d33073d6-f656-4396-bba2-3534935d7c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
21096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3520921096
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3045641431
Short name T2226
Test name
Test status
Simulation time 742240733 ps
CPU time 1.85 seconds
Started Jul 04 06:14:12 PM PDT 24
Finished Jul 04 06:14:14 PM PDT 24
Peak memory 206456 kb
Host smart-53cc76f7-4e92-4749-899c-ee83c9c2cf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30456
41431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3045641431
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1588099420
Short name T2354
Test name
Test status
Simulation time 11849057234 ps
CPU time 21.68 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:14:29 PM PDT 24
Peak memory 206472 kb
Host smart-c7ae4353-c803-4f09-abac-703702d055b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15880
99420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1588099420
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.1256116964
Short name T2185
Test name
Test status
Simulation time 366523917 ps
CPU time 1.22 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206116 kb
Host smart-98b9a339-d364-4de2-bbf2-c5cca2d8b727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12561
16964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.1256116964
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1883320640
Short name T2218
Test name
Test status
Simulation time 146180691 ps
CPU time 0.75 seconds
Started Jul 04 06:14:10 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206204 kb
Host smart-05f901e3-3817-4429-8a16-ddffd3b5f1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18833
20640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1883320640
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1415471950
Short name T2606
Test name
Test status
Simulation time 31372262 ps
CPU time 0.65 seconds
Started Jul 04 06:14:06 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206184 kb
Host smart-39e5b072-9c2f-4232-86aa-5d9c84fcec5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
71950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1415471950
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3501515976
Short name T1068
Test name
Test status
Simulation time 950883259 ps
CPU time 2.31 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206440 kb
Host smart-c747cb3c-27be-4944-81ee-91cbf5aa88cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
15976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3501515976
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1374733730
Short name T202
Test name
Test status
Simulation time 226233760 ps
CPU time 1.58 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:10 PM PDT 24
Peak memory 206356 kb
Host smart-452730ea-e0a6-4778-909d-cc9ae11a9c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13747
33730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1374733730
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4281365102
Short name T1964
Test name
Test status
Simulation time 242636245 ps
CPU time 0.9 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:14:08 PM PDT 24
Peak memory 206128 kb
Host smart-8a254ad0-1e83-4f67-90fc-5250eca9b9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813
65102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4281365102
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2670345114
Short name T614
Test name
Test status
Simulation time 155873035 ps
CPU time 0.78 seconds
Started Jul 04 06:14:06 PM PDT 24
Finished Jul 04 06:14:07 PM PDT 24
Peak memory 206172 kb
Host smart-46b7910b-2b98-43ab-9390-12df70772852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26703
45114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2670345114
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1908113473
Short name T1152
Test name
Test status
Simulation time 214115574 ps
CPU time 0.89 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206128 kb
Host smart-05b57c22-ca57-430a-864e-ca74576c57c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19081
13473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1908113473
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1520766367
Short name T988
Test name
Test status
Simulation time 206764210 ps
CPU time 0.85 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206200 kb
Host smart-cc181291-a818-4400-a3cd-7a24e244da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15207
66367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1520766367
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.896589871
Short name T538
Test name
Test status
Simulation time 23313456158 ps
CPU time 22.35 seconds
Started Jul 04 06:14:09 PM PDT 24
Finished Jul 04 06:14:32 PM PDT 24
Peak memory 206228 kb
Host smart-2df5b841-d6d4-4c80-8b3f-3033135d69ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89658
9871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.896589871
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1036020072
Short name T2658
Test name
Test status
Simulation time 3308737243 ps
CPU time 3.85 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206236 kb
Host smart-4d023dbc-360a-404e-bdfa-61f8a2e4364a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10360
20072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1036020072
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.783695679
Short name T1737
Test name
Test status
Simulation time 10543101027 ps
CPU time 80.09 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206536 kb
Host smart-766d9777-dece-4039-955c-c73589980dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78369
5679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.783695679
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3111424225
Short name T2561
Test name
Test status
Simulation time 4206768711 ps
CPU time 115.13 seconds
Started Jul 04 06:14:10 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206444 kb
Host smart-44075ae4-114f-486b-8a9a-7df29df749a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3111424225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3111424225
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.570548221
Short name T1681
Test name
Test status
Simulation time 245159087 ps
CPU time 0.88 seconds
Started Jul 04 06:14:10 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206196 kb
Host smart-55446601-c045-4bf6-b9c3-e02693cc234e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=570548221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.570548221
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.4095139397
Short name T1758
Test name
Test status
Simulation time 264183974 ps
CPU time 0.96 seconds
Started Jul 04 06:14:10 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206156 kb
Host smart-f69f9d7c-432b-4ad6-a7d8-ad6f1593a6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
39397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.4095139397
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.14768906
Short name T2593
Test name
Test status
Simulation time 4420148130 ps
CPU time 117.64 seconds
Started Jul 04 06:14:10 PM PDT 24
Finished Jul 04 06:16:08 PM PDT 24
Peak memory 206484 kb
Host smart-7a7ebcd8-95ab-4da3-a27c-70df67285d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.14768906
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.572739913
Short name T1895
Test name
Test status
Simulation time 5638897964 ps
CPU time 41.59 seconds
Started Jul 04 06:14:09 PM PDT 24
Finished Jul 04 06:14:51 PM PDT 24
Peak memory 206540 kb
Host smart-47c680e4-631f-4596-9d0a-a5e75bd07c0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=572739913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.572739913
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.236563869
Short name T1936
Test name
Test status
Simulation time 157010182 ps
CPU time 0.85 seconds
Started Jul 04 06:14:09 PM PDT 24
Finished Jul 04 06:14:10 PM PDT 24
Peak memory 206220 kb
Host smart-6561f2e4-aaf9-4c42-a29d-eb73c9ff5c61
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=236563869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.236563869
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2179451499
Short name T653
Test name
Test status
Simulation time 170405483 ps
CPU time 0.81 seconds
Started Jul 04 06:14:10 PM PDT 24
Finished Jul 04 06:14:11 PM PDT 24
Peak memory 206156 kb
Host smart-de79ba8d-3f13-41df-94ad-7f9c9468ff4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
51499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2179451499
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2894249370
Short name T2049
Test name
Test status
Simulation time 232612564 ps
CPU time 0.85 seconds
Started Jul 04 06:14:07 PM PDT 24
Finished Jul 04 06:14:08 PM PDT 24
Peak memory 206208 kb
Host smart-90be7329-7062-49ac-a93a-c1d3f956fec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
49370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2894249370
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.4052795211
Short name T2106
Test name
Test status
Simulation time 175129063 ps
CPU time 0.83 seconds
Started Jul 04 06:14:08 PM PDT 24
Finished Jul 04 06:14:09 PM PDT 24
Peak memory 206196 kb
Host smart-c4e11b66-2778-48d9-b158-c8cdc9f00ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527
95211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.4052795211
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3406253271
Short name T2174
Test name
Test status
Simulation time 179131038 ps
CPU time 0.85 seconds
Started Jul 04 06:14:11 PM PDT 24
Finished Jul 04 06:14:12 PM PDT 24
Peak memory 206172 kb
Host smart-ba728500-c32f-4f3c-8f19-0c3fe10b88f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
53271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3406253271
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2506247541
Short name T1169
Test name
Test status
Simulation time 155554376 ps
CPU time 0.83 seconds
Started Jul 04 06:14:11 PM PDT 24
Finished Jul 04 06:14:12 PM PDT 24
Peak memory 206176 kb
Host smart-9cfdd06f-3390-4b9e-98bc-604044ba800c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
47541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2506247541
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2183023982
Short name T192
Test name
Test status
Simulation time 154768680 ps
CPU time 0.81 seconds
Started Jul 04 06:14:14 PM PDT 24
Finished Jul 04 06:14:15 PM PDT 24
Peak memory 206192 kb
Host smart-90a30b35-024b-42fb-82b5-32f5f1ed3c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21830
23982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2183023982
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3129662830
Short name T1946
Test name
Test status
Simulation time 186826422 ps
CPU time 0.84 seconds
Started Jul 04 06:14:17 PM PDT 24
Finished Jul 04 06:14:18 PM PDT 24
Peak memory 206188 kb
Host smart-35220d5a-b531-4053-b6f1-f560b972a1f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3129662830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3129662830
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2482123627
Short name T2636
Test name
Test status
Simulation time 169198266 ps
CPU time 0.78 seconds
Started Jul 04 06:14:15 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206192 kb
Host smart-6c5cb1bd-e1d9-4598-9591-e916f73790fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24821
23627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2482123627
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2235859255
Short name T1730
Test name
Test status
Simulation time 46622466 ps
CPU time 0.66 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:21 PM PDT 24
Peak memory 206116 kb
Host smart-5b721290-293c-4d25-b151-d53202592a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22358
59255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2235859255
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3755194258
Short name T270
Test name
Test status
Simulation time 19145577372 ps
CPU time 45.53 seconds
Started Jul 04 06:14:14 PM PDT 24
Finished Jul 04 06:15:00 PM PDT 24
Peak memory 206452 kb
Host smart-9530e32e-7678-46cb-9e7d-f0ad2d6443f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
94258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3755194258
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1362435568
Short name T918
Test name
Test status
Simulation time 180815206 ps
CPU time 0.85 seconds
Started Jul 04 06:14:13 PM PDT 24
Finished Jul 04 06:14:14 PM PDT 24
Peak memory 206180 kb
Host smart-3c296427-3746-453d-9c81-449e24a99cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13624
35568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1362435568
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1802047283
Short name T420
Test name
Test status
Simulation time 189743777 ps
CPU time 0.82 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:17 PM PDT 24
Peak memory 206228 kb
Host smart-6288a3b9-a600-4f09-bddc-5b8a5f2772cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18020
47283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1802047283
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1564712164
Short name T612
Test name
Test status
Simulation time 222102134 ps
CPU time 0.89 seconds
Started Jul 04 06:14:15 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206212 kb
Host smart-28c1dd34-c5f1-4dd9-9df6-57c292a5c880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
12164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1564712164
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2112589034
Short name T2364
Test name
Test status
Simulation time 150008542 ps
CPU time 0.78 seconds
Started Jul 04 06:14:15 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206216 kb
Host smart-eb09e4bd-50b1-4a38-81c0-3556f2d39c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21125
89034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2112589034
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3009465143
Short name T2589
Test name
Test status
Simulation time 145253169 ps
CPU time 0.75 seconds
Started Jul 04 06:14:14 PM PDT 24
Finished Jul 04 06:14:15 PM PDT 24
Peak memory 206140 kb
Host smart-022d4fed-3c6c-4e6b-ae70-7e26e01d01b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30094
65143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3009465143
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.759915020
Short name T1414
Test name
Test status
Simulation time 169849905 ps
CPU time 0.78 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:17 PM PDT 24
Peak memory 206124 kb
Host smart-52bedfa7-3442-4bcd-a56d-9269576f3d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75991
5020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.759915020
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3871752359
Short name T237
Test name
Test status
Simulation time 150620035 ps
CPU time 0.79 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:17 PM PDT 24
Peak memory 206212 kb
Host smart-80f08a00-9002-466e-acbf-c8b29bb48600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
52359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3871752359
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.605378844
Short name T1293
Test name
Test status
Simulation time 190930083 ps
CPU time 0.88 seconds
Started Jul 04 06:14:17 PM PDT 24
Finished Jul 04 06:14:18 PM PDT 24
Peak memory 206180 kb
Host smart-8e7d3f2e-665c-48a1-9cb5-fe535c534863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60537
8844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.605378844
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1769804361
Short name T1606
Test name
Test status
Simulation time 4101561304 ps
CPU time 31.55 seconds
Started Jul 04 06:14:14 PM PDT 24
Finished Jul 04 06:14:46 PM PDT 24
Peak memory 206508 kb
Host smart-bebffb11-3bb3-49e4-a5c0-1d418340e0f1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1769804361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1769804361
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1509389760
Short name T855
Test name
Test status
Simulation time 171178619 ps
CPU time 0.8 seconds
Started Jul 04 06:14:13 PM PDT 24
Finished Jul 04 06:14:14 PM PDT 24
Peak memory 206224 kb
Host smart-55841397-a810-4cc1-bf38-90e89de4c493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
89760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1509389760
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2829902906
Short name T1721
Test name
Test status
Simulation time 234168609 ps
CPU time 0.82 seconds
Started Jul 04 06:14:13 PM PDT 24
Finished Jul 04 06:14:14 PM PDT 24
Peak memory 206180 kb
Host smart-f07eeb8c-80ba-450d-ba74-0ba058bb3592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28299
02906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2829902906
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3046329374
Short name T1011
Test name
Test status
Simulation time 1032445092 ps
CPU time 2.1 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:18 PM PDT 24
Peak memory 206336 kb
Host smart-67d7c655-af91-45f7-91ae-d9aba1211703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463
29374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3046329374
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3023133011
Short name T1956
Test name
Test status
Simulation time 3504897679 ps
CPU time 25.8 seconds
Started Jul 04 06:14:19 PM PDT 24
Finished Jul 04 06:14:45 PM PDT 24
Peak memory 206492 kb
Host smart-e86d5d01-35c3-469f-a0ae-383e0e5aca2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
33011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3023133011
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2334158649
Short name T1350
Test name
Test status
Simulation time 39574344 ps
CPU time 0.64 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206268 kb
Host smart-b07033c5-16da-4497-a3c9-5e1570ab0f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2334158649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2334158649
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3316844973
Short name T2146
Test name
Test status
Simulation time 4264259550 ps
CPU time 5.28 seconds
Started Jul 04 06:14:19 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206460 kb
Host smart-81a73a9e-96bb-4b82-83d1-6e48ba73bb8f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3316844973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3316844973
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3829687624
Short name T445
Test name
Test status
Simulation time 13383212648 ps
CPU time 14.99 seconds
Started Jul 04 06:14:15 PM PDT 24
Finished Jul 04 06:14:31 PM PDT 24
Peak memory 206464 kb
Host smart-ce0e5ed8-1620-47fc-867d-cbe80261ccc3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3829687624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3829687624
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3016656496
Short name T1106
Test name
Test status
Simulation time 23348976388 ps
CPU time 21.24 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:37 PM PDT 24
Peak memory 206440 kb
Host smart-1dfa9141-49a2-4ec1-9b0c-78549ff417c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3016656496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3016656496
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.481534189
Short name T1828
Test name
Test status
Simulation time 145980822 ps
CPU time 0.76 seconds
Started Jul 04 06:14:18 PM PDT 24
Finished Jul 04 06:14:19 PM PDT 24
Peak memory 206212 kb
Host smart-19266142-49c9-4621-b820-c0aa67c36c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48153
4189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.481534189
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.2817293702
Short name T587
Test name
Test status
Simulation time 150248395 ps
CPU time 0.78 seconds
Started Jul 04 06:14:15 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206176 kb
Host smart-5ab5a33d-d140-467c-ade8-1e699597c51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
93702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.2817293702
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3828919042
Short name T1122
Test name
Test status
Simulation time 291599009 ps
CPU time 1.13 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:17 PM PDT 24
Peak memory 206176 kb
Host smart-e7ff1922-2c80-42b2-983e-b1b2dfe5ac2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38289
19042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3828919042
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3565846476
Short name T1212
Test name
Test status
Simulation time 1504000909 ps
CPU time 3.36 seconds
Started Jul 04 06:14:14 PM PDT 24
Finished Jul 04 06:14:17 PM PDT 24
Peak memory 206384 kb
Host smart-c514d381-43d2-4862-b5f4-4619a52c0de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35658
46476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3565846476
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1355614902
Short name T2158
Test name
Test status
Simulation time 8912768025 ps
CPU time 15.85 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:36 PM PDT 24
Peak memory 206140 kb
Host smart-7943915b-4731-43d8-90a6-086a378f8f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
14902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1355614902
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1622867853
Short name T1450
Test name
Test status
Simulation time 444863784 ps
CPU time 1.36 seconds
Started Jul 04 06:14:18 PM PDT 24
Finished Jul 04 06:14:19 PM PDT 24
Peak memory 206204 kb
Host smart-258985e0-d60e-44de-82f1-f009763538ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
67853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1622867853
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3118698552
Short name T1285
Test name
Test status
Simulation time 183552746 ps
CPU time 0.79 seconds
Started Jul 04 06:14:14 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206204 kb
Host smart-b763b89a-f1ad-49bd-a9de-e5f51b6f161c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186
98552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3118698552
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1453638471
Short name T782
Test name
Test status
Simulation time 44075386 ps
CPU time 0.66 seconds
Started Jul 04 06:14:15 PM PDT 24
Finished Jul 04 06:14:16 PM PDT 24
Peak memory 206168 kb
Host smart-adc5c36a-e0f7-43df-b53a-097e502f1cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
38471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1453638471
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3523929853
Short name T1039
Test name
Test status
Simulation time 898715175 ps
CPU time 2.02 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:18 PM PDT 24
Peak memory 206432 kb
Host smart-263bea6b-3c4b-4674-b422-1dcec0c5020b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239
29853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3523929853
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2272913034
Short name T2690
Test name
Test status
Simulation time 436049997 ps
CPU time 2.44 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:19 PM PDT 24
Peak memory 206396 kb
Host smart-507c6813-f2a5-449d-8d89-2c4e0ac423ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
13034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2272913034
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3865591171
Short name T1238
Test name
Test status
Simulation time 139211405 ps
CPU time 0.77 seconds
Started Jul 04 06:14:18 PM PDT 24
Finished Jul 04 06:14:19 PM PDT 24
Peak memory 206188 kb
Host smart-78812830-58af-4901-9b7b-2b084fc62e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38655
91171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3865591171
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3484620597
Short name T1470
Test name
Test status
Simulation time 233624565 ps
CPU time 0.9 seconds
Started Jul 04 06:14:18 PM PDT 24
Finished Jul 04 06:14:19 PM PDT 24
Peak memory 206224 kb
Host smart-9f4bb410-7709-4e14-8dc1-04e2f5dd3bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34846
20597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3484620597
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3193419705
Short name T390
Test name
Test status
Simulation time 199482902 ps
CPU time 0.84 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:17 PM PDT 24
Peak memory 206200 kb
Host smart-7144c7b3-fc40-4f5c-8e10-d85ee62f7b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31934
19705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3193419705
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2851436809
Short name T2506
Test name
Test status
Simulation time 23283275062 ps
CPU time 24.26 seconds
Started Jul 04 06:14:16 PM PDT 24
Finished Jul 04 06:14:40 PM PDT 24
Peak memory 206264 kb
Host smart-bc348c0d-641f-4ff4-8331-586d404e3b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28514
36809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2851436809
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3134563255
Short name T428
Test name
Test status
Simulation time 3332235028 ps
CPU time 4.64 seconds
Started Jul 04 06:14:18 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206276 kb
Host smart-2a5bdb9a-ad53-4d6c-a53b-36a6dce8b2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31345
63255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3134563255
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1853652048
Short name T2328
Test name
Test status
Simulation time 7861784797 ps
CPU time 58.46 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:15:19 PM PDT 24
Peak memory 206544 kb
Host smart-3a44d2ee-3276-4ab7-a0f4-7dceb04a32eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
52048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1853652048
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1618299095
Short name T1789
Test name
Test status
Simulation time 5206705027 ps
CPU time 51.06 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206408 kb
Host smart-d94fd79b-7458-4901-978c-41b6d8f14aec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1618299095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1618299095
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.293844784
Short name T2442
Test name
Test status
Simulation time 292253865 ps
CPU time 0.91 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206188 kb
Host smart-d95ff405-5ee7-44f6-9b84-0127aa5516a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=293844784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.293844784
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2485406227
Short name T635
Test name
Test status
Simulation time 189448757 ps
CPU time 0.83 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206196 kb
Host smart-b0c51a72-1307-413e-911f-5f6953fab840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24854
06227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2485406227
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1844909266
Short name T1553
Test name
Test status
Simulation time 2986067523 ps
CPU time 80.7 seconds
Started Jul 04 06:14:25 PM PDT 24
Finished Jul 04 06:15:46 PM PDT 24
Peak memory 206392 kb
Host smart-04cb8fa9-861a-48ef-bb52-496097046cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18449
09266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1844909266
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.4076497072
Short name T2398
Test name
Test status
Simulation time 3725432048 ps
CPU time 35.72 seconds
Started Jul 04 06:14:21 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206484 kb
Host smart-472ccb25-7129-4871-9d8b-f412b5b2f1e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4076497072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.4076497072
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1950260292
Short name T2191
Test name
Test status
Simulation time 153811902 ps
CPU time 0.8 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206216 kb
Host smart-ea1e05f1-3f3e-4e07-b4e9-9d2c29e8f54b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1950260292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1950260292
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.704997585
Short name T2490
Test name
Test status
Simulation time 154187881 ps
CPU time 0.81 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206188 kb
Host smart-ff4f0fec-48e2-4b34-85e6-d9e9d43c1fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70499
7585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.704997585
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.954799581
Short name T143
Test name
Test status
Simulation time 211180185 ps
CPU time 0.87 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206212 kb
Host smart-e163bd3c-d492-4e06-8923-353b556e914a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95479
9581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.954799581
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.108811963
Short name T483
Test name
Test status
Simulation time 175537626 ps
CPU time 0.84 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206160 kb
Host smart-d4de5121-296f-4c09-bfbf-5ca96e324b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10881
1963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.108811963
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3376924872
Short name T2628
Test name
Test status
Simulation time 244886822 ps
CPU time 0.87 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:21 PM PDT 24
Peak memory 206212 kb
Host smart-05b32e69-ce0d-41c3-9fec-5f038ab312cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
24872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3376924872
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.234740044
Short name T1380
Test name
Test status
Simulation time 179323252 ps
CPU time 0.87 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206196 kb
Host smart-21a83f42-f0f8-43da-b108-913d4f7848cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23474
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.234740044
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.478529922
Short name T816
Test name
Test status
Simulation time 172114324 ps
CPU time 0.78 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:21 PM PDT 24
Peak memory 206180 kb
Host smart-de3d968d-edbe-4c64-813c-3f92778ed151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47852
9922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.478529922
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2375619683
Short name T2582
Test name
Test status
Simulation time 237279982 ps
CPU time 0.92 seconds
Started Jul 04 06:14:21 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206216 kb
Host smart-d28ad8d0-2d5e-447e-934b-8c217038681f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2375619683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2375619683
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3531010580
Short name T1396
Test name
Test status
Simulation time 154851415 ps
CPU time 0.8 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206172 kb
Host smart-66652874-1a02-4be7-9505-8df81a3b2e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
10580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3531010580
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1437268893
Short name T1838
Test name
Test status
Simulation time 34085509 ps
CPU time 0.64 seconds
Started Jul 04 06:14:25 PM PDT 24
Finished Jul 04 06:14:26 PM PDT 24
Peak memory 206208 kb
Host smart-6c18cf3b-e686-4303-bc1a-36fff9f9a56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
68893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1437268893
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.481542477
Short name T86
Test name
Test status
Simulation time 12101327778 ps
CPU time 27.74 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:51 PM PDT 24
Peak memory 206460 kb
Host smart-2335b161-e1cf-4e74-87f1-96630e93c572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48154
2477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.481542477
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3922439611
Short name T1095
Test name
Test status
Simulation time 168592331 ps
CPU time 0.87 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:22 PM PDT 24
Peak memory 206208 kb
Host smart-a071bc57-b5c7-4d94-b9c7-7277186ca004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39224
39611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3922439611
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3184762101
Short name T2224
Test name
Test status
Simulation time 165778770 ps
CPU time 0.84 seconds
Started Jul 04 06:14:21 PM PDT 24
Finished Jul 04 06:14:22 PM PDT 24
Peak memory 206160 kb
Host smart-c090a36f-b770-4825-a42a-70e9d68b8284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31847
62101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3184762101
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1134475698
Short name T979
Test name
Test status
Simulation time 232588125 ps
CPU time 0.86 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206160 kb
Host smart-fc20b88c-a756-4454-9d4b-adb586e12e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11344
75698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1134475698
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1347252860
Short name T348
Test name
Test status
Simulation time 181365453 ps
CPU time 0.88 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206132 kb
Host smart-2635a7fb-8999-439c-aa31-33bf81b32c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13472
52860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1347252860
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1693027984
Short name T857
Test name
Test status
Simulation time 175895437 ps
CPU time 0.76 seconds
Started Jul 04 06:14:21 PM PDT 24
Finished Jul 04 06:14:22 PM PDT 24
Peak memory 206228 kb
Host smart-2244c15a-5a70-41e3-8da8-7d1b8050544b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16930
27984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1693027984
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2565268058
Short name T1665
Test name
Test status
Simulation time 184516330 ps
CPU time 0.8 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:14:26 PM PDT 24
Peak memory 206152 kb
Host smart-f6058d5a-9cd5-4a30-992c-9b1d4b00b350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
68058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2565268058
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1333840899
Short name T498
Test name
Test status
Simulation time 152562718 ps
CPU time 0.78 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206224 kb
Host smart-5d49817a-5f8f-4238-b20c-f115c733af66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
40899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1333840899
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3659866448
Short name T1428
Test name
Test status
Simulation time 260575502 ps
CPU time 1.01 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206192 kb
Host smart-03748e05-3dce-49b3-8f42-a2a3a65beadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36598
66448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3659866448
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1515698310
Short name T758
Test name
Test status
Simulation time 3375740182 ps
CPU time 31.6 seconds
Started Jul 04 06:14:21 PM PDT 24
Finished Jul 04 06:14:53 PM PDT 24
Peak memory 206520 kb
Host smart-06da4821-2e01-43d9-a3f4-133227036023
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1515698310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1515698310
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1263910365
Short name T2512
Test name
Test status
Simulation time 152903499 ps
CPU time 0.8 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206204 kb
Host smart-a48a736b-e501-4c2c-bb57-72c2887f5498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12639
10365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1263910365
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3380019990
Short name T344
Test name
Test status
Simulation time 169443628 ps
CPU time 0.81 seconds
Started Jul 04 06:14:20 PM PDT 24
Finished Jul 04 06:14:21 PM PDT 24
Peak memory 206188 kb
Host smart-8bc304f8-eb8c-4894-ab99-679c11b6aa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
19990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3380019990
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.60111126
Short name T2508
Test name
Test status
Simulation time 684791525 ps
CPU time 1.75 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206188 kb
Host smart-36dbf058-3e77-47af-9786-8df5381a7658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60111
126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.60111126
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3186589689
Short name T1839
Test name
Test status
Simulation time 3928033694 ps
CPU time 103.96 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206448 kb
Host smart-be47503c-2606-46c5-8fee-881c29b8d0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31865
89689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3186589689
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.4071481256
Short name T2491
Test name
Test status
Simulation time 76594141 ps
CPU time 0.71 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206264 kb
Host smart-623c9ccc-b056-4b2d-bca6-4ae1da0b1c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4071481256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.4071481256
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2753648847
Short name T2630
Test name
Test status
Simulation time 4159732613 ps
CPU time 4.67 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:32 PM PDT 24
Peak memory 206264 kb
Host smart-469bf1e7-1b7b-4a5e-bbd5-128cd939857d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2753648847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2753648847
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1328037429
Short name T1863
Test name
Test status
Simulation time 13313298242 ps
CPU time 14.31 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:38 PM PDT 24
Peak memory 206276 kb
Host smart-2364123d-f736-4976-8dba-6462f8330954
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1328037429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1328037429
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3842705499
Short name T1573
Test name
Test status
Simulation time 23339757578 ps
CPU time 23.06 seconds
Started Jul 04 06:14:25 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206356 kb
Host smart-6e2510f2-13fb-439c-9e28-a11256347c47
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3842705499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3842705499
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1033602394
Short name T688
Test name
Test status
Simulation time 153765050 ps
CPU time 0.89 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206160 kb
Host smart-efb36a38-d649-47d8-be86-568dda65b8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10336
02394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1033602394
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3963156411
Short name T1258
Test name
Test status
Simulation time 145043787 ps
CPU time 0.89 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:24 PM PDT 24
Peak memory 206172 kb
Host smart-68dbd785-1552-4e6b-a03d-05e52d20a78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39631
56411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3963156411
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3286476661
Short name T768
Test name
Test status
Simulation time 518614930 ps
CPU time 1.57 seconds
Started Jul 04 06:14:21 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206428 kb
Host smart-3bf79cf5-16e1-4336-80f8-a494f6a7e219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32864
76661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3286476661
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.335915454
Short name T1337
Test name
Test status
Simulation time 1101326038 ps
CPU time 2.53 seconds
Started Jul 04 06:14:28 PM PDT 24
Finished Jul 04 06:14:31 PM PDT 24
Peak memory 206400 kb
Host smart-ba2d84ac-2aaf-4bdb-93d8-ddab5bdbdda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
5454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.335915454
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3109965050
Short name T94
Test name
Test status
Simulation time 15856400657 ps
CPU time 28.42 seconds
Started Jul 04 06:14:29 PM PDT 24
Finished Jul 04 06:14:58 PM PDT 24
Peak memory 206512 kb
Host smart-aa7946e5-0c11-46e3-85e0-d69f2f932dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31099
65050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3109965050
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1472697050
Short name T2632
Test name
Test status
Simulation time 405281343 ps
CPU time 1.22 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:23 PM PDT 24
Peak memory 206188 kb
Host smart-cf5abc09-f6ea-4d53-bca8-1d1f158dbca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14726
97050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1472697050
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.739333118
Short name T1177
Test name
Test status
Simulation time 134678514 ps
CPU time 0.8 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206212 kb
Host smart-24e8fea2-0600-4fb9-b54c-24e3ebbf1e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73933
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.739333118
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1755438802
Short name T675
Test name
Test status
Simulation time 36459811 ps
CPU time 0.68 seconds
Started Jul 04 06:14:23 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206192 kb
Host smart-ab0e6186-f646-4854-90db-cdceb2eade33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17554
38802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1755438802
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2898131520
Short name T1150
Test name
Test status
Simulation time 958185841 ps
CPU time 2.23 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206352 kb
Host smart-fc9e6c56-9bf4-48d8-9cf5-7cc0e8b7641f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981
31520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2898131520
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2512848050
Short name T1371
Test name
Test status
Simulation time 314231594 ps
CPU time 2.32 seconds
Started Jul 04 06:14:22 PM PDT 24
Finished Jul 04 06:14:25 PM PDT 24
Peak memory 206420 kb
Host smart-fd9bbf90-f9b1-4e21-831e-4b312bb9b1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25128
48050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2512848050
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1571833119
Short name T474
Test name
Test status
Simulation time 221371632 ps
CPU time 0.89 seconds
Started Jul 04 06:14:24 PM PDT 24
Finished Jul 04 06:14:26 PM PDT 24
Peak memory 206192 kb
Host smart-feb00f28-a9e5-4c9a-a8b2-0c6230015ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
33119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1571833119
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.464678298
Short name T29
Test name
Test status
Simulation time 147174333 ps
CPU time 0.73 seconds
Started Jul 04 06:14:28 PM PDT 24
Finished Jul 04 06:14:29 PM PDT 24
Peak memory 206196 kb
Host smart-f48c9020-5cc5-405b-8b03-86ec31c6c5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46467
8298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.464678298
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2694241809
Short name T460
Test name
Test status
Simulation time 157339457 ps
CPU time 0.81 seconds
Started Jul 04 06:14:29 PM PDT 24
Finished Jul 04 06:14:30 PM PDT 24
Peak memory 206196 kb
Host smart-d5895d33-85c3-435d-89f4-e75aeb303e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26942
41809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2694241809
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.976361036
Short name T1461
Test name
Test status
Simulation time 7289019068 ps
CPU time 208.92 seconds
Started Jul 04 06:14:25 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 206392 kb
Host smart-b1b035e3-4a98-476a-ac55-02560b51f816
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=976361036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.976361036
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1180885902
Short name T671
Test name
Test status
Simulation time 173752670 ps
CPU time 0.79 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206224 kb
Host smart-4d01ca7d-5243-47a5-ba24-c893dbe9781f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11808
85902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1180885902
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3448618485
Short name T2585
Test name
Test status
Simulation time 23317236780 ps
CPU time 23.13 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206268 kb
Host smart-0cb3e304-b61d-4e65-95ed-68c076da8585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34486
18485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3448618485
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2123649103
Short name T1237
Test name
Test status
Simulation time 3310555384 ps
CPU time 4.02 seconds
Started Jul 04 06:14:26 PM PDT 24
Finished Jul 04 06:14:30 PM PDT 24
Peak memory 206268 kb
Host smart-d68d2529-c726-4cd5-a630-a7f70875298e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236
49103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2123649103
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2673076330
Short name T1454
Test name
Test status
Simulation time 8475443657 ps
CPU time 79.64 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:15:47 PM PDT 24
Peak memory 206428 kb
Host smart-f660fc61-ac74-45c1-ac47-eae6934b7687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
76330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2673076330
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.4041472846
Short name T1279
Test name
Test status
Simulation time 5439455240 ps
CPU time 154.76 seconds
Started Jul 04 06:14:25 PM PDT 24
Finished Jul 04 06:17:00 PM PDT 24
Peak memory 206444 kb
Host smart-1eb45312-38dc-4596-aa6a-0ec666699277
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4041472846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.4041472846
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.401413297
Short name T381
Test name
Test status
Simulation time 260850853 ps
CPU time 0.87 seconds
Started Jul 04 06:14:30 PM PDT 24
Finished Jul 04 06:14:31 PM PDT 24
Peak memory 206188 kb
Host smart-8e655645-2ee0-4e34-bd26-36504b1cdf52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=401413297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.401413297
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2007784675
Short name T1493
Test name
Test status
Simulation time 228416588 ps
CPU time 0.87 seconds
Started Jul 04 06:14:30 PM PDT 24
Finished Jul 04 06:14:31 PM PDT 24
Peak memory 206176 kb
Host smart-72568bcc-31e7-40f7-a5bd-a494b28dd56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
84675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2007784675
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.738031518
Short name T803
Test name
Test status
Simulation time 5036549628 ps
CPU time 140.73 seconds
Started Jul 04 06:14:30 PM PDT 24
Finished Jul 04 06:16:51 PM PDT 24
Peak memory 206472 kb
Host smart-43b668b4-5608-4f90-948e-244fe30543da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73803
1518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.738031518
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.4016253189
Short name T419
Test name
Test status
Simulation time 5607244658 ps
CPU time 156.19 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:17:03 PM PDT 24
Peak memory 206460 kb
Host smart-eed3fd65-ba6f-46ed-86eb-dedf3375d99d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4016253189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.4016253189
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.817273927
Short name T514
Test name
Test status
Simulation time 157149094 ps
CPU time 0.81 seconds
Started Jul 04 06:14:28 PM PDT 24
Finished Jul 04 06:14:30 PM PDT 24
Peak memory 206212 kb
Host smart-37d665a5-7e8b-4746-b934-41e20123c3d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=817273927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.817273927
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.8496299
Short name T1161
Test name
Test status
Simulation time 138432475 ps
CPU time 0.82 seconds
Started Jul 04 06:14:29 PM PDT 24
Finished Jul 04 06:14:30 PM PDT 24
Peak memory 206220 kb
Host smart-1688ec91-ab7a-4dac-b3bd-7f192a7cc2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84962
99 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.8496299
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.560137792
Short name T1775
Test name
Test status
Simulation time 284013581 ps
CPU time 0.87 seconds
Started Jul 04 06:14:32 PM PDT 24
Finished Jul 04 06:14:33 PM PDT 24
Peak memory 206200 kb
Host smart-60c5743d-3294-4ec6-84e4-2a1d901862a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56013
7792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.560137792
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3339538882
Short name T1301
Test name
Test status
Simulation time 214885533 ps
CPU time 0.87 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206176 kb
Host smart-324af194-d5ce-480e-8152-dc040241c1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33395
38882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3339538882
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3413370546
Short name T1327
Test name
Test status
Simulation time 183059660 ps
CPU time 0.87 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206224 kb
Host smart-afd02218-ec8a-4b93-bfeb-62dae426d06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34133
70546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3413370546
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2238869870
Short name T1837
Test name
Test status
Simulation time 154028641 ps
CPU time 0.79 seconds
Started Jul 04 06:14:26 PM PDT 24
Finished Jul 04 06:14:27 PM PDT 24
Peak memory 206188 kb
Host smart-9c2d18ec-9d8d-4003-a95b-0a422650cd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
69870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2238869870
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.129333767
Short name T2296
Test name
Test status
Simulation time 141467424 ps
CPU time 0.76 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206152 kb
Host smart-ea7dc1cc-7383-4e31-bdd1-67f2562535bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12933
3767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.129333767
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.1644054160
Short name T1516
Test name
Test status
Simulation time 239024179 ps
CPU time 1.01 seconds
Started Jul 04 06:14:30 PM PDT 24
Finished Jul 04 06:14:31 PM PDT 24
Peak memory 206192 kb
Host smart-1ac44bfd-1ee8-42c0-873b-04b6e05ba096
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1644054160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.1644054160
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2183965244
Short name T1963
Test name
Test status
Simulation time 157750834 ps
CPU time 0.8 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:29 PM PDT 24
Peak memory 206188 kb
Host smart-dc620a82-b97a-4280-9354-a06bab07e469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21839
65244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2183965244
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1962347726
Short name T1419
Test name
Test status
Simulation time 38037602 ps
CPU time 0.66 seconds
Started Jul 04 06:14:28 PM PDT 24
Finished Jul 04 06:14:29 PM PDT 24
Peak memory 206196 kb
Host smart-02ee0d8c-740f-40a0-b356-d9cefd970d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19623
47726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1962347726
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1391047838
Short name T2509
Test name
Test status
Simulation time 12564886577 ps
CPU time 27.74 seconds
Started Jul 04 06:14:29 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206504 kb
Host smart-6619b11f-60f8-42ec-a54d-6522e1cc0c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13910
47838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1391047838
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1610693559
Short name T306
Test name
Test status
Simulation time 219822075 ps
CPU time 0.88 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206160 kb
Host smart-80a1f53f-1225-4230-949b-c5eb42df8a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16106
93559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1610693559
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3398571789
Short name T811
Test name
Test status
Simulation time 162112062 ps
CPU time 0.79 seconds
Started Jul 04 06:14:27 PM PDT 24
Finished Jul 04 06:14:28 PM PDT 24
Peak memory 206224 kb
Host smart-3af9160a-b542-4acb-8f14-bf3aa5f87724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
71789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3398571789
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.941341901
Short name T1719
Test name
Test status
Simulation time 248720932 ps
CPU time 0.94 seconds
Started Jul 04 06:14:30 PM PDT 24
Finished Jul 04 06:14:31 PM PDT 24
Peak memory 206180 kb
Host smart-a7e110ce-00bf-45aa-8fbb-13461f02695e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94134
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.941341901
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.2088690335
Short name T1522
Test name
Test status
Simulation time 249390662 ps
CPU time 0.86 seconds
Started Jul 04 06:14:28 PM PDT 24
Finished Jul 04 06:14:30 PM PDT 24
Peak memory 206140 kb
Host smart-45e72150-0d23-4446-90cf-c86ccf7b6dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886
90335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.2088690335
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.641482136
Short name T90
Test name
Test status
Simulation time 137659496 ps
CPU time 0.76 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206196 kb
Host smart-ea3ce833-561d-4995-a5ee-0ebe82e29ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64148
2136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.641482136
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3720355564
Short name T2032
Test name
Test status
Simulation time 145704584 ps
CPU time 0.77 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:14:36 PM PDT 24
Peak memory 206220 kb
Host smart-db773d71-ff71-499d-8cb2-05895a8dda47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203
55564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3720355564
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2339713342
Short name T1999
Test name
Test status
Simulation time 147351997 ps
CPU time 0.79 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206164 kb
Host smart-ec009504-bdbd-4afd-9acd-a387d83795a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23397
13342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2339713342
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.19443896
Short name T372
Test name
Test status
Simulation time 200903411 ps
CPU time 0.96 seconds
Started Jul 04 06:14:39 PM PDT 24
Finished Jul 04 06:14:40 PM PDT 24
Peak memory 206220 kb
Host smart-800ea45f-b9ce-44c5-b3e1-cefccce0c692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.19443896
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.4279193107
Short name T32
Test name
Test status
Simulation time 6547781741 ps
CPU time 62.1 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206444 kb
Host smart-93e361f3-71d5-466f-bc14-683987ac1a73
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4279193107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.4279193107
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2431125520
Short name T149
Test name
Test status
Simulation time 170438689 ps
CPU time 0.88 seconds
Started Jul 04 06:14:37 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206144 kb
Host smart-0019a4db-a1f2-45e4-9dce-633996ffca14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24311
25520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2431125520
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2757190067
Short name T1346
Test name
Test status
Simulation time 228907622 ps
CPU time 0.92 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:14:37 PM PDT 24
Peak memory 206216 kb
Host smart-714bd2ba-736c-4fdc-aee9-2b09b18b0f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27571
90067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2757190067
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.503316939
Short name T1153
Test name
Test status
Simulation time 772198280 ps
CPU time 1.86 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:14:37 PM PDT 24
Peak memory 206452 kb
Host smart-8ae16b2f-b204-4e37-8b33-05563aa88a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50331
6939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.503316939
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1977709921
Short name T1171
Test name
Test status
Simulation time 7568088934 ps
CPU time 55.84 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:15:32 PM PDT 24
Peak memory 206448 kb
Host smart-2c3d393a-8d1f-4233-a0f5-6031765c8be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19777
09921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1977709921
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.4175348711
Short name T1379
Test name
Test status
Simulation time 60361510 ps
CPU time 0.72 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206276 kb
Host smart-9908aa76-a45c-4e96-b18a-b0cea96244aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4175348711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.4175348711
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2918800158
Short name T1355
Test name
Test status
Simulation time 3651088795 ps
CPU time 4.41 seconds
Started Jul 04 06:14:37 PM PDT 24
Finished Jul 04 06:14:42 PM PDT 24
Peak memory 206260 kb
Host smart-25122858-9810-4fba-8cec-4957fe43c20a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2918800158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2918800158
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2904420407
Short name T2173
Test name
Test status
Simulation time 13333377764 ps
CPU time 11.7 seconds
Started Jul 04 06:14:37 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206508 kb
Host smart-de53e64c-6b1d-437b-ac9e-882cff9226b6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2904420407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2904420407
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1861054528
Short name T15
Test name
Test status
Simulation time 23355618316 ps
CPU time 21.51 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206496 kb
Host smart-44907a59-89b5-4d7c-967c-5c66cdf87d78
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1861054528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1861054528
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2337126488
Short name T423
Test name
Test status
Simulation time 177017443 ps
CPU time 0.88 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206144 kb
Host smart-6c09e8a5-c363-468a-9e6e-0c84893dad8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
26488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2337126488
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1848246876
Short name T609
Test name
Test status
Simulation time 154979175 ps
CPU time 0.8 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:14:34 PM PDT 24
Peak memory 206132 kb
Host smart-f96d390c-6b0d-4f85-af2c-b3862d85a077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
46876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1848246876
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3950061403
Short name T184
Test name
Test status
Simulation time 496200588 ps
CPU time 1.66 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:14:38 PM PDT 24
Peak memory 206404 kb
Host smart-a4e46e3d-e6bf-4e58-bde0-06d19c74239f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
61403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3950061403
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2578661005
Short name T2133
Test name
Test status
Simulation time 701918936 ps
CPU time 1.85 seconds
Started Jul 04 06:14:39 PM PDT 24
Finished Jul 04 06:14:41 PM PDT 24
Peak memory 206220 kb
Host smart-57abca83-e659-4348-a693-d3563c19b927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25786
61005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2578661005
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2858998689
Short name T1024
Test name
Test status
Simulation time 17262479839 ps
CPU time 38.03 seconds
Started Jul 04 06:14:37 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206396 kb
Host smart-808b058b-9ccb-47b1-ab49-7117cfacf71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28589
98689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2858998689
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4257369265
Short name T1373
Test name
Test status
Simulation time 476100461 ps
CPU time 1.37 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:14:37 PM PDT 24
Peak memory 206172 kb
Host smart-e4cace74-3d78-4b0e-80ed-5718932107e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42573
69265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4257369265
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2757506660
Short name T2308
Test name
Test status
Simulation time 167562015 ps
CPU time 0.8 seconds
Started Jul 04 06:14:33 PM PDT 24
Finished Jul 04 06:14:34 PM PDT 24
Peak memory 206172 kb
Host smart-8645553a-a4d4-4aea-ae12-c597e3ac270b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
06660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2757506660
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1939038568
Short name T1416
Test name
Test status
Simulation time 45822201 ps
CPU time 0.66 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:14:37 PM PDT 24
Peak memory 206188 kb
Host smart-14f9cbf9-b32c-43e6-b80a-8f2bcdcc3e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
38568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1939038568
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1789881500
Short name T2006
Test name
Test status
Simulation time 731609140 ps
CPU time 1.8 seconds
Started Jul 04 06:14:38 PM PDT 24
Finished Jul 04 06:14:40 PM PDT 24
Peak memory 206372 kb
Host smart-901a79b8-dbfc-4bfa-8f57-c7a0dbe74b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
81500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1789881500
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.434310301
Short name T2394
Test name
Test status
Simulation time 289400291 ps
CPU time 1.47 seconds
Started Jul 04 06:14:38 PM PDT 24
Finished Jul 04 06:14:40 PM PDT 24
Peak memory 206360 kb
Host smart-b67283af-5a7d-4168-a695-4b33b1737575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43431
0301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.434310301
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2571222192
Short name T1157
Test name
Test status
Simulation time 261671645 ps
CPU time 0.94 seconds
Started Jul 04 06:14:38 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206180 kb
Host smart-111ba04b-3020-4e9e-8c73-726148f2f141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25712
22192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2571222192
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.557745276
Short name T560
Test name
Test status
Simulation time 151973454 ps
CPU time 0.76 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:14:37 PM PDT 24
Peak memory 206192 kb
Host smart-08342cb4-fd45-4013-be98-86fe0d2e24ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55774
5276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.557745276
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3683079415
Short name T2579
Test name
Test status
Simulation time 204186413 ps
CPU time 0.86 seconds
Started Jul 04 06:14:38 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206220 kb
Host smart-2ad7c05f-bd07-4873-98a0-e31deb81197c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36830
79415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3683079415
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3900957342
Short name T2601
Test name
Test status
Simulation time 203916139 ps
CPU time 0.85 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:14:36 PM PDT 24
Peak memory 206156 kb
Host smart-ae884472-d3ca-496d-853b-d3b9adf453c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
57342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3900957342
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.547729760
Short name T1517
Test name
Test status
Simulation time 23437102735 ps
CPU time 26.69 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206272 kb
Host smart-53d6db00-44e5-40a7-96b0-27ae1440c659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54772
9760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.547729760
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.782314548
Short name T2092
Test name
Test status
Simulation time 3330291855 ps
CPU time 4.04 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:14:39 PM PDT 24
Peak memory 206240 kb
Host smart-ca20da6e-8394-4202-9730-ebdae5bb2457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78231
4548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.782314548
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2799974894
Short name T91
Test name
Test status
Simulation time 7548440201 ps
CPU time 57.4 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:15:33 PM PDT 24
Peak memory 206476 kb
Host smart-96b762b8-d4b3-4a7f-b008-dfb186fc7aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27999
74894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2799974894
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2779892210
Short name T2542
Test name
Test status
Simulation time 3865586925 ps
CPU time 26.33 seconds
Started Jul 04 06:14:34 PM PDT 24
Finished Jul 04 06:15:01 PM PDT 24
Peak memory 206440 kb
Host smart-656f1683-83fe-4d50-90d0-cee114811b10
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2779892210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2779892210
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.788092963
Short name T1907
Test name
Test status
Simulation time 241042782 ps
CPU time 0.95 seconds
Started Jul 04 06:14:35 PM PDT 24
Finished Jul 04 06:14:36 PM PDT 24
Peak memory 206232 kb
Host smart-b3a7314c-5477-406e-99d5-3799132acb6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=788092963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.788092963
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2727917182
Short name T22
Test name
Test status
Simulation time 204843901 ps
CPU time 0.92 seconds
Started Jul 04 06:14:33 PM PDT 24
Finished Jul 04 06:14:35 PM PDT 24
Peak memory 206192 kb
Host smart-95b9c7bb-be80-44c8-9b1f-83620e2b364a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27279
17182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2727917182
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1907559858
Short name T2157
Test name
Test status
Simulation time 5465262558 ps
CPU time 52.9 seconds
Started Jul 04 06:14:36 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206448 kb
Host smart-c95ab2d5-b7dd-4bbf-90c0-68831fc50981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19075
59858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1907559858
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.939552210
Short name T618
Test name
Test status
Simulation time 6293192036 ps
CPU time 179.63 seconds
Started Jul 04 06:14:41 PM PDT 24
Finished Jul 04 06:17:41 PM PDT 24
Peak memory 206460 kb
Host smart-b0653a48-f6b7-4ff1-bbac-ed33f573ed17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=939552210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.939552210
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2877211198
Short name T725
Test name
Test status
Simulation time 146146348 ps
CPU time 0.76 seconds
Started Jul 04 06:14:42 PM PDT 24
Finished Jul 04 06:14:43 PM PDT 24
Peak memory 206216 kb
Host smart-c90e3874-1e3c-4410-aea6-d5a23b2a1ac1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2877211198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2877211198
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1201689144
Short name T2107
Test name
Test status
Simulation time 164953969 ps
CPU time 0.76 seconds
Started Jul 04 06:14:42 PM PDT 24
Finished Jul 04 06:14:43 PM PDT 24
Peak memory 206184 kb
Host smart-18c2f1a3-5689-43d0-b1f1-1b29caf180d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
89144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1201689144
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1061645530
Short name T120
Test name
Test status
Simulation time 260941772 ps
CPU time 0.93 seconds
Started Jul 04 06:14:42 PM PDT 24
Finished Jul 04 06:14:43 PM PDT 24
Peak memory 206224 kb
Host smart-3478041b-fcf6-4400-8d9e-dc959b296a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10616
45530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1061645530
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1574389992
Short name T2449
Test name
Test status
Simulation time 229273808 ps
CPU time 0.88 seconds
Started Jul 04 06:14:44 PM PDT 24
Finished Jul 04 06:14:45 PM PDT 24
Peak memory 206132 kb
Host smart-bc2bdd5b-a04a-4809-b06a-7b0e0e0e2606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15743
89992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1574389992
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.186913887
Short name T1308
Test name
Test status
Simulation time 152121949 ps
CPU time 0.79 seconds
Started Jul 04 06:14:44 PM PDT 24
Finished Jul 04 06:14:45 PM PDT 24
Peak memory 206196 kb
Host smart-a6d9fcbf-fdda-4e19-b48b-d398cbe9a53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18691
3887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.186913887
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3710764
Short name T2035
Test name
Test status
Simulation time 196558776 ps
CPU time 0.83 seconds
Started Jul 04 06:14:41 PM PDT 24
Finished Jul 04 06:14:42 PM PDT 24
Peak memory 206176 kb
Host smart-57886697-ed38-4c97-afff-64055d2403ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
64 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3710764
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1739110864
Short name T1592
Test name
Test status
Simulation time 183719355 ps
CPU time 0.81 seconds
Started Jul 04 06:14:45 PM PDT 24
Finished Jul 04 06:14:46 PM PDT 24
Peak memory 206176 kb
Host smart-4d50b1b6-efa6-4181-80e6-c76c98626a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17391
10864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1739110864
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.393357026
Short name T2307
Test name
Test status
Simulation time 209523862 ps
CPU time 0.85 seconds
Started Jul 04 06:14:41 PM PDT 24
Finished Jul 04 06:14:42 PM PDT 24
Peak memory 206212 kb
Host smart-976ef6eb-93c8-41ba-adca-86298e07703c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=393357026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.393357026
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3164554518
Short name T737
Test name
Test status
Simulation time 199530991 ps
CPU time 0.78 seconds
Started Jul 04 06:14:40 PM PDT 24
Finished Jul 04 06:14:41 PM PDT 24
Peak memory 206160 kb
Host smart-8d3de446-c7cf-44e5-a68f-016425b94a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
54518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3164554518
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.207158988
Short name T1121
Test name
Test status
Simulation time 64074171 ps
CPU time 0.7 seconds
Started Jul 04 06:14:42 PM PDT 24
Finished Jul 04 06:14:42 PM PDT 24
Peak memory 206104 kb
Host smart-b0a26c9e-43fc-47d3-a770-9badd1b34365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
8988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.207158988
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3012603091
Short name T1260
Test name
Test status
Simulation time 15915053611 ps
CPU time 35.93 seconds
Started Jul 04 06:14:41 PM PDT 24
Finished Jul 04 06:15:17 PM PDT 24
Peak memory 206524 kb
Host smart-28ae96df-7692-4495-8e5e-32c71f422bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30126
03091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3012603091
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2347700419
Short name T1103
Test name
Test status
Simulation time 193827206 ps
CPU time 0.84 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206196 kb
Host smart-ce0e52af-900f-43ee-9742-2843d67006c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23477
00419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2347700419
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1507868407
Short name T1714
Test name
Test status
Simulation time 232594183 ps
CPU time 0.94 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206192 kb
Host smart-9d2ef400-4b85-4592-8d88-f5aa896fe2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15078
68407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1507868407
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1429454241
Short name T1087
Test name
Test status
Simulation time 174294318 ps
CPU time 0.79 seconds
Started Jul 04 06:14:44 PM PDT 24
Finished Jul 04 06:14:45 PM PDT 24
Peak memory 206136 kb
Host smart-0a67f5f7-c03a-45f5-80ae-02d124452f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14294
54241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1429454241
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.4190198901
Short name T1636
Test name
Test status
Simulation time 191168411 ps
CPU time 0.86 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206144 kb
Host smart-6f5531bb-909b-4d99-bb48-87e105423aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41901
98901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.4190198901
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1682705985
Short name T785
Test name
Test status
Simulation time 160516409 ps
CPU time 0.79 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:14:48 PM PDT 24
Peak memory 206164 kb
Host smart-18fe3433-b986-458a-a117-f0de46a5f2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
05985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1682705985
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1312321184
Short name T1440
Test name
Test status
Simulation time 155077362 ps
CPU time 0.76 seconds
Started Jul 04 06:14:44 PM PDT 24
Finished Jul 04 06:14:45 PM PDT 24
Peak memory 206208 kb
Host smart-c16514b3-da80-4546-ba71-2bb3c92d1e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13123
21184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1312321184
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2536087150
Short name T750
Test name
Test status
Simulation time 153940036 ps
CPU time 0.8 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206200 kb
Host smart-b97ee243-e44d-4758-a45a-be97b2123c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25360
87150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2536087150
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3728093587
Short name T389
Test name
Test status
Simulation time 239607973 ps
CPU time 1.01 seconds
Started Jul 04 06:14:45 PM PDT 24
Finished Jul 04 06:14:46 PM PDT 24
Peak memory 206128 kb
Host smart-90318f43-9ee2-43b0-a9bc-3a8a9b581d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37280
93587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3728093587
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.370667347
Short name T2504
Test name
Test status
Simulation time 3912173780 ps
CPU time 109.01 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:16:37 PM PDT 24
Peak memory 206516 kb
Host smart-f2f7e340-b02f-4d35-823d-85161ded4bc2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=370667347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.370667347
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1819220753
Short name T1343
Test name
Test status
Simulation time 143186539 ps
CPU time 0.78 seconds
Started Jul 04 06:14:46 PM PDT 24
Finished Jul 04 06:14:47 PM PDT 24
Peak memory 206164 kb
Host smart-c903afbe-4272-4785-a0ea-f08dabb3e14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
20753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1819220753
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1279275867
Short name T2282
Test name
Test status
Simulation time 179321487 ps
CPU time 0.81 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206212 kb
Host smart-3a61ff78-3ee0-4781-a2fa-83b8f5f05fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792
75867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1279275867
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3610550424
Short name T1404
Test name
Test status
Simulation time 1096457118 ps
CPU time 2.33 seconds
Started Jul 04 06:14:45 PM PDT 24
Finished Jul 04 06:14:47 PM PDT 24
Peak memory 206456 kb
Host smart-089a5c76-f67c-45cf-bf38-17868fd54e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36105
50424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3610550424
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2297927112
Short name T1597
Test name
Test status
Simulation time 5149385196 ps
CPU time 51.32 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:15:40 PM PDT 24
Peak memory 206432 kb
Host smart-369d1b37-e5a6-4aab-9e3f-13bf158e905f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
27112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2297927112
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2569056609
Short name T2696
Test name
Test status
Simulation time 37488435 ps
CPU time 0.7 seconds
Started Jul 04 06:07:21 PM PDT 24
Finished Jul 04 06:07:22 PM PDT 24
Peak memory 206256 kb
Host smart-ee1f8ace-64a4-4fcc-afba-88d16971764d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2569056609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2569056609
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3204329536
Short name T7
Test name
Test status
Simulation time 3422182737 ps
CPU time 4.44 seconds
Started Jul 04 06:06:49 PM PDT 24
Finished Jul 04 06:06:54 PM PDT 24
Peak memory 206464 kb
Host smart-5cc8e1ab-987b-462c-b966-1e51139b8653
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3204329536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3204329536
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.921741107
Short name T738
Test name
Test status
Simulation time 13431560120 ps
CPU time 14.43 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206488 kb
Host smart-8c6e0cf8-58c8-461a-96c6-b16bc6f53875
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=921741107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.921741107
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1531192896
Short name T1134
Test name
Test status
Simulation time 23337952331 ps
CPU time 30.72 seconds
Started Jul 04 06:06:52 PM PDT 24
Finished Jul 04 06:07:22 PM PDT 24
Peak memory 205892 kb
Host smart-3a2cfe88-58ed-4799-b1c3-c2d984f3986d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1531192896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.1531192896
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3197219204
Short name T746
Test name
Test status
Simulation time 236083720 ps
CPU time 0.91 seconds
Started Jul 04 06:06:50 PM PDT 24
Finished Jul 04 06:06:51 PM PDT 24
Peak memory 206176 kb
Host smart-fa1e94f2-a90a-4224-81d1-19233f351975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31972
19204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3197219204
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.4039635283
Short name T57
Test name
Test status
Simulation time 156201666 ps
CPU time 0.81 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:06:49 PM PDT 24
Peak memory 206212 kb
Host smart-f35e9578-286e-4e9d-8771-60e62bd67647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
35283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.4039635283
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3619969272
Short name T85
Test name
Test status
Simulation time 135602850 ps
CPU time 0.82 seconds
Started Jul 04 06:06:51 PM PDT 24
Finished Jul 04 06:06:52 PM PDT 24
Peak memory 206188 kb
Host smart-1f659f43-bb27-4078-8cf6-cd3fbfbac2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36199
69272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3619969272
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3329655619
Short name T2373
Test name
Test status
Simulation time 141613216 ps
CPU time 0.75 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:06:49 PM PDT 24
Peak memory 206184 kb
Host smart-c3744c9d-cdea-4a1a-90ab-be51a1e2dafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33296
55619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3329655619
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2491508549
Short name T2689
Test name
Test status
Simulation time 144869261 ps
CPU time 0.74 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:06:49 PM PDT 24
Peak memory 206188 kb
Host smart-d05bb6cb-7737-4719-a797-22946e1de6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24915
08549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2491508549
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1494673135
Short name T1723
Test name
Test status
Simulation time 295045214 ps
CPU time 0.95 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:06:49 PM PDT 24
Peak memory 206224 kb
Host smart-764b1c85-b7fd-4a24-ae54-799f161d433d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14946
73135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1494673135
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.437681420
Short name T2183
Test name
Test status
Simulation time 15190568314 ps
CPU time 31.17 seconds
Started Jul 04 06:06:48 PM PDT 24
Finished Jul 04 06:07:20 PM PDT 24
Peak memory 206488 kb
Host smart-7011df4c-56b7-4936-ae8e-acea837e3d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43768
1420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.437681420
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1484703864
Short name T1497
Test name
Test status
Simulation time 492450240 ps
CPU time 1.47 seconds
Started Jul 04 06:06:56 PM PDT 24
Finished Jul 04 06:06:58 PM PDT 24
Peak memory 206144 kb
Host smart-7bd9c711-033d-4048-a37b-d88bacb8f2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14847
03864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1484703864
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.969232001
Short name T1698
Test name
Test status
Simulation time 212465499 ps
CPU time 0.79 seconds
Started Jul 04 06:06:56 PM PDT 24
Finished Jul 04 06:06:57 PM PDT 24
Peak memory 206180 kb
Host smart-96e40187-d1b5-42d0-93a3-64c85548df70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96923
2001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.969232001
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2367954295
Short name T849
Test name
Test status
Simulation time 133219696 ps
CPU time 0.75 seconds
Started Jul 04 06:06:55 PM PDT 24
Finished Jul 04 06:06:56 PM PDT 24
Peak memory 206196 kb
Host smart-2ca81e83-2fe2-4233-83c0-ba9699817f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23679
54295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2367954295
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3693789633
Short name T2474
Test name
Test status
Simulation time 856854420 ps
CPU time 1.93 seconds
Started Jul 04 06:06:55 PM PDT 24
Finished Jul 04 06:06:57 PM PDT 24
Peak memory 206444 kb
Host smart-7eae3bc3-b09a-4d9e-b68f-84b1864157e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
89633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3693789633
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.535690873
Short name T1912
Test name
Test status
Simulation time 167149601 ps
CPU time 1.4 seconds
Started Jul 04 06:06:54 PM PDT 24
Finished Jul 04 06:06:56 PM PDT 24
Peak memory 206316 kb
Host smart-ce291624-08cf-4821-b28c-9c89997fb37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53569
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.535690873
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.149917368
Short name T1638
Test name
Test status
Simulation time 112184573304 ps
CPU time 159.96 seconds
Started Jul 04 06:06:54 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206476 kb
Host smart-d555e7df-034b-4abf-ae1c-f863412da878
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=149917368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.149917368
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.135211873
Short name T2685
Test name
Test status
Simulation time 119069996565 ps
CPU time 187.94 seconds
Started Jul 04 06:06:56 PM PDT 24
Finished Jul 04 06:10:04 PM PDT 24
Peak memory 206488 kb
Host smart-a445c427-e63c-4498-a5ca-6c7dd2c7e3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135211873 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.135211873
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.565581054
Short name T1746
Test name
Test status
Simulation time 118100575347 ps
CPU time 159.3 seconds
Started Jul 04 06:06:56 PM PDT 24
Finished Jul 04 06:09:35 PM PDT 24
Peak memory 206436 kb
Host smart-7a4d88b4-6123-4d2a-80c4-89c0ffc0bfdc
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=565581054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.565581054
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2779002810
Short name T727
Test name
Test status
Simulation time 118290817347 ps
CPU time 155.33 seconds
Started Jul 04 06:06:54 PM PDT 24
Finished Jul 04 06:09:30 PM PDT 24
Peak memory 206496 kb
Host smart-a0c1d63c-861f-49d2-a509-171621a4a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779002810 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2779002810
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.4044804523
Short name T367
Test name
Test status
Simulation time 102162386895 ps
CPU time 150.3 seconds
Started Jul 04 06:06:54 PM PDT 24
Finished Jul 04 06:09:24 PM PDT 24
Peak memory 206472 kb
Host smart-fd58e472-ca26-44a4-9ce5-5074db26671f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40448
04523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.4044804523
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.844727413
Short name T236
Test name
Test status
Simulation time 187741257 ps
CPU time 0.85 seconds
Started Jul 04 06:06:55 PM PDT 24
Finished Jul 04 06:06:56 PM PDT 24
Peak memory 206200 kb
Host smart-7d13c461-6664-4542-af5d-a662eac49190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84472
7413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.844727413
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1578136816
Short name T2324
Test name
Test status
Simulation time 155461459 ps
CPU time 0.79 seconds
Started Jul 04 06:06:56 PM PDT 24
Finished Jul 04 06:06:57 PM PDT 24
Peak memory 206220 kb
Host smart-6286ec0f-3da8-438b-baee-fbf4137a8893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15781
36816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1578136816
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.303432193
Short name T2066
Test name
Test status
Simulation time 218128316 ps
CPU time 0.88 seconds
Started Jul 04 06:06:53 PM PDT 24
Finished Jul 04 06:06:54 PM PDT 24
Peak memory 206184 kb
Host smart-7897fd3f-c5c3-45ba-b8b2-0777ec8c7a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343
2193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.303432193
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3391784890
Short name T2182
Test name
Test status
Simulation time 6175344910 ps
CPU time 59.69 seconds
Started Jul 04 06:06:56 PM PDT 24
Finished Jul 04 06:07:56 PM PDT 24
Peak memory 206424 kb
Host smart-a6894958-eb5a-471a-878e-848a9a0e772a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3391784890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3391784890
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3516631888
Short name T492
Test name
Test status
Simulation time 163255388 ps
CPU time 0.84 seconds
Started Jul 04 06:07:01 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206144 kb
Host smart-136549b4-c7a8-4359-bad5-139a97e0186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35166
31888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3516631888
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1338876389
Short name T1976
Test name
Test status
Simulation time 23333460171 ps
CPU time 22.67 seconds
Started Jul 04 06:07:04 PM PDT 24
Finished Jul 04 06:07:27 PM PDT 24
Peak memory 206272 kb
Host smart-92d9f72f-f822-4596-85ef-4c44f58fb82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
76389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1338876389
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.900349597
Short name T473
Test name
Test status
Simulation time 3357355244 ps
CPU time 3.94 seconds
Started Jul 04 06:07:02 PM PDT 24
Finished Jul 04 06:07:06 PM PDT 24
Peak memory 206184 kb
Host smart-1f8b043e-1f33-43cb-aa48-1011b40cd9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90034
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.900349597
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3197241257
Short name T820
Test name
Test status
Simulation time 11496532045 ps
CPU time 115.96 seconds
Started Jul 04 06:07:04 PM PDT 24
Finished Jul 04 06:09:00 PM PDT 24
Peak memory 206532 kb
Host smart-f7a610f3-f482-4090-9a30-173ff2e7d1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31972
41257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3197241257
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.36138358
Short name T1618
Test name
Test status
Simulation time 5376884339 ps
CPU time 145.59 seconds
Started Jul 04 06:07:00 PM PDT 24
Finished Jul 04 06:09:26 PM PDT 24
Peak memory 206440 kb
Host smart-1e31d23c-1f18-4f50-ab49-d56a210be1e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=36138358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.36138358
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1451776353
Short name T2027
Test name
Test status
Simulation time 279358756 ps
CPU time 0.94 seconds
Started Jul 04 06:07:02 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206188 kb
Host smart-5e10e69a-d54f-46cb-aebe-5f407e8953da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1451776353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1451776353
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2619681764
Short name T814
Test name
Test status
Simulation time 191206620 ps
CPU time 0.91 seconds
Started Jul 04 06:07:02 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206208 kb
Host smart-844c0a40-3d45-4617-896a-713010f928dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26196
81764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2619681764
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.917165570
Short name T160
Test name
Test status
Simulation time 4233676311 ps
CPU time 44.06 seconds
Started Jul 04 06:07:01 PM PDT 24
Finished Jul 04 06:07:46 PM PDT 24
Peak memory 206432 kb
Host smart-3e2f25a8-b72e-4f60-8f9d-728061d5b848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91716
5570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.917165570
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3548086982
Short name T1255
Test name
Test status
Simulation time 7881041474 ps
CPU time 222.96 seconds
Started Jul 04 06:07:05 PM PDT 24
Finished Jul 04 06:10:48 PM PDT 24
Peak memory 206420 kb
Host smart-2bdeabf0-1907-49a8-aa5f-9a85024b35a9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3548086982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3548086982
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.512936177
Short name T700
Test name
Test status
Simulation time 159784001 ps
CPU time 0.85 seconds
Started Jul 04 06:07:02 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206192 kb
Host smart-95e196c8-6161-4352-b612-c5fb274f883b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=512936177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.512936177
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.589967428
Short name T1634
Test name
Test status
Simulation time 161039479 ps
CPU time 0.79 seconds
Started Jul 04 06:07:01 PM PDT 24
Finished Jul 04 06:07:02 PM PDT 24
Peak memory 206212 kb
Host smart-3d86f23f-b44a-4fbd-b7f0-35a5992dcb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58996
7428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.589967428
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2290731490
Short name T1374
Test name
Test status
Simulation time 222424252 ps
CPU time 0.82 seconds
Started Jul 04 06:07:05 PM PDT 24
Finished Jul 04 06:07:06 PM PDT 24
Peak memory 206208 kb
Host smart-53dcc6d4-c4da-4250-9dca-efe8d070ff26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22907
31490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2290731490
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.4101301094
Short name T1902
Test name
Test status
Simulation time 158124868 ps
CPU time 0.79 seconds
Started Jul 04 06:07:02 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206188 kb
Host smart-aa60a9a8-b1b8-4440-bce3-b7397ae64d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41013
01094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.4101301094
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3056694640
Short name T2054
Test name
Test status
Simulation time 189324644 ps
CPU time 0.9 seconds
Started Jul 04 06:07:02 PM PDT 24
Finished Jul 04 06:07:03 PM PDT 24
Peak memory 206208 kb
Host smart-aa238e36-401f-4d89-a745-5238bb4ec0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30566
94640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3056694640
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3770023255
Short name T2494
Test name
Test status
Simulation time 189621519 ps
CPU time 0.85 seconds
Started Jul 04 06:07:00 PM PDT 24
Finished Jul 04 06:07:01 PM PDT 24
Peak memory 206188 kb
Host smart-903134c0-cfdd-4934-8086-414e708d8bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37700
23255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3770023255
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3359369625
Short name T1162
Test name
Test status
Simulation time 152291250 ps
CPU time 0.77 seconds
Started Jul 04 06:07:11 PM PDT 24
Finished Jul 04 06:07:12 PM PDT 24
Peak memory 206180 kb
Host smart-9253e284-a5c9-434c-9b6d-4889d48d47ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
69625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3359369625
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3718517903
Short name T1829
Test name
Test status
Simulation time 248491294 ps
CPU time 0.99 seconds
Started Jul 04 06:07:09 PM PDT 24
Finished Jul 04 06:07:10 PM PDT 24
Peak memory 206208 kb
Host smart-0b427890-971e-49c3-be2a-d3e5a6f4de7c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3718517903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3718517903
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1995679386
Short name T50
Test name
Test status
Simulation time 235671136 ps
CPU time 1 seconds
Started Jul 04 06:07:10 PM PDT 24
Finished Jul 04 06:07:11 PM PDT 24
Peak memory 206172 kb
Host smart-1c618f32-b85e-43b9-b8b8-141afa4e5520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19956
79386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1995679386
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.298817052
Short name T1044
Test name
Test status
Simulation time 155617945 ps
CPU time 0.74 seconds
Started Jul 04 06:07:10 PM PDT 24
Finished Jul 04 06:07:11 PM PDT 24
Peak memory 206204 kb
Host smart-89ea8407-fb69-402a-9f72-89486251b4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
7052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.298817052
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3889818915
Short name T923
Test name
Test status
Simulation time 38269477 ps
CPU time 0.67 seconds
Started Jul 04 06:07:12 PM PDT 24
Finished Jul 04 06:07:13 PM PDT 24
Peak memory 206156 kb
Host smart-78e4d689-27d4-4598-9711-cc727ca8a746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38898
18915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3889818915
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.775843549
Short name T942
Test name
Test status
Simulation time 8016424409 ps
CPU time 18.41 seconds
Started Jul 04 06:07:14 PM PDT 24
Finished Jul 04 06:07:32 PM PDT 24
Peak memory 206508 kb
Host smart-6485f560-e247-4f84-b059-9a06726e0ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77584
3549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.775843549
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.606996261
Short name T1510
Test name
Test status
Simulation time 194991663 ps
CPU time 0.84 seconds
Started Jul 04 06:07:09 PM PDT 24
Finished Jul 04 06:07:10 PM PDT 24
Peak memory 206220 kb
Host smart-f39cee9f-e148-4c1d-9a8c-7b8a851520a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60699
6261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.606996261
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1723768874
Short name T1133
Test name
Test status
Simulation time 228197212 ps
CPU time 0.87 seconds
Started Jul 04 06:07:11 PM PDT 24
Finished Jul 04 06:07:12 PM PDT 24
Peak memory 206188 kb
Host smart-96606a86-a303-4677-a78c-436b81a20569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
68874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1723768874
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.778684152
Short name T194
Test name
Test status
Simulation time 11088740006 ps
CPU time 212.44 seconds
Started Jul 04 06:07:09 PM PDT 24
Finished Jul 04 06:10:41 PM PDT 24
Peak memory 206516 kb
Host smart-0162306b-c2bb-4a6f-8058-124e54c492c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=778684152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.778684152
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.903994969
Short name T186
Test name
Test status
Simulation time 18557740306 ps
CPU time 105.7 seconds
Started Jul 04 06:07:12 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206428 kb
Host smart-8b886302-35f5-4d24-8215-e433cfeddc48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=903994969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.903994969
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.522494216
Short name T478
Test name
Test status
Simulation time 168021763 ps
CPU time 0.83 seconds
Started Jul 04 06:07:10 PM PDT 24
Finished Jul 04 06:07:11 PM PDT 24
Peak memory 206188 kb
Host smart-af6d4834-8242-4265-ab27-505bc211bd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52249
4216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.522494216
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.201839623
Short name T1058
Test name
Test status
Simulation time 156736824 ps
CPU time 0.82 seconds
Started Jul 04 06:07:11 PM PDT 24
Finished Jul 04 06:07:12 PM PDT 24
Peak memory 206184 kb
Host smart-8ac640ef-39f2-4c4e-b826-a48b9f2044e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20183
9623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.201839623
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2945812289
Short name T1572
Test name
Test status
Simulation time 202710513 ps
CPU time 0.82 seconds
Started Jul 04 06:07:16 PM PDT 24
Finished Jul 04 06:07:17 PM PDT 24
Peak memory 206220 kb
Host smart-432d2e70-22f9-4b60-afd6-d71bc39577de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29458
12289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2945812289
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.346403793
Short name T2319
Test name
Test status
Simulation time 154674652 ps
CPU time 0.82 seconds
Started Jul 04 06:07:17 PM PDT 24
Finished Jul 04 06:07:18 PM PDT 24
Peak memory 206196 kb
Host smart-9b645226-e52c-48ae-a990-66fda1819e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34640
3793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.346403793
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.118471992
Short name T213
Test name
Test status
Simulation time 390110120 ps
CPU time 1.17 seconds
Started Jul 04 06:07:17 PM PDT 24
Finished Jul 04 06:07:19 PM PDT 24
Peak memory 224068 kb
Host smart-481ba542-18d7-4fb7-ad45-761d9e43ffa6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=118471992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.118471992
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.70650066
Short name T2399
Test name
Test status
Simulation time 429411175 ps
CPU time 1.37 seconds
Started Jul 04 06:07:21 PM PDT 24
Finished Jul 04 06:07:23 PM PDT 24
Peak memory 206208 kb
Host smart-a3671cdf-cc98-4f14-9975-b8ff2a25e72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70650
066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.70650066
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2546432616
Short name T171
Test name
Test status
Simulation time 171143339 ps
CPU time 0.85 seconds
Started Jul 04 06:07:19 PM PDT 24
Finished Jul 04 06:07:20 PM PDT 24
Peak memory 206212 kb
Host smart-ed576607-df34-461c-825e-521ef77d98e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25464
32616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2546432616
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2162044167
Short name T861
Test name
Test status
Simulation time 150319299 ps
CPU time 0.77 seconds
Started Jul 04 06:07:21 PM PDT 24
Finished Jul 04 06:07:22 PM PDT 24
Peak memory 206204 kb
Host smart-b22512ef-b632-4196-b045-7773653d7a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21620
44167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2162044167
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3793582465
Short name T1367
Test name
Test status
Simulation time 158659591 ps
CPU time 0.78 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:16 PM PDT 24
Peak memory 206148 kb
Host smart-8b6231f3-3710-4757-8fa8-201605707528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37935
82465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3793582465
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.611157598
Short name T512
Test name
Test status
Simulation time 224807998 ps
CPU time 0.97 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:16 PM PDT 24
Peak memory 206176 kb
Host smart-82a79baf-67a3-4549-a10e-73e9b9176955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61115
7598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.611157598
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.971356137
Short name T617
Test name
Test status
Simulation time 6050013191 ps
CPU time 174.49 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:10:10 PM PDT 24
Peak memory 206452 kb
Host smart-439dd807-1db8-4382-ad8a-6324b0e072ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=971356137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.971356137
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1217601425
Short name T2197
Test name
Test status
Simulation time 172112021 ps
CPU time 0.81 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:16 PM PDT 24
Peak memory 206216 kb
Host smart-28bd6f22-a230-4333-96bc-f47fe23fdc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176
01425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1217601425
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3702198036
Short name T1431
Test name
Test status
Simulation time 189244122 ps
CPU time 0.83 seconds
Started Jul 04 06:07:21 PM PDT 24
Finished Jul 04 06:07:22 PM PDT 24
Peak memory 206208 kb
Host smart-6ae2e230-80b7-4fdd-a8b2-c4eeb4a0133e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021
98036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3702198036
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2705033340
Short name T819
Test name
Test status
Simulation time 262558404 ps
CPU time 0.96 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:17 PM PDT 24
Peak memory 206208 kb
Host smart-85872770-7505-4515-9381-90d60f9b34eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27050
33340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2705033340
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1253643197
Short name T2440
Test name
Test status
Simulation time 4289580522 ps
CPU time 40.22 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206536 kb
Host smart-2786d005-58c3-4c9b-9806-5826de00f152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12536
43197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1253643197
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.2456050280
Short name T1259
Test name
Test status
Simulation time 37040304 ps
CPU time 0.66 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206184 kb
Host smart-664c2ead-be49-45de-9302-13b143771c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2456050280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.2456050280
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2963880585
Short name T525
Test name
Test status
Simulation time 3367078130 ps
CPU time 5.07 seconds
Started Jul 04 06:14:49 PM PDT 24
Finished Jul 04 06:14:54 PM PDT 24
Peak memory 206264 kb
Host smart-15b97fe4-d026-483d-9ba4-6ac21af721e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2963880585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2963880585
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2302244449
Short name T1661
Test name
Test status
Simulation time 13430554424 ps
CPU time 12.54 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:15:00 PM PDT 24
Peak memory 206480 kb
Host smart-d102e487-1083-4d9a-848c-d8931b8c46cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2302244449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2302244449
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3802573888
Short name T13
Test name
Test status
Simulation time 23314918083 ps
CPU time 30.09 seconds
Started Jul 04 06:14:46 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206236 kb
Host smart-92c5cce6-38d2-400c-8fae-b4ef493ddad3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3802573888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3802573888
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3875776808
Short name T578
Test name
Test status
Simulation time 201829581 ps
CPU time 0.87 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206176 kb
Host smart-f5997fcd-8aab-4c48-b9d9-83e2dd3302e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38757
76808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3875776808
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4291725793
Short name T2093
Test name
Test status
Simulation time 190153037 ps
CPU time 0.83 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206164 kb
Host smart-667d36b5-26f3-4db2-9af9-d53234e048c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
25793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4291725793
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3342245696
Short name T2671
Test name
Test status
Simulation time 523439215 ps
CPU time 1.66 seconds
Started Jul 04 06:14:46 PM PDT 24
Finished Jul 04 06:14:47 PM PDT 24
Peak memory 206420 kb
Host smart-6c6cccf6-b487-4e69-b773-e9f7f2fc78ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33422
45696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3342245696
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1357206146
Short name T1917
Test name
Test status
Simulation time 1197422019 ps
CPU time 2.65 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206340 kb
Host smart-455a6577-d145-4e4d-95c4-1ab0aab13f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
06146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1357206146
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3530531851
Short name T2151
Test name
Test status
Simulation time 15984854620 ps
CPU time 30.7 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:15:18 PM PDT 24
Peak memory 206456 kb
Host smart-29ed2248-404f-4aab-9f5d-bdaf5d78117c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35305
31851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3530531851
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1999519304
Short name T490
Test name
Test status
Simulation time 321706820 ps
CPU time 1.12 seconds
Started Jul 04 06:14:53 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206192 kb
Host smart-18b0a47d-b4f3-4151-be98-d38c9e4ef3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
19304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1999519304
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3840788832
Short name T975
Test name
Test status
Simulation time 148141013 ps
CPU time 0.77 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206208 kb
Host smart-e1831928-f0b0-49e4-bb5f-55bf8c29fa2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
88832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3840788832
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3029653754
Short name T1527
Test name
Test status
Simulation time 40186963 ps
CPU time 0.7 seconds
Started Jul 04 06:14:50 PM PDT 24
Finished Jul 04 06:14:51 PM PDT 24
Peak memory 206200 kb
Host smart-455592c3-752e-4e3c-b07e-078de6d2c94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30296
53754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3029653754
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3887775029
Short name T1026
Test name
Test status
Simulation time 855282628 ps
CPU time 2.36 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206420 kb
Host smart-0224e56c-26fd-42af-9080-7597d85ce42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
75029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3887775029
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4279609818
Short name T1668
Test name
Test status
Simulation time 179321371 ps
CPU time 1.28 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206340 kb
Host smart-f769ba5a-62eb-4659-a834-7306cf5d98cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42796
09818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4279609818
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.595535470
Short name T913
Test name
Test status
Simulation time 146786149 ps
CPU time 0.8 seconds
Started Jul 04 06:14:49 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206204 kb
Host smart-50c2057f-8f24-400a-a811-b83625869944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59553
5470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.595535470
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1567551990
Short name T1779
Test name
Test status
Simulation time 147601247 ps
CPU time 0.86 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206188 kb
Host smart-baeff915-aeb6-4ab9-82c8-36d52ef3f7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15675
51990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1567551990
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2767324158
Short name T2413
Test name
Test status
Simulation time 186923569 ps
CPU time 0.85 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206220 kb
Host smart-0d5bc611-885b-4aef-a222-3d207ae45057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
24158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2767324158
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2426257608
Short name T1473
Test name
Test status
Simulation time 5302929251 ps
CPU time 137.82 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:17:05 PM PDT 24
Peak memory 206516 kb
Host smart-4245dc9c-56b7-4995-8e3e-34d09559c464
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2426257608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2426257608
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3840255165
Short name T1137
Test name
Test status
Simulation time 198917221 ps
CPU time 0.85 seconds
Started Jul 04 06:14:46 PM PDT 24
Finished Jul 04 06:14:47 PM PDT 24
Peak memory 206192 kb
Host smart-b5da84e3-5f39-4572-bb09-ba2ae62f8f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38402
55165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3840255165
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1426412019
Short name T1423
Test name
Test status
Simulation time 23324502782 ps
CPU time 24.48 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:15:13 PM PDT 24
Peak memory 206252 kb
Host smart-760d4251-ecf1-4c14-9b87-19333d5b3735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14264
12019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1426412019
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.730314481
Short name T2021
Test name
Test status
Simulation time 3355203022 ps
CPU time 3.83 seconds
Started Jul 04 06:14:46 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206288 kb
Host smart-16351644-3566-4319-a31b-5462270da7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73031
4481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.730314481
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2250250827
Short name T948
Test name
Test status
Simulation time 9095472106 ps
CPU time 82.09 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206552 kb
Host smart-24e6d736-b249-47ab-ad40-cf1915423d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22502
50827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2250250827
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3228948584
Short name T1037
Test name
Test status
Simulation time 3453682221 ps
CPU time 24.2 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:15:19 PM PDT 24
Peak memory 206528 kb
Host smart-b46af519-d88a-43b3-a15c-349cf2025ad3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3228948584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3228948584
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1258328134
Short name T370
Test name
Test status
Simulation time 241710763 ps
CPU time 0.93 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206156 kb
Host smart-05b65cc9-5365-4f3c-a2fc-81b07383aca8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1258328134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1258328134
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3973933089
Short name T2060
Test name
Test status
Simulation time 184965187 ps
CPU time 0.89 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206160 kb
Host smart-f05f4d4f-6255-42de-b0bf-171e8e69fe76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39739
33089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3973933089
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1576482092
Short name T682
Test name
Test status
Simulation time 4508774726 ps
CPU time 120.39 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:16:55 PM PDT 24
Peak memory 206472 kb
Host smart-07097862-9c19-46fb-b041-6cafa9e5e851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15764
82092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1576482092
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3181474068
Short name T1666
Test name
Test status
Simulation time 4365588377 ps
CPU time 39.14 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206428 kb
Host smart-6cfb9846-5a32-4d18-b87d-fe08684c1ac0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3181474068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3181474068
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2480773849
Short name T347
Test name
Test status
Simulation time 181044385 ps
CPU time 0.88 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206128 kb
Host smart-8e6380b0-68a6-47dc-9c10-2a61940b6b28
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2480773849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2480773849
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2563545079
Short name T904
Test name
Test status
Simulation time 151647604 ps
CPU time 0.79 seconds
Started Jul 04 06:14:53 PM PDT 24
Finished Jul 04 06:14:54 PM PDT 24
Peak memory 206204 kb
Host smart-d89a217c-5b33-4dd6-9da5-a1633505ff55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
45079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2563545079
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3963909266
Short name T128
Test name
Test status
Simulation time 152999405 ps
CPU time 0.77 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206224 kb
Host smart-aa058d97-7a3f-4610-8905-659f1937304b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
09266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3963909266
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1558205256
Short name T1051
Test name
Test status
Simulation time 175844296 ps
CPU time 0.83 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206212 kb
Host smart-d910547a-0e5f-4f1e-8077-68cd52dbb50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15582
05256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1558205256
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2496958052
Short name T901
Test name
Test status
Simulation time 173787533 ps
CPU time 0.82 seconds
Started Jul 04 06:14:49 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206180 kb
Host smart-bbaff105-c3c5-4d75-8247-f3123a608ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24969
58052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2496958052
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1412558438
Short name T2109
Test name
Test status
Simulation time 193842013 ps
CPU time 0.84 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206188 kb
Host smart-51f6671c-81c3-4f55-8fee-1f8c09453a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14125
58438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1412558438
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.73487603
Short name T1500
Test name
Test status
Simulation time 153308109 ps
CPU time 0.77 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206192 kb
Host smart-9d3865e2-cba2-4ed0-a539-b379aad5ebb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73487
603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.73487603
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3322689189
Short name T2661
Test name
Test status
Simulation time 228287044 ps
CPU time 0.92 seconds
Started Jul 04 06:14:55 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206156 kb
Host smart-fbae362c-4401-4149-8f2a-b38057d67fe8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3322689189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3322689189
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1447995496
Short name T1567
Test name
Test status
Simulation time 148982224 ps
CPU time 0.75 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206180 kb
Host smart-77c2c880-a45f-4bd9-9dce-a01a504df833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14479
95496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1447995496
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3008887031
Short name T808
Test name
Test status
Simulation time 47196077 ps
CPU time 0.68 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206212 kb
Host smart-c855e466-63e3-4d85-87e6-1a4df10db4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30088
87031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3008887031
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.930416275
Short name T2266
Test name
Test status
Simulation time 12333344899 ps
CPU time 26.91 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206472 kb
Host smart-7a967d78-1543-47cb-b607-a3ee43b8be45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93041
6275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.930416275
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2076454280
Short name T1671
Test name
Test status
Simulation time 195111325 ps
CPU time 0.86 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206180 kb
Host smart-b3114322-a854-4e95-8b28-aeeca3969034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20764
54280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2076454280
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3698251319
Short name T1727
Test name
Test status
Simulation time 268931657 ps
CPU time 0.95 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206204 kb
Host smart-24194a76-9599-4532-b413-3e89125a4daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36982
51319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3698251319
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1039497066
Short name T2172
Test name
Test status
Simulation time 238714935 ps
CPU time 0.98 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:14:49 PM PDT 24
Peak memory 206204 kb
Host smart-97888cc8-b8fd-44e7-bfaa-873a12707671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10394
97066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1039497066
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3509849044
Short name T960
Test name
Test status
Simulation time 157742092 ps
CPU time 0.8 seconds
Started Jul 04 06:14:47 PM PDT 24
Finished Jul 04 06:14:48 PM PDT 24
Peak memory 206188 kb
Host smart-ff23957b-dac6-4819-a1f3-0d2a2eeb2502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
49044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3509849044
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1004570930
Short name T489
Test name
Test status
Simulation time 145772684 ps
CPU time 0.75 seconds
Started Jul 04 06:14:49 PM PDT 24
Finished Jul 04 06:14:50 PM PDT 24
Peak memory 206176 kb
Host smart-733e5bf0-fcc6-4b7f-8222-91882a35f3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10045
70930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1004570930
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.666351266
Short name T1739
Test name
Test status
Simulation time 145524536 ps
CPU time 0.79 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:58 PM PDT 24
Peak memory 206140 kb
Host smart-948efe82-33af-4a7b-bfa6-db158bbe6b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66635
1266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.666351266
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4222521836
Short name T2292
Test name
Test status
Simulation time 148137275 ps
CPU time 0.78 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:58 PM PDT 24
Peak memory 206152 kb
Host smart-3cbf4f26-70ea-4804-a419-1e8541233b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42225
21836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4222521836
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3982979436
Short name T2205
Test name
Test status
Simulation time 214761068 ps
CPU time 0.97 seconds
Started Jul 04 06:14:51 PM PDT 24
Finished Jul 04 06:14:52 PM PDT 24
Peak memory 206172 kb
Host smart-130fefdd-153a-40fd-a82c-4639ef6c8025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39829
79436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3982979436
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2265641187
Short name T874
Test name
Test status
Simulation time 5082346956 ps
CPU time 47.05 seconds
Started Jul 04 06:14:45 PM PDT 24
Finished Jul 04 06:15:32 PM PDT 24
Peak memory 206476 kb
Host smart-32c6dc7b-cc00-4f57-a814-0312b9000ad9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2265641187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2265641187
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.65820040
Short name T1619
Test name
Test status
Simulation time 176718431 ps
CPU time 0.77 seconds
Started Jul 04 06:14:55 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206148 kb
Host smart-dbfe7c0e-67c4-448b-9a1d-0975eac4791f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65820
040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.65820040
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3700474321
Short name T2361
Test name
Test status
Simulation time 197037279 ps
CPU time 0.91 seconds
Started Jul 04 06:14:51 PM PDT 24
Finished Jul 04 06:14:52 PM PDT 24
Peak memory 206176 kb
Host smart-a4fc577e-d2fb-4a07-925e-5e75ba5c2fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37004
74321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3700474321
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.2973694349
Short name T1534
Test name
Test status
Simulation time 785493324 ps
CPU time 1.94 seconds
Started Jul 04 06:14:57 PM PDT 24
Finished Jul 04 06:14:59 PM PDT 24
Peak memory 206444 kb
Host smart-e33ff5d0-ee1e-451f-87a9-45fdc99dd3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29736
94349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.2973694349
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3627667488
Short name T1170
Test name
Test status
Simulation time 7161742760 ps
CPU time 67.69 seconds
Started Jul 04 06:14:48 PM PDT 24
Finished Jul 04 06:15:57 PM PDT 24
Peak memory 206528 kb
Host smart-a598ccc7-e908-4e8c-ad03-c9d47197bbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36276
67488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3627667488
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3503780646
Short name T1365
Test name
Test status
Simulation time 45752466 ps
CPU time 0.64 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:05 PM PDT 24
Peak memory 206484 kb
Host smart-8b3bd5cc-cb02-4347-819b-b8665cc8755b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3503780646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3503780646
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3194183619
Short name T1784
Test name
Test status
Simulation time 3564230647 ps
CPU time 3.93 seconds
Started Jul 04 06:14:55 PM PDT 24
Finished Jul 04 06:14:59 PM PDT 24
Peak memory 206472 kb
Host smart-3a2dfc8d-8a43-44e9-bf46-c534b30773c9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3194183619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3194183619
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.845621502
Short name T1566
Test name
Test status
Simulation time 13402918356 ps
CPU time 11.67 seconds
Started Jul 04 06:14:57 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206468 kb
Host smart-c696a5be-4d9f-4e9c-ab79-f386159ea157
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=845621502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.845621502
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1117505128
Short name T2615
Test name
Test status
Simulation time 23381183269 ps
CPU time 24.19 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:15:21 PM PDT 24
Peak memory 206520 kb
Host smart-52eda94c-df50-416a-a1b0-a4ec6d73825e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1117505128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1117505128
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1658130001
Short name T2605
Test name
Test status
Simulation time 150809824 ps
CPU time 0.78 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206236 kb
Host smart-187acdf6-fc35-4e94-afbd-d646fcb54f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
30001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1658130001
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3161485801
Short name T1929
Test name
Test status
Simulation time 169965848 ps
CPU time 0.85 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206176 kb
Host smart-62278be9-8e4f-46d2-be29-0b848787b6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
85801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3161485801
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2331814585
Short name T1993
Test name
Test status
Simulation time 218889396 ps
CPU time 0.92 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206180 kb
Host smart-7dc8f131-f811-401e-9088-0c15d2417ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23318
14585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2331814585
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2412650026
Short name T1492
Test name
Test status
Simulation time 1108707723 ps
CPU time 2.66 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:58 PM PDT 24
Peak memory 206384 kb
Host smart-4e2d0dfd-1e47-4ed4-bbcc-892e371d32e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126
50026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2412650026
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2564436907
Short name T1729
Test name
Test status
Simulation time 15585317405 ps
CPU time 31.09 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:15:26 PM PDT 24
Peak memory 206508 kb
Host smart-7607910b-312c-408d-984f-c52b5dbdbbb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
36907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2564436907
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.868661275
Short name T1292
Test name
Test status
Simulation time 543587112 ps
CPU time 1.52 seconds
Started Jul 04 06:14:55 PM PDT 24
Finished Jul 04 06:14:57 PM PDT 24
Peak memory 206184 kb
Host smart-ec8b047b-22bb-47ac-881c-a42152ccb1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86866
1275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.868661275
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1820574226
Short name T2385
Test name
Test status
Simulation time 182204237 ps
CPU time 0.8 seconds
Started Jul 04 06:14:53 PM PDT 24
Finished Jul 04 06:14:54 PM PDT 24
Peak memory 206212 kb
Host smart-0b0a1943-8848-422c-9c58-5180905f0a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
74226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1820574226
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3666175132
Short name T980
Test name
Test status
Simulation time 36565736 ps
CPU time 0.67 seconds
Started Jul 04 06:14:58 PM PDT 24
Finished Jul 04 06:14:59 PM PDT 24
Peak memory 206152 kb
Host smart-c0e749a2-a8f3-4310-834e-28f715817023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36661
75132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3666175132
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1561864647
Short name T1325
Test name
Test status
Simulation time 855470482 ps
CPU time 2.13 seconds
Started Jul 04 06:14:53 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206336 kb
Host smart-3f311e62-e0bb-4821-9015-90dff9693c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
64647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1561864647
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2764851286
Short name T1977
Test name
Test status
Simulation time 178125604 ps
CPU time 1.69 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206336 kb
Host smart-9d161532-819d-40dc-b79d-77491693d15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
51286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2764851286
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2347005874
Short name T2181
Test name
Test status
Simulation time 263049061 ps
CPU time 0.95 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206208 kb
Host smart-035a7ec9-a0f1-41b4-9c58-d90435cddbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
05874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2347005874
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2683992405
Short name T1715
Test name
Test status
Simulation time 146329608 ps
CPU time 0.76 seconds
Started Jul 04 06:14:57 PM PDT 24
Finished Jul 04 06:14:58 PM PDT 24
Peak memory 206204 kb
Host smart-2657dcbe-287f-45d0-8be7-e232b6fd410d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26839
92405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2683992405
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4057427835
Short name T2212
Test name
Test status
Simulation time 214329212 ps
CPU time 0.88 seconds
Started Jul 04 06:14:53 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206108 kb
Host smart-fc2a07c2-7179-4bd9-8fc4-7fbd11dff656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40574
27835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4057427835
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.263812839
Short name T2045
Test name
Test status
Simulation time 191887230 ps
CPU time 0.85 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206220 kb
Host smart-083b419f-0a46-42dd-8825-0492f2c2619b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381
2839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.263812839
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.713871653
Short name T1125
Test name
Test status
Simulation time 23351344960 ps
CPU time 26.69 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:15:23 PM PDT 24
Peak memory 206244 kb
Host smart-e20e6918-7159-463a-8777-2bd2b3ed006d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71387
1653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.713871653
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3203185523
Short name T1849
Test name
Test status
Simulation time 3278039609 ps
CPU time 4.18 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:59 PM PDT 24
Peak memory 206260 kb
Host smart-74198e57-b5ee-4cd9-bde5-c2ff385edf85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32031
85523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3203185523
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3690267315
Short name T496
Test name
Test status
Simulation time 5368621465 ps
CPU time 50.33 seconds
Started Jul 04 06:14:56 PM PDT 24
Finished Jul 04 06:15:46 PM PDT 24
Peak memory 206488 kb
Host smart-ddac555e-dce7-4d85-999b-2fa2e4f7be70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36902
67315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3690267315
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3262706297
Short name T1659
Test name
Test status
Simulation time 6222856619 ps
CPU time 171.52 seconds
Started Jul 04 06:14:52 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 206408 kb
Host smart-d2cc2d41-5010-43b1-8c5c-15b00f064c72
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3262706297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3262706297
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.57533171
Short name T468
Test name
Test status
Simulation time 235953082 ps
CPU time 0.9 seconds
Started Jul 04 06:14:53 PM PDT 24
Finished Jul 04 06:14:54 PM PDT 24
Peak memory 206180 kb
Host smart-badf7af5-f620-4dcc-9b63-5f266930a618
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=57533171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.57533171
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2094376424
Short name T411
Test name
Test status
Simulation time 187342345 ps
CPU time 0.85 seconds
Started Jul 04 06:14:59 PM PDT 24
Finished Jul 04 06:15:00 PM PDT 24
Peak memory 206204 kb
Host smart-21a801c1-781e-40ed-9a21-0d66c6acbc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
76424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2094376424
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3056239834
Short name T900
Test name
Test status
Simulation time 5882603691 ps
CPU time 157.05 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:17:32 PM PDT 24
Peak memory 206392 kb
Host smart-15742216-947e-46be-9f2c-6ca2bb590cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30562
39834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3056239834
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.4219283461
Short name T1521
Test name
Test status
Simulation time 3529359083 ps
CPU time 25.52 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:15:20 PM PDT 24
Peak memory 206380 kb
Host smart-1a965460-d9ee-44b4-91ee-33ec964ea944
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4219283461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.4219283461
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2603834193
Short name T613
Test name
Test status
Simulation time 162646277 ps
CPU time 0.79 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:55 PM PDT 24
Peak memory 206176 kb
Host smart-bad9c19c-4b8a-4fa6-b859-5a010bf29f5d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2603834193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2603834193
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.906237763
Short name T1443
Test name
Test status
Simulation time 158944665 ps
CPU time 0.79 seconds
Started Jul 04 06:14:55 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206176 kb
Host smart-a9174f82-d6ab-48a2-b665-e30d988f1724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90623
7763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.906237763
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.927164669
Short name T2007
Test name
Test status
Simulation time 219849650 ps
CPU time 0.85 seconds
Started Jul 04 06:14:54 PM PDT 24
Finished Jul 04 06:14:56 PM PDT 24
Peak memory 206204 kb
Host smart-41c3c63c-08c7-40bf-ad1c-ce6a80c56632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92716
4669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.927164669
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.746495588
Short name T1064
Test name
Test status
Simulation time 183171980 ps
CPU time 0.88 seconds
Started Jul 04 06:14:57 PM PDT 24
Finished Jul 04 06:14:58 PM PDT 24
Peak memory 206192 kb
Host smart-51a15951-af72-4558-863a-ee82ba94cd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74649
5588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.746495588
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1994369231
Short name T1102
Test name
Test status
Simulation time 166306927 ps
CPU time 0.84 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206180 kb
Host smart-367d03de-a303-430e-be57-14022e8e0093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19943
69231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1994369231
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2047459867
Short name T720
Test name
Test status
Simulation time 171923654 ps
CPU time 0.8 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:01 PM PDT 24
Peak memory 206188 kb
Host smart-c1072790-a5f8-44ee-af32-e39db5466e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20474
59867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2047459867
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3062756918
Short name T697
Test name
Test status
Simulation time 160475574 ps
CPU time 0.79 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:01 PM PDT 24
Peak memory 206160 kb
Host smart-b47cfee4-aafc-41ac-bab8-070d213cf939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30627
56918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3062756918
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1126770147
Short name T1750
Test name
Test status
Simulation time 284265195 ps
CPU time 1.1 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206184 kb
Host smart-1cb4c8da-ca5e-4e3e-9acd-55faa422a30c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1126770147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1126770147
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3544211435
Short name T2190
Test name
Test status
Simulation time 151627268 ps
CPU time 0.8 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:05 PM PDT 24
Peak memory 206104 kb
Host smart-bd2b915d-14bc-4bff-81f3-a72fb97a34e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35442
11435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3544211435
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.308806308
Short name T2051
Test name
Test status
Simulation time 86308565 ps
CPU time 0.72 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206224 kb
Host smart-0b859e9d-4244-473c-96e7-baf5658723f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
6308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.308806308
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1835986075
Short name T2498
Test name
Test status
Simulation time 12861894966 ps
CPU time 29.7 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:15:33 PM PDT 24
Peak memory 206492 kb
Host smart-461fa5ae-8de7-4759-bf96-461672aab143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18359
86075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1835986075
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2748349906
Short name T972
Test name
Test status
Simulation time 204484049 ps
CPU time 0.84 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206160 kb
Host smart-66f35119-5921-42de-9ad8-381f17bbdb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27483
49906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2748349906
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.640093471
Short name T409
Test name
Test status
Simulation time 182046888 ps
CPU time 0.86 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206212 kb
Host smart-7757ee4b-b41c-40f5-b8a2-446be1547a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64009
3471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.640093471
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1833633245
Short name T2537
Test name
Test status
Simulation time 188347714 ps
CPU time 0.84 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206216 kb
Host smart-9ce2350e-951e-4b42-8621-7a07170c6826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
33245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1833633245
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1235889886
Short name T1708
Test name
Test status
Simulation time 177485624 ps
CPU time 0.88 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206208 kb
Host smart-286fdc39-fb7b-41f1-bb2c-44fc9fdde1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12358
89886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1235889886
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1332667880
Short name T1369
Test name
Test status
Simulation time 163651383 ps
CPU time 0.81 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206176 kb
Host smart-6e429afc-7c30-4a00-9bec-17bdc4c5c385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13326
67880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1332667880
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1242987889
Short name T117
Test name
Test status
Simulation time 145944429 ps
CPU time 0.8 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206164 kb
Host smart-87f8ad01-eb39-469f-8695-3bffba42326a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12429
87889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1242987889
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3699862468
Short name T98
Test name
Test status
Simulation time 152084172 ps
CPU time 0.77 seconds
Started Jul 04 06:15:06 PM PDT 24
Finished Jul 04 06:15:07 PM PDT 24
Peak memory 206172 kb
Host smart-77f4bc97-7860-4242-9fc2-e0ecac6a7d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36998
62468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3699862468
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.86073092
Short name T2039
Test name
Test status
Simulation time 249334126 ps
CPU time 0.93 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206172 kb
Host smart-7f22e680-5256-457f-890a-27c5b935ac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86073
092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.86073092
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.845675658
Short name T806
Test name
Test status
Simulation time 4806444401 ps
CPU time 32.82 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206752 kb
Host smart-60bf1650-b7e7-4c3b-a5c0-43f0dce6d63c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=845675658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.845675658
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.854559443
Short name T929
Test name
Test status
Simulation time 229313591 ps
CPU time 0.91 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206176 kb
Host smart-42e6c741-9c08-4a0d-898e-f0ccbff2eb01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85455
9443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.854559443
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4225879499
Short name T2334
Test name
Test status
Simulation time 174591349 ps
CPU time 0.8 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206196 kb
Host smart-586a990b-83d1-4116-bd3c-729dc0553f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42258
79499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4225879499
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.384472245
Short name T843
Test name
Test status
Simulation time 873587059 ps
CPU time 1.96 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206376 kb
Host smart-158e7e4b-522b-4858-bec7-357bdb938b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38447
2245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.384472245
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2538048594
Short name T2643
Test name
Test status
Simulation time 7946006547 ps
CPU time 53.52 seconds
Started Jul 04 06:15:08 PM PDT 24
Finished Jul 04 06:16:02 PM PDT 24
Peak memory 206380 kb
Host smart-60b8687d-7439-47a3-8faf-a113e87d91f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
48594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2538048594
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.4157957481
Short name T1451
Test name
Test status
Simulation time 42549472 ps
CPU time 0.67 seconds
Started Jul 04 06:15:19 PM PDT 24
Finished Jul 04 06:15:20 PM PDT 24
Peak memory 206184 kb
Host smart-21caf674-f5f8-4a53-b71a-8539032863c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4157957481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.4157957481
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.4012484887
Short name T2273
Test name
Test status
Simulation time 4271888713 ps
CPU time 5.27 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206748 kb
Host smart-015ac43a-e582-4d6a-bf09-331aa8dd1af4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4012484887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.4012484887
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1888278033
Short name T663
Test name
Test status
Simulation time 13406268809 ps
CPU time 14.44 seconds
Started Jul 04 06:15:05 PM PDT 24
Finished Jul 04 06:15:20 PM PDT 24
Peak memory 206504 kb
Host smart-a3343cba-259a-4ca3-bd39-1ee2fb1767f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1888278033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1888278033
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3692247194
Short name T480
Test name
Test status
Simulation time 23480312653 ps
CPU time 22.8 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:25 PM PDT 24
Peak memory 206264 kb
Host smart-542064fb-b777-44a2-a94c-4ff9fb81504c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3692247194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3692247194
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2407128309
Short name T2501
Test name
Test status
Simulation time 159423135 ps
CPU time 0.83 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206212 kb
Host smart-61d03b9d-61a8-4c23-bef1-e99f5abf6cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
28309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2407128309
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2232662165
Short name T375
Test name
Test status
Simulation time 144615423 ps
CPU time 0.74 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:05 PM PDT 24
Peak memory 206176 kb
Host smart-f623c1e3-3291-4711-af88-ba382e90a27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
62165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2232662165
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2075061814
Short name T696
Test name
Test status
Simulation time 149742698 ps
CPU time 0.82 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206208 kb
Host smart-dca7a3bd-95a2-4f76-bf46-45916df87f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
61814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2075061814
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.996595577
Short name T1375
Test name
Test status
Simulation time 881615644 ps
CPU time 2.04 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:03 PM PDT 24
Peak memory 206424 kb
Host smart-e17345a9-0c11-4449-a07b-2c83e4a09be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99659
5577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.996595577
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3235519719
Short name T2428
Test name
Test status
Simulation time 8413588806 ps
CPU time 15.39 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:15:19 PM PDT 24
Peak memory 206436 kb
Host smart-c74c3a1b-3f17-4981-8f92-513085ed96e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32355
19719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3235519719
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1761753710
Short name T1616
Test name
Test status
Simulation time 318782774 ps
CPU time 1.09 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206180 kb
Host smart-7bd94926-ed11-49f0-8233-edd7481d834d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17617
53710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1761753710
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1668719880
Short name T810
Test name
Test status
Simulation time 140474654 ps
CPU time 0.76 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206208 kb
Host smart-ecb1f61c-c505-47e4-a527-15e90a3fbdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16687
19880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1668719880
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2853835436
Short name T2126
Test name
Test status
Simulation time 122881116 ps
CPU time 0.71 seconds
Started Jul 04 06:15:05 PM PDT 24
Finished Jul 04 06:15:06 PM PDT 24
Peak memory 206148 kb
Host smart-ad427390-1747-42eb-b543-4f3d40d204ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
35436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2853835436
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3067792055
Short name T1154
Test name
Test status
Simulation time 907203864 ps
CPU time 2.34 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:15:05 PM PDT 24
Peak memory 206404 kb
Host smart-87496200-6616-4737-a49a-e19400366983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30677
92055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3067792055
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2771307778
Short name T931
Test name
Test status
Simulation time 153055076 ps
CPU time 1.28 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:01 PM PDT 24
Peak memory 206404 kb
Host smart-1bf4951b-e5b5-43a2-abef-09993d8c0b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27713
07778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2771307778
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2420572240
Short name T2623
Test name
Test status
Simulation time 199962014 ps
CPU time 0.84 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206144 kb
Host smart-7b20e65b-0737-4070-873b-4825ff7b62ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
72240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2420572240
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2360640418
Short name T2497
Test name
Test status
Simulation time 160999520 ps
CPU time 0.79 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206208 kb
Host smart-645858c3-b91f-4628-bd51-8565865331a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23606
40418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2360640418
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.763925076
Short name T2370
Test name
Test status
Simulation time 231535960 ps
CPU time 1.04 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206192 kb
Host smart-4693c670-04ec-474b-af3a-7af6852a0345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76392
5076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.763925076
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3387653486
Short name T965
Test name
Test status
Simulation time 290920039 ps
CPU time 0.93 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206196 kb
Host smart-b9b1a611-3e63-4297-be80-e64d1ff2dc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33876
53486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3387653486
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1217478379
Short name T1319
Test name
Test status
Simulation time 23355743043 ps
CPU time 24.34 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206180 kb
Host smart-cbdae54d-aa29-4169-8110-4b7b5a922e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12174
78379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1217478379
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3160786418
Short name T1069
Test name
Test status
Simulation time 3365510608 ps
CPU time 3.74 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:08 PM PDT 24
Peak memory 206192 kb
Host smart-9a03f3c8-954a-4c6d-98b8-6ff1302947e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31607
86418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3160786418
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2118563603
Short name T481
Test name
Test status
Simulation time 12884776278 ps
CPU time 359.72 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:21:05 PM PDT 24
Peak memory 206496 kb
Host smart-800d7c56-a154-41f0-ae35-cc5d6b479f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
63603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2118563603
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.936472251
Short name T515
Test name
Test status
Simulation time 5771655547 ps
CPU time 165.94 seconds
Started Jul 04 06:15:06 PM PDT 24
Finished Jul 04 06:17:52 PM PDT 24
Peak memory 206420 kb
Host smart-1a6c6b99-c7ac-47fe-ba18-e92958418bfb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=936472251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.936472251
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.4103274759
Short name T1010
Test name
Test status
Simulation time 268333787 ps
CPU time 0.88 seconds
Started Jul 04 06:15:00 PM PDT 24
Finished Jul 04 06:15:02 PM PDT 24
Peak memory 206216 kb
Host smart-551f8288-fb69-4cbe-9f3c-047f493588a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4103274759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.4103274759
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1757020337
Short name T1900
Test name
Test status
Simulation time 204073492 ps
CPU time 0.9 seconds
Started Jul 04 06:15:02 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206208 kb
Host smart-5fa3b7ca-8ad5-4d6e-abaa-7c30035e2da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17570
20337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1757020337
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3013137126
Short name T2120
Test name
Test status
Simulation time 3662892233 ps
CPU time 103.3 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:16:47 PM PDT 24
Peak memory 206472 kb
Host smart-fda33e29-2fe9-453f-84f9-471aa67ac803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
37126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3013137126
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2716070043
Short name T1686
Test name
Test status
Simulation time 4503518774 ps
CPU time 42.52 seconds
Started Jul 04 06:15:01 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206492 kb
Host smart-51f75a43-fb3d-4438-8c90-53e2f7ee7878
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2716070043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2716070043
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2437441296
Short name T755
Test name
Test status
Simulation time 168722583 ps
CPU time 0.79 seconds
Started Jul 04 06:15:03 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206192 kb
Host smart-c0c5dc1e-8b96-48d8-88b8-d25c6e8996d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2437441296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2437441296
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2752104946
Short name T2558
Test name
Test status
Simulation time 155246500 ps
CPU time 0.84 seconds
Started Jul 04 06:15:06 PM PDT 24
Finished Jul 04 06:15:07 PM PDT 24
Peak memory 206152 kb
Host smart-b5d95f53-b66e-4636-a2ad-462bd94bc690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27521
04946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2752104946
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.643194309
Short name T1640
Test name
Test status
Simulation time 250506853 ps
CPU time 0.86 seconds
Started Jul 04 06:15:05 PM PDT 24
Finished Jul 04 06:15:06 PM PDT 24
Peak memory 206172 kb
Host smart-31c02413-0786-4b50-8a1c-03fa7ee6516f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64319
4309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.643194309
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2876524811
Short name T722
Test name
Test status
Simulation time 173956536 ps
CPU time 0.76 seconds
Started Jul 04 06:15:07 PM PDT 24
Finished Jul 04 06:15:08 PM PDT 24
Peak memory 206204 kb
Host smart-736ccc21-cf64-4c33-b274-8b4c6883aa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765
24811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2876524811
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1271281623
Short name T922
Test name
Test status
Simulation time 143991410 ps
CPU time 0.76 seconds
Started Jul 04 06:15:04 PM PDT 24
Finished Jul 04 06:15:05 PM PDT 24
Peak memory 206204 kb
Host smart-1193376a-1b32-449b-ac49-9ffc10f03584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12712
81623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1271281623
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2945320968
Short name T1503
Test name
Test status
Simulation time 189185450 ps
CPU time 0.77 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:11 PM PDT 24
Peak memory 206204 kb
Host smart-3a325a7b-2c9e-4afd-886d-f474b1108cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
20968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2945320968
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1380894355
Short name T188
Test name
Test status
Simulation time 162378154 ps
CPU time 0.84 seconds
Started Jul 04 06:15:08 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206192 kb
Host smart-5f84a7f3-f714-40a3-b198-c493aeae8c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13808
94355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1380894355
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3196197394
Short name T2284
Test name
Test status
Simulation time 230229590 ps
CPU time 0.96 seconds
Started Jul 04 06:15:08 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206228 kb
Host smart-43cd6392-4858-4f65-b23d-339fc1551a1b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3196197394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3196197394
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1687427832
Short name T459
Test name
Test status
Simulation time 194240865 ps
CPU time 0.84 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:11 PM PDT 24
Peak memory 206124 kb
Host smart-3b181dc0-9c06-4946-a34a-dd42181822aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16874
27832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1687427832
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.535852352
Short name T530
Test name
Test status
Simulation time 42719452 ps
CPU time 0.67 seconds
Started Jul 04 06:15:05 PM PDT 24
Finished Jul 04 06:15:06 PM PDT 24
Peak memory 206184 kb
Host smart-3a8846ad-a3b3-4f12-9db1-0ea89e403e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53585
2352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.535852352
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2067327592
Short name T1933
Test name
Test status
Simulation time 20847866866 ps
CPU time 45.42 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206504 kb
Host smart-9739c5b3-3e79-49d1-b4f4-8d2abc24ee5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20673
27592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2067327592
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1923504833
Short name T1788
Test name
Test status
Simulation time 157589538 ps
CPU time 0.77 seconds
Started Jul 04 06:15:19 PM PDT 24
Finished Jul 04 06:15:21 PM PDT 24
Peak memory 206120 kb
Host smart-e1d4749d-1ee8-4aeb-9243-9522570357e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
04833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1923504833
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4144508019
Short name T1164
Test name
Test status
Simulation time 305524802 ps
CPU time 1.07 seconds
Started Jul 04 06:15:08 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206172 kb
Host smart-eb619d00-078d-42ea-892a-30c74bbe5ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41445
08019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4144508019
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.1309502362
Short name T704
Test name
Test status
Simulation time 210665512 ps
CPU time 0.87 seconds
Started Jul 04 06:15:07 PM PDT 24
Finished Jul 04 06:15:08 PM PDT 24
Peak memory 206208 kb
Host smart-505bbc9a-4662-4509-b987-7dd02109e6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
02362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.1309502362
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3913357959
Short name T2697
Test name
Test status
Simulation time 189957497 ps
CPU time 0.91 seconds
Started Jul 04 06:15:19 PM PDT 24
Finished Jul 04 06:15:21 PM PDT 24
Peak memory 206104 kb
Host smart-e7adc64e-efdc-4593-9f67-fd7e69410e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39133
57959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3913357959
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.894474057
Short name T1001
Test name
Test status
Simulation time 176209880 ps
CPU time 0.79 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:11 PM PDT 24
Peak memory 206188 kb
Host smart-3cd68119-63ac-49c1-b27a-23c25b5d5ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89447
4057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.894474057
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2809514975
Short name T2001
Test name
Test status
Simulation time 162088661 ps
CPU time 0.81 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:11 PM PDT 24
Peak memory 206140 kb
Host smart-b964a008-9256-4370-b79c-f87df4797768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28095
14975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2809514975
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2674352139
Short name T970
Test name
Test status
Simulation time 196729273 ps
CPU time 0.86 seconds
Started Jul 04 06:15:09 PM PDT 24
Finished Jul 04 06:15:10 PM PDT 24
Peak memory 206188 kb
Host smart-c3735e29-641e-4daa-8822-6ceaae6b6b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
52139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2674352139
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3211365725
Short name T2244
Test name
Test status
Simulation time 256921945 ps
CPU time 0.99 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:11 PM PDT 24
Peak memory 206204 kb
Host smart-ea1b916f-e3be-4f80-a6f1-84ea214dc220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32113
65725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3211365725
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.684703987
Short name T1888
Test name
Test status
Simulation time 3239462683 ps
CPU time 30.43 seconds
Started Jul 04 06:15:07 PM PDT 24
Finished Jul 04 06:15:38 PM PDT 24
Peak memory 206560 kb
Host smart-03e11c64-43b7-423b-8dc5-67b6ddb4748a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=684703987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.684703987
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2976792517
Short name T394
Test name
Test status
Simulation time 141175443 ps
CPU time 0.76 seconds
Started Jul 04 06:15:06 PM PDT 24
Finished Jul 04 06:15:06 PM PDT 24
Peak memory 206172 kb
Host smart-63fb5411-b15e-4ef2-a13e-c42c369b5b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
92517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2976792517
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3506446563
Short name T641
Test name
Test status
Simulation time 187483475 ps
CPU time 0.89 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:11 PM PDT 24
Peak memory 206168 kb
Host smart-0a93c0db-5f54-4f66-bd1c-5eefce820b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35064
46563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3506446563
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1655306315
Short name T424
Test name
Test status
Simulation time 569774007 ps
CPU time 1.68 seconds
Started Jul 04 06:15:07 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206204 kb
Host smart-a3be9130-7667-40cc-8e7d-ce24ad675cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16553
06315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1655306315
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2479268921
Short name T1331
Test name
Test status
Simulation time 4363635458 ps
CPU time 41.9 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:53 PM PDT 24
Peak memory 206528 kb
Host smart-7d691864-a65e-4801-970f-0159a7c093cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24792
68921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2479268921
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1025793763
Short name T2388
Test name
Test status
Simulation time 36746560 ps
CPU time 0.66 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:22 PM PDT 24
Peak memory 206260 kb
Host smart-96d896c3-1954-40a4-95d0-a60482ed94e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1025793763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1025793763
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3873030607
Short name T1427
Test name
Test status
Simulation time 3567752601 ps
CPU time 4.58 seconds
Started Jul 04 06:15:19 PM PDT 24
Finished Jul 04 06:15:25 PM PDT 24
Peak memory 206444 kb
Host smart-7a127ee7-9109-4148-83bc-93817852c114
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3873030607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3873030607
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.4287252481
Short name T776
Test name
Test status
Simulation time 13346139386 ps
CPU time 16.79 seconds
Started Jul 04 06:15:08 PM PDT 24
Finished Jul 04 06:15:25 PM PDT 24
Peak memory 206268 kb
Host smart-2d4106fb-acdd-4c80-ac04-5f322f47648a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4287252481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.4287252481
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1935536001
Short name T2410
Test name
Test status
Simulation time 23343507380 ps
CPU time 24.97 seconds
Started Jul 04 06:15:19 PM PDT 24
Finished Jul 04 06:15:45 PM PDT 24
Peak memory 206196 kb
Host smart-85c5f7dd-4fe2-4a30-892d-a0940d0cf61f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1935536001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1935536001
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.595776849
Short name T764
Test name
Test status
Simulation time 174435970 ps
CPU time 0.85 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:12 PM PDT 24
Peak memory 206212 kb
Host smart-99594ee6-0711-4629-96bf-27e128547ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59577
6849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.595776849
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.947500349
Short name T1491
Test name
Test status
Simulation time 176412110 ps
CPU time 0.77 seconds
Started Jul 04 06:15:19 PM PDT 24
Finished Jul 04 06:15:20 PM PDT 24
Peak memory 206124 kb
Host smart-cce029af-b9f0-443d-932b-f8d9b97b8ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94750
0349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.947500349
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2451357027
Short name T1207
Test name
Test status
Simulation time 407270071 ps
CPU time 1.44 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:27 PM PDT 24
Peak memory 206120 kb
Host smart-e5057d9b-8398-40a2-b403-12452943ee84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
57027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2451357027
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.406376463
Short name T395
Test name
Test status
Simulation time 419793338 ps
CPU time 1.19 seconds
Started Jul 04 06:15:08 PM PDT 24
Finished Jul 04 06:15:09 PM PDT 24
Peak memory 206228 kb
Host smart-ace63993-3843-4bda-8728-10c8b813f50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
6463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.406376463
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1294330847
Short name T2430
Test name
Test status
Simulation time 14320004901 ps
CPU time 25.89 seconds
Started Jul 04 06:15:10 PM PDT 24
Finished Jul 04 06:15:36 PM PDT 24
Peak memory 206536 kb
Host smart-7d97625a-72c7-4831-ae60-f104d110dc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12943
30847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1294330847
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1284145074
Short name T2507
Test name
Test status
Simulation time 396673718 ps
CPU time 1.25 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206216 kb
Host smart-616e0b8c-edbc-43e4-bb2d-1be3d7868b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
45074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1284145074
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2579768599
Short name T709
Test name
Test status
Simulation time 136911676 ps
CPU time 0.78 seconds
Started Jul 04 06:15:13 PM PDT 24
Finished Jul 04 06:15:14 PM PDT 24
Peak memory 206220 kb
Host smart-559b7da2-9873-4ae5-805e-9f2c2c968be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25797
68599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2579768599
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3647262945
Short name T1762
Test name
Test status
Simulation time 45201788 ps
CPU time 0.67 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:15 PM PDT 24
Peak memory 206176 kb
Host smart-825bb33d-caa9-455a-ac6a-58d66222efb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36472
62945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3647262945
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3074378653
Short name T1189
Test name
Test status
Simulation time 832762616 ps
CPU time 2.14 seconds
Started Jul 04 06:15:12 PM PDT 24
Finished Jul 04 06:15:15 PM PDT 24
Peak memory 206420 kb
Host smart-660e8730-fecb-4ab7-b9ab-79092560b399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743
78653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3074378653
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3682195200
Short name T1505
Test name
Test status
Simulation time 372252469 ps
CPU time 2.22 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:17 PM PDT 24
Peak memory 206320 kb
Host smart-fa0e5165-c888-4514-98ec-6c2f78879d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
95200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3682195200
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.316052916
Short name T1411
Test name
Test status
Simulation time 227227605 ps
CPU time 0.87 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206204 kb
Host smart-2b17c5aa-624c-4fe3-adad-a915d2501a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.316052916
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3959062302
Short name T1340
Test name
Test status
Simulation time 139143850 ps
CPU time 0.74 seconds
Started Jul 04 06:15:16 PM PDT 24
Finished Jul 04 06:15:17 PM PDT 24
Peak memory 206196 kb
Host smart-08c96367-4c92-4b9e-870d-58c2b1acf737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39590
62302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3959062302
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2599621758
Short name T771
Test name
Test status
Simulation time 287761798 ps
CPU time 1.02 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206144 kb
Host smart-c85e89ef-d3b5-468b-b1c2-c32281d23a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25996
21758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2599621758
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.1929906271
Short name T744
Test name
Test status
Simulation time 6624108999 ps
CPU time 65.83 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206492 kb
Host smart-2d89ab0b-c974-424f-84f0-d4cc83520f72
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1929906271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1929906271
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.985099682
Short name T903
Test name
Test status
Simulation time 195785736 ps
CPU time 0.85 seconds
Started Jul 04 06:15:16 PM PDT 24
Finished Jul 04 06:15:17 PM PDT 24
Peak memory 206196 kb
Host smart-4c028330-4f21-440c-9930-90d4562c840a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98509
9682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.985099682
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3407555883
Short name T2122
Test name
Test status
Simulation time 23319278402 ps
CPU time 22.85 seconds
Started Jul 04 06:15:16 PM PDT 24
Finished Jul 04 06:15:39 PM PDT 24
Peak memory 206260 kb
Host smart-f20221de-8222-403c-98e7-a56ed1734005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075
55883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3407555883
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2972164112
Short name T1961
Test name
Test status
Simulation time 3274745022 ps
CPU time 3.6 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206188 kb
Host smart-df6cde0c-e2ac-4918-991c-c1cda2e7acd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29721
64112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2972164112
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1186505457
Short name T1392
Test name
Test status
Simulation time 7843310236 ps
CPU time 56.3 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206460 kb
Host smart-e9252739-9c6d-4b80-8573-ded04c2bdf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
05457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1186505457
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3277691027
Short name T1407
Test name
Test status
Simulation time 5913375992 ps
CPU time 54.48 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206472 kb
Host smart-16c2861c-8aca-4e4a-968b-d0b96f5e1b1f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3277691027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3277691027
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.840320199
Short name T1905
Test name
Test status
Simulation time 241887728 ps
CPU time 0.88 seconds
Started Jul 04 06:15:13 PM PDT 24
Finished Jul 04 06:15:14 PM PDT 24
Peak memory 206204 kb
Host smart-648b88c8-9f5e-40a9-9338-da0e62533808
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=840320199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.840320199
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2489424861
Short name T1583
Test name
Test status
Simulation time 189752537 ps
CPU time 0.92 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:15 PM PDT 24
Peak memory 206192 kb
Host smart-0b4c8973-ef15-48bc-90ab-fae841c2091c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24894
24861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2489424861
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3254684465
Short name T2279
Test name
Test status
Simulation time 4790762383 ps
CPU time 134.26 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 206424 kb
Host smart-76e32c63-d2ee-46b1-8614-e8482be6a6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546
84465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3254684465
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.799733827
Short name T506
Test name
Test status
Simulation time 8050228870 ps
CPU time 232.32 seconds
Started Jul 04 06:15:17 PM PDT 24
Finished Jul 04 06:19:09 PM PDT 24
Peak memory 206480 kb
Host smart-82fbbf2a-d34c-4544-b35c-e883d5f0c9f7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=799733827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.799733827
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3672043362
Short name T268
Test name
Test status
Simulation time 151259813 ps
CPU time 0.8 seconds
Started Jul 04 06:15:17 PM PDT 24
Finished Jul 04 06:15:18 PM PDT 24
Peak memory 206212 kb
Host smart-f756c8ca-f60a-4547-889e-fdcf544b5b3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3672043362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3672043362
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1958342094
Short name T2079
Test name
Test status
Simulation time 153864340 ps
CPU time 0.79 seconds
Started Jul 04 06:15:13 PM PDT 24
Finished Jul 04 06:15:14 PM PDT 24
Peak memory 206184 kb
Host smart-abd7dc3a-86f3-421c-8206-aad184932957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
42094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1958342094
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1352541085
Short name T1722
Test name
Test status
Simulation time 216006651 ps
CPU time 0.82 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:27 PM PDT 24
Peak memory 206128 kb
Host smart-f055863a-ecc0-47ce-9bdd-ffc0ce1d2509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13525
41085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1352541085
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1394183876
Short name T2061
Test name
Test status
Simulation time 219310201 ps
CPU time 0.87 seconds
Started Jul 04 06:15:16 PM PDT 24
Finished Jul 04 06:15:18 PM PDT 24
Peak memory 206124 kb
Host smart-b35900c8-2474-4c38-9c02-270555dd1d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13941
83876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1394183876
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2318116766
Short name T1744
Test name
Test status
Simulation time 209982012 ps
CPU time 0.85 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206208 kb
Host smart-31495c7d-8fca-4b37-b39a-f191be1e2f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
16766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2318116766
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.923391911
Short name T1466
Test name
Test status
Simulation time 173500980 ps
CPU time 0.81 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206212 kb
Host smart-b17048f8-5185-40df-b201-c78b3ee31381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92339
1911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.923391911
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1226711441
Short name T1909
Test name
Test status
Simulation time 145295099 ps
CPU time 0.78 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206192 kb
Host smart-f75c9df1-2091-4b4e-9559-23c209677183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12267
11441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1226711441
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1544357342
Short name T2046
Test name
Test status
Simulation time 221954650 ps
CPU time 0.95 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206184 kb
Host smart-ce1a2414-e9d6-4839-8c3d-f05356af956a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1544357342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1544357342
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3710640127
Short name T594
Test name
Test status
Simulation time 158285951 ps
CPU time 0.77 seconds
Started Jul 04 06:15:15 PM PDT 24
Finished Jul 04 06:15:16 PM PDT 24
Peak memory 206204 kb
Host smart-aea96e5f-8e54-4f9f-9787-2497785b02bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37106
40127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3710640127
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2810870458
Short name T1192
Test name
Test status
Simulation time 16179091873 ps
CPU time 40.43 seconds
Started Jul 04 06:15:18 PM PDT 24
Finished Jul 04 06:15:59 PM PDT 24
Peak memory 206472 kb
Host smart-93e7de74-f2eb-4f43-ba0e-88ddcdcd0acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28108
70458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2810870458
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2446139079
Short name T2433
Test name
Test status
Simulation time 179149232 ps
CPU time 0.85 seconds
Started Jul 04 06:15:17 PM PDT 24
Finished Jul 04 06:15:18 PM PDT 24
Peak memory 206208 kb
Host smart-1506c5de-a9e4-4dfb-b371-99ca97342472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24461
39079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2446139079
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3449890621
Short name T2160
Test name
Test status
Simulation time 285791306 ps
CPU time 0.91 seconds
Started Jul 04 06:15:14 PM PDT 24
Finished Jul 04 06:15:15 PM PDT 24
Peak memory 206204 kb
Host smart-2cd0a135-9c88-4d10-aad2-ee2469734097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34498
90621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3449890621
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2930333880
Short name T1502
Test name
Test status
Simulation time 158882191 ps
CPU time 0.81 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206168 kb
Host smart-33f32970-51d8-4594-9659-3378689a4086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29303
33880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2930333880
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2132887431
Short name T633
Test name
Test status
Simulation time 196307160 ps
CPU time 0.87 seconds
Started Jul 04 06:15:22 PM PDT 24
Finished Jul 04 06:15:23 PM PDT 24
Peak memory 206212 kb
Host smart-cd1a889c-3aaa-4967-9b30-7630f1a7ed57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21328
87431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2132887431
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2832618751
Short name T1998
Test name
Test status
Simulation time 145877655 ps
CPU time 0.76 seconds
Started Jul 04 06:15:23 PM PDT 24
Finished Jul 04 06:15:24 PM PDT 24
Peak memory 206200 kb
Host smart-49a84e08-e1e4-4deb-8ad6-4111314c2953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
18751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2832618751
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3124174676
Short name T597
Test name
Test status
Simulation time 147167645 ps
CPU time 0.74 seconds
Started Jul 04 06:15:22 PM PDT 24
Finished Jul 04 06:15:23 PM PDT 24
Peak memory 206136 kb
Host smart-91e0fc09-bbe9-453a-8213-6d613ece15f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241
74676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3124174676
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2335830630
Short name T1484
Test name
Test status
Simulation time 194571276 ps
CPU time 0.79 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:27 PM PDT 24
Peak memory 206192 kb
Host smart-7edbd049-c13b-49c0-a0e1-43b53bb5d6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
30630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2335830630
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2819062813
Short name T2135
Test name
Test status
Simulation time 231532731 ps
CPU time 0.98 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:22 PM PDT 24
Peak memory 206200 kb
Host smart-8bfe6672-c482-4f50-8a5d-54a4dcd81f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
62813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2819062813
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.69191827
Short name T1876
Test name
Test status
Simulation time 4773632168 ps
CPU time 45.09 seconds
Started Jul 04 06:15:25 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206472 kb
Host smart-cb690c1e-e77d-428d-9e3c-7d4f227cceaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=69191827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.69191827
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1789214083
Short name T1957
Test name
Test status
Simulation time 148934925 ps
CPU time 0.78 seconds
Started Jul 04 06:15:22 PM PDT 24
Finished Jul 04 06:15:23 PM PDT 24
Peak memory 206204 kb
Host smart-cbe42654-f6b2-46ea-86aa-e6d4f962e549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17892
14083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1789214083
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.393831705
Short name T351
Test name
Test status
Simulation time 165990894 ps
CPU time 0.8 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:22 PM PDT 24
Peak memory 206168 kb
Host smart-f43de60e-56ee-411b-83e6-00a71fd07f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39383
1705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.393831705
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3426310136
Short name T2325
Test name
Test status
Simulation time 1038316982 ps
CPU time 2.24 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206404 kb
Host smart-7c197430-a39a-4fd5-97e4-c23ff0523579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263
10136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3426310136
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3747105931
Short name T2281
Test name
Test status
Simulation time 5219733152 ps
CPU time 51.85 seconds
Started Jul 04 06:15:22 PM PDT 24
Finished Jul 04 06:16:14 PM PDT 24
Peak memory 206520 kb
Host smart-af372f6c-2281-456c-a55d-e40379a48134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37471
05931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3747105931
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.309197564
Short name T2424
Test name
Test status
Simulation time 30754169 ps
CPU time 0.64 seconds
Started Jul 04 06:15:30 PM PDT 24
Finished Jul 04 06:15:31 PM PDT 24
Peak memory 206160 kb
Host smart-17b78c59-fe7a-4e4a-8171-368b47f167a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=309197564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.309197564
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.4131761190
Short name T747
Test name
Test status
Simulation time 4162758209 ps
CPU time 4.73 seconds
Started Jul 04 06:15:25 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206484 kb
Host smart-72c5e9f9-f032-4f92-83d6-ce75ce70e4ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4131761190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.4131761190
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2713340544
Short name T8
Test name
Test status
Simulation time 13435957551 ps
CPU time 12.61 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:39 PM PDT 24
Peak memory 206436 kb
Host smart-858c71f7-f3ce-4027-b407-46c281c3309c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2713340544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2713340544
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2848904273
Short name T1506
Test name
Test status
Simulation time 23323027053 ps
CPU time 21.58 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206372 kb
Host smart-026ee431-0770-49d0-b9be-a9e0a6e89a1b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2848904273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2848904273
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.986707825
Short name T2024
Test name
Test status
Simulation time 149891793 ps
CPU time 0.77 seconds
Started Jul 04 06:15:23 PM PDT 24
Finished Jul 04 06:15:24 PM PDT 24
Peak memory 206208 kb
Host smart-331e12b1-5264-4e01-b7f3-69fbf64bd87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98670
7825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.986707825
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2571288979
Short name T2534
Test name
Test status
Simulation time 160832182 ps
CPU time 0.77 seconds
Started Jul 04 06:15:20 PM PDT 24
Finished Jul 04 06:15:22 PM PDT 24
Peak memory 206204 kb
Host smart-81cb451d-fc80-4f93-af31-53748daea53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25712
88979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2571288979
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1885468074
Short name T2459
Test name
Test status
Simulation time 448625690 ps
CPU time 1.35 seconds
Started Jul 04 06:15:24 PM PDT 24
Finished Jul 04 06:15:26 PM PDT 24
Peak memory 206412 kb
Host smart-8731bb01-a8ce-4578-944b-4e03aefb3ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18854
68074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1885468074
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3342748010
Short name T2076
Test name
Test status
Simulation time 6494392019 ps
CPU time 11.86 seconds
Started Jul 04 06:15:22 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206436 kb
Host smart-b04850bd-9153-455f-96f3-40a6a796d207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33427
48010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3342748010
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.4043957313
Short name T898
Test name
Test status
Simulation time 392196769 ps
CPU time 1.14 seconds
Started Jul 04 06:15:23 PM PDT 24
Finished Jul 04 06:15:25 PM PDT 24
Peak memory 206180 kb
Host smart-2cfa3253-ce3b-4211-816f-b8c7909f8de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
57313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.4043957313
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2009713662
Short name T1981
Test name
Test status
Simulation time 166136691 ps
CPU time 0.76 seconds
Started Jul 04 06:15:20 PM PDT 24
Finished Jul 04 06:15:21 PM PDT 24
Peak memory 206208 kb
Host smart-ed293b70-b43e-44e2-a6a4-c34154105f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097
13662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2009713662
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2290117503
Short name T1508
Test name
Test status
Simulation time 66524068 ps
CPU time 0.68 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:22 PM PDT 24
Peak memory 206176 kb
Host smart-7189c21d-2500-4739-a3a1-237eb9d85a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22901
17503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2290117503
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3636678970
Short name T2434
Test name
Test status
Simulation time 824852513 ps
CPU time 1.98 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206332 kb
Host smart-197976be-523f-4f67-a0fd-6c63fc30a7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
78970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3636678970
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.967025506
Short name T985
Test name
Test status
Simulation time 316030135 ps
CPU time 1.9 seconds
Started Jul 04 06:15:22 PM PDT 24
Finished Jul 04 06:15:25 PM PDT 24
Peak memory 206440 kb
Host smart-6f62e643-ce96-4911-bfd8-36c84e84bec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96702
5506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.967025506
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.758112450
Short name T1995
Test name
Test status
Simulation time 223891799 ps
CPU time 0.88 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206156 kb
Host smart-3683bd12-f56e-4991-81e9-948826dd1c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75811
2450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.758112450
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3596185844
Short name T535
Test name
Test status
Simulation time 161652337 ps
CPU time 0.77 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206152 kb
Host smart-d653429c-5e82-4344-a8db-820f033e41b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
85844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3596185844
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3327073432
Short name T1341
Test name
Test status
Simulation time 174117056 ps
CPU time 0.84 seconds
Started Jul 04 06:15:21 PM PDT 24
Finished Jul 04 06:15:22 PM PDT 24
Peak memory 206176 kb
Host smart-f53b8f77-5254-4b87-bc6d-20301270805d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
73432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3327073432
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1959812570
Short name T1078
Test name
Test status
Simulation time 238946697 ps
CPU time 0.87 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:27 PM PDT 24
Peak memory 206184 kb
Host smart-edafa67e-d3d9-48af-b6a3-2bb7aa6d5be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
12570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1959812570
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1394218512
Short name T2069
Test name
Test status
Simulation time 23369294743 ps
CPU time 25.86 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:52 PM PDT 24
Peak memory 206236 kb
Host smart-bb532b5d-17ed-4fe7-914b-39d0d71ad49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13942
18512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1394218512
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3028019349
Short name T1124
Test name
Test status
Simulation time 3296213214 ps
CPU time 3.75 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:31 PM PDT 24
Peak memory 206280 kb
Host smart-a4e1692a-2954-4073-a4e5-5a936b4480b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30280
19349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3028019349
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.103702845
Short name T602
Test name
Test status
Simulation time 6337668155 ps
CPU time 171.4 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:18:21 PM PDT 24
Peak memory 206476 kb
Host smart-2266648f-6744-484e-be89-a5202b3976fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
2845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.103702845
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1311493683
Short name T2153
Test name
Test status
Simulation time 5409207732 ps
CPU time 45.74 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:16:15 PM PDT 24
Peak memory 206464 kb
Host smart-41a89d93-bd29-400f-a638-9de1dd526e9a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1311493683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1311493683
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1087086517
Short name T1234
Test name
Test status
Simulation time 274129141 ps
CPU time 0.97 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206128 kb
Host smart-da83e3fb-efc0-4666-b1d4-3931d3169667
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1087086517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1087086517
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4221157127
Short name T2204
Test name
Test status
Simulation time 218570616 ps
CPU time 0.92 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206180 kb
Host smart-48984865-59c3-45f0-8efe-2bae7b51a901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42211
57127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4221157127
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.2284110234
Short name T6
Test name
Test status
Simulation time 6048275605 ps
CPU time 54.6 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:16:24 PM PDT 24
Peak memory 206412 kb
Host smart-3f74e41b-a5f1-45f7-9f19-102ae7e4b031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22841
10234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.2284110234
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.2016354293
Short name T2389
Test name
Test status
Simulation time 5163746789 ps
CPU time 141.75 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 206512 kb
Host smart-32301e4f-7310-474a-9fb2-f3b9ceaf83ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2016354293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.2016354293
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2697206898
Short name T25
Test name
Test status
Simulation time 154100648 ps
CPU time 0.78 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206176 kb
Host smart-b8e9d051-0aeb-45eb-8005-00d6dd2a88bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2697206898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2697206898
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2061684152
Short name T2312
Test name
Test status
Simulation time 184020147 ps
CPU time 0.82 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206148 kb
Host smart-e014ff86-e36e-4dc2-a9aa-0352b117179d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616
84152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2061684152
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2870848703
Short name T2121
Test name
Test status
Simulation time 216836376 ps
CPU time 0.87 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206108 kb
Host smart-ce2176d0-6ed3-4564-ace6-f7728d5976ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28708
48703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2870848703
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.117415350
Short name T2237
Test name
Test status
Simulation time 210710255 ps
CPU time 0.88 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206132 kb
Host smart-1b558025-dcf5-4b68-a2d1-510be616dc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
5350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.117415350
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.476615115
Short name T1233
Test name
Test status
Simulation time 147332715 ps
CPU time 0.75 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206192 kb
Host smart-b5233917-8da4-49f2-ae08-3db2d074f828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47661
5115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.476615115
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2096587813
Short name T863
Test name
Test status
Simulation time 194910670 ps
CPU time 0.83 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206120 kb
Host smart-a6259c42-0749-4232-af0a-16fdba2b662c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965
87813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2096587813
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.779763752
Short name T177
Test name
Test status
Simulation time 186522275 ps
CPU time 0.85 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206108 kb
Host smart-e8492d30-f947-4029-b34e-4ac246bf02b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77976
3752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.779763752
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.4227299566
Short name T1642
Test name
Test status
Simulation time 200684568 ps
CPU time 0.91 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206172 kb
Host smart-10673d27-8dd5-4bb0-9c07-d4c6273a546b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4227299566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.4227299566
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3474434106
Short name T2402
Test name
Test status
Simulation time 158094171 ps
CPU time 0.84 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206060 kb
Host smart-581dbec8-1bae-41c2-8ed0-8783e0f11942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34744
34106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3474434106
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.864399679
Short name T2347
Test name
Test status
Simulation time 110534065 ps
CPU time 0.7 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206188 kb
Host smart-83ef8da1-f4d0-48a0-b21a-378ee55e2714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86439
9679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.864399679
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3029966403
Short name T2458
Test name
Test status
Simulation time 6223985411 ps
CPU time 14.74 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206436 kb
Host smart-d0682d40-1573-4e4b-8c08-99257eb860fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
66403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3029966403
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3536539849
Short name T1883
Test name
Test status
Simulation time 196178851 ps
CPU time 0.93 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206204 kb
Host smart-f114dd1b-9d65-44b8-86df-f290727d43cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
39849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3536539849
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3172220598
Short name T986
Test name
Test status
Simulation time 231311877 ps
CPU time 0.91 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206192 kb
Host smart-bf3094bb-1ef6-44dd-9e91-aa94fea3c4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31722
20598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3172220598
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3177527344
Short name T2567
Test name
Test status
Simulation time 221535739 ps
CPU time 0.96 seconds
Started Jul 04 06:15:29 PM PDT 24
Finished Jul 04 06:15:31 PM PDT 24
Peak memory 206148 kb
Host smart-627aa85c-16e3-43b6-a206-299bb20c3ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31775
27344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3177527344
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.684863240
Short name T467
Test name
Test status
Simulation time 163169104 ps
CPU time 0.82 seconds
Started Jul 04 06:15:26 PM PDT 24
Finished Jul 04 06:15:27 PM PDT 24
Peak memory 206192 kb
Host smart-f38629ca-9146-40a8-9c21-c6a2ca9bc6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68486
3240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.684863240
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3913853301
Short name T2112
Test name
Test status
Simulation time 166081157 ps
CPU time 0.75 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206204 kb
Host smart-765b761e-4fac-4b07-9e44-a57a477bdd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
53301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3913853301
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2682650126
Short name T2486
Test name
Test status
Simulation time 162917962 ps
CPU time 0.78 seconds
Started Jul 04 06:15:30 PM PDT 24
Finished Jul 04 06:15:31 PM PDT 24
Peak memory 206140 kb
Host smart-99d00a4d-3000-491e-837e-1ab2d1cbb030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826
50126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2682650126
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1876573505
Short name T1551
Test name
Test status
Simulation time 155424832 ps
CPU time 0.79 seconds
Started Jul 04 06:15:25 PM PDT 24
Finished Jul 04 06:15:26 PM PDT 24
Peak memory 206108 kb
Host smart-dd070e14-fd25-41c7-a183-28ba9d7ce32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18765
73505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1876573505
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1576607387
Short name T1063
Test name
Test status
Simulation time 216900052 ps
CPU time 0.92 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206172 kb
Host smart-c6c5e4b0-6297-4a42-871c-0a2bf63dddbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15766
07387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1576607387
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2109347610
Short name T358
Test name
Test status
Simulation time 3454755140 ps
CPU time 94.24 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:17:02 PM PDT 24
Peak memory 206564 kb
Host smart-fb1484a5-a283-4ebe-8613-024397da3d06
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2109347610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2109347610
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.169217929
Short name T607
Test name
Test status
Simulation time 175400160 ps
CPU time 0.79 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:15:30 PM PDT 24
Peak memory 206184 kb
Host smart-3ba1984b-a105-4a91-abe1-1024440d63fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16921
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.169217929
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2116841809
Short name T576
Test name
Test status
Simulation time 163804448 ps
CPU time 0.78 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206180 kb
Host smart-1ee6704c-feb7-46a7-9522-6b67af013a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21168
41809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2116841809
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.3302848888
Short name T678
Test name
Test status
Simulation time 1428456146 ps
CPU time 2.89 seconds
Started Jul 04 06:15:25 PM PDT 24
Finished Jul 04 06:15:28 PM PDT 24
Peak memory 206436 kb
Host smart-68f0f1d9-f8da-4949-bd22-761c8895458a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33028
48888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3302848888
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1203357717
Short name T1813
Test name
Test status
Simulation time 5606836268 ps
CPU time 42.65 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206392 kb
Host smart-64e33a34-407a-4ca0-83d3-7fdc22450a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12033
57717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1203357717
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1584869553
Short name T1381
Test name
Test status
Simulation time 72744442 ps
CPU time 0.67 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206256 kb
Host smart-fd20103e-9006-4279-89ec-d819c84480f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1584869553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1584869553
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1952832607
Short name T1347
Test name
Test status
Simulation time 3985424261 ps
CPU time 4.69 seconds
Started Jul 04 06:15:28 PM PDT 24
Finished Jul 04 06:15:33 PM PDT 24
Peak memory 206420 kb
Host smart-1cb12ab3-4ba4-40af-adb6-e10d433de438
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1952832607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1952832607
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3621155798
Short name T2675
Test name
Test status
Simulation time 13352041457 ps
CPU time 12.54 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206272 kb
Host smart-1fe7e740-575f-4406-b504-896c49622a63
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3621155798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3621155798
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.324154899
Short name T1421
Test name
Test status
Simulation time 23398590822 ps
CPU time 25.64 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:53 PM PDT 24
Peak memory 206268 kb
Host smart-45e47182-f0e8-4214-b735-17109cdb12a7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=324154899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.324154899
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.750242864
Short name T1540
Test name
Test status
Simulation time 154082989 ps
CPU time 0.81 seconds
Started Jul 04 06:15:27 PM PDT 24
Finished Jul 04 06:15:29 PM PDT 24
Peak memory 206092 kb
Host smart-2899694e-8b64-4b6e-9e61-01d6b98e1bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75024
2864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.750242864
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.456642396
Short name T883
Test name
Test status
Simulation time 159110335 ps
CPU time 0.8 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:35 PM PDT 24
Peak memory 206164 kb
Host smart-203521ea-7830-4662-974f-8d455ab613fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45664
2396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.456642396
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3052185686
Short name T802
Test name
Test status
Simulation time 487428867 ps
CPU time 1.55 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:36 PM PDT 24
Peak memory 206412 kb
Host smart-349516af-18f7-448a-94af-2be56c0f53ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30521
85686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3052185686
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2959186534
Short name T1862
Test name
Test status
Simulation time 531639724 ps
CPU time 1.53 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:35 PM PDT 24
Peak memory 206212 kb
Host smart-bfc03618-2acc-4406-9f31-d0dc24825594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29591
86534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2959186534
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.4170339579
Short name T1320
Test name
Test status
Simulation time 8119208971 ps
CPU time 15.61 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:15:52 PM PDT 24
Peak memory 206488 kb
Host smart-30883fb4-5200-428d-afbd-d0cdb4c50c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41703
39579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.4170339579
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3884789696
Short name T920
Test name
Test status
Simulation time 421660369 ps
CPU time 1.25 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:35 PM PDT 24
Peak memory 206192 kb
Host smart-c887a36e-c081-41a4-8b6f-5f3f596bc36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38847
89696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3884789696
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.77560448
Short name T1674
Test name
Test status
Simulation time 142050090 ps
CPU time 0.75 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206208 kb
Host smart-bdf6b608-0db3-497a-bae4-a37235495693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77560
448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.77560448
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2240828001
Short name T1372
Test name
Test status
Simulation time 38153842 ps
CPU time 0.67 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206156 kb
Host smart-4f22ffde-1676-4704-a83d-0787f4b9842c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
28001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2240828001
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3620971353
Short name T1426
Test name
Test status
Simulation time 852679721 ps
CPU time 2.05 seconds
Started Jul 04 06:15:38 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206360 kb
Host smart-c18941e0-1734-482d-8527-381d81c11e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36209
71353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3620971353
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1971331767
Short name T463
Test name
Test status
Simulation time 254638842 ps
CPU time 2.22 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:15:38 PM PDT 24
Peak memory 206400 kb
Host smart-40f698b3-9484-4967-a1fa-718266116dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19713
31767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1971331767
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.838303103
Short name T352
Test name
Test status
Simulation time 198627266 ps
CPU time 0.86 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:35 PM PDT 24
Peak memory 206204 kb
Host smart-6b8a085f-0cb3-4458-9b2c-c2647d3857bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83830
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.838303103
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1289803398
Short name T1975
Test name
Test status
Simulation time 178069508 ps
CPU time 0.76 seconds
Started Jul 04 06:15:35 PM PDT 24
Finished Jul 04 06:15:36 PM PDT 24
Peak memory 206196 kb
Host smart-e55828ea-88e2-4f9d-b16c-d93fe97cd9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
03398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1289803398
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3115772685
Short name T1931
Test name
Test status
Simulation time 199978643 ps
CPU time 0.86 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206108 kb
Host smart-1d4628e7-90d3-4ac6-9234-4cef238f80e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31157
72685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3115772685
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2902337085
Short name T2162
Test name
Test status
Simulation time 7256318115 ps
CPU time 70.19 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:16:44 PM PDT 24
Peak memory 206476 kb
Host smart-1f188ab8-7d9c-4acc-b12b-8c0eb141df65
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2902337085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2902337085
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2064731820
Short name T518
Test name
Test status
Simulation time 205794217 ps
CPU time 0.92 seconds
Started Jul 04 06:15:38 PM PDT 24
Finished Jul 04 06:15:39 PM PDT 24
Peak memory 206172 kb
Host smart-be7aeeb4-0ad9-4bf9-9354-c74f76faba4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
31820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2064731820
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.4241204527
Short name T2340
Test name
Test status
Simulation time 23309612336 ps
CPU time 24.91 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206188 kb
Host smart-6c8bcf2d-fc88-4322-b518-a8389846f663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
04527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.4241204527
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.685907323
Short name T399
Test name
Test status
Simulation time 3297493582 ps
CPU time 4.06 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206256 kb
Host smart-9ea2b54e-24e8-45ad-9d14-b84e966d81b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68590
7323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.685907323
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.596205960
Short name T2656
Test name
Test status
Simulation time 6726343932 ps
CPU time 65.29 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:16:40 PM PDT 24
Peak memory 206524 kb
Host smart-f808d337-9364-40af-962f-f18064e51989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59620
5960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.596205960
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3779986702
Short name T1555
Test name
Test status
Simulation time 6595359921 ps
CPU time 182.6 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:18:37 PM PDT 24
Peak memory 206464 kb
Host smart-efdf7639-a334-4726-8f94-99f095c165c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3779986702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3779986702
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3397258125
Short name T1644
Test name
Test status
Simulation time 240372959 ps
CPU time 0.93 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206172 kb
Host smart-a3ba87a9-f339-41e5-87e8-8bf48b6493a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3397258125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3397258125
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1225072587
Short name T1321
Test name
Test status
Simulation time 186346500 ps
CPU time 0.88 seconds
Started Jul 04 06:15:35 PM PDT 24
Finished Jul 04 06:15:36 PM PDT 24
Peak memory 206160 kb
Host smart-8abf8c0a-c04d-4093-84de-4ea932127527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12250
72587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1225072587
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.1429878946
Short name T2631
Test name
Test status
Simulation time 4212802640 ps
CPU time 115.63 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:17:39 PM PDT 24
Peak memory 206448 kb
Host smart-03158a54-bbb2-4849-a29a-3f0a13c13e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14298
78946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.1429878946
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.489858026
Short name T2694
Test name
Test status
Simulation time 3763134540 ps
CPU time 98.91 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:17:12 PM PDT 24
Peak memory 206420 kb
Host smart-d0e4e4a4-75f4-46b7-8cfd-203408a6433b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=489858026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.489858026
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3533931888
Short name T1008
Test name
Test status
Simulation time 206254331 ps
CPU time 0.82 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206180 kb
Host smart-9d5f9f42-e270-4d74-bd38-e5532e40c30b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3533931888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3533931888
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2309587774
Short name T990
Test name
Test status
Simulation time 140614054 ps
CPU time 0.73 seconds
Started Jul 04 06:15:32 PM PDT 24
Finished Jul 04 06:15:33 PM PDT 24
Peak memory 206156 kb
Host smart-f6aee5fe-1fd4-4af3-89e3-efad59fcdece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23095
87774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2309587774
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1846011176
Short name T2355
Test name
Test status
Simulation time 187099704 ps
CPU time 0.79 seconds
Started Jul 04 06:15:38 PM PDT 24
Finished Jul 04 06:15:38 PM PDT 24
Peak memory 206164 kb
Host smart-3eadb6a2-1307-4369-b0d6-397a07c3dc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18460
11176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1846011176
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1880995733
Short name T1185
Test name
Test status
Simulation time 159695974 ps
CPU time 0.8 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:15:40 PM PDT 24
Peak memory 206172 kb
Host smart-10ae6fb5-15e1-46a2-b745-0d45eb4a4486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18809
95733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1880995733
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2281745515
Short name T365
Test name
Test status
Simulation time 183795912 ps
CPU time 0.85 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206208 kb
Host smart-68cc85e3-13de-4037-810a-0ae90b403f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22817
45515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2281745515
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.858026748
Short name T1969
Test name
Test status
Simulation time 171487568 ps
CPU time 0.79 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206220 kb
Host smart-d7526268-7364-472b-be69-89484255c844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85802
6748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.858026748
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.306862244
Short name T842
Test name
Test status
Simulation time 146716613 ps
CPU time 0.79 seconds
Started Jul 04 06:15:38 PM PDT 24
Finished Jul 04 06:15:39 PM PDT 24
Peak memory 206152 kb
Host smart-42e49c62-93b4-471f-a6f6-dd221e5db695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
2244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.306862244
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.4126525096
Short name T427
Test name
Test status
Simulation time 212564922 ps
CPU time 0.93 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:35 PM PDT 24
Peak memory 206180 kb
Host smart-dd2a47b9-e4ae-4aee-86be-e682cf94e03e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4126525096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.4126525096
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.266494574
Short name T211
Test name
Test status
Simulation time 141362947 ps
CPU time 0.8 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:36 PM PDT 24
Peak memory 206180 kb
Host smart-9dd8dce4-5e3d-44a1-9bc4-53e13ffdc06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26649
4574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.266494574
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.426469224
Short name T1915
Test name
Test status
Simulation time 40102128 ps
CPU time 0.73 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206200 kb
Host smart-90812b89-71d8-407b-9795-40810f341493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
9224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.426469224
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3935353336
Short name T2317
Test name
Test status
Simulation time 6858232085 ps
CPU time 16.51 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:16:00 PM PDT 24
Peak memory 206548 kb
Host smart-0ef75adc-786f-429f-8a20-6dcc94690d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
53336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3935353336
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.911641548
Short name T1266
Test name
Test status
Simulation time 192117647 ps
CPU time 0.87 seconds
Started Jul 04 06:15:38 PM PDT 24
Finished Jul 04 06:15:39 PM PDT 24
Peak memory 206168 kb
Host smart-ff3ae3e0-6575-4651-8706-17ba491784b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91164
1548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.911641548
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1268176588
Short name T2464
Test name
Test status
Simulation time 230229562 ps
CPU time 0.88 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206188 kb
Host smart-d8721d50-c60e-45c4-b975-415244ea9fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12681
76588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1268176588
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.88744524
Short name T1378
Test name
Test status
Simulation time 169798415 ps
CPU time 0.84 seconds
Started Jul 04 06:15:34 PM PDT 24
Finished Jul 04 06:15:35 PM PDT 24
Peak memory 206236 kb
Host smart-24dfff21-d9b5-4515-af89-f21b5d5bc0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88744
524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.88744524
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3692457836
Short name T410
Test name
Test status
Simulation time 194389916 ps
CPU time 0.86 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206160 kb
Host smart-326fcd2d-01c0-44d5-a09b-4abc40ba73aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924
57836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3692457836
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2277150584
Short name T2089
Test name
Test status
Simulation time 162874399 ps
CPU time 0.81 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206184 kb
Host smart-f1ed7ab8-1ee9-4eeb-b0b7-c6dcb80eaee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22771
50584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2277150584
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2820040427
Short name T2650
Test name
Test status
Simulation time 149531236 ps
CPU time 0.79 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:15:40 PM PDT 24
Peak memory 206168 kb
Host smart-970e13af-d076-4204-b0e9-1479208159fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
40427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2820040427
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1331168030
Short name T1856
Test name
Test status
Simulation time 149744102 ps
CPU time 0.83 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:15:37 PM PDT 24
Peak memory 206208 kb
Host smart-3378210c-b755-4019-9456-3b9fbcdbb64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
68030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1331168030
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3765693078
Short name T1632
Test name
Test status
Simulation time 198647937 ps
CPU time 0.9 seconds
Started Jul 04 06:15:35 PM PDT 24
Finished Jul 04 06:15:36 PM PDT 24
Peak memory 206212 kb
Host smart-53ae199f-1418-4549-8a2d-3493e74399ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37656
93078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3765693078
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1311774819
Short name T2470
Test name
Test status
Simulation time 6927519987 ps
CPU time 193.6 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:18:53 PM PDT 24
Peak memory 206488 kb
Host smart-62414f89-55e4-4317-9908-7b50d7b67634
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1311774819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1311774819
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2543647042
Short name T1797
Test name
Test status
Simulation time 187617683 ps
CPU time 0.82 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206212 kb
Host smart-6fb332ad-025e-482c-9b03-0b7fd4f3179e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25436
47042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2543647042
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.95098127
Short name T2152
Test name
Test status
Simulation time 163741570 ps
CPU time 0.85 seconds
Started Jul 04 06:15:33 PM PDT 24
Finished Jul 04 06:15:34 PM PDT 24
Peak memory 206172 kb
Host smart-4ab4d4c2-4de1-4afd-8bea-690e89325545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95098
127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.95098127
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.722821432
Short name T619
Test name
Test status
Simulation time 885045726 ps
CPU time 2.11 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:47 PM PDT 24
Peak memory 206460 kb
Host smart-5a179930-af59-4d2d-8c41-2830b2af3356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72282
1432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.722821432
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3179184220
Short name T827
Test name
Test status
Simulation time 2612675408 ps
CPU time 72.11 seconds
Started Jul 04 06:15:36 PM PDT 24
Finished Jul 04 06:16:48 PM PDT 24
Peak memory 206512 kb
Host smart-7c35e867-ca69-411c-af67-5e77d5366866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31791
84220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3179184220
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.4032431237
Short name T2444
Test name
Test status
Simulation time 70337397 ps
CPU time 0.69 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206236 kb
Host smart-713a0d5a-7dc0-493b-ab48-a065504dc375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4032431237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.4032431237
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1571209882
Short name T2222
Test name
Test status
Simulation time 3956589385 ps
CPU time 5 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:47 PM PDT 24
Peak memory 206468 kb
Host smart-cc5fb01d-bd36-44a9-be4f-21021fc3bc58
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1571209882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1571209882
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2911683648
Short name T223
Test name
Test status
Simulation time 13346673080 ps
CPU time 13.07 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206252 kb
Host smart-216fb0d7-2df6-45b5-bef5-202d6f3882e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2911683648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2911683648
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2779671724
Short name T1040
Test name
Test status
Simulation time 23344553979 ps
CPU time 26.78 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:16:08 PM PDT 24
Peak memory 206268 kb
Host smart-e17b1cd4-07b9-4f9f-bbb5-1d0fb5114785
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2779671724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2779671724
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1473501845
Short name T1235
Test name
Test status
Simulation time 187864676 ps
CPU time 0.87 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:42 PM PDT 24
Peak memory 206208 kb
Host smart-d1295f49-4f72-4ddf-9bbc-339e08eabbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14735
01845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1473501845
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3351096133
Short name T1115
Test name
Test status
Simulation time 215521988 ps
CPU time 0.84 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206172 kb
Host smart-d3e46163-164e-47e1-9c22-bea633656259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33510
96133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3351096133
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3775430979
Short name T1581
Test name
Test status
Simulation time 337053101 ps
CPU time 1.18 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206168 kb
Host smart-953fcdc4-e523-4a66-ac6c-50bb2db6d2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37754
30979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3775430979
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.561680098
Short name T180
Test name
Test status
Simulation time 1433733568 ps
CPU time 3.37 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:48 PM PDT 24
Peak memory 206412 kb
Host smart-0d308eb7-68b7-415b-8e8f-de267384bdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56168
0098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.561680098
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2889359410
Short name T736
Test name
Test status
Simulation time 19306484081 ps
CPU time 37.59 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:16:21 PM PDT 24
Peak memory 206468 kb
Host smart-52560af0-f958-4e4b-a745-0fd8c6880853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
59410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2889359410
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3997292291
Short name T337
Test name
Test status
Simulation time 401542173 ps
CPU time 1.28 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206160 kb
Host smart-c6ab19e2-4e49-4210-a95c-45510d79b167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39972
92291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3997292291
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.784603400
Short name T1281
Test name
Test status
Simulation time 140475698 ps
CPU time 0.76 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:42 PM PDT 24
Peak memory 206188 kb
Host smart-3a67c248-9aa9-41df-9932-d4eb0b69943f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78460
3400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.784603400
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2049983730
Short name T2297
Test name
Test status
Simulation time 64077099 ps
CPU time 0.69 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:45 PM PDT 24
Peak memory 206196 kb
Host smart-0cadced3-d9e4-4ffb-b1b9-745512414dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
83730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2049983730
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.366469666
Short name T1291
Test name
Test status
Simulation time 986102029 ps
CPU time 2.5 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206368 kb
Host smart-11a2f159-5267-4ded-aa42-ba857b24a736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36646
9666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.366469666
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.789628850
Short name T2243
Test name
Test status
Simulation time 301693967 ps
CPU time 2.04 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:15:45 PM PDT 24
Peak memory 206324 kb
Host smart-75ad9409-cf27-4125-94a3-ad25cee8b2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78962
8850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.789628850
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1083260114
Short name T562
Test name
Test status
Simulation time 206309419 ps
CPU time 0.82 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:15:40 PM PDT 24
Peak memory 206196 kb
Host smart-e6374f5d-a278-4e65-bd38-54254750ecf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10832
60114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1083260114
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2600911819
Short name T603
Test name
Test status
Simulation time 146743807 ps
CPU time 0.8 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206168 kb
Host smart-45a37b0f-b2b8-44c8-8c74-7e0e36e8ed93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26009
11819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2600911819
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2239752747
Short name T377
Test name
Test status
Simulation time 216615345 ps
CPU time 0.94 seconds
Started Jul 04 06:15:39 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206196 kb
Host smart-fbf91369-8e34-41a4-9501-5060b779bd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22397
52747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2239752747
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3440490517
Short name T934
Test name
Test status
Simulation time 5071712832 ps
CPU time 38.1 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206548 kb
Host smart-20d0c7ad-422f-46d4-b92a-7c9072f59cc3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3440490517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3440490517
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3602197693
Short name T664
Test name
Test status
Simulation time 175155684 ps
CPU time 0.81 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:47 PM PDT 24
Peak memory 206212 kb
Host smart-72638de9-b34e-4984-9352-95b1aeeb62ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36021
97693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3602197693
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2325050035
Short name T1791
Test name
Test status
Simulation time 23344851770 ps
CPU time 26.14 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:16:09 PM PDT 24
Peak memory 206196 kb
Host smart-9a0d7aef-4acc-46df-b5a7-cc101c2ed351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250
50035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2325050035
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1015392096
Short name T1795
Test name
Test status
Simulation time 3275802500 ps
CPU time 3.51 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:49 PM PDT 24
Peak memory 206280 kb
Host smart-9f2ba0b4-7587-4bc2-a385-d28692a4f6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10153
92096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1015392096
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3960279996
Short name T2406
Test name
Test status
Simulation time 8685532531 ps
CPU time 89.38 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 206568 kb
Host smart-46bec2e4-6cea-49de-9720-d8c5b63c40a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602
79996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3960279996
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2793962455
Short name T1549
Test name
Test status
Simulation time 5286437288 ps
CPU time 37.21 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206460 kb
Host smart-5d1d5608-b92b-412d-9203-f0150fcdf8b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2793962455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2793962455
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2616818902
Short name T1760
Test name
Test status
Simulation time 297848106 ps
CPU time 0.97 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206204 kb
Host smart-4245966f-f063-443b-93e8-6567330ee2f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2616818902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2616818902
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.4117393605
Short name T1655
Test name
Test status
Simulation time 192176945 ps
CPU time 0.86 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206216 kb
Host smart-b6db2918-f13a-4828-8fef-d3478230b0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41173
93605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.4117393605
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4094771433
Short name T2454
Test name
Test status
Simulation time 6450466363 ps
CPU time 46.95 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:16:27 PM PDT 24
Peak memory 206396 kb
Host smart-a549d5da-54d6-473a-b24b-9da8458070b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40947
71433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4094771433
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3180363576
Short name T1385
Test name
Test status
Simulation time 4365169169 ps
CPU time 38.99 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206452 kb
Host smart-904f23ea-7c80-4fe7-90d9-47ce6cf21c42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3180363576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3180363576
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.4269855363
Short name T1034
Test name
Test status
Simulation time 158555429 ps
CPU time 0.8 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206212 kb
Host smart-6601ed40-8099-4ab1-9cc7-46938dd3bda5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4269855363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.4269855363
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1271933538
Short name T2678
Test name
Test status
Simulation time 174928750 ps
CPU time 0.8 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:47 PM PDT 24
Peak memory 206196 kb
Host smart-ea396c92-dd70-4f57-8a44-af69420a8f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719
33538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1271933538
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1190582201
Short name T121
Test name
Test status
Simulation time 197158358 ps
CPU time 0.85 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206156 kb
Host smart-ace224eb-f8a2-4e0e-9738-918e1db18268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11905
82201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1190582201
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.344137588
Short name T1937
Test name
Test status
Simulation time 188534636 ps
CPU time 0.79 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:46 PM PDT 24
Peak memory 206160 kb
Host smart-4d193106-7bec-406a-af08-d892796d4a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34413
7588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.344137588
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.767729494
Short name T844
Test name
Test status
Simulation time 168917343 ps
CPU time 0.84 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:42 PM PDT 24
Peak memory 206180 kb
Host smart-04e6169d-2c11-44b8-a50e-c95432722760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76772
9494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.767729494
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3098808845
Short name T818
Test name
Test status
Simulation time 203900586 ps
CPU time 0.79 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206212 kb
Host smart-12849e67-d3b7-44fd-b910-a3977b5295fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30988
08845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3098808845
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1594033238
Short name T189
Test name
Test status
Simulation time 165179218 ps
CPU time 0.81 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206172 kb
Host smart-c0b9d3fb-d55d-4bd5-837b-c37457dcdefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
33238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1594033238
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.378732417
Short name T1757
Test name
Test status
Simulation time 215963527 ps
CPU time 0.96 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:42 PM PDT 24
Peak memory 206196 kb
Host smart-ce348959-6643-46b3-ad3c-f38c2584b938
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=378732417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.378732417
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.715759275
Short name T2644
Test name
Test status
Simulation time 176091845 ps
CPU time 0.77 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206152 kb
Host smart-d8c15db5-e10e-4a8f-8349-76f626b6b45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71575
9275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.715759275
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1993106516
Short name T1433
Test name
Test status
Simulation time 61539301 ps
CPU time 0.7 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:42 PM PDT 24
Peak memory 206196 kb
Host smart-ec84b549-55bd-47e6-9604-a0bf735766c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19931
06516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1993106516
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2605218711
Short name T1874
Test name
Test status
Simulation time 16100618822 ps
CPU time 42.31 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:16:25 PM PDT 24
Peak memory 206516 kb
Host smart-69289851-9665-4119-92d1-ed13bdf009ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26052
18711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2605218711
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3516472486
Short name T1368
Test name
Test status
Simulation time 181549571 ps
CPU time 0.82 seconds
Started Jul 04 06:15:43 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206168 kb
Host smart-9643f341-87f9-42d6-8056-99d9081c802f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35164
72486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3516472486
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.479758363
Short name T441
Test name
Test status
Simulation time 228839325 ps
CPU time 0.94 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206200 kb
Host smart-d9a2de05-a802-4d69-a18b-6811b0f65768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47975
8363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.479758363
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3150030403
Short name T840
Test name
Test status
Simulation time 201835143 ps
CPU time 0.84 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206168 kb
Host smart-df336ce9-82bf-4315-bdb9-f2eb9bccc506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500
30403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3150030403
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.2736054353
Short name T1528
Test name
Test status
Simulation time 190465780 ps
CPU time 0.84 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:15:41 PM PDT 24
Peak memory 206184 kb
Host smart-6d23c83c-0e16-474a-b79d-806147113bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27360
54353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.2736054353
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2228365000
Short name T1211
Test name
Test status
Simulation time 169815408 ps
CPU time 0.79 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206160 kb
Host smart-f3fc04b3-02dd-4ace-8ecf-8c516ec46659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
65000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2228365000
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1056126247
Short name T501
Test name
Test status
Simulation time 146993323 ps
CPU time 0.77 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:15:42 PM PDT 24
Peak memory 206188 kb
Host smart-530bfab0-2d65-4e0b-8a58-e682ebb13205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
26247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1056126247
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3274011736
Short name T2271
Test name
Test status
Simulation time 157413839 ps
CPU time 0.83 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:46 PM PDT 24
Peak memory 206220 kb
Host smart-628aa03f-29c8-4090-adc8-2661abdd8f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740
11736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3274011736
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2224300781
Short name T2432
Test name
Test status
Simulation time 245203248 ps
CPU time 0.97 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:15:44 PM PDT 24
Peak memory 206156 kb
Host smart-263efbb6-e371-4acc-91ed-86b88243311c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243
00781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2224300781
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3891629578
Short name T977
Test name
Test status
Simulation time 4473611465 ps
CPU time 132.44 seconds
Started Jul 04 06:15:41 PM PDT 24
Finished Jul 04 06:17:55 PM PDT 24
Peak memory 206520 kb
Host smart-34087e84-e53c-45f0-a86e-b87a22a47d65
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3891629578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3891629578
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2696759753
Short name T2592
Test name
Test status
Simulation time 180162718 ps
CPU time 0.8 seconds
Started Jul 04 06:15:44 PM PDT 24
Finished Jul 04 06:15:45 PM PDT 24
Peak memory 206212 kb
Host smart-b65159fc-aff1-4e31-bf0c-fa4c7f017568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26967
59753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2696759753
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1091037648
Short name T2528
Test name
Test status
Simulation time 152545948 ps
CPU time 0.76 seconds
Started Jul 04 06:15:42 PM PDT 24
Finished Jul 04 06:15:43 PM PDT 24
Peak memory 206208 kb
Host smart-8c0a0755-cbe9-463b-b7fc-08549bb5fe9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10910
37648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1091037648
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2421657639
Short name T482
Test name
Test status
Simulation time 366272013 ps
CPU time 1.18 seconds
Started Jul 04 06:15:45 PM PDT 24
Finished Jul 04 06:15:47 PM PDT 24
Peak memory 206208 kb
Host smart-bc350444-350f-4f97-a54d-5eb995456ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
57639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2421657639
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.526018792
Short name T349
Test name
Test status
Simulation time 3871282482 ps
CPU time 29.81 seconds
Started Jul 04 06:15:40 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206508 kb
Host smart-13503772-de4a-4a01-9e9c-b3a8da29acb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52601
8792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.526018792
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.2994201041
Short name T206
Test name
Test status
Simulation time 35783338 ps
CPU time 0.68 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206272 kb
Host smart-33e8408f-efd0-4130-bdea-fd5697254c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2994201041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2994201041
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.144373920
Short name T1682
Test name
Test status
Simulation time 4437544481 ps
CPU time 5.69 seconds
Started Jul 04 06:15:48 PM PDT 24
Finished Jul 04 06:15:54 PM PDT 24
Peak memory 206188 kb
Host smart-d8c37131-8599-4b55-a95d-430a3d5de93a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=144373920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.144373920
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1958335924
Short name T1453
Test name
Test status
Simulation time 13329518805 ps
CPU time 15.24 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:16:02 PM PDT 24
Peak memory 206520 kb
Host smart-d01f80c4-e78c-4db2-835a-cbc429a42089
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1958335924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1958335924
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3770307260
Short name T1393
Test name
Test status
Simulation time 23377292229 ps
CPU time 27.97 seconds
Started Jul 04 06:15:49 PM PDT 24
Finished Jul 04 06:16:17 PM PDT 24
Peak memory 206508 kb
Host smart-f2969a77-7a65-43eb-bb99-f5226f221bb1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3770307260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.3770307260
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.4293674865
Short name T896
Test name
Test status
Simulation time 150586531 ps
CPU time 0.78 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206224 kb
Host smart-c5c2e3e7-0978-45e4-97ed-aeb2d2ecfbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
74865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.4293674865
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2532549675
Short name T1584
Test name
Test status
Simulation time 146959535 ps
CPU time 0.79 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206212 kb
Host smart-58628ad0-7e76-4a1a-a94e-11badf1e2512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25325
49675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2532549675
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.777119639
Short name T2043
Test name
Test status
Simulation time 281304629 ps
CPU time 1.02 seconds
Started Jul 04 06:15:46 PM PDT 24
Finished Jul 04 06:15:48 PM PDT 24
Peak memory 206212 kb
Host smart-ab286ff0-2eb3-4da6-8cae-eeb6a20f6c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77711
9639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.777119639
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3804143076
Short name T1210
Test name
Test status
Simulation time 576633590 ps
CPU time 1.6 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:15:49 PM PDT 24
Peak memory 206124 kb
Host smart-2802257b-cc5e-4da7-a648-3773afdf66be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38041
43076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3804143076
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2820029468
Short name T2057
Test name
Test status
Simulation time 8541499089 ps
CPU time 15.96 seconds
Started Jul 04 06:15:46 PM PDT 24
Finished Jul 04 06:16:03 PM PDT 24
Peak memory 206460 kb
Host smart-3248c5d2-64e0-411b-869d-400c9fd6c201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
29468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2820029468
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4237798788
Short name T1481
Test name
Test status
Simulation time 370414665 ps
CPU time 1.19 seconds
Started Jul 04 06:15:49 PM PDT 24
Finished Jul 04 06:15:50 PM PDT 24
Peak memory 206172 kb
Host smart-86771d93-52d8-40b5-9876-ddc14b192cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377
98788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4237798788
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3765603647
Short name T936
Test name
Test status
Simulation time 140674399 ps
CPU time 0.73 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:15:48 PM PDT 24
Peak memory 206160 kb
Host smart-952f965f-72f3-4325-bf1d-928ee8ab47db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37656
03647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3765603647
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2910803272
Short name T2668
Test name
Test status
Simulation time 36370983 ps
CPU time 0.69 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206104 kb
Host smart-70ba4db5-e2dd-4fe9-902f-9f1c79196198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
03272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2910803272
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3327937256
Short name T557
Test name
Test status
Simulation time 948819641 ps
CPU time 2.21 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:52 PM PDT 24
Peak memory 206448 kb
Host smart-2457d2e6-e8e1-46e3-9dac-c7b32f82301b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33279
37256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3327937256
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1612262754
Short name T1236
Test name
Test status
Simulation time 282628983 ps
CPU time 1.72 seconds
Started Jul 04 06:15:49 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206456 kb
Host smart-7a513222-7c25-4efc-827f-0fe60cd0ca42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16122
62754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1612262754
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1444730721
Short name T1921
Test name
Test status
Simulation time 206683536 ps
CPU time 0.88 seconds
Started Jul 04 06:15:51 PM PDT 24
Finished Jul 04 06:15:52 PM PDT 24
Peak memory 206196 kb
Host smart-3b5a93ac-b966-4b7e-b7b4-46aaa09ca780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
30721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1444730721
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2066661274
Short name T1657
Test name
Test status
Simulation time 150605044 ps
CPU time 0.84 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206176 kb
Host smart-98b82fc4-040b-432d-9080-9911b75f43e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
61274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2066661274
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1672622588
Short name T494
Test name
Test status
Simulation time 234844540 ps
CPU time 0.92 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:15:48 PM PDT 24
Peak memory 206192 kb
Host smart-70b1868b-a87e-405b-8d1f-de2bb130903d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16726
22588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1672622588
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.1533464925
Short name T2627
Test name
Test status
Simulation time 4941442813 ps
CPU time 34.83 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:16:25 PM PDT 24
Peak memory 206432 kb
Host smart-816148eb-a4b1-4021-9a06-77cae5840a9e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1533464925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.1533464925
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3028406084
Short name T2104
Test name
Test status
Simulation time 270095020 ps
CPU time 0.94 seconds
Started Jul 04 06:15:51 PM PDT 24
Finished Jul 04 06:15:52 PM PDT 24
Peak memory 206220 kb
Host smart-09dde0e0-dc75-4ff5-8c02-588d180206e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30284
06084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3028406084
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.455949066
Short name T2516
Test name
Test status
Simulation time 23347364292 ps
CPU time 23.58 seconds
Started Jul 04 06:15:46 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206236 kb
Host smart-f75992a4-05d5-4b40-a798-f06a6b1695b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45594
9066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.455949066
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2304419789
Short name T1547
Test name
Test status
Simulation time 3338016128 ps
CPU time 4.07 seconds
Started Jul 04 06:15:49 PM PDT 24
Finished Jul 04 06:15:53 PM PDT 24
Peak memory 206272 kb
Host smart-8bcd39aa-71f1-4885-a0e4-924ed211a373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23044
19789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2304419789
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.367976883
Short name T1351
Test name
Test status
Simulation time 8836738478 ps
CPU time 68.15 seconds
Started Jul 04 06:15:46 PM PDT 24
Finished Jul 04 06:16:54 PM PDT 24
Peak memory 206508 kb
Host smart-1a03fef2-2f04-4978-b422-45753ad0df98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36797
6883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.367976883
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.505720801
Short name T1990
Test name
Test status
Simulation time 3804184263 ps
CPU time 26.78 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:16:14 PM PDT 24
Peak memory 206384 kb
Host smart-69017b53-5e44-4159-a838-1022dd0ba225
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=505720801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.505720801
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1064248373
Short name T1336
Test name
Test status
Simulation time 242245516 ps
CPU time 0.95 seconds
Started Jul 04 06:15:50 PM PDT 24
Finished Jul 04 06:15:51 PM PDT 24
Peak memory 206172 kb
Host smart-39bb4d84-8539-4925-aebc-19e699bc6ca7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1064248373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1064248373
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3190423128
Short name T1447
Test name
Test status
Simulation time 200725225 ps
CPU time 0.89 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:15:48 PM PDT 24
Peak memory 206208 kb
Host smart-ee1d0156-703e-4690-b810-174b0d9c51f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
23128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3190423128
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.371929376
Short name T2090
Test name
Test status
Simulation time 6136937287 ps
CPU time 62.55 seconds
Started Jul 04 06:15:47 PM PDT 24
Finished Jul 04 06:16:50 PM PDT 24
Peak memory 206508 kb
Host smart-f6ea4931-acae-44ba-849f-284aa45c55ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37192
9376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.371929376
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2367731655
Short name T757
Test name
Test status
Simulation time 6438320741 ps
CPU time 188.27 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:19:03 PM PDT 24
Peak memory 206416 kb
Host smart-98b288fb-4b15-4a20-b9ad-24e152582467
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2367731655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2367731655
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3235297162
Short name T2353
Test name
Test status
Simulation time 169250347 ps
CPU time 0.82 seconds
Started Jul 04 06:15:56 PM PDT 24
Finished Jul 04 06:15:57 PM PDT 24
Peak memory 206180 kb
Host smart-3db4d4d9-a45a-4770-bf2a-99e2142cda85
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3235297162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3235297162
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3487934078
Short name T1763
Test name
Test status
Simulation time 140609114 ps
CPU time 0.8 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206108 kb
Host smart-4de92fd6-e981-46ea-aaa0-317d17c9f781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34879
34078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3487934078
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1092376609
Short name T2478
Test name
Test status
Simulation time 193008036 ps
CPU time 0.91 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:59 PM PDT 24
Peak memory 206144 kb
Host smart-21e052e4-0dc0-41b0-aeb5-a75ac062cf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
76609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1092376609
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2124327549
Short name T1728
Test name
Test status
Simulation time 184276112 ps
CPU time 0.77 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206184 kb
Host smart-27b4422a-6bfc-4e4d-b9cd-94d7a67f88fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21243
27549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2124327549
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3143836822
Short name T1002
Test name
Test status
Simulation time 172305317 ps
CPU time 0.81 seconds
Started Jul 04 06:15:53 PM PDT 24
Finished Jul 04 06:15:54 PM PDT 24
Peak memory 206132 kb
Host smart-073f3cbd-e40d-424f-abb2-f114fb86e9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31438
36822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3143836822
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3254462824
Short name T1359
Test name
Test status
Simulation time 158907705 ps
CPU time 0.79 seconds
Started Jul 04 06:15:53 PM PDT 24
Finished Jul 04 06:15:54 PM PDT 24
Peak memory 206168 kb
Host smart-b14670b7-cf51-4890-a81b-462afe0942d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32544
62824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3254462824
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3211347830
Short name T475
Test name
Test status
Simulation time 230564300 ps
CPU time 0.99 seconds
Started Jul 04 06:15:56 PM PDT 24
Finished Jul 04 06:15:57 PM PDT 24
Peak memory 206228 kb
Host smart-20d42629-97e7-4307-9cce-024d64db169e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3211347830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3211347830
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3402526903
Short name T626
Test name
Test status
Simulation time 168676613 ps
CPU time 0.78 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206108 kb
Host smart-ad85ad2d-ac5d-42d7-b37c-719e2c915ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
26903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3402526903
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3032610496
Short name T37
Test name
Test status
Simulation time 32211528 ps
CPU time 0.73 seconds
Started Jul 04 06:15:59 PM PDT 24
Finished Jul 04 06:16:00 PM PDT 24
Peak memory 206180 kb
Host smart-95f1b1ea-45f2-41c5-a9a1-68c7c953f60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
10496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3032610496
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.605712280
Short name T1294
Test name
Test status
Simulation time 13756949021 ps
CPU time 30.7 seconds
Started Jul 04 06:15:58 PM PDT 24
Finished Jul 04 06:16:28 PM PDT 24
Peak memory 206512 kb
Host smart-99462a6a-c2d8-4327-a09e-6fa833464c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60571
2280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.605712280
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2404159808
Short name T833
Test name
Test status
Simulation time 204718682 ps
CPU time 0.85 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206220 kb
Host smart-075589a1-c136-400d-8250-8bd483f8edcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
59808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2404159808
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.364642245
Short name T800
Test name
Test status
Simulation time 164968078 ps
CPU time 0.78 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206188 kb
Host smart-6f9b5523-0885-41c2-9f1d-46b88846dae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36464
2245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.364642245
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.4005131346
Short name T1819
Test name
Test status
Simulation time 178709032 ps
CPU time 0.81 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206212 kb
Host smart-f3ddd4e9-a475-4db5-b402-b234dc155546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40051
31346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.4005131346
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1295906220
Short name T917
Test name
Test status
Simulation time 225498392 ps
CPU time 0.93 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206144 kb
Host smart-114f9d22-0820-4196-8cc0-501b5a419f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12959
06220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1295906220
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.716824005
Short name T1214
Test name
Test status
Simulation time 153240743 ps
CPU time 0.83 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206196 kb
Host smart-d381d431-bf7d-4ba2-adaa-06bb0135038b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71682
4005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.716824005
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.64761556
Short name T345
Test name
Test status
Simulation time 175429878 ps
CPU time 0.78 seconds
Started Jul 04 06:15:59 PM PDT 24
Finished Jul 04 06:16:00 PM PDT 24
Peak memory 206172 kb
Host smart-059b6095-ba80-4344-ae0d-c3bb2e4e2181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64761
556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.64761556
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1901150587
Short name T1221
Test name
Test status
Simulation time 154474239 ps
CPU time 0.82 seconds
Started Jul 04 06:15:59 PM PDT 24
Finished Jul 04 06:16:00 PM PDT 24
Peak memory 206200 kb
Host smart-f5826bed-e9e1-43e3-959f-5b897b799d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19011
50587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1901150587
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1587563709
Short name T1352
Test name
Test status
Simulation time 284033840 ps
CPU time 0.98 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206192 kb
Host smart-f9ac7eb5-049a-4720-b17f-2ef52e26e00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15875
63709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1587563709
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.49703985
Short name T1467
Test name
Test status
Simulation time 6776292266 ps
CPU time 48.08 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:16:44 PM PDT 24
Peak memory 206452 kb
Host smart-b8eab77b-45b6-4cc3-8938-3b58a586777a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=49703985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.49703985
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3317140852
Short name T359
Test name
Test status
Simulation time 158278108 ps
CPU time 0.77 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206232 kb
Host smart-c215acb0-2c78-4186-ba92-4db30f16be52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
40852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3317140852
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3674334292
Short name T396
Test name
Test status
Simulation time 183584007 ps
CPU time 0.8 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206216 kb
Host smart-af837851-9d13-4d5e-85ec-298a6b0df1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36743
34292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3674334292
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3940287802
Short name T2563
Test name
Test status
Simulation time 938326341 ps
CPU time 2.09 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206448 kb
Host smart-5a8811f6-a961-4147-8467-310c41f80d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39402
87802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3940287802
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.84118959
Short name T673
Test name
Test status
Simulation time 5393814216 ps
CPU time 148.61 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 206484 kb
Host smart-94df0295-c7e3-42be-8246-d5bfa314c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84118
959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.84118959
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.4147926419
Short name T204
Test name
Test status
Simulation time 39362516 ps
CPU time 0.7 seconds
Started Jul 04 06:16:12 PM PDT 24
Finished Jul 04 06:16:13 PM PDT 24
Peak memory 206192 kb
Host smart-81a83622-1b8a-4b94-bbca-413e2a79a26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4147926419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.4147926419
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.4266123523
Short name T561
Test name
Test status
Simulation time 3743615787 ps
CPU time 5.04 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:59 PM PDT 24
Peak memory 206468 kb
Host smart-344cadff-8a20-47a1-ae83-a14cb36de363
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4266123523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.4266123523
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1329382929
Short name T1006
Test name
Test status
Simulation time 13512914893 ps
CPU time 14.17 seconds
Started Jul 04 06:15:56 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206504 kb
Host smart-1aeb35de-00e3-4e42-b932-22af07574b89
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1329382929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1329382929
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.179850189
Short name T1446
Test name
Test status
Simulation time 23368160490 ps
CPU time 21.26 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:16:16 PM PDT 24
Peak memory 206464 kb
Host smart-236d2087-67a2-4f61-a03f-2b7d19af8e76
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=179850189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.179850189
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1888013087
Short name T1979
Test name
Test status
Simulation time 222115852 ps
CPU time 0.86 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206140 kb
Host smart-405d461c-6c9a-4156-8063-85b8363469ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
13087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1888013087
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.873917558
Short name T1345
Test name
Test status
Simulation time 148844593 ps
CPU time 0.79 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206188 kb
Host smart-8b07d3c0-5455-41f3-ae1e-5c2997f5c03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87391
7558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.873917558
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3086925919
Short name T1256
Test name
Test status
Simulation time 239411394 ps
CPU time 0.98 seconds
Started Jul 04 06:15:53 PM PDT 24
Finished Jul 04 06:15:54 PM PDT 24
Peak memory 206192 kb
Host smart-6e238a7f-26e2-484c-9ef7-bdf3378a9cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30869
25919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3086925919
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2921563716
Short name T430
Test name
Test status
Simulation time 387679355 ps
CPU time 1.19 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:59 PM PDT 24
Peak memory 206184 kb
Host smart-9f2768cf-87c6-458e-ac15-26222ee75376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29215
63716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2921563716
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.357395204
Short name T114
Test name
Test status
Simulation time 9153478534 ps
CPU time 18.23 seconds
Started Jul 04 06:15:56 PM PDT 24
Finished Jul 04 06:16:14 PM PDT 24
Peak memory 206452 kb
Host smart-f2701704-af42-4d4f-84ec-2622591dac6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35739
5204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.357395204
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2026552341
Short name T660
Test name
Test status
Simulation time 291006811 ps
CPU time 1.07 seconds
Started Jul 04 06:15:55 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206172 kb
Host smart-b45f46df-d893-4e94-bc12-ae9e5f18f02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20265
52341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2026552341
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.235257538
Short name T44
Test name
Test status
Simulation time 140967154 ps
CPU time 0.73 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206108 kb
Host smart-e0ea2807-bfbc-4418-a4f6-fc98149b7d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23525
7538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.235257538
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3605606174
Short name T2294
Test name
Test status
Simulation time 73985755 ps
CPU time 0.71 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:55 PM PDT 24
Peak memory 206152 kb
Host smart-1f38a666-3029-4c22-9c20-afe47ba3e061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36056
06174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3605606174
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4009932860
Short name T516
Test name
Test status
Simulation time 917346374 ps
CPU time 2.06 seconds
Started Jul 04 06:15:54 PM PDT 24
Finished Jul 04 06:15:56 PM PDT 24
Peak memory 206432 kb
Host smart-a4589599-12b6-49eb-9d1e-d1f4d8e45816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
32860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4009932860
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.673637581
Short name T723
Test name
Test status
Simulation time 164135451 ps
CPU time 1.46 seconds
Started Jul 04 06:15:57 PM PDT 24
Finished Jul 04 06:15:59 PM PDT 24
Peak memory 206432 kb
Host smart-914f26a5-4f4b-4121-9db8-521748462745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67363
7581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.673637581
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.642034013
Short name T2576
Test name
Test status
Simulation time 240963245 ps
CPU time 1.04 seconds
Started Jul 04 06:15:56 PM PDT 24
Finished Jul 04 06:15:58 PM PDT 24
Peak memory 206156 kb
Host smart-b5da432b-c8ff-440f-ba0b-f50e2613c7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64203
4013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.642034013
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1246057055
Short name T2254
Test name
Test status
Simulation time 185502385 ps
CPU time 0.83 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206192 kb
Host smart-20b8624d-7dd3-45a3-9792-29096666b932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12460
57055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1246057055
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1193171420
Short name T1694
Test name
Test status
Simulation time 196874064 ps
CPU time 0.87 seconds
Started Jul 04 06:16:08 PM PDT 24
Finished Jul 04 06:16:09 PM PDT 24
Peak memory 206168 kb
Host smart-862ae187-9f8b-44f5-a283-3de2db3564be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11931
71420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1193171420
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1903795405
Short name T1017
Test name
Test status
Simulation time 265592263 ps
CPU time 0.91 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206192 kb
Host smart-061b259a-8b90-4f69-8266-0ee6222c4aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
95405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1903795405
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.4235200517
Short name T1456
Test name
Test status
Simulation time 23263068431 ps
CPU time 21.65 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:25 PM PDT 24
Peak memory 206240 kb
Host smart-d3c07fdf-aeed-4540-8e5f-dddc31dc16a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
00517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.4235200517
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.59670282
Short name T1204
Test name
Test status
Simulation time 3266395441 ps
CPU time 3.78 seconds
Started Jul 04 06:16:06 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206228 kb
Host smart-e0f5f999-23a6-4f81-896a-91921d5d7268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59670
282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.59670282
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3688031817
Short name T2175
Test name
Test status
Simulation time 7693748291 ps
CPU time 57.97 seconds
Started Jul 04 06:16:06 PM PDT 24
Finished Jul 04 06:17:04 PM PDT 24
Peak memory 206528 kb
Host smart-f8e9cc39-4bd4-4982-92c9-e89c621991f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
31817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3688031817
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3604422828
Short name T404
Test name
Test status
Simulation time 5015552381 ps
CPU time 43.99 seconds
Started Jul 04 06:16:06 PM PDT 24
Finished Jul 04 06:16:50 PM PDT 24
Peak memory 206516 kb
Host smart-d25d5e58-6cc4-4a9a-8705-d40c5d45f483
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3604422828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3604422828
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3574177133
Short name T2132
Test name
Test status
Simulation time 260237099 ps
CPU time 1.02 seconds
Started Jul 04 06:16:06 PM PDT 24
Finished Jul 04 06:16:08 PM PDT 24
Peak memory 206176 kb
Host smart-0b25d526-55b6-464b-aee6-f1bbcf24e0eb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3574177133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3574177133
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3001761144
Short name T539
Test name
Test status
Simulation time 186259744 ps
CPU time 0.85 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206192 kb
Host smart-b2fe5e46-ffe0-40d0-b4c6-36119c1396f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017
61144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3001761144
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.444950488
Short name T2556
Test name
Test status
Simulation time 4105509100 ps
CPU time 33.99 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:39 PM PDT 24
Peak memory 206448 kb
Host smart-50b0ac87-89b5-4959-894e-2b7d3235c1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44495
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.444950488
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.361821833
Short name T339
Test name
Test status
Simulation time 4809463632 ps
CPU time 35.84 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:41 PM PDT 24
Peak memory 206504 kb
Host smart-ec4972bd-9fec-4715-a6ea-ef4789ca2746
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=361821833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.361821833
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.995261257
Short name T2350
Test name
Test status
Simulation time 229556854 ps
CPU time 0.86 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:04 PM PDT 24
Peak memory 206176 kb
Host smart-0857c813-c273-4943-ab16-c84fa310ec67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=995261257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.995261257
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2233656483
Short name T951
Test name
Test status
Simulation time 139097401 ps
CPU time 0.77 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206184 kb
Host smart-562773d8-ad5c-4f66-915b-fed12237a9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
56483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2233656483
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.904953340
Short name T148
Test name
Test status
Simulation time 209304026 ps
CPU time 0.88 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206128 kb
Host smart-07bc8f6d-b936-48ce-95d0-2e418f5fe974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90495
3340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.904953340
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3285021287
Short name T2119
Test name
Test status
Simulation time 176135620 ps
CPU time 0.81 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206184 kb
Host smart-770f6c70-1bc3-4b9f-a1b5-9acd60cfffce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32850
21287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3285021287
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3822801763
Short name T1091
Test name
Test status
Simulation time 194355037 ps
CPU time 0.84 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206200 kb
Host smart-ee19ba86-d1c7-4714-aa0f-71aa8796de27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38228
01763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3822801763
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3823971232
Short name T1244
Test name
Test status
Simulation time 197098875 ps
CPU time 0.84 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206160 kb
Host smart-66a357b7-9084-4978-bbe1-ad2a6dfd735d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
71232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3823971232
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.77210616
Short name T845
Test name
Test status
Simulation time 146835311 ps
CPU time 0.84 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206196 kb
Host smart-c043cd77-773a-4a01-ae5c-cb796e43284f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77210
616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.77210616
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1798640358
Short name T658
Test name
Test status
Simulation time 219915979 ps
CPU time 0.94 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206188 kb
Host smart-d1b36a02-4563-4d53-ade7-814fefb99d71
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1798640358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1798640358
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3426777450
Short name T2080
Test name
Test status
Simulation time 188999353 ps
CPU time 0.87 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:04 PM PDT 24
Peak memory 206196 kb
Host smart-ffc60c81-4256-4906-8477-4f39bb458551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34267
77450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3426777450
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1075546696
Short name T1201
Test name
Test status
Simulation time 58078572 ps
CPU time 0.69 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206228 kb
Host smart-4885fc57-57b1-4dae-94c4-a6dc3eda5ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
46696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1075546696
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1040713857
Short name T790
Test name
Test status
Simulation time 8519540286 ps
CPU time 20.39 seconds
Started Jul 04 06:16:06 PM PDT 24
Finished Jul 04 06:16:26 PM PDT 24
Peak memory 206540 kb
Host smart-91109bd9-bb16-48a8-88a1-2debd9f6c936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10407
13857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1040713857
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3244780793
Short name T1014
Test name
Test status
Simulation time 166312401 ps
CPU time 0.8 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:04 PM PDT 24
Peak memory 206216 kb
Host smart-281e21cf-8d79-4ced-9fd5-49e5ef620fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32447
80793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3244780793
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.4076786731
Short name T1706
Test name
Test status
Simulation time 191273926 ps
CPU time 0.9 seconds
Started Jul 04 06:16:06 PM PDT 24
Finished Jul 04 06:16:07 PM PDT 24
Peak memory 206196 kb
Host smart-3b29717e-6b8e-40d5-9015-3f8f5e7d273e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
86731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.4076786731
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2878911714
Short name T610
Test name
Test status
Simulation time 235270807 ps
CPU time 0.85 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206112 kb
Host smart-c347c153-2757-4b42-8530-b641461325a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
11714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2878911714
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2310365866
Short name T1075
Test name
Test status
Simulation time 151378171 ps
CPU time 0.77 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:04 PM PDT 24
Peak memory 206180 kb
Host smart-40dbe980-50a3-4236-9d3c-10f385de15d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
65866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2310365866
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2235855683
Short name T2473
Test name
Test status
Simulation time 180095136 ps
CPU time 0.82 seconds
Started Jul 04 06:16:07 PM PDT 24
Finished Jul 04 06:16:09 PM PDT 24
Peak memory 206176 kb
Host smart-a082e786-4178-4f79-80ca-d80e1adc07ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22358
55683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2235855683
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1015155272
Short name T834
Test name
Test status
Simulation time 190647064 ps
CPU time 0.81 seconds
Started Jul 04 06:16:05 PM PDT 24
Finished Jul 04 06:16:06 PM PDT 24
Peak memory 206156 kb
Host smart-343d87d2-6a04-4a7d-9384-4ab086373069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10151
55272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1015155272
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3932929079
Short name T2479
Test name
Test status
Simulation time 149625232 ps
CPU time 0.83 seconds
Started Jul 04 06:16:03 PM PDT 24
Finished Jul 04 06:16:04 PM PDT 24
Peak memory 206224 kb
Host smart-fe3bff0b-a93b-4dc1-b088-93776c78a8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39329
29079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3932929079
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1588906636
Short name T544
Test name
Test status
Simulation time 292400554 ps
CPU time 1.02 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206200 kb
Host smart-d7e659d5-631c-4feb-bf02-885dffc1ca38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15889
06636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1588906636
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1382824210
Short name T1673
Test name
Test status
Simulation time 4894772051 ps
CPU time 133.53 seconds
Started Jul 04 06:16:07 PM PDT 24
Finished Jul 04 06:18:21 PM PDT 24
Peak memory 206528 kb
Host smart-9e014c65-ca82-489e-bb83-b260eae350f8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1382824210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1382824210
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3850292627
Short name T804
Test name
Test status
Simulation time 156266314 ps
CPU time 0.8 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:16:05 PM PDT 24
Peak memory 206132 kb
Host smart-2b04882a-31a2-4513-a109-f466c9064239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
92627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3850292627
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.4006912091
Short name T1267
Test name
Test status
Simulation time 195976504 ps
CPU time 0.84 seconds
Started Jul 04 06:16:07 PM PDT 24
Finished Jul 04 06:16:09 PM PDT 24
Peak memory 206172 kb
Host smart-634e8808-aa52-4cf7-8476-b3fe84195f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40069
12091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4006912091
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.312861895
Short name T1802
Test name
Test status
Simulation time 688306662 ps
CPU time 1.69 seconds
Started Jul 04 06:16:12 PM PDT 24
Finished Jul 04 06:16:13 PM PDT 24
Peak memory 206404 kb
Host smart-02ec536e-1737-492a-908b-f7dc5ad3bab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31286
1895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.312861895
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.533645217
Short name T42
Test name
Test status
Simulation time 5285394126 ps
CPU time 150.33 seconds
Started Jul 04 06:16:04 PM PDT 24
Finished Jul 04 06:18:34 PM PDT 24
Peak memory 206476 kb
Host smart-96291d0c-cada-4355-ac7c-d285d140a9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53364
5217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.533645217
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.294087379
Short name T1982
Test name
Test status
Simulation time 39689347 ps
CPU time 0.69 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206236 kb
Host smart-874c108c-46a3-417a-82a4-5f61edb48604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=294087379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.294087379
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3059812320
Short name T1452
Test name
Test status
Simulation time 4180480944 ps
CPU time 5.31 seconds
Started Jul 04 06:16:10 PM PDT 24
Finished Jul 04 06:16:16 PM PDT 24
Peak memory 206260 kb
Host smart-20cf599c-411f-4f9f-bd1a-06efe3461501
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3059812320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3059812320
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3212159266
Short name T1113
Test name
Test status
Simulation time 13355348601 ps
CPU time 14.53 seconds
Started Jul 04 06:16:18 PM PDT 24
Finished Jul 04 06:16:33 PM PDT 24
Peak memory 206452 kb
Host smart-9be7ee70-7506-44ca-9a15-5baacfc51c74
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3212159266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3212159266
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1263655537
Short name T2680
Test name
Test status
Simulation time 23392764528 ps
CPU time 23.31 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:33 PM PDT 24
Peak memory 206440 kb
Host smart-06ce8e2f-e12b-43ed-9162-1372391a1f7e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1263655537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1263655537
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.464370243
Short name T1949
Test name
Test status
Simulation time 200398062 ps
CPU time 0.84 seconds
Started Jul 04 06:16:10 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206196 kb
Host smart-61edcc1b-3665-438d-ba96-b6399461b819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46437
0243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.464370243
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.680319280
Short name T2003
Test name
Test status
Simulation time 143429571 ps
CPU time 0.79 seconds
Started Jul 04 06:16:14 PM PDT 24
Finished Jul 04 06:16:15 PM PDT 24
Peak memory 206160 kb
Host smart-a36a9ab5-47ef-47b1-b73c-82a32be7a989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68031
9280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.680319280
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2140618391
Short name T2008
Test name
Test status
Simulation time 407320498 ps
CPU time 1.25 seconds
Started Jul 04 06:16:18 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206200 kb
Host smart-979e6d83-b9b3-4712-a9c4-ee3b484f1034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21406
18391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2140618391
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2294019392
Short name T166
Test name
Test status
Simulation time 1251822931 ps
CPU time 2.88 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:13 PM PDT 24
Peak memory 206428 kb
Host smart-fbf92dd1-7469-4b4b-9e2e-8224c2f4833e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22940
19392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2294019392
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.4176285982
Short name T95
Test name
Test status
Simulation time 22390843521 ps
CPU time 43.28 seconds
Started Jul 04 06:16:10 PM PDT 24
Finished Jul 04 06:16:53 PM PDT 24
Peak memory 206532 kb
Host smart-3854ec3a-8009-4365-ad7d-84dc49d484b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41762
85982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.4176285982
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3667492411
Short name T593
Test name
Test status
Simulation time 462097299 ps
CPU time 1.31 seconds
Started Jul 04 06:16:17 PM PDT 24
Finished Jul 04 06:16:18 PM PDT 24
Peak memory 206188 kb
Host smart-b954e77f-f7ba-4e49-87bd-a46e16067bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
92411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3667492411
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1560164284
Short name T2117
Test name
Test status
Simulation time 136699756 ps
CPU time 0.74 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206204 kb
Host smart-a2319fcb-fcf8-4c05-ba08-eede77203e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15601
64284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1560164284
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.4115486951
Short name T2128
Test name
Test status
Simulation time 51896903 ps
CPU time 0.69 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206164 kb
Host smart-a3924931-11bf-4620-a86c-1d8aa5d9f4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
86951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.4115486951
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.920636899
Short name T1886
Test name
Test status
Simulation time 854125410 ps
CPU time 1.87 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206476 kb
Host smart-c78ae149-8571-4607-9677-cc5a58280334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92063
6899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.920636899
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1466515489
Short name T1353
Test name
Test status
Simulation time 167074371 ps
CPU time 1.5 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206424 kb
Host smart-9e728aa0-a27f-4fe0-830f-15265bdda14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14665
15489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1466515489
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2689654167
Short name T1110
Test name
Test status
Simulation time 236386815 ps
CPU time 0.93 seconds
Started Jul 04 06:16:10 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206192 kb
Host smart-fb59341d-8af5-4799-8d04-4f3a2462375d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
54167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2689654167
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2486483326
Short name T1488
Test name
Test status
Simulation time 141617950 ps
CPU time 0.78 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206204 kb
Host smart-1a15f9d3-0382-47fb-9b45-dcbc8b46f57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24864
83326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2486483326
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3632972662
Short name T1867
Test name
Test status
Simulation time 188829302 ps
CPU time 0.81 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206212 kb
Host smart-32880553-7489-4044-a349-fa5b0fb530ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36329
72662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3632972662
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.760853784
Short name T2493
Test name
Test status
Simulation time 11582531834 ps
CPU time 122.36 seconds
Started Jul 04 06:16:08 PM PDT 24
Finished Jul 04 06:18:11 PM PDT 24
Peak memory 206536 kb
Host smart-c4e2ac13-b811-44d2-b76d-4fcc14cc762a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=760853784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.760853784
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1436683040
Short name T360
Test name
Test status
Simulation time 249276346 ps
CPU time 0.86 seconds
Started Jul 04 06:16:18 PM PDT 24
Finished Jul 04 06:16:19 PM PDT 24
Peak memory 206208 kb
Host smart-97ea2d79-6255-412d-b245-91cf9fa9fdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14366
83040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1436683040
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3544758905
Short name T2166
Test name
Test status
Simulation time 23357026959 ps
CPU time 23.03 seconds
Started Jul 04 06:16:18 PM PDT 24
Finished Jul 04 06:16:42 PM PDT 24
Peak memory 206056 kb
Host smart-dd3ab06a-cd3f-4e8f-a529-6a416d4f422c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
58905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3544758905
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3312471557
Short name T551
Test name
Test status
Simulation time 3309170392 ps
CPU time 4.2 seconds
Started Jul 04 06:16:16 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206216 kb
Host smart-f72bd915-378c-4dfd-a6f9-63eaba798aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33124
71557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3312471557
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2887031894
Short name T1805
Test name
Test status
Simulation time 7710769990 ps
CPU time 57.16 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:17:08 PM PDT 24
Peak memory 206508 kb
Host smart-aba63cc3-9f62-4856-8c25-47aaf3f63cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
31894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2887031894
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3119042885
Short name T1220
Test name
Test status
Simulation time 7603411025 ps
CPU time 196.53 seconds
Started Jul 04 06:16:12 PM PDT 24
Finished Jul 04 06:19:29 PM PDT 24
Peak memory 206396 kb
Host smart-bbd1283b-ee6e-4aab-ba68-830eeb302a13
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3119042885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3119042885
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.747094037
Short name T453
Test name
Test status
Simulation time 260984807 ps
CPU time 0.93 seconds
Started Jul 04 06:16:10 PM PDT 24
Finished Jul 04 06:16:11 PM PDT 24
Peak memory 206184 kb
Host smart-f0720c6d-e3b7-49af-8654-d34d913d09d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=747094037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.747094037
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2357106915
Short name T2648
Test name
Test status
Simulation time 223174485 ps
CPU time 0.88 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206160 kb
Host smart-71a17531-6214-4aee-81b3-e6335bac8175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23571
06915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2357106915
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1785596877
Short name T996
Test name
Test status
Simulation time 5159333162 ps
CPU time 148.86 seconds
Started Jul 04 06:16:08 PM PDT 24
Finished Jul 04 06:18:37 PM PDT 24
Peak memory 206428 kb
Host smart-5063667a-cc36-4c25-a238-0c34c2e6a36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17855
96877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1785596877
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2829716417
Short name T984
Test name
Test status
Simulation time 4580773976 ps
CPU time 121.13 seconds
Started Jul 04 06:16:10 PM PDT 24
Finished Jul 04 06:18:11 PM PDT 24
Peak memory 206452 kb
Host smart-2020004b-12b3-4618-a7e4-da7f29bfc5b5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2829716417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2829716417
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2890198581
Short name T835
Test name
Test status
Simulation time 151511522 ps
CPU time 0.81 seconds
Started Jul 04 06:16:15 PM PDT 24
Finished Jul 04 06:16:16 PM PDT 24
Peak memory 206164 kb
Host smart-008eb5d4-c775-4d48-9d8b-78ee9470500f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2890198581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2890198581
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2782197933
Short name T2557
Test name
Test status
Simulation time 153957177 ps
CPU time 0.78 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206208 kb
Host smart-b07b3758-e2cc-4834-af00-01f707f8678c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27821
97933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2782197933
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1379551798
Short name T124
Test name
Test status
Simulation time 193865879 ps
CPU time 0.84 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206172 kb
Host smart-6427c45e-ba4f-4fa6-86dc-ba8cdbae868f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13795
51798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1379551798
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.398643948
Short name T1254
Test name
Test status
Simulation time 220318126 ps
CPU time 0.91 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:13 PM PDT 24
Peak memory 206112 kb
Host smart-acebfa0e-810b-4b5c-a68d-3d362120b06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
3948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.398643948
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2771229220
Short name T1299
Test name
Test status
Simulation time 226131174 ps
CPU time 0.94 seconds
Started Jul 04 06:16:17 PM PDT 24
Finished Jul 04 06:16:19 PM PDT 24
Peak memory 206220 kb
Host smart-dd521751-f6f4-4e70-b75c-b26eaab4b40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27712
29220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2771229220
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3198994776
Short name T343
Test name
Test status
Simulation time 205619897 ps
CPU time 0.82 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206188 kb
Host smart-b33c1850-d95e-4a56-b541-93d939311365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
94776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3198994776
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.811808339
Short name T598
Test name
Test status
Simulation time 151849265 ps
CPU time 0.81 seconds
Started Jul 04 06:16:17 PM PDT 24
Finished Jul 04 06:16:18 PM PDT 24
Peak memory 206200 kb
Host smart-ad357568-b4b0-4642-9ade-74aa14e98bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81180
8339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.811808339
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3355492161
Short name T893
Test name
Test status
Simulation time 242246637 ps
CPU time 0.99 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206192 kb
Host smart-664dfe22-0bc2-4f3d-bb62-be1418aa3bfb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3355492161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3355492161
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3470960398
Short name T976
Test name
Test status
Simulation time 142260475 ps
CPU time 0.74 seconds
Started Jul 04 06:16:23 PM PDT 24
Finished Jul 04 06:16:23 PM PDT 24
Peak memory 206200 kb
Host smart-222c4559-0909-4e1f-8c40-b239006d7139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34709
60398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3470960398
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1570442835
Short name T1202
Test name
Test status
Simulation time 41804243 ps
CPU time 0.78 seconds
Started Jul 04 06:16:18 PM PDT 24
Finished Jul 04 06:16:20 PM PDT 24
Peak memory 206216 kb
Host smart-29ec5178-a823-434e-bdcf-e80520f71948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
42835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1570442835
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.355191352
Short name T886
Test name
Test status
Simulation time 23325989676 ps
CPU time 55.08 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:17:04 PM PDT 24
Peak memory 206540 kb
Host smart-a5abb3d4-7e90-4946-815a-452d25c30e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
1352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.355191352
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1475845464
Short name T2139
Test name
Test status
Simulation time 163564236 ps
CPU time 0.81 seconds
Started Jul 04 06:16:17 PM PDT 24
Finished Jul 04 06:16:18 PM PDT 24
Peak memory 206208 kb
Host smart-11037a2b-56c4-435f-880f-92fed5764867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
45464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1475845464
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.547973261
Short name T2610
Test name
Test status
Simulation time 296097637 ps
CPU time 0.99 seconds
Started Jul 04 06:16:14 PM PDT 24
Finished Jul 04 06:16:15 PM PDT 24
Peak memory 206164 kb
Host smart-1ceb0737-6769-4a38-bdc7-7d484cad0a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54797
3261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.547973261
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.852836269
Short name T2050
Test name
Test status
Simulation time 264561297 ps
CPU time 0.92 seconds
Started Jul 04 06:16:14 PM PDT 24
Finished Jul 04 06:16:16 PM PDT 24
Peak memory 206204 kb
Host smart-c03c5210-ef28-48ad-b4cb-3ce3e5529f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85283
6269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.852836269
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.59540766
Short name T2672
Test name
Test status
Simulation time 228761083 ps
CPU time 0.85 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206176 kb
Host smart-2cd6749c-a8be-4f14-9f72-5ff2c082cb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59540
766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.59540766
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.4134020379
Short name T1834
Test name
Test status
Simulation time 160059968 ps
CPU time 0.81 seconds
Started Jul 04 06:16:21 PM PDT 24
Finished Jul 04 06:16:22 PM PDT 24
Peak memory 206220 kb
Host smart-b47699d0-a155-4d14-880a-b090dcb97ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41340
20379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4134020379
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3391879935
Short name T823
Test name
Test status
Simulation time 196345927 ps
CPU time 0.89 seconds
Started Jul 04 06:16:15 PM PDT 24
Finished Jul 04 06:16:16 PM PDT 24
Peak memory 206160 kb
Host smart-490b2e4b-e0ad-4f5f-ae39-0f837abc6cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33918
79935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3391879935
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3453433447
Short name T616
Test name
Test status
Simulation time 235755307 ps
CPU time 0.94 seconds
Started Jul 04 06:16:09 PM PDT 24
Finished Jul 04 06:16:10 PM PDT 24
Peak memory 206180 kb
Host smart-4aae8ca6-24fb-458d-87de-9480458aef29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34534
33447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3453433447
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1171759270
Short name T2703
Test name
Test status
Simulation time 3596654455 ps
CPU time 93.24 seconds
Started Jul 04 06:16:14 PM PDT 24
Finished Jul 04 06:17:48 PM PDT 24
Peak memory 206520 kb
Host smart-6f9c11aa-ece4-4cd4-85aa-1c088828a571
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1171759270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1171759270
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.81608154
Short name T2159
Test name
Test status
Simulation time 159349303 ps
CPU time 0.78 seconds
Started Jul 04 06:16:12 PM PDT 24
Finished Jul 04 06:16:13 PM PDT 24
Peak memory 206124 kb
Host smart-f7404234-557b-4bad-817e-1f4fee67b28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81608
154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.81608154
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3198963861
Short name T775
Test name
Test status
Simulation time 165622442 ps
CPU time 0.78 seconds
Started Jul 04 06:16:11 PM PDT 24
Finished Jul 04 06:16:12 PM PDT 24
Peak memory 206124 kb
Host smart-6495928e-ead9-48cd-9c25-6938ed84e15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
63861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3198963861
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3225747947
Short name T1248
Test name
Test status
Simulation time 1363162886 ps
CPU time 3.07 seconds
Started Jul 04 06:16:12 PM PDT 24
Finished Jul 04 06:16:15 PM PDT 24
Peak memory 206392 kb
Host smart-99353996-29cc-4732-9dc9-d654bf2c7820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257
47947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3225747947
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2766757614
Short name T320
Test name
Test status
Simulation time 4432093730 ps
CPU time 121.99 seconds
Started Jul 04 06:16:16 PM PDT 24
Finished Jul 04 06:18:19 PM PDT 24
Peak memory 206552 kb
Host smart-e9521e24-d666-4192-8fc4-5df3e98159fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27667
57614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2766757614
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.444865321
Short name T945
Test name
Test status
Simulation time 34774454 ps
CPU time 0.65 seconds
Started Jul 04 06:07:39 PM PDT 24
Finished Jul 04 06:07:40 PM PDT 24
Peak memory 206496 kb
Host smart-ec594a24-c4b0-4b1e-800e-2eb95f237225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=444865321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.444865321
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.360587756
Short name T2275
Test name
Test status
Simulation time 4105258045 ps
CPU time 4.42 seconds
Started Jul 04 06:07:19 PM PDT 24
Finished Jul 04 06:07:23 PM PDT 24
Peak memory 206532 kb
Host smart-6440984b-c9ec-40b7-aa26-815035c80b66
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=360587756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.360587756
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3035302847
Short name T2261
Test name
Test status
Simulation time 13312735686 ps
CPU time 15.73 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:31 PM PDT 24
Peak memory 206268 kb
Host smart-7799f26b-8c30-4922-afe6-866a29d1721b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3035302847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3035302847
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2536520688
Short name T1574
Test name
Test status
Simulation time 23362103845 ps
CPU time 21.82 seconds
Started Jul 04 06:07:17 PM PDT 24
Finished Jul 04 06:07:39 PM PDT 24
Peak memory 206432 kb
Host smart-85956e89-7307-44c0-8856-06f725b75aa9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2536520688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2536520688
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.4065941047
Short name T852
Test name
Test status
Simulation time 168760817 ps
CPU time 0.78 seconds
Started Jul 04 06:07:16 PM PDT 24
Finished Jul 04 06:07:17 PM PDT 24
Peak memory 206192 kb
Host smart-62f75722-29b3-4f4c-aa95-67af5a30c486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40659
41047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.4065941047
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.4291855042
Short name T63
Test name
Test status
Simulation time 217439239 ps
CPU time 0.9 seconds
Started Jul 04 06:07:15 PM PDT 24
Finished Jul 04 06:07:16 PM PDT 24
Peak memory 206208 kb
Host smart-bca3ffb7-c766-487a-b161-a5fc6fb62848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42918
55042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.4291855042
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3013885096
Short name T193
Test name
Test status
Simulation time 601558051 ps
CPU time 1.72 seconds
Started Jul 04 06:07:19 PM PDT 24
Finished Jul 04 06:07:21 PM PDT 24
Peak memory 206448 kb
Host smart-d8b762b5-e507-49a3-b786-2907e2accad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
85096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3013885096
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2076006105
Short name T61
Test name
Test status
Simulation time 1082220994 ps
CPU time 2.67 seconds
Started Jul 04 06:07:23 PM PDT 24
Finished Jul 04 06:07:26 PM PDT 24
Peak memory 206348 kb
Host smart-2a09c80b-c31f-47ec-b331-d7674a41f3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20760
06105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2076006105
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2992111504
Short name T112
Test name
Test status
Simulation time 12566138794 ps
CPU time 24.26 seconds
Started Jul 04 06:07:22 PM PDT 24
Finished Jul 04 06:07:47 PM PDT 24
Peak memory 206492 kb
Host smart-0119f3cc-89a1-46fe-abd4-d76e4ab7ba2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29921
11504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2992111504
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.4218290166
Short name T373
Test name
Test status
Simulation time 468021121 ps
CPU time 1.49 seconds
Started Jul 04 06:07:25 PM PDT 24
Finished Jul 04 06:07:26 PM PDT 24
Peak memory 206128 kb
Host smart-efb68c5e-def4-4ae2-81ac-533b1f38c8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42182
90166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.4218290166
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.4212034349
Short name T1400
Test name
Test status
Simulation time 146356780 ps
CPU time 0.75 seconds
Started Jul 04 06:07:21 PM PDT 24
Finished Jul 04 06:07:22 PM PDT 24
Peak memory 206180 kb
Host smart-92cebc97-4149-4662-b14b-685737e2d5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42120
34349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.4212034349
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1671471422
Short name T1142
Test name
Test status
Simulation time 59771459 ps
CPU time 0.68 seconds
Started Jul 04 06:07:23 PM PDT 24
Finished Jul 04 06:07:23 PM PDT 24
Peak memory 206216 kb
Host smart-cad26db7-05d5-4f5a-8655-64734b1c2f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16714
71422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1671471422
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3753900898
Short name T1870
Test name
Test status
Simulation time 846250440 ps
CPU time 2.09 seconds
Started Jul 04 06:07:22 PM PDT 24
Finished Jul 04 06:07:24 PM PDT 24
Peak memory 206372 kb
Host smart-1c6a87bb-9978-4ef6-8c90-730dbcfb1858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37539
00898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3753900898
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2908067537
Short name T1276
Test name
Test status
Simulation time 184906394 ps
CPU time 2.01 seconds
Started Jul 04 06:07:23 PM PDT 24
Finished Jul 04 06:07:25 PM PDT 24
Peak memory 206392 kb
Host smart-c078dffc-2f08-4c21-a3c4-d2164874a93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29080
67537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2908067537
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.802758053
Short name T2097
Test name
Test status
Simulation time 238851359 ps
CPU time 0.88 seconds
Started Jul 04 06:07:22 PM PDT 24
Finished Jul 04 06:07:23 PM PDT 24
Peak memory 206220 kb
Host smart-a4ef8032-73da-4edd-8d1b-6a4c848f178e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80275
8053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.802758053
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.326015860
Short name T550
Test name
Test status
Simulation time 138803660 ps
CPU time 0.75 seconds
Started Jul 04 06:07:23 PM PDT 24
Finished Jul 04 06:07:24 PM PDT 24
Peak memory 206136 kb
Host smart-10e0adb2-6629-4b00-8db0-6f031b639fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32601
5860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.326015860
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2483977495
Short name T1904
Test name
Test status
Simulation time 226397530 ps
CPU time 0.92 seconds
Started Jul 04 06:07:24 PM PDT 24
Finished Jul 04 06:07:25 PM PDT 24
Peak memory 206144 kb
Host smart-54c7b868-c304-4f7d-b039-bc4188d13130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
77495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2483977495
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3354969638
Short name T825
Test name
Test status
Simulation time 218738569 ps
CPU time 0.89 seconds
Started Jul 04 06:07:23 PM PDT 24
Finished Jul 04 06:07:24 PM PDT 24
Peak memory 206200 kb
Host smart-8a3ba9b2-0d46-40d4-907e-ef79e16f7257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33549
69638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3354969638
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.65735626
Short name T1927
Test name
Test status
Simulation time 23346076154 ps
CPU time 26.66 seconds
Started Jul 04 06:07:22 PM PDT 24
Finished Jul 04 06:07:49 PM PDT 24
Peak memory 206256 kb
Host smart-85690a81-5438-4100-a6a2-b3651fa4885a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65735
626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.65735626
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2241277296
Short name T2115
Test name
Test status
Simulation time 3279134581 ps
CPU time 3.92 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:07:35 PM PDT 24
Peak memory 206272 kb
Host smart-da1b1e7d-917d-4f23-9676-20ac8999174f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
77296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2241277296
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.833838053
Short name T912
Test name
Test status
Simulation time 7453580139 ps
CPU time 66.85 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:08:37 PM PDT 24
Peak memory 206548 kb
Host smart-a5505857-55f5-4373-bddb-dc535dd6fe10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83383
8053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.833838053
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1008623449
Short name T2230
Test name
Test status
Simulation time 4285633243 ps
CPU time 40.39 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:08:10 PM PDT 24
Peak memory 206508 kb
Host smart-e8b83cc1-13e6-4196-bd0b-20c4423fbc64
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1008623449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1008623449
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3523945373
Short name T954
Test name
Test status
Simulation time 233695297 ps
CPU time 0.92 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:32 PM PDT 24
Peak memory 206176 kb
Host smart-088cb66d-667a-4e95-874d-a08c31096fdf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3523945373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3523945373
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2234778238
Short name T584
Test name
Test status
Simulation time 196124591 ps
CPU time 0.85 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:07:33 PM PDT 24
Peak memory 206184 kb
Host smart-14cb3379-98df-447c-b802-e6d4e21fa182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22347
78238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2234778238
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.487028694
Short name T2200
Test name
Test status
Simulation time 3453975952 ps
CPU time 93.52 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:09:03 PM PDT 24
Peak memory 206432 kb
Host smart-6547bdee-4b5a-4f35-a3d8-6ab3ae0686f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48702
8694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.487028694
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2140587359
Short name T848
Test name
Test status
Simulation time 5184451864 ps
CPU time 138 seconds
Started Jul 04 06:07:32 PM PDT 24
Finished Jul 04 06:09:50 PM PDT 24
Peak memory 206464 kb
Host smart-15e25596-690a-47e3-a60f-a023170c0689
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2140587359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2140587359
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1649606304
Short name T1403
Test name
Test status
Simulation time 157519141 ps
CPU time 0.8 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:31 PM PDT 24
Peak memory 206212 kb
Host smart-2a479a7a-01d5-49fa-bbcc-fda1a831ca07
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1649606304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1649606304
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3422345312
Short name T1726
Test name
Test status
Simulation time 147880110 ps
CPU time 0.77 seconds
Started Jul 04 06:07:28 PM PDT 24
Finished Jul 04 06:07:29 PM PDT 24
Peak memory 206212 kb
Host smart-39661854-4bd2-4877-a102-dcb91ea61596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34223
45312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3422345312
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3450571272
Short name T2288
Test name
Test status
Simulation time 184687842 ps
CPU time 0.83 seconds
Started Jul 04 06:07:28 PM PDT 24
Finished Jul 04 06:07:29 PM PDT 24
Peak memory 206224 kb
Host smart-12597591-72a8-42b5-be0e-6cd908518297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34505
71272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3450571272
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1253803643
Short name T2053
Test name
Test status
Simulation time 182850577 ps
CPU time 0.85 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:32 PM PDT 24
Peak memory 206196 kb
Host smart-68711337-a291-475a-a701-b3c6b5dd006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538
03643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1253803643
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2153375601
Short name T1246
Test name
Test status
Simulation time 163273799 ps
CPU time 0.84 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:07:33 PM PDT 24
Peak memory 206168 kb
Host smart-b9b3cda4-6c52-419a-8323-d19af4f6eac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
75601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2153375601
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3626772871
Short name T1766
Test name
Test status
Simulation time 177222936 ps
CPU time 0.8 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:07:32 PM PDT 24
Peak memory 206200 kb
Host smart-1c5bf48c-7dbc-4efa-9bd9-13b853d92a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36267
72871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3626772871
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4131668645
Short name T1287
Test name
Test status
Simulation time 197871652 ps
CPU time 0.79 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:31 PM PDT 24
Peak memory 206184 kb
Host smart-18a2968b-5302-46d7-b0a0-e6145bdca2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
68645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4131668645
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.4037400626
Short name T2481
Test name
Test status
Simulation time 219294894 ps
CPU time 0.96 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:07:33 PM PDT 24
Peak memory 206208 kb
Host smart-4dbabd47-ff06-4784-83a8-af9275083dad
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4037400626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.4037400626
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3992297992
Short name T632
Test name
Test status
Simulation time 169180854 ps
CPU time 0.81 seconds
Started Jul 04 06:07:29 PM PDT 24
Finished Jul 04 06:07:30 PM PDT 24
Peak memory 206192 kb
Host smart-225e4156-b3d5-48be-bb1a-037f12046f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39922
97992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3992297992
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.88862787
Short name T1030
Test name
Test status
Simulation time 30902259 ps
CPU time 0.69 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:31 PM PDT 24
Peak memory 206200 kb
Host smart-c4006e4e-318e-43d6-add8-7778042afb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88862
787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.88862787
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1989517021
Short name T273
Test name
Test status
Simulation time 21462256345 ps
CPU time 46.15 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:08:18 PM PDT 24
Peak memory 206528 kb
Host smart-67a5278a-db5d-4fe8-bd78-674895d31a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
17021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1989517021
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.63636561
Short name T1755
Test name
Test status
Simulation time 161774517 ps
CPU time 0.84 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:31 PM PDT 24
Peak memory 206224 kb
Host smart-cd7f2676-4b07-4409-94e7-5468d2f0b453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63636
561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.63636561
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.207720806
Short name T1575
Test name
Test status
Simulation time 156394294 ps
CPU time 0.76 seconds
Started Jul 04 06:07:29 PM PDT 24
Finished Jul 04 06:07:30 PM PDT 24
Peak memory 206220 kb
Host smart-ab30d619-c562-4d29-9f39-ec0920b1bb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
0806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.207720806
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.643471144
Short name T181
Test name
Test status
Simulation time 10247758101 ps
CPU time 65.14 seconds
Started Jul 04 06:07:37 PM PDT 24
Finished Jul 04 06:08:43 PM PDT 24
Peak memory 206560 kb
Host smart-f1d32671-83c3-461f-93af-9fa599c111e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=643471144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.643471144
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.548294665
Short name T2700
Test name
Test status
Simulation time 19843490898 ps
CPU time 118.52 seconds
Started Jul 04 06:07:35 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 206440 kb
Host smart-f2ac4293-e2f5-457b-a492-54e2beadff74
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=548294665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.548294665
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2366447708
Short name T1816
Test name
Test status
Simulation time 11530347794 ps
CPU time 54.64 seconds
Started Jul 04 06:07:43 PM PDT 24
Finished Jul 04 06:08:38 PM PDT 24
Peak memory 206752 kb
Host smart-87bdd76c-7606-4135-94bc-c4922e450331
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2366447708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2366447708
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2694933710
Short name T681
Test name
Test status
Simulation time 169647514 ps
CPU time 0.78 seconds
Started Jul 04 06:07:30 PM PDT 24
Finished Jul 04 06:07:31 PM PDT 24
Peak memory 206172 kb
Host smart-78444767-e689-44f5-9031-ada31dec5ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26949
33710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2694933710
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2297792382
Short name T1641
Test name
Test status
Simulation time 207824201 ps
CPU time 0.84 seconds
Started Jul 04 06:07:31 PM PDT 24
Finished Jul 04 06:07:32 PM PDT 24
Peak memory 206208 kb
Host smart-91bc539d-9868-4497-a980-634f505cae92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22977
92382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2297792382
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2438307894
Short name T75
Test name
Test status
Simulation time 163733868 ps
CPU time 0.79 seconds
Started Jul 04 06:07:37 PM PDT 24
Finished Jul 04 06:07:38 PM PDT 24
Peak memory 206176 kb
Host smart-f5df4df2-fd0a-4a46-a864-6f62d7ae3c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24383
07894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2438307894
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3703345377
Short name T1658
Test name
Test status
Simulation time 147380821 ps
CPU time 0.75 seconds
Started Jul 04 06:07:36 PM PDT 24
Finished Jul 04 06:07:37 PM PDT 24
Peak memory 206176 kb
Host smart-fe922486-9cc1-4dff-83e9-e388fd277153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
45377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3703345377
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.4285998036
Short name T1745
Test name
Test status
Simulation time 157261159 ps
CPU time 0.77 seconds
Started Jul 04 06:07:36 PM PDT 24
Finished Jul 04 06:07:37 PM PDT 24
Peak memory 206172 kb
Host smart-13948826-0e16-4033-954f-c52c77838b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42859
98036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.4285998036
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2896936700
Short name T2067
Test name
Test status
Simulation time 201742731 ps
CPU time 0.86 seconds
Started Jul 04 06:07:37 PM PDT 24
Finished Jul 04 06:07:38 PM PDT 24
Peak memory 206204 kb
Host smart-1349b276-67a7-46ba-87ec-6dd755bb9c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
36700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2896936700
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2270745516
Short name T1967
Test name
Test status
Simulation time 3675663440 ps
CPU time 100.96 seconds
Started Jul 04 06:07:37 PM PDT 24
Finished Jul 04 06:09:19 PM PDT 24
Peak memory 206536 kb
Host smart-7baf7d1d-fc21-443b-829f-28389de0b6fc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2270745516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2270745516
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2276948316
Short name T668
Test name
Test status
Simulation time 174819552 ps
CPU time 0.78 seconds
Started Jul 04 06:07:36 PM PDT 24
Finished Jul 04 06:07:37 PM PDT 24
Peak memory 206128 kb
Host smart-bf569c17-3c92-4e48-b477-02bdf5ab3e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22769
48316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2276948316
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3970140786
Short name T858
Test name
Test status
Simulation time 158396717 ps
CPU time 0.76 seconds
Started Jul 04 06:07:39 PM PDT 24
Finished Jul 04 06:07:40 PM PDT 24
Peak memory 206192 kb
Host smart-09f5b93f-d301-4013-8557-4ed234137a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39701
40786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3970140786
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.303822160
Short name T266
Test name
Test status
Simulation time 807924349 ps
CPU time 2.11 seconds
Started Jul 04 06:07:37 PM PDT 24
Finished Jul 04 06:07:39 PM PDT 24
Peak memory 206448 kb
Host smart-a358754b-1c0d-4584-baf1-637342428e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.303822160
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.4228200559
Short name T1004
Test name
Test status
Simulation time 3866823755 ps
CPU time 37.18 seconds
Started Jul 04 06:07:39 PM PDT 24
Finished Jul 04 06:08:16 PM PDT 24
Peak memory 206512 kb
Host smart-2e079ae6-9755-41fd-a09a-3bd0b7e10c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42282
00559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.4228200559
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3191554202
Short name T2116
Test name
Test status
Simulation time 55298693 ps
CPU time 0.7 seconds
Started Jul 04 06:08:01 PM PDT 24
Finished Jul 04 06:08:02 PM PDT 24
Peak memory 206264 kb
Host smart-5050ed85-399b-425c-b120-0f469d520486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3191554202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3191554202
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.216738368
Short name T2365
Test name
Test status
Simulation time 4589278169 ps
CPU time 6.68 seconds
Started Jul 04 06:07:40 PM PDT 24
Finished Jul 04 06:07:47 PM PDT 24
Peak memory 206744 kb
Host smart-790009ef-d17d-4618-8f52-eef0d9fdf1d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=216738368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.216738368
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.423616291
Short name T568
Test name
Test status
Simulation time 13382839572 ps
CPU time 11.87 seconds
Started Jul 04 06:07:36 PM PDT 24
Finished Jul 04 06:07:48 PM PDT 24
Peak memory 206508 kb
Host smart-1facbff5-b271-46c1-b903-fe55de968a2f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=423616291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.423616291
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1619780545
Short name T1298
Test name
Test status
Simulation time 23520402027 ps
CPU time 23.99 seconds
Started Jul 04 06:07:41 PM PDT 24
Finished Jul 04 06:08:05 PM PDT 24
Peak memory 206756 kb
Host smart-823438a2-ba36-4c34-bbaf-dbe5b1b08385
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1619780545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.1619780545
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4155697356
Short name T1702
Test name
Test status
Simulation time 160728558 ps
CPU time 0.77 seconds
Started Jul 04 06:07:43 PM PDT 24
Finished Jul 04 06:07:44 PM PDT 24
Peak memory 206212 kb
Host smart-0084306d-af6f-4c88-88e6-a67cc2b5d600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
97356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4155697356
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.914616094
Short name T2417
Test name
Test status
Simulation time 143203031 ps
CPU time 0.8 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:07:46 PM PDT 24
Peak memory 206152 kb
Host smart-062a56e7-c176-48d7-a52d-61deec2f0411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91461
6094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.914616094
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2866818011
Short name T1513
Test name
Test status
Simulation time 364170497 ps
CPU time 1.26 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:07:46 PM PDT 24
Peak memory 206160 kb
Host smart-e984d244-ed6b-4ccd-bfbc-afc37bdf90d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
18011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2866818011
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1338029792
Short name T2199
Test name
Test status
Simulation time 1069808663 ps
CPU time 2.38 seconds
Started Jul 04 06:07:44 PM PDT 24
Finished Jul 04 06:07:46 PM PDT 24
Peak memory 206408 kb
Host smart-c09eead2-635c-4444-b71d-625ab62557d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
29792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1338029792
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2050125118
Short name T888
Test name
Test status
Simulation time 11098438476 ps
CPU time 19.77 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:08:05 PM PDT 24
Peak memory 206488 kb
Host smart-004b2c85-e8ac-4d9e-81ef-f64fed498801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20501
25118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2050125118
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.110967500
Short name T1339
Test name
Test status
Simulation time 425565040 ps
CPU time 1.33 seconds
Started Jul 04 06:07:44 PM PDT 24
Finished Jul 04 06:07:45 PM PDT 24
Peak memory 206180 kb
Host smart-1a917aac-579e-4cfe-8292-4a5d39b89807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11096
7500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.110967500
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3959031730
Short name T1691
Test name
Test status
Simulation time 136239993 ps
CPU time 0.78 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:07:46 PM PDT 24
Peak memory 206140 kb
Host smart-253245f7-4f36-457f-9d49-c6fb1518e30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39590
31730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3959031730
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2339119252
Short name T567
Test name
Test status
Simulation time 50110176 ps
CPU time 0.67 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:07:46 PM PDT 24
Peak memory 206160 kb
Host smart-e3e87637-7cee-4703-a953-043ac8f2a894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391
19252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2339119252
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2540952673
Short name T2522
Test name
Test status
Simulation time 815249559 ps
CPU time 2.08 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:07:48 PM PDT 24
Peak memory 206424 kb
Host smart-94f171b2-d9ac-47de-bdfc-aa8873893c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25409
52673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2540952673
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1469029735
Short name T487
Test name
Test status
Simulation time 373371913 ps
CPU time 2.4 seconds
Started Jul 04 06:07:45 PM PDT 24
Finished Jul 04 06:07:47 PM PDT 24
Peak memory 206372 kb
Host smart-4c8b5949-46f1-4aa8-b33e-b209496ed75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690
29735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1469029735
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1217840339
Short name T2369
Test name
Test status
Simulation time 241042103 ps
CPU time 0.94 seconds
Started Jul 04 06:07:44 PM PDT 24
Finished Jul 04 06:07:45 PM PDT 24
Peak memory 206212 kb
Host smart-3ae527f4-e144-499b-a42c-d30a8ed97fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12178
40339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1217840339
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3614967583
Short name T2094
Test name
Test status
Simulation time 170532774 ps
CPU time 0.82 seconds
Started Jul 04 06:07:51 PM PDT 24
Finished Jul 04 06:07:52 PM PDT 24
Peak memory 206192 kb
Host smart-04807d5b-bbf8-401a-9a48-a7aaa48b65d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
67583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3614967583
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2453038800
Short name T540
Test name
Test status
Simulation time 221405890 ps
CPU time 0.88 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206200 kb
Host smart-24c7aab2-8c6e-4351-86a4-9774c07b7b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24530
38800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2453038800
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.787190100
Short name T644
Test name
Test status
Simulation time 167719434 ps
CPU time 0.85 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:07:53 PM PDT 24
Peak memory 206176 kb
Host smart-d3359bce-9786-4252-a125-45c895de7f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78719
0100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.787190100
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1105963877
Short name T927
Test name
Test status
Simulation time 23304848981 ps
CPU time 22.79 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:08:17 PM PDT 24
Peak memory 206268 kb
Host smart-479ed496-00b2-4ead-952c-987a4edef876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11059
63877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1105963877
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3088172540
Short name T669
Test name
Test status
Simulation time 3366995942 ps
CPU time 4.66 seconds
Started Jul 04 06:07:53 PM PDT 24
Finished Jul 04 06:07:58 PM PDT 24
Peak memory 206256 kb
Host smart-3e8e2d63-18d9-486d-8bb5-24d84ad5dc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30881
72540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3088172540
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1787964474
Short name T718
Test name
Test status
Simulation time 8241443982 ps
CPU time 80.27 seconds
Started Jul 04 06:07:53 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206524 kb
Host smart-ca42ec44-cb23-44a9-b2ec-7ef5cec7586f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17879
64474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1787964474
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.4094717248
Short name T1135
Test name
Test status
Simulation time 4935863574 ps
CPU time 45.7 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:08:40 PM PDT 24
Peak memory 206460 kb
Host smart-2619af10-8664-4ac9-ab39-798dc21c4955
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4094717248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.4094717248
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2411823135
Short name T873
Test name
Test status
Simulation time 255677370 ps
CPU time 0.9 seconds
Started Jul 04 06:07:53 PM PDT 24
Finished Jul 04 06:07:54 PM PDT 24
Peak memory 206216 kb
Host smart-6e7b9291-471d-4de0-ba5f-1f0280fad82d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2411823135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2411823135
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3199326577
Short name T1579
Test name
Test status
Simulation time 206122499 ps
CPU time 0.89 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:56 PM PDT 24
Peak memory 206196 kb
Host smart-20b70fa4-a9f0-4c69-b45a-34030852c6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
26577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3199326577
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2278366283
Short name T440
Test name
Test status
Simulation time 5733893173 ps
CPU time 37.57 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:08:30 PM PDT 24
Peak memory 206508 kb
Host smart-efeecc3b-acb5-46bc-9fe9-2e8c6c92561b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
66283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2278366283
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3419311188
Short name T400
Test name
Test status
Simulation time 4834038986 ps
CPU time 44.9 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:08:38 PM PDT 24
Peak memory 206420 kb
Host smart-8570570e-c20e-4445-80a8-e996ce15aaeb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3419311188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3419311188
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.551759906
Short name T943
Test name
Test status
Simulation time 151371507 ps
CPU time 0.81 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206148 kb
Host smart-89b12d4a-0e52-4d0a-a334-0144eb42b731
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=551759906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.551759906
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1635970751
Short name T1893
Test name
Test status
Simulation time 145845343 ps
CPU time 0.77 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:07:53 PM PDT 24
Peak memory 206192 kb
Host smart-7c3f6f7d-81ac-45c5-bdf2-2ab3d3c1919e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16359
70751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1635970751
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3198336956
Short name T137
Test name
Test status
Simulation time 192042656 ps
CPU time 0.84 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206212 kb
Host smart-814cd06a-1da4-4633-8981-dc54acdfe297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983
36956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3198336956
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2635253600
Short name T521
Test name
Test status
Simulation time 180628741 ps
CPU time 0.89 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:07:54 PM PDT 24
Peak memory 206204 kb
Host smart-54bbbb51-278b-433e-93b7-8a9d73c33472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26352
53600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2635253600
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3803719217
Short name T528
Test name
Test status
Simulation time 169977641 ps
CPU time 0.85 seconds
Started Jul 04 06:07:53 PM PDT 24
Finished Jul 04 06:07:54 PM PDT 24
Peak memory 206180 kb
Host smart-f4a8eea1-72fa-4122-a59d-2f7186efcef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38037
19217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3803719217
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1955541369
Short name T1199
Test name
Test status
Simulation time 154102384 ps
CPU time 0.78 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206192 kb
Host smart-d7ef8da6-15ce-46e0-b671-b3b168ac2da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19555
41369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1955541369
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2956284524
Short name T1062
Test name
Test status
Simulation time 150160922 ps
CPU time 0.78 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:07:53 PM PDT 24
Peak memory 206204 kb
Host smart-405736be-9223-409e-a7c1-d5494d93d991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29562
84524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2956284524
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3590240231
Short name T1769
Test name
Test status
Simulation time 211236998 ps
CPU time 0.89 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:07:53 PM PDT 24
Peak memory 206188 kb
Host smart-4698f9a6-5d53-4093-8942-439b6a44a489
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3590240231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3590240231
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.177448545
Short name T476
Test name
Test status
Simulation time 143867454 ps
CPU time 0.8 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206212 kb
Host smart-ef5a63e3-1138-4931-bfec-12e43ce7a86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17744
8545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.177448545
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4291810970
Short name T27
Test name
Test status
Simulation time 33282372 ps
CPU time 0.67 seconds
Started Jul 04 06:07:52 PM PDT 24
Finished Jul 04 06:07:53 PM PDT 24
Peak memory 206184 kb
Host smart-22044743-8402-4273-a8f8-e877d01ee6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42918
10970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4291810970
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3858833378
Short name T271
Test name
Test status
Simulation time 9354757633 ps
CPU time 20.35 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:08:15 PM PDT 24
Peak memory 206552 kb
Host smart-ad160ec8-fb55-403c-91ff-49a3c04863d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
33378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3858833378
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1246713768
Short name T1986
Test name
Test status
Simulation time 166242510 ps
CPU time 0.83 seconds
Started Jul 04 06:07:54 PM PDT 24
Finished Jul 04 06:07:55 PM PDT 24
Peak memory 206208 kb
Host smart-eddbb507-cd55-4596-8c16-58e22136e98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
13768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1246713768
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1724341711
Short name T1388
Test name
Test status
Simulation time 257784570 ps
CPU time 0.95 seconds
Started Jul 04 06:08:00 PM PDT 24
Finished Jul 04 06:08:01 PM PDT 24
Peak memory 206152 kb
Host smart-b819526a-fad5-4b6d-bfef-c154a692a24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
41711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1724341711
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1971836143
Short name T169
Test name
Test status
Simulation time 10053043790 ps
CPU time 65.32 seconds
Started Jul 04 06:07:58 PM PDT 24
Finished Jul 04 06:09:04 PM PDT 24
Peak memory 206512 kb
Host smart-881f82a3-6b75-4f92-acf2-c3f56f2e29b9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1971836143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1971836143
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.110806772
Short name T2691
Test name
Test status
Simulation time 8349014753 ps
CPU time 39.5 seconds
Started Jul 04 06:08:02 PM PDT 24
Finished Jul 04 06:08:42 PM PDT 24
Peak memory 206504 kb
Host smart-1d0e1c4a-d6bd-487c-8720-4e532fb954fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=110806772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.110806772
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3447873721
Short name T706
Test name
Test status
Simulation time 11825728992 ps
CPU time 79.31 seconds
Started Jul 04 06:08:01 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206420 kb
Host smart-ae8756e3-9d3e-4058-987d-0c9a83fd69d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3447873721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3447873721
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2943851500
Short name T638
Test name
Test status
Simulation time 255676413 ps
CPU time 0.93 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:01 PM PDT 24
Peak memory 206212 kb
Host smart-a5843b36-d53a-493e-be7b-28990bf90f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
51500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2943851500
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2061892203
Short name T324
Test name
Test status
Simulation time 229612668 ps
CPU time 0.84 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:00 PM PDT 24
Peak memory 206184 kb
Host smart-3915aef6-7afc-4d1f-8b30-5641384c1c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
92203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2061892203
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3280008435
Short name T569
Test name
Test status
Simulation time 146991458 ps
CPU time 0.86 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:00 PM PDT 24
Peak memory 206196 kb
Host smart-6c612bf1-12e4-4316-85c7-ae3e0f96b089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32800
08435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3280008435
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1092511163
Short name T2267
Test name
Test status
Simulation time 163645730 ps
CPU time 0.76 seconds
Started Jul 04 06:08:00 PM PDT 24
Finished Jul 04 06:08:01 PM PDT 24
Peak memory 206216 kb
Host smart-484010aa-182d-4eee-8f16-d44e190a7468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10925
11163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1092511163
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1117703085
Short name T774
Test name
Test status
Simulation time 159928537 ps
CPU time 0.82 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:00 PM PDT 24
Peak memory 206144 kb
Host smart-fd559fcc-ef0d-4e58-813e-b9ac79758174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11177
03085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1117703085
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.840727658
Short name T338
Test name
Test status
Simulation time 206250840 ps
CPU time 0.91 seconds
Started Jul 04 06:08:03 PM PDT 24
Finished Jul 04 06:08:04 PM PDT 24
Peak memory 206192 kb
Host smart-c5d1af6e-c2dd-4e6d-814d-3476a4172101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84072
7658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.840727658
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1583912014
Short name T2259
Test name
Test status
Simulation time 5446596220 ps
CPU time 37.8 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:37 PM PDT 24
Peak memory 206516 kb
Host smart-fbdc8165-2e4f-47d3-88f8-4931b55425f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1583912014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1583912014
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2601957898
Short name T545
Test name
Test status
Simulation time 188168854 ps
CPU time 0.85 seconds
Started Jul 04 06:08:00 PM PDT 24
Finished Jul 04 06:08:02 PM PDT 24
Peak memory 206224 kb
Host smart-a252a69b-586a-4103-9d68-33e5537ee023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
57898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2601957898
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.506436779
Short name T1913
Test name
Test status
Simulation time 146512456 ps
CPU time 0.78 seconds
Started Jul 04 06:07:58 PM PDT 24
Finished Jul 04 06:07:59 PM PDT 24
Peak memory 206196 kb
Host smart-2c535ce2-b1fb-4595-821a-888c6e99f9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50643
6779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.506436779
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3364433521
Short name T1468
Test name
Test status
Simulation time 1206697783 ps
CPU time 2.79 seconds
Started Jul 04 06:08:00 PM PDT 24
Finished Jul 04 06:08:03 PM PDT 24
Peak memory 206440 kb
Host smart-6e8df568-9d0e-4ef1-b0ea-63303e24f0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33644
33521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3364433521
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3731859770
Short name T1683
Test name
Test status
Simulation time 5051358446 ps
CPU time 37.34 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:37 PM PDT 24
Peak memory 206472 kb
Host smart-bc4502e2-776b-48b4-ba95-0f4ce57a2663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37318
59770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3731859770
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2281271805
Short name T991
Test name
Test status
Simulation time 64414388 ps
CPU time 0.68 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:28 PM PDT 24
Peak memory 206252 kb
Host smart-ece7b22b-bf04-4924-9ea8-c57128c57295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2281271805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2281271805
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2784853005
Short name T2588
Test name
Test status
Simulation time 3611227970 ps
CPU time 4.19 seconds
Started Jul 04 06:08:00 PM PDT 24
Finished Jul 04 06:08:04 PM PDT 24
Peak memory 206268 kb
Host smart-12e90567-2859-4dc2-b029-0347d31dc0f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2784853005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2784853005
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2839547212
Short name T1143
Test name
Test status
Simulation time 13361380583 ps
CPU time 14.26 seconds
Started Jul 04 06:08:01 PM PDT 24
Finished Jul 04 06:08:16 PM PDT 24
Peak memory 206468 kb
Host smart-4cb8a135-0c52-4a8d-8395-eb44c9be357e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2839547212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2839547212
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2106643315
Short name T1208
Test name
Test status
Simulation time 23568665275 ps
CPU time 24.35 seconds
Started Jul 04 06:08:01 PM PDT 24
Finished Jul 04 06:08:25 PM PDT 24
Peak memory 206428 kb
Host smart-dad58216-7662-4984-818b-d756fffae8ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2106643315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2106643315
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2895666393
Short name T1209
Test name
Test status
Simulation time 198551959 ps
CPU time 0.83 seconds
Started Jul 04 06:07:59 PM PDT 24
Finished Jul 04 06:08:00 PM PDT 24
Peak memory 206176 kb
Host smart-0c793dd3-f6af-4e4c-9d71-f38f4c89e9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28956
66393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2895666393
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3277015406
Short name T110
Test name
Test status
Simulation time 185265933 ps
CPU time 0.87 seconds
Started Jul 04 06:08:00 PM PDT 24
Finished Jul 04 06:08:01 PM PDT 24
Peak memory 206212 kb
Host smart-3925bc90-d9ef-4c98-af2f-44bb4b963894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770
15406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3277015406
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3455604119
Short name T2372
Test name
Test status
Simulation time 159852706 ps
CPU time 0.77 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:08:09 PM PDT 24
Peak memory 206200 kb
Host smart-de9fde51-f61e-459c-930b-71a720b50f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34556
04119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3455604119
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1431455239
Short name T1669
Test name
Test status
Simulation time 495332241 ps
CPU time 1.39 seconds
Started Jul 04 06:08:09 PM PDT 24
Finished Jul 04 06:08:11 PM PDT 24
Peak memory 206204 kb
Host smart-7e37e7c0-176a-4578-984d-f22c69884849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314
55239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1431455239
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.1402017572
Short name T1533
Test name
Test status
Simulation time 326901416 ps
CPU time 1.22 seconds
Started Jul 04 06:08:09 PM PDT 24
Finished Jul 04 06:08:10 PM PDT 24
Peak memory 206192 kb
Host smart-1a955c74-4bcf-42ce-b953-9454e7b86ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14020
17572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.1402017572
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1336131018
Short name T1455
Test name
Test status
Simulation time 137455933 ps
CPU time 0.79 seconds
Started Jul 04 06:08:05 PM PDT 24
Finished Jul 04 06:08:06 PM PDT 24
Peak memory 206180 kb
Host smart-d26dfb50-2317-4415-8ad2-a7710765e51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
31018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1336131018
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1459255262
Short name T1890
Test name
Test status
Simulation time 55527579 ps
CPU time 0.65 seconds
Started Jul 04 06:08:05 PM PDT 24
Finished Jul 04 06:08:06 PM PDT 24
Peak memory 206216 kb
Host smart-d8baa4ee-7c26-4f19-a368-ffb008b66010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14592
55262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1459255262
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1909804976
Short name T880
Test name
Test status
Simulation time 839693729 ps
CPU time 2.09 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:08:11 PM PDT 24
Peak memory 206388 kb
Host smart-f41792ed-9f48-4075-9615-81f9f87a1210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
04976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1909804976
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3735734350
Short name T2163
Test name
Test status
Simulation time 156317417 ps
CPU time 1.53 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:08:09 PM PDT 24
Peak memory 206456 kb
Host smart-4bb42a53-96ee-4595-b7d0-640b110de48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357
34350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3735734350
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3887162309
Short name T1697
Test name
Test status
Simulation time 179850387 ps
CPU time 0.8 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:08:09 PM PDT 24
Peak memory 206208 kb
Host smart-8a2efa6b-7115-4269-b504-86bb20eab7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
62309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3887162309
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.218648749
Short name T2366
Test name
Test status
Simulation time 179863882 ps
CPU time 0.79 seconds
Started Jul 04 06:08:09 PM PDT 24
Finished Jul 04 06:08:10 PM PDT 24
Peak memory 206204 kb
Host smart-0545ee2d-e993-4528-8cc4-b8e48a3bae19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
8749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.218648749
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3295973130
Short name T520
Test name
Test status
Simulation time 174747642 ps
CPU time 0.8 seconds
Started Jul 04 06:08:05 PM PDT 24
Finished Jul 04 06:08:06 PM PDT 24
Peak memory 206176 kb
Host smart-1d44dc6a-6375-4ddc-856b-6c6df36d1883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32959
73130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3295973130
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1125349125
Short name T2192
Test name
Test status
Simulation time 7526446403 ps
CPU time 204.47 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 206504 kb
Host smart-6a452ebf-583a-4152-8297-6d710fee497f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1125349125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1125349125
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.641250435
Short name T941
Test name
Test status
Simulation time 192938975 ps
CPU time 0.9 seconds
Started Jul 04 06:08:09 PM PDT 24
Finished Jul 04 06:08:10 PM PDT 24
Peak memory 206208 kb
Host smart-73fd6bd0-fa77-47d2-ad05-3d6cc77913c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64125
0435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.641250435
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3926912894
Short name T1550
Test name
Test status
Simulation time 23265729873 ps
CPU time 22.66 seconds
Started Jul 04 06:08:07 PM PDT 24
Finished Jul 04 06:08:30 PM PDT 24
Peak memory 206268 kb
Host smart-d20264d8-9925-4e90-b5e5-d4bddbe357c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
12894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3926912894
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.86689670
Short name T2083
Test name
Test status
Simulation time 3310712611 ps
CPU time 3.92 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:08:12 PM PDT 24
Peak memory 206208 kb
Host smart-0f1808c5-a827-49c9-b27f-07953c9eabae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86689
670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.86689670
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1053097357
Short name T1557
Test name
Test status
Simulation time 11895817996 ps
CPU time 341.86 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:13:50 PM PDT 24
Peak memory 206520 kb
Host smart-8924d7b6-f580-41f3-ad0f-6d179206e9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530
97357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1053097357
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2320515968
Short name T1257
Test name
Test status
Simulation time 7598029875 ps
CPU time 53.04 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:09:01 PM PDT 24
Peak memory 206508 kb
Host smart-18581794-027d-4231-9af1-e0551580c189
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2320515968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2320515968
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3803388484
Short name T2587
Test name
Test status
Simulation time 294647596 ps
CPU time 0.94 seconds
Started Jul 04 06:08:08 PM PDT 24
Finished Jul 04 06:08:09 PM PDT 24
Peak memory 206148 kb
Host smart-ecfed582-605f-4700-90f7-2c8b55ffa65c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3803388484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3803388484
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.883858946
Short name T342
Test name
Test status
Simulation time 219533250 ps
CPU time 0.85 seconds
Started Jul 04 06:08:05 PM PDT 24
Finished Jul 04 06:08:07 PM PDT 24
Peak memory 206224 kb
Host smart-63ae66b0-4d37-4261-b0aa-7ca60d2606a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88385
8946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.883858946
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2379240184
Short name T553
Test name
Test status
Simulation time 3731670217 ps
CPU time 101.49 seconds
Started Jul 04 06:08:05 PM PDT 24
Finished Jul 04 06:09:46 PM PDT 24
Peak memory 206480 kb
Host smart-32398e57-cdf0-43f7-80b4-5cec3c203e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
40184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2379240184
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1962756830
Short name T2298
Test name
Test status
Simulation time 3498358078 ps
CPU time 31.32 seconds
Started Jul 04 06:08:06 PM PDT 24
Finished Jul 04 06:08:38 PM PDT 24
Peak memory 206456 kb
Host smart-331ce095-6e90-4e78-b8fd-2435fa2b73e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1962756830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1962756830
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3366557639
Short name T2577
Test name
Test status
Simulation time 152602500 ps
CPU time 0.78 seconds
Started Jul 04 06:08:07 PM PDT 24
Finished Jul 04 06:08:08 PM PDT 24
Peak memory 206212 kb
Host smart-6d21531e-4cd6-4c1f-b1e5-290e44c12df2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3366557639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3366557639
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2904686689
Short name T1317
Test name
Test status
Simulation time 159396633 ps
CPU time 0.8 seconds
Started Jul 04 06:08:06 PM PDT 24
Finished Jul 04 06:08:07 PM PDT 24
Peak memory 206208 kb
Host smart-60032f48-fed1-438c-8d08-9f64177335a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29046
86689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2904686689
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1094308861
Short name T1635
Test name
Test status
Simulation time 203800999 ps
CPU time 0.84 seconds
Started Jul 04 06:08:11 PM PDT 24
Finished Jul 04 06:08:12 PM PDT 24
Peak memory 206200 kb
Host smart-2ac235f4-36bc-4c85-8f21-1c9ba007c811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
08861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1094308861
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.4227247548
Short name T1302
Test name
Test status
Simulation time 181682596 ps
CPU time 0.81 seconds
Started Jul 04 06:08:12 PM PDT 24
Finished Jul 04 06:08:13 PM PDT 24
Peak memory 206176 kb
Host smart-3263fe05-4c95-49de-b48c-e020324142ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42272
47548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.4227247548
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2953528408
Short name T2597
Test name
Test status
Simulation time 179826309 ps
CPU time 0.85 seconds
Started Jul 04 06:08:14 PM PDT 24
Finished Jul 04 06:08:15 PM PDT 24
Peak memory 206168 kb
Host smart-9977c9ff-026d-4222-ab58-a4cb67e3aa55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29535
28408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2953528408
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1351318893
Short name T1941
Test name
Test status
Simulation time 173198635 ps
CPU time 0.81 seconds
Started Jul 04 06:08:13 PM PDT 24
Finished Jul 04 06:08:14 PM PDT 24
Peak memory 206212 kb
Host smart-366c3120-cbd0-485a-91e4-691ccd82a975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
18893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1351318893
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2889909045
Short name T1389
Test name
Test status
Simulation time 151965761 ps
CPU time 0.78 seconds
Started Jul 04 06:08:12 PM PDT 24
Finished Jul 04 06:08:13 PM PDT 24
Peak memory 206212 kb
Host smart-4ebfdcb7-ed04-4b02-a8b3-5527c4685901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28899
09045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2889909045
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1059863474
Short name T666
Test name
Test status
Simulation time 212095681 ps
CPU time 0.88 seconds
Started Jul 04 06:08:13 PM PDT 24
Finished Jul 04 06:08:14 PM PDT 24
Peak memory 206180 kb
Host smart-dd8d62e2-a7c0-4b37-a34d-8b56bae0dc61
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1059863474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1059863474
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.4289642498
Short name T1582
Test name
Test status
Simulation time 134796745 ps
CPU time 0.72 seconds
Started Jul 04 06:08:13 PM PDT 24
Finished Jul 04 06:08:13 PM PDT 24
Peak memory 206180 kb
Host smart-af7f11fd-af7a-4353-acc7-e6e1b6ececb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42896
42498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.4289642498
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3957314781
Short name T1029
Test name
Test status
Simulation time 103244805 ps
CPU time 0.68 seconds
Started Jul 04 06:08:14 PM PDT 24
Finished Jul 04 06:08:15 PM PDT 24
Peak memory 206200 kb
Host smart-03b22777-252c-4401-8ae4-6796b73d4907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
14781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3957314781
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.920742718
Short name T1754
Test name
Test status
Simulation time 13291037379 ps
CPU time 30.1 seconds
Started Jul 04 06:08:14 PM PDT 24
Finished Jul 04 06:08:44 PM PDT 24
Peak memory 206504 kb
Host smart-aacae624-110d-45ce-a332-2a4b83a3b62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92074
2718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.920742718
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.666770053
Short name T2595
Test name
Test status
Simulation time 160800276 ps
CPU time 0.79 seconds
Started Jul 04 06:08:14 PM PDT 24
Finished Jul 04 06:08:15 PM PDT 24
Peak memory 206212 kb
Host smart-9b4857d0-d99f-40ed-8455-b443711c0048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66677
0053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.666770053
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1070602627
Short name T2096
Test name
Test status
Simulation time 163569450 ps
CPU time 0.79 seconds
Started Jul 04 06:08:12 PM PDT 24
Finished Jul 04 06:08:13 PM PDT 24
Peak memory 206204 kb
Host smart-64d90588-f70a-4412-b645-abe056416978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10706
02627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1070602627
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.124180546
Short name T2310
Test name
Test status
Simulation time 7681946498 ps
CPU time 38.86 seconds
Started Jul 04 06:08:14 PM PDT 24
Finished Jul 04 06:08:53 PM PDT 24
Peak memory 206460 kb
Host smart-46919e7c-18ce-427f-8a8c-b0b7c3422c8b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=124180546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.124180546
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1068546736
Short name T153
Test name
Test status
Simulation time 4241138020 ps
CPU time 25.24 seconds
Started Jul 04 06:08:12 PM PDT 24
Finished Jul 04 06:08:37 PM PDT 24
Peak memory 206484 kb
Host smart-e87981eb-cc0e-434b-88a6-7b5e0a5307c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1068546736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1068546736
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3947104570
Short name T674
Test name
Test status
Simulation time 13304731625 ps
CPU time 92.5 seconds
Started Jul 04 06:08:13 PM PDT 24
Finished Jul 04 06:09:46 PM PDT 24
Peak memory 206452 kb
Host smart-3cea1fda-e68d-453e-b6c7-6cf19ade7a66
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3947104570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3947104570
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.398831255
Short name T1672
Test name
Test status
Simulation time 246560449 ps
CPU time 0.98 seconds
Started Jul 04 06:08:13 PM PDT 24
Finished Jul 04 06:08:14 PM PDT 24
Peak memory 206160 kb
Host smart-f704ce2b-96d9-4eb0-8eed-323cd246c56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39883
1255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.398831255
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1392108192
Short name T1072
Test name
Test status
Simulation time 161511895 ps
CPU time 0.82 seconds
Started Jul 04 06:08:13 PM PDT 24
Finished Jul 04 06:08:14 PM PDT 24
Peak memory 206208 kb
Host smart-a4bed1ac-4bf4-4af2-9c32-17a450c7fc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
08192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1392108192
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1977921015
Short name T2063
Test name
Test status
Simulation time 167758786 ps
CPU time 0.76 seconds
Started Jul 04 06:08:23 PM PDT 24
Finished Jul 04 06:08:24 PM PDT 24
Peak memory 206196 kb
Host smart-b0e7c4ff-61f0-4a56-a71f-8b24f26bf208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19779
21015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1977921015
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2124772293
Short name T793
Test name
Test status
Simulation time 146112762 ps
CPU time 0.75 seconds
Started Jul 04 06:08:20 PM PDT 24
Finished Jul 04 06:08:21 PM PDT 24
Peak memory 206192 kb
Host smart-55c9acf1-cbea-46b0-88b6-3fbd7364d868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
72293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2124772293
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1155857567
Short name T588
Test name
Test status
Simulation time 161121118 ps
CPU time 0.79 seconds
Started Jul 04 06:08:20 PM PDT 24
Finished Jul 04 06:08:21 PM PDT 24
Peak memory 206176 kb
Host smart-ea03699d-70fb-4c3b-833a-b21727615333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11558
57567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1155857567
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1331881656
Short name T851
Test name
Test status
Simulation time 215358845 ps
CPU time 0.87 seconds
Started Jul 04 06:08:19 PM PDT 24
Finished Jul 04 06:08:20 PM PDT 24
Peak memory 206208 kb
Host smart-d91d79d0-a3b5-4b6a-8d6c-b7b8e5e7f2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13318
81656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1331881656
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.765272891
Short name T465
Test name
Test status
Simulation time 6665704008 ps
CPU time 192.84 seconds
Started Jul 04 06:08:21 PM PDT 24
Finished Jul 04 06:11:34 PM PDT 24
Peak memory 206520 kb
Host smart-12dee9a6-7623-494d-bcf8-1b5f80bf9f26
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=765272891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.765272891
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1445324118
Short name T2624
Test name
Test status
Simulation time 180248718 ps
CPU time 0.9 seconds
Started Jul 04 06:08:21 PM PDT 24
Finished Jul 04 06:08:22 PM PDT 24
Peak memory 206176 kb
Host smart-c04d6ec1-d667-4ddc-a12f-22b502dfcee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14453
24118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1445324118
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2917709518
Short name T1747
Test name
Test status
Simulation time 173419569 ps
CPU time 0.83 seconds
Started Jul 04 06:08:19 PM PDT 24
Finished Jul 04 06:08:20 PM PDT 24
Peak memory 206128 kb
Host smart-3908df50-2019-4345-b89d-617761902b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29177
09518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2917709518
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3783944501
Short name T2626
Test name
Test status
Simulation time 1022405974 ps
CPU time 2.12 seconds
Started Jul 04 06:08:24 PM PDT 24
Finished Jul 04 06:08:26 PM PDT 24
Peak memory 206380 kb
Host smart-801f2fbf-0c66-4e67-b1d1-af97fb422041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
44501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3783944501
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.222926646
Short name T742
Test name
Test status
Simulation time 5147385787 ps
CPU time 46.65 seconds
Started Jul 04 06:08:22 PM PDT 24
Finished Jul 04 06:09:08 PM PDT 24
Peak memory 206460 kb
Host smart-24b5019c-bdf0-453f-a0ae-c1ea693e8e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
6646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.222926646
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.4268264618
Short name T205
Test name
Test status
Simulation time 65555747 ps
CPU time 0.66 seconds
Started Jul 04 06:08:41 PM PDT 24
Finished Jul 04 06:08:41 PM PDT 24
Peak memory 206248 kb
Host smart-694e2460-a5ba-4767-ba0d-bff5ca45171f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4268264618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.4268264618
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2927819887
Short name T949
Test name
Test status
Simulation time 4219106403 ps
CPU time 4.74 seconds
Started Jul 04 06:08:26 PM PDT 24
Finished Jul 04 06:08:31 PM PDT 24
Peak memory 206292 kb
Host smart-a19a379f-e25e-4f4a-b1c0-bd38c8c8d05a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2927819887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2927819887
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1558196877
Short name T1198
Test name
Test status
Simulation time 13321144435 ps
CPU time 13.36 seconds
Started Jul 04 06:08:32 PM PDT 24
Finished Jul 04 06:08:45 PM PDT 24
Peak memory 205980 kb
Host smart-73729dfc-bf37-4841-914f-cf481bffebc4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1558196877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1558196877
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1180697537
Short name T2437
Test name
Test status
Simulation time 23314851888 ps
CPU time 24.17 seconds
Started Jul 04 06:08:31 PM PDT 24
Finished Jul 04 06:08:55 PM PDT 24
Peak memory 206268 kb
Host smart-af362e59-e3f7-4888-81ba-27ce482b3c08
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1180697537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.1180697537
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4224691276
Short name T341
Test name
Test status
Simulation time 186561030 ps
CPU time 0.83 seconds
Started Jul 04 06:08:28 PM PDT 24
Finished Jul 04 06:08:29 PM PDT 24
Peak memory 206164 kb
Host smart-987020d9-7c7f-4ab4-9faa-a9c79b85072d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42246
91276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4224691276
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1353128017
Short name T2376
Test name
Test status
Simulation time 158590331 ps
CPU time 0.78 seconds
Started Jul 04 06:08:26 PM PDT 24
Finished Jul 04 06:08:27 PM PDT 24
Peak memory 206164 kb
Host smart-a2f84c83-9c3d-42de-8d9c-25471f96494b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
28017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1353128017
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.463029796
Short name T191
Test name
Test status
Simulation time 475234821 ps
CPU time 1.59 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:29 PM PDT 24
Peak memory 206188 kb
Host smart-fe788435-4d13-4f62-8e0c-623393deb338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46302
9796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.463029796
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3781979749
Short name T2503
Test name
Test status
Simulation time 508214187 ps
CPU time 1.53 seconds
Started Jul 04 06:08:32 PM PDT 24
Finished Jul 04 06:08:34 PM PDT 24
Peak memory 205896 kb
Host smart-bd6b0773-dd35-4def-96ca-03f7c17acb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
79749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3781979749
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.218935072
Short name T2144
Test name
Test status
Simulation time 20592559263 ps
CPU time 45.34 seconds
Started Jul 04 06:08:28 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206384 kb
Host smart-d24f5958-b1cf-4ab1-ad05-678cca38c35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21893
5072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.218935072
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.4159060556
Short name T1980
Test name
Test status
Simulation time 409899168 ps
CPU time 1.39 seconds
Started Jul 04 06:08:30 PM PDT 24
Finished Jul 04 06:08:32 PM PDT 24
Peak memory 206196 kb
Host smart-62760ad1-f546-49bf-947e-d44dfaf6179d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41590
60556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.4159060556
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1185092373
Short name T968
Test name
Test status
Simulation time 136499124 ps
CPU time 0.73 seconds
Started Jul 04 06:08:29 PM PDT 24
Finished Jul 04 06:08:30 PM PDT 24
Peak memory 206192 kb
Host smart-128de586-efa7-40a1-bdec-8f8b056ee852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
92373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1185092373
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2895952134
Short name T953
Test name
Test status
Simulation time 30351194 ps
CPU time 0.67 seconds
Started Jul 04 06:08:28 PM PDT 24
Finished Jul 04 06:08:29 PM PDT 24
Peak memory 206168 kb
Host smart-6bb53b84-abf4-45de-b037-635322cde0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28959
52134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2895952134
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3500443704
Short name T1105
Test name
Test status
Simulation time 953539087 ps
CPU time 2.13 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:30 PM PDT 24
Peak memory 206424 kb
Host smart-a9843089-b9ad-45cc-a1a0-564bd55550d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004
43704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3500443704
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.195398763
Short name T2529
Test name
Test status
Simulation time 395838526 ps
CPU time 2.19 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:30 PM PDT 24
Peak memory 206452 kb
Host smart-f21fe66c-c060-44e1-8d5d-55218c7cf0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19539
8763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.195398763
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1418810992
Short name T118
Test name
Test status
Simulation time 191033177 ps
CPU time 0.88 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:28 PM PDT 24
Peak memory 206140 kb
Host smart-124a194d-0a3c-41f3-ad8e-c638022caab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14188
10992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1418810992
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2086162388
Short name T2465
Test name
Test status
Simulation time 138825570 ps
CPU time 0.77 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:28 PM PDT 24
Peak memory 206208 kb
Host smart-c4f57c16-a9d4-4377-8584-d72075d2c8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
62388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2086162388
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2982222787
Short name T878
Test name
Test status
Simulation time 190866079 ps
CPU time 0.85 seconds
Started Jul 04 06:08:32 PM PDT 24
Finished Jul 04 06:08:33 PM PDT 24
Peak memory 206060 kb
Host smart-82bd705f-2cd2-4dca-ada2-7d382e350e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822
22787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2982222787
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.3982671089
Short name T296
Test name
Test status
Simulation time 6166282400 ps
CPU time 43.25 seconds
Started Jul 04 06:08:32 PM PDT 24
Finished Jul 04 06:09:15 PM PDT 24
Peak memory 206272 kb
Host smart-d57daa09-b4d4-4caf-a73c-2ee6f4ec36c2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3982671089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3982671089
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.419278043
Short name T1833
Test name
Test status
Simulation time 205567645 ps
CPU time 0.89 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:28 PM PDT 24
Peak memory 206220 kb
Host smart-5e993d4e-d1bb-43a8-be96-7ea9026e662e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41927
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.419278043
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2180281372
Short name T1613
Test name
Test status
Simulation time 23300187290 ps
CPU time 26.46 seconds
Started Jul 04 06:08:29 PM PDT 24
Finished Jul 04 06:08:56 PM PDT 24
Peak memory 206256 kb
Host smart-e338ca95-90ee-44f4-87ef-113b7aa479b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21802
81372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2180281372
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2062786040
Short name T1718
Test name
Test status
Simulation time 3265538254 ps
CPU time 3.65 seconds
Started Jul 04 06:08:27 PM PDT 24
Finished Jul 04 06:08:31 PM PDT 24
Peak memory 206244 kb
Host smart-3d982b42-01a6-4bba-99d7-dec877631724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627
86040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2062786040
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.1550042760
Short name T1884
Test name
Test status
Simulation time 6553744114 ps
CPU time 46.77 seconds
Started Jul 04 06:08:31 PM PDT 24
Finished Jul 04 06:09:18 PM PDT 24
Peak memory 206532 kb
Host smart-ebe07ef4-cd64-4cb4-bd8b-9f033d6a6208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15500
42760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1550042760
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.33065352
Short name T615
Test name
Test status
Simulation time 5650065819 ps
CPU time 166.31 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:11:20 PM PDT 24
Peak memory 206516 kb
Host smart-8df4993a-41ab-4f15-bb7f-0b9b5463b8c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=33065352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.33065352
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2270937680
Short name T1552
Test name
Test status
Simulation time 329490167 ps
CPU time 1.14 seconds
Started Jul 04 06:08:38 PM PDT 24
Finished Jul 04 06:08:39 PM PDT 24
Peak memory 206200 kb
Host smart-f287e416-d898-4f7a-b1c2-b604cf81c217
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2270937680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2270937680
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1878971805
Short name T2231
Test name
Test status
Simulation time 208695373 ps
CPU time 0.88 seconds
Started Jul 04 06:08:35 PM PDT 24
Finished Jul 04 06:08:36 PM PDT 24
Peak memory 206208 kb
Host smart-c4d39db6-97a9-447d-94f2-1d48abe3d9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
71805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1878971805
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.610829484
Short name T650
Test name
Test status
Simulation time 5128655269 ps
CPU time 37.85 seconds
Started Jul 04 06:08:35 PM PDT 24
Finished Jul 04 06:09:13 PM PDT 24
Peak memory 206480 kb
Host smart-337bead4-46ca-41d6-ac2b-92bcc215bece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61082
9484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.610829484
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1521996453
Short name T1643
Test name
Test status
Simulation time 6366522658 ps
CPU time 59.1 seconds
Started Jul 04 06:08:33 PM PDT 24
Finished Jul 04 06:09:32 PM PDT 24
Peak memory 206524 kb
Host smart-d4a099e7-5a9b-415e-a104-0d045929acc0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1521996453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1521996453
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.705534175
Short name T508
Test name
Test status
Simulation time 176087982 ps
CPU time 0.86 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 206188 kb
Host smart-42986041-56c5-4878-8e9f-5ab4eeab483b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=705534175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.705534175
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2753341102
Short name T439
Test name
Test status
Simulation time 150194016 ps
CPU time 0.79 seconds
Started Jul 04 06:08:35 PM PDT 24
Finished Jul 04 06:08:36 PM PDT 24
Peak memory 206196 kb
Host smart-d6a07e6d-9c93-4c5d-a8cf-fcd5e51e8f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27533
41102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2753341102
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3013337420
Short name T132
Test name
Test status
Simulation time 217389673 ps
CPU time 0.95 seconds
Started Jul 04 06:08:38 PM PDT 24
Finished Jul 04 06:08:39 PM PDT 24
Peak memory 206180 kb
Host smart-97184f0c-c617-4f4c-a484-c2bacdb9373d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30133
37420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3013337420
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1097577949
Short name T1229
Test name
Test status
Simulation time 170395699 ps
CPU time 0.85 seconds
Started Jul 04 06:08:33 PM PDT 24
Finished Jul 04 06:08:34 PM PDT 24
Peak memory 206208 kb
Host smart-f97ad675-faeb-4884-8c0f-8653bda1bc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10975
77949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1097577949
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1633150722
Short name T2641
Test name
Test status
Simulation time 198335668 ps
CPU time 0.88 seconds
Started Jul 04 06:08:35 PM PDT 24
Finished Jul 04 06:08:36 PM PDT 24
Peak memory 206188 kb
Host smart-35c3722c-9478-4a60-ae48-40719e55f46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16331
50722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1633150722
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1048514316
Short name T2327
Test name
Test status
Simulation time 235520955 ps
CPU time 0.85 seconds
Started Jul 04 06:08:35 PM PDT 24
Finished Jul 04 06:08:36 PM PDT 24
Peak memory 206204 kb
Host smart-379de0bb-64dc-4c1b-a32b-b2b08f223cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485
14316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1048514316
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.620879695
Short name T1654
Test name
Test status
Simulation time 190161598 ps
CPU time 0.81 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 206180 kb
Host smart-1fca3371-905e-466e-9e2e-8a62611f2f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62087
9695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.620879695
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1730807723
Short name T407
Test name
Test status
Simulation time 183214869 ps
CPU time 0.85 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 206220 kb
Host smart-cf90d56b-f172-4b89-a738-6777ddb5fc50
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1730807723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1730807723
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2040179845
Short name T2221
Test name
Test status
Simulation time 143705248 ps
CPU time 0.8 seconds
Started Jul 04 06:08:36 PM PDT 24
Finished Jul 04 06:08:37 PM PDT 24
Peak memory 206128 kb
Host smart-a5e61692-4344-4293-8df0-38b17feb251b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401
79845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2040179845
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.346918128
Short name T826
Test name
Test status
Simulation time 34056429 ps
CPU time 0.64 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 206168 kb
Host smart-6adc17da-ce8a-4349-a0d2-f13b8e1c4c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34691
8128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.346918128
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3661213052
Short name T1593
Test name
Test status
Simulation time 15015986364 ps
CPU time 37.73 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:09:12 PM PDT 24
Peak memory 214660 kb
Host smart-c5da3d0d-fb40-4ec8-9df0-fa37ea8d7037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36612
13052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3661213052
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.638247404
Short name T2380
Test name
Test status
Simulation time 191006882 ps
CPU time 0.84 seconds
Started Jul 04 06:08:36 PM PDT 24
Finished Jul 04 06:08:37 PM PDT 24
Peak memory 206212 kb
Host smart-97ffdf82-54bb-4cbf-91a5-bb8c6db1a752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63824
7404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.638247404
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3886363274
Short name T1953
Test name
Test status
Simulation time 231619336 ps
CPU time 0.87 seconds
Started Jul 04 06:08:37 PM PDT 24
Finished Jul 04 06:08:38 PM PDT 24
Peak memory 206200 kb
Host smart-d2126da7-4a3f-430f-9200-26e105959b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
63274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3886363274
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1872402962
Short name T654
Test name
Test status
Simulation time 11188844532 ps
CPU time 94.68 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:10:09 PM PDT 24
Peak memory 206464 kb
Host smart-882ca6ab-1b09-41f7-bf07-5501223fd337
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1872402962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1872402962
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3639129945
Short name T197
Test name
Test status
Simulation time 9429937841 ps
CPU time 154.16 seconds
Started Jul 04 06:08:37 PM PDT 24
Finished Jul 04 06:11:12 PM PDT 24
Peak memory 206556 kb
Host smart-3f6eaf2c-508d-46eb-9e30-226d073b316e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3639129945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3639129945
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2756722366
Short name T1835
Test name
Test status
Simulation time 12138578207 ps
CPU time 90.76 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:10:04 PM PDT 24
Peak memory 206508 kb
Host smart-f00c3e9e-1486-494b-a0b8-d2b1183691f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2756722366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2756722366
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.632178559
Short name T1537
Test name
Test status
Simulation time 267478542 ps
CPU time 0.97 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 206176 kb
Host smart-71b41465-b040-4698-a70b-30c52d715bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63217
8559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.632178559
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2875257053
Short name T1646
Test name
Test status
Simulation time 173780021 ps
CPU time 0.77 seconds
Started Jul 04 06:08:34 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 206212 kb
Host smart-b40964c5-8dd7-4d36-a7cb-85a554b6da30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28752
57053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2875257053
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.704037313
Short name T1703
Test name
Test status
Simulation time 183970735 ps
CPU time 0.78 seconds
Started Jul 04 06:08:35 PM PDT 24
Finished Jul 04 06:08:36 PM PDT 24
Peak memory 206184 kb
Host smart-6ec86ad0-24ca-4371-9a71-37e3650c40b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70403
7313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.704037313
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4169464664
Short name T2124
Test name
Test status
Simulation time 159250142 ps
CPU time 0.79 seconds
Started Jul 04 06:08:41 PM PDT 24
Finished Jul 04 06:08:42 PM PDT 24
Peak memory 206208 kb
Host smart-faa536f4-c914-492c-86c1-e5d384202cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
64664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4169464664
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.344418002
Short name T1156
Test name
Test status
Simulation time 169613576 ps
CPU time 0.82 seconds
Started Jul 04 06:08:41 PM PDT 24
Finished Jul 04 06:08:42 PM PDT 24
Peak memory 206192 kb
Host smart-9b6930de-9528-4f30-9aad-1d310de2cd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34441
8002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.344418002
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3239537803
Short name T796
Test name
Test status
Simulation time 178012910 ps
CPU time 0.85 seconds
Started Jul 04 06:08:41 PM PDT 24
Finished Jul 04 06:08:43 PM PDT 24
Peak memory 206196 kb
Host smart-527016dd-a582-42e9-ae2e-7dd85adca501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32395
37803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3239537803
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1211269400
Short name T1012
Test name
Test status
Simulation time 4575163509 ps
CPU time 39.48 seconds
Started Jul 04 06:08:41 PM PDT 24
Finished Jul 04 06:09:20 PM PDT 24
Peak memory 206504 kb
Host smart-a072020d-e9cb-4282-b48e-d8ad697f6e64
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1211269400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1211269400
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3340379642
Short name T2543
Test name
Test status
Simulation time 181223555 ps
CPU time 0.82 seconds
Started Jul 04 06:08:42 PM PDT 24
Finished Jul 04 06:08:43 PM PDT 24
Peak memory 206180 kb
Host smart-72ad3e7f-6d5d-4f0c-a5af-4c8a3a675bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33403
79642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3340379642
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.4174573312
Short name T1627
Test name
Test status
Simulation time 189545338 ps
CPU time 0.81 seconds
Started Jul 04 06:08:43 PM PDT 24
Finished Jul 04 06:08:44 PM PDT 24
Peak memory 206204 kb
Host smart-8f4cb755-4e52-4d98-aff1-438ca1544d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745
73312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.4174573312
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2083449881
Short name T356
Test name
Test status
Simulation time 1142510748 ps
CPU time 2.56 seconds
Started Jul 04 06:08:48 PM PDT 24
Finished Jul 04 06:08:50 PM PDT 24
Peak memory 206364 kb
Host smart-a0e97651-61a2-4be2-be69-62979297704d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834
49881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2083449881
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3021292666
Short name T813
Test name
Test status
Simulation time 7713446046 ps
CPU time 60.77 seconds
Started Jul 04 06:08:45 PM PDT 24
Finished Jul 04 06:09:46 PM PDT 24
Peak memory 206440 kb
Host smart-0fee8f34-3e51-4fce-add6-eb9d8c2e32cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30212
92666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3021292666
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.376830953
Short name T1501
Test name
Test status
Simulation time 69450895 ps
CPU time 0.68 seconds
Started Jul 04 06:09:04 PM PDT 24
Finished Jul 04 06:09:05 PM PDT 24
Peak memory 206268 kb
Host smart-1be80b5d-4f94-46fa-9028-72ee052c7638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=376830953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.376830953
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2845350984
Short name T1178
Test name
Test status
Simulation time 3477642865 ps
CPU time 4.1 seconds
Started Jul 04 06:08:42 PM PDT 24
Finished Jul 04 06:08:46 PM PDT 24
Peak memory 206436 kb
Host smart-2783d797-7c73-4a4c-a9cb-9ba0e738d4dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2845350984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2845350984
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.4052609977
Short name T807
Test name
Test status
Simulation time 13404338201 ps
CPU time 13.22 seconds
Started Jul 04 06:08:42 PM PDT 24
Finished Jul 04 06:08:56 PM PDT 24
Peak memory 206284 kb
Host smart-84b27706-86e2-4810-867a-d9771cde3dc3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4052609977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.4052609977
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3467394371
Short name T245
Test name
Test status
Simulation time 23413533872 ps
CPU time 22.65 seconds
Started Jul 04 06:08:43 PM PDT 24
Finished Jul 04 06:09:05 PM PDT 24
Peak memory 206548 kb
Host smart-565e9a8e-41bf-4664-8478-a4d43ac65123
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3467394371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3467394371
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2533347055
Short name T1906
Test name
Test status
Simulation time 171112200 ps
CPU time 0.79 seconds
Started Jul 04 06:08:42 PM PDT 24
Finished Jul 04 06:08:43 PM PDT 24
Peak memory 206144 kb
Host smart-04ac3141-39f9-4936-96cf-b2dc59c032d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25333
47055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2533347055
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1257362458
Short name T477
Test name
Test status
Simulation time 151947043 ps
CPU time 0.79 seconds
Started Jul 04 06:08:41 PM PDT 24
Finished Jul 04 06:08:42 PM PDT 24
Peak memory 206180 kb
Host smart-a2e24c76-0fd5-45c8-82dc-dd1eb00fd316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
62458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1257362458
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2343124654
Short name T2338
Test name
Test status
Simulation time 410910625 ps
CPU time 1.35 seconds
Started Jul 04 06:08:45 PM PDT 24
Finished Jul 04 06:08:47 PM PDT 24
Peak memory 206200 kb
Host smart-62b09a76-213d-459b-a4a4-844445faccc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
24654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2343124654
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1409652765
Short name T1097
Test name
Test status
Simulation time 277909077 ps
CPU time 0.92 seconds
Started Jul 04 06:08:43 PM PDT 24
Finished Jul 04 06:08:44 PM PDT 24
Peak memory 206196 kb
Host smart-5071a54c-2a70-4b97-bdfd-74ae9a59831a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14096
52765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1409652765
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.335085107
Short name T2438
Test name
Test status
Simulation time 16307488214 ps
CPU time 31.76 seconds
Started Jul 04 06:08:43 PM PDT 24
Finished Jul 04 06:09:15 PM PDT 24
Peak memory 206544 kb
Host smart-a0b4ee71-5f3f-4643-8b3b-e29fa517a25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33508
5107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.335085107
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3498614856
Short name T1845
Test name
Test status
Simulation time 443948825 ps
CPU time 1.27 seconds
Started Jul 04 06:08:43 PM PDT 24
Finished Jul 04 06:08:44 PM PDT 24
Peak memory 206192 kb
Host smart-881e2bd8-ea32-41c8-9139-5565b14f2574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
14856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3498614856
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2908081410
Short name T2278
Test name
Test status
Simulation time 148360017 ps
CPU time 0.77 seconds
Started Jul 04 06:08:42 PM PDT 24
Finished Jul 04 06:08:43 PM PDT 24
Peak memory 206140 kb
Host smart-4d728946-cf6a-4d69-adc1-4361714243b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29080
81410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2908081410
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.762272564
Short name T35
Test name
Test status
Simulation time 58575359 ps
CPU time 0.67 seconds
Started Jul 04 06:08:54 PM PDT 24
Finished Jul 04 06:08:54 PM PDT 24
Peak memory 206204 kb
Host smart-b2f7b08a-226d-47d4-92da-b1f0cc648b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76227
2564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.762272564
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3722245210
Short name T993
Test name
Test status
Simulation time 804755701 ps
CPU time 2.23 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:52 PM PDT 24
Peak memory 206408 kb
Host smart-518a421f-2212-4b3f-a872-44e47b243c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37222
45210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3722245210
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1136148124
Short name T1457
Test name
Test status
Simulation time 157914026 ps
CPU time 1.35 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:52 PM PDT 24
Peak memory 206400 kb
Host smart-4353c921-0d0a-4e55-8816-603fe2722b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
48124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1136148124
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3935375081
Short name T1520
Test name
Test status
Simulation time 167923380 ps
CPU time 0.85 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 206204 kb
Host smart-9961da9c-18ff-4065-99e6-bf1738fb0790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
75081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3935375081
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.4272624937
Short name T333
Test name
Test status
Simulation time 145654278 ps
CPU time 0.76 seconds
Started Jul 04 06:08:54 PM PDT 24
Finished Jul 04 06:08:55 PM PDT 24
Peak memory 206212 kb
Host smart-ee1dc133-1757-4e67-8960-355e7e7e2384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42726
24937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.4272624937
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.727844120
Short name T2207
Test name
Test status
Simulation time 165929465 ps
CPU time 0.77 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:50 PM PDT 24
Peak memory 206124 kb
Host smart-5bc30da1-d06e-4604-a29b-35a63015bd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72784
4120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.727844120
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1784996939
Short name T103
Test name
Test status
Simulation time 5725013475 ps
CPU time 49.45 seconds
Started Jul 04 06:08:49 PM PDT 24
Finished Jul 04 06:09:39 PM PDT 24
Peak memory 206512 kb
Host smart-bdde3c75-a92c-4d1b-bbe7-2acd08f4225b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1784996939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1784996939
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2391077497
Short name T1459
Test name
Test status
Simulation time 229693093 ps
CPU time 0.9 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:52 PM PDT 24
Peak memory 206224 kb
Host smart-90d14337-4de3-497c-bbc4-18be92008052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23910
77497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2391077497
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.4259548237
Short name T209
Test name
Test status
Simulation time 23276434219 ps
CPU time 24.65 seconds
Started Jul 04 06:08:54 PM PDT 24
Finished Jul 04 06:09:18 PM PDT 24
Peak memory 206272 kb
Host smart-4bf825e6-db01-43ff-9298-7e1610147710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42595
48237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.4259548237
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4064582512
Short name T1085
Test name
Test status
Simulation time 3336299863 ps
CPU time 3.83 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:54 PM PDT 24
Peak memory 206284 kb
Host smart-f83f21d4-f21d-447c-96bd-299e1eabb167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40645
82512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4064582512
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3610585186
Short name T1228
Test name
Test status
Simulation time 8852343130 ps
CPU time 238.08 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:12:49 PM PDT 24
Peak memory 206556 kb
Host smart-144a28dc-214c-4199-a45d-a945ac328e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36105
85186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3610585186
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3496799841
Short name T1054
Test name
Test status
Simulation time 5367969640 ps
CPU time 156.83 seconds
Started Jul 04 06:08:51 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 206428 kb
Host smart-a683d3de-1399-47cd-8d8d-bb8b99891ad2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3496799841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3496799841
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2284668066
Short name T627
Test name
Test status
Simulation time 247603506 ps
CPU time 0.91 seconds
Started Jul 04 06:08:49 PM PDT 24
Finished Jul 04 06:08:50 PM PDT 24
Peak memory 206188 kb
Host smart-2cf12ed2-91ea-44f3-955f-023393a7c844
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2284668066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2284668066
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2515020901
Short name T2111
Test name
Test status
Simulation time 191807017 ps
CPU time 0.88 seconds
Started Jul 04 06:08:51 PM PDT 24
Finished Jul 04 06:08:52 PM PDT 24
Peak memory 206128 kb
Host smart-3c217274-6703-4098-aa43-e40a1a37dd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25150
20901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2515020901
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.4095215547
Short name T2499
Test name
Test status
Simulation time 3744753229 ps
CPU time 26.26 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:09:16 PM PDT 24
Peak memory 206472 kb
Host smart-1420f62f-8411-48c3-8d9a-22f31c8852f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
15547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.4095215547
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2456265272
Short name T157
Test name
Test status
Simulation time 5397867125 ps
CPU time 144.08 seconds
Started Jul 04 06:08:49 PM PDT 24
Finished Jul 04 06:11:14 PM PDT 24
Peak memory 206432 kb
Host smart-57e814f8-ee84-41b6-af3e-86083bdacb37
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2456265272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2456265272
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.4196085624
Short name T353
Test name
Test status
Simulation time 208545545 ps
CPU time 0.83 seconds
Started Jul 04 06:08:54 PM PDT 24
Finished Jul 04 06:08:55 PM PDT 24
Peak memory 206212 kb
Host smart-7472c45a-c817-4cef-8ec1-cf6bba47d636
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4196085624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.4196085624
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.330584767
Short name T1996
Test name
Test status
Simulation time 153079253 ps
CPU time 0.77 seconds
Started Jul 04 06:08:53 PM PDT 24
Finished Jul 04 06:08:54 PM PDT 24
Peak memory 206188 kb
Host smart-9df4b8e7-b346-49e1-88c9-60156735c384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33058
4767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.330584767
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3075189515
Short name T2666
Test name
Test status
Simulation time 221622788 ps
CPU time 0.92 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 206136 kb
Host smart-de613e32-a4ea-409e-a8b8-ddd9b1b3092f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30751
89515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3075189515
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3473697294
Short name T794
Test name
Test status
Simulation time 180957545 ps
CPU time 0.81 seconds
Started Jul 04 06:08:54 PM PDT 24
Finished Jul 04 06:08:55 PM PDT 24
Peak memory 206208 kb
Host smart-8f785fd5-42b3-43a4-ab28-4ffc36478316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34736
97294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3473697294
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.228617990
Short name T717
Test name
Test status
Simulation time 161489219 ps
CPU time 0.76 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 206416 kb
Host smart-4bc1e9b4-5b05-4198-8691-058c5a4967cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22861
7990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.228617990
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4104465009
Short name T1483
Test name
Test status
Simulation time 153710442 ps
CPU time 0.77 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 206192 kb
Host smart-a74e0762-2fe1-48ac-8eeb-b0322909577d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
65009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4104465009
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2329552576
Short name T724
Test name
Test status
Simulation time 171147867 ps
CPU time 0.78 seconds
Started Jul 04 06:08:54 PM PDT 24
Finished Jul 04 06:08:55 PM PDT 24
Peak memory 206188 kb
Host smart-de2d6b5c-7304-45b5-8ac0-c7233af9934c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23295
52576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2329552576
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1611150510
Short name T2011
Test name
Test status
Simulation time 186518945 ps
CPU time 0.84 seconds
Started Jul 04 06:08:52 PM PDT 24
Finished Jul 04 06:08:53 PM PDT 24
Peak memory 206208 kb
Host smart-1281f0ed-e81b-4006-a1a3-cc9ab404ae2a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1611150510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1611150510
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3022719812
Short name T2502
Test name
Test status
Simulation time 165612720 ps
CPU time 0.74 seconds
Started Jul 04 06:08:52 PM PDT 24
Finished Jul 04 06:08:53 PM PDT 24
Peak memory 206180 kb
Host smart-a2384d19-bbcc-497e-b968-3029decbd4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
19812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3022719812
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2456289403
Short name T1335
Test name
Test status
Simulation time 36423161 ps
CPU time 0.64 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 206412 kb
Host smart-2160bd64-310f-4849-88b3-8d0b188beb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
89403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2456289403
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2570666004
Short name T88
Test name
Test status
Simulation time 23131137185 ps
CPU time 51.39 seconds
Started Jul 04 06:08:53 PM PDT 24
Finished Jul 04 06:09:45 PM PDT 24
Peak memory 206552 kb
Host smart-bd46c567-4614-4f25-b927-d02cac033c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
66004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2570666004
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2498406387
Short name T573
Test name
Test status
Simulation time 158556836 ps
CPU time 0.84 seconds
Started Jul 04 06:08:50 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 206208 kb
Host smart-f5c5e2b3-0590-4e1e-9363-e7b546e181df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24984
06387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2498406387
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2611265823
Short name T1738
Test name
Test status
Simulation time 153109351 ps
CPU time 0.84 seconds
Started Jul 04 06:08:49 PM PDT 24
Finished Jul 04 06:08:50 PM PDT 24
Peak memory 206232 kb
Host smart-866a21cf-b898-4489-9b5d-5e7abc8f20b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
65823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2611265823
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.670873095
Short name T163
Test name
Test status
Simulation time 16086116383 ps
CPU time 366.65 seconds
Started Jul 04 06:08:58 PM PDT 24
Finished Jul 04 06:15:04 PM PDT 24
Peak memory 206532 kb
Host smart-3b87f935-a2eb-4914-b302-c8277884d9b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=670873095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.670873095
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.910361387
Short name T2164
Test name
Test status
Simulation time 7967861542 ps
CPU time 35.9 seconds
Started Jul 04 06:09:00 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 206448 kb
Host smart-f9aca296-a946-4fda-8d0b-53870299f33b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=910361387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.910361387
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.631086139
Short name T639
Test name
Test status
Simulation time 213132119 ps
CPU time 0.92 seconds
Started Jul 04 06:08:57 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206164 kb
Host smart-5c97a91e-6624-428b-b0a0-2d8d79b04b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63108
6139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.631086139
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2003429422
Short name T327
Test name
Test status
Simulation time 184343290 ps
CPU time 0.82 seconds
Started Jul 04 06:08:57 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206212 kb
Host smart-0055790b-42a9-4290-839e-7825f8bad012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20034
29422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2003429422
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3727225954
Short name T1803
Test name
Test status
Simulation time 161140733 ps
CPU time 0.78 seconds
Started Jul 04 06:08:59 PM PDT 24
Finished Jul 04 06:09:00 PM PDT 24
Peak memory 206220 kb
Host smart-f4543458-af46-4b02-8e20-171f0cac978d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37272
25954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3727225954
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3693824726
Short name T908
Test name
Test status
Simulation time 160274236 ps
CPU time 0.75 seconds
Started Jul 04 06:08:57 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206208 kb
Host smart-8804ee6d-6ee0-4f23-82d9-833e7c96112a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
24726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3693824726
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2158690221
Short name T1541
Test name
Test status
Simulation time 181317596 ps
CPU time 0.85 seconds
Started Jul 04 06:08:58 PM PDT 24
Finished Jul 04 06:08:59 PM PDT 24
Peak memory 206176 kb
Host smart-df49612d-2651-45b7-9321-6a6d3ee2a78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21586
90221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2158690221
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.4159272137
Short name T1538
Test name
Test status
Simulation time 237163568 ps
CPU time 0.99 seconds
Started Jul 04 06:08:56 PM PDT 24
Finished Jul 04 06:08:57 PM PDT 24
Peak memory 206172 kb
Host smart-a6f55df4-c47f-44de-b7f8-f494a0c6390e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592
72137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.4159272137
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.174677789
Short name T1897
Test name
Test status
Simulation time 4056686441 ps
CPU time 35.95 seconds
Started Jul 04 06:08:57 PM PDT 24
Finished Jul 04 06:09:33 PM PDT 24
Peak memory 206476 kb
Host smart-4c69646b-7729-4f2f-b557-e57653713362
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=174677789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.174677789
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.331987245
Short name T1390
Test name
Test status
Simulation time 198711559 ps
CPU time 0.86 seconds
Started Jul 04 06:08:57 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206228 kb
Host smart-3c008002-a18a-4d5f-b979-6b696eb2a5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
7245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.331987245
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1221277334
Short name T531
Test name
Test status
Simulation time 156946003 ps
CPU time 0.78 seconds
Started Jul 04 06:08:57 PM PDT 24
Finished Jul 04 06:08:58 PM PDT 24
Peak memory 206188 kb
Host smart-f90a7d41-b3b0-4c2d-a012-d9ce38069e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12212
77334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1221277334
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3526337221
Short name T732
Test name
Test status
Simulation time 203669048 ps
CPU time 0.87 seconds
Started Jul 04 06:09:04 PM PDT 24
Finished Jul 04 06:09:05 PM PDT 24
Peak memory 206176 kb
Host smart-d3a3bb80-cb31-449a-9c19-3df16a76ade0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35263
37221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3526337221
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3267802733
Short name T383
Test name
Test status
Simulation time 4978462705 ps
CPU time 132.26 seconds
Started Jul 04 06:08:59 PM PDT 24
Finished Jul 04 06:11:11 PM PDT 24
Peak memory 206528 kb
Host smart-c9ba0a75-e01d-459d-8ec7-ad71975c43b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678
02733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3267802733
Directory /workspace/9.usbdev_streaming_out/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%