Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	87957	1		T1	14		T2	3		T3	3
all_values[1]	87957	1		T1	14		T2	3		T3	3
all_values[2]	87957	1		T1	14		T2	3		T3	3
all_values[3]	87957	1		T1	14		T2	3		T3	3
all_values[4]	87957	1		T1	14		T2	3		T3	3
all_values[5]	87957	1		T1	14		T2	3		T3	3
all_values[6]	87957	1		T1	14		T2	3		T3	3
all_values[7]	87957	1		T1	14		T2	3		T3	3
all_values[8]	87957	1		T1	14		T2	3		T3	3
all_values[9]	87957	1		T1	14		T2	3		T3	3
all_values[10]	87957	1		T1	14		T2	3		T3	3
all_values[11]	87957	1		T1	14		T2	3		T3	3
all_values[12]	87957	1		T1	14		T2	3		T3	3
all_values[13]	87957	1		T1	14		T2	3		T3	3
all_values[14]	87957	1		T1	14		T2	3		T3	3
all_values[15]	87957	1		T1	14		T2	3		T3	3
all_values[16]	87957	1		T1	14		T2	3		T3	3
all_values[17]	87957	1		T1	14		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1576269	1		T1	238		T2	51		T3	54
auto[1]	6957	1		T1	14		T2	3		T37	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1578099	1		T1	252		T2	54		T3	54
auto[1]	5127	1		T218	113		T219	126		T221	73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86982	1		T1	14		T3	3		T4	2
all_values[0]	auto[0]	auto[1]	144	1		T219	3		T221	4		T222	2
all_values[0]	auto[1]	auto[0]	702	1		T2	3		T37	3		T46	4
all_values[0]	auto[1]	auto[1]	129	1		T218	3		T221	1		T222	6
all_values[1]	auto[0]	auto[0]	86145	1		T2	3		T3	3		T4	2
all_values[1]	auto[0]	auto[1]	141	1		T218	4		T219	1		T221	1
all_values[1]	auto[1]	auto[0]	1535	1		T1	14		T54	3		T7	2
all_values[1]	auto[1]	auto[1]	136	1		T218	4		T219	5		T221	4
all_values[2]	auto[0]	auto[0]	87540	1		T1	14		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	138	1		T218	4		T219	5		T221	5
all_values[2]	auto[1]	auto[0]	129	1		T43	2		T47	2		T48	2
all_values[2]	auto[1]	auto[1]	150	1		T218	3		T219	3		T222	4
all_values[3]	auto[0]	auto[0]	86250	1		T1	14		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	128	1		T218	6		T219	2		T220	5
all_values[3]	auto[1]	auto[0]	1424	1		T70	1394		T219	2		T221	1
all_values[3]	auto[1]	auto[1]	155	1		T218	2		T219	4		T294	1
all_values[4]	auto[0]	auto[0]	87639	1		T1	14		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	129	1		T219	2		T221	4		T220	2
all_values[4]	auto[1]	auto[0]	23	1		T71	2		T222	1		T294	1
all_values[4]	auto[1]	auto[1]	166	1		T218	8		T219	6		T221	1
all_values[5]	auto[0]	auto[0]	87644	1		T1	14		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	129	1		T218	2		T219	7		T222	3
all_values[5]	auto[1]	auto[0]	37	1		T218	2		T294	1		T290	1
all_values[5]	auto[1]	auto[1]	147	1		T218	3		T219	1		T221	5
all_values[6]	auto[0]	auto[0]	87653	1		T1	14		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	133	1		T219	2		T220	4		T222	2
all_values[6]	auto[1]	auto[0]	37	1		T218	2		T221	1		T220	1
all_values[6]	auto[1]	auto[1]	134	1		T219	6		T222	5		T295	5
all_values[7]	auto[0]	auto[0]	87625	1		T1	14		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	166	1		T218	6		T219	5		T221	5
all_values[7]	auto[1]	auto[0]	23	1		T55	2		T56	2		T57	2
all_values[7]	auto[1]	auto[1]	143	1		T219	3		T220	4		T222	2
all_values[8]	auto[0]	auto[0]	87620	1		T1	14		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	147	1		T218	2		T221	3		T222	6
all_values[8]	auto[1]	auto[0]	43	1		T59	11		T218	2		T220	1
all_values[8]	auto[1]	auto[1]	147	1		T218	3		T219	7		T221	2
all_values[9]	auto[0]	auto[0]	87621	1		T1	14		T2	3		T3	3
all_values[9]	auto[0]	auto[1]	136	1		T218	3		T219	6		T221	4
all_values[9]	auto[1]	auto[0]	48	1		T67	5		T68	5		T69	5
all_values[9]	auto[1]	auto[1]	152	1		T218	5		T219	2		T220	1
all_values[10]	auto[0]	auto[0]	87647	1		T1	14		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	152	1		T218	1		T219	6		T221	1
all_values[10]	auto[1]	auto[0]	27	1		T218	2		T221	1		T220	1
all_values[10]	auto[1]	auto[1]	131	1		T218	5		T219	2		T221	3
all_values[11]	auto[0]	auto[0]	87538	1		T1	14		T2	3		T3	3
all_values[11]	auto[0]	auto[1]	152	1		T218	7		T219	4		T221	3
all_values[11]	auto[1]	auto[0]	132	1		T52	2		T76	2		T77	2
all_values[11]	auto[1]	auto[1]	135	1		T218	1		T219	3		T221	1
all_values[12]	auto[0]	auto[0]	87627	1		T1	14		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	153	1		T218	6		T219	3		T221	5
all_values[12]	auto[1]	auto[0]	48	1		T80	3		T81	3		T82	3
all_values[12]	auto[1]	auto[1]	129	1		T219	4		T220	5		T222	3
all_values[13]	auto[0]	auto[0]	87648	1		T1	14		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	130	1		T218	3		T219	6		T221	4
all_values[13]	auto[1]	auto[0]	30	1		T295	2		T290	2		T291	1
all_values[13]	auto[1]	auto[1]	149	1		T218	5		T219	2		T220	4
all_values[14]	auto[0]	auto[0]	87636	1		T1	14		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	158	1		T218	8		T219	6		T221	3
all_values[14]	auto[1]	auto[0]	30	1		T221	1		T292	5		T296	1
all_values[14]	auto[1]	auto[1]	133	1		T219	2		T220	4		T222	1
all_values[15]	auto[0]	auto[0]	87642	1		T1	14		T2	3		T3	3
all_values[15]	auto[0]	auto[1]	138	1		T218	5		T219	3		T221	5
all_values[15]	auto[1]	auto[0]	20	1		T297	1		T298	1		T299	1
all_values[15]	auto[1]	auto[1]	157	1		T218	1		T219	3		T220	5
all_values[16]	auto[0]	auto[0]	87619	1		T1	14		T2	3		T3	3
all_values[16]	auto[0]	auto[1]	151	1		T218	1		T219	2		T221	5
all_values[16]	auto[1]	auto[0]	51	1		T73	8		T74	8		T75	8
all_values[16]	auto[1]	auto[1]	136	1		T218	7		T219	6		T220	2
all_values[17]	auto[0]	auto[0]	87650	1		T1	14		T2	3		T3	3
all_values[17]	auto[0]	auto[1]	118	1		T218	1		T219	1		T221	1
all_values[17]	auto[1]	auto[0]	34	1		T62	2		T218	1		T219	3
all_values[17]	auto[1]	auto[1]	155	1		T218	4		T219	3		T221	3