Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	87957	1		T1	14		T2	3		T3	3
all_pins[1]	87957	1		T1	14		T2	3		T3	3
all_pins[2]	87957	1		T1	14		T2	3		T3	3
all_pins[3]	87957	1		T1	14		T2	3		T3	3
all_pins[4]	87957	1		T1	14		T2	3		T3	3
all_pins[5]	87957	1		T1	14		T2	3		T3	3
all_pins[6]	87957	1		T1	14		T2	3		T3	3
all_pins[7]	87957	1		T1	14		T2	3		T3	3
all_pins[8]	87957	1		T1	14		T2	3		T3	3
all_pins[9]	87957	1		T1	14		T2	3		T3	3
all_pins[10]	87957	1		T1	14		T2	3		T3	3
all_pins[11]	87957	1		T1	14		T2	3		T3	3
all_pins[12]	87957	1		T1	14		T2	3		T3	3
all_pins[13]	87957	1		T1	14		T2	3		T3	3
all_pins[14]	87957	1		T1	14		T2	3		T3	3
all_pins[15]	87957	1		T1	14		T2	3		T3	3
all_pins[16]	87957	1		T1	14		T2	3		T3	3
all_pins[17]	87957	1		T1	14		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1580955	1		T1	240		T2	54		T3	54
values[0x1]	2271	1		T1	12		T52	1		T46	1
transitions[0x0=>0x1]	1981	1		T1	12		T52	1		T46	1
transitions[0x1=>0x0]	1990	1		T1	12		T52	1		T46	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87850	1		T1	14		T2	3		T3	3
all_pins[0]	values[0x1]	107	1		T46	1		T53	1		T300	1
all_pins[0]	transitions[0x0=>0x1]	98	1		T46	1		T53	1		T300	1
all_pins[0]	transitions[0x1=>0x0]	986	1		T1	12		T54	1		T7	1
all_pins[1]	values[0x0]	86962	1		T1	2		T2	3		T3	3
all_pins[1]	values[0x1]	995	1		T1	12		T54	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	980	1		T1	12		T54	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	122	1		T43	1		T47	1		T48	1
all_pins[2]	values[0x0]	87820	1		T1	14		T2	3		T3	3
all_pins[2]	values[0x1]	137	1		T43	1		T47	1		T48	1
all_pins[2]	transitions[0x0=>0x1]	118	1		T43	1		T47	1		T48	1
all_pins[2]	transitions[0x1=>0x0]	45	1		T70	1		T219	2		T294	1
all_pins[3]	values[0x0]	87893	1		T1	14		T2	3		T3	3
all_pins[3]	values[0x1]	64	1		T70	1		T219	2		T294	1
all_pins[3]	transitions[0x0=>0x1]	42	1		T70	1		T295	2		T292	1
all_pins[3]	transitions[0x1=>0x0]	54	1		T71	1		T218	6		T219	1
all_pins[4]	values[0x0]	87881	1		T1	14		T2	3		T3	3
all_pins[4]	values[0x1]	76	1		T71	1		T218	6		T219	3
all_pins[4]	transitions[0x0=>0x1]	56	1		T71	1		T218	4		T219	3
all_pins[4]	transitions[0x1=>0x0]	43	1		T219	1		T221	1		T220	1
all_pins[5]	values[0x0]	87894	1		T1	14		T2	3		T3	3
all_pins[5]	values[0x1]	63	1		T218	2		T219	1		T221	2
all_pins[5]	transitions[0x0=>0x1]	49	1		T218	2		T219	1		T221	2
all_pins[5]	transitions[0x1=>0x0]	46	1		T219	4		T295	2		T290	3
all_pins[6]	values[0x0]	87897	1		T1	14		T2	3		T3	3
all_pins[6]	values[0x1]	60	1		T219	4		T295	2		T290	4
all_pins[6]	transitions[0x0=>0x1]	49	1		T219	3		T295	2		T290	4
all_pins[6]	transitions[0x1=>0x0]	51	1		T55	1		T56	1		T57	1
all_pins[7]	values[0x0]	87895	1		T1	14		T2	3		T3	3
all_pins[7]	values[0x1]	62	1		T55	1		T56	1		T57	1
all_pins[7]	transitions[0x0=>0x1]	41	1		T55	1		T56	1		T57	1
all_pins[7]	transitions[0x1=>0x0]	48	1		T59	1		T218	1		T219	2
all_pins[8]	values[0x0]	87888	1		T1	14		T2	3		T3	3
all_pins[8]	values[0x1]	69	1		T59	1		T218	1		T219	4
all_pins[8]	transitions[0x0=>0x1]	51	1		T59	1		T219	3		T221	2
all_pins[8]	transitions[0x1=>0x0]	65	1		T67	2		T68	2		T69	2
all_pins[9]	values[0x0]	87874	1		T1	14		T2	3		T3	3
all_pins[9]	values[0x1]	83	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x0=>0x1]	67	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x1=>0x0]	33	1		T218	1		T219	1		T221	2
all_pins[10]	values[0x0]	87908	1		T1	14		T2	3		T3	3
all_pins[10]	values[0x1]	49	1		T218	4		T219	1		T221	2
all_pins[10]	transitions[0x0=>0x1]	42	1		T218	4		T219	1		T221	2
all_pins[10]	transitions[0x1=>0x0]	102	1		T52	1		T76	1		T77	1
all_pins[11]	values[0x0]	87848	1		T1	14		T2	3		T3	3
all_pins[11]	values[0x1]	109	1		T52	1		T76	1		T77	1
all_pins[11]	transitions[0x0=>0x1]	98	1		T52	1		T76	1		T77	1
all_pins[11]	transitions[0x1=>0x0]	43	1		T80	1		T81	1		T82	1
all_pins[12]	values[0x0]	87903	1		T1	14		T2	3		T3	3
all_pins[12]	values[0x1]	54	1		T80	1		T81	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	40	1		T80	1		T81	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	47	1		T218	2		T290	1		T298	1
all_pins[13]	values[0x0]	87896	1		T1	14		T2	3		T3	3
all_pins[13]	values[0x1]	61	1		T218	2		T294	1		T290	1
all_pins[13]	transitions[0x0=>0x1]	38	1		T218	2		T294	1		T298	1
all_pins[13]	transitions[0x1=>0x0]	54	1		T219	1		T294	1		T290	5
all_pins[14]	values[0x0]	87880	1		T1	14		T2	3		T3	3
all_pins[14]	values[0x1]	77	1		T219	1		T294	1		T290	6
all_pins[14]	transitions[0x0=>0x1]	62	1		T219	1		T290	5		T291	1
all_pins[14]	transitions[0x1=>0x0]	59	1		T218	1		T219	2		T222	2
all_pins[15]	values[0x0]	87883	1		T1	14		T2	3		T3	3
all_pins[15]	values[0x1]	74	1		T218	1		T219	2		T222	2
all_pins[15]	transitions[0x0=>0x1]	49	1		T218	1		T222	2		T294	1
all_pins[15]	transitions[0x1=>0x0]	52	1		T73	4		T74	4		T75	4
all_pins[16]	values[0x0]	87880	1		T1	14		T2	3		T3	3
all_pins[16]	values[0x1]	77	1		T73	4		T74	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	62	1		T73	4		T74	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	39	1		T62	1		T220	1		T222	1
all_pins[17]	values[0x0]	87903	1		T1	14		T2	3		T3	3
all_pins[17]	values[0x1]	54	1		T62	1		T218	1		T219	1
all_pins[17]	transitions[0x0=>0x1]	39	1		T62	1		T218	1		T219	1
all_pins[17]	transitions[0x1=>0x0]	101	1		T46	1		T53	1		T300	1