Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1		T218	7		T219	7		T221	4
all_values[1]	290	1		T218	7		T219	7		T221	4
all_values[2]	290	1		T218	7		T219	7		T221	4
all_values[3]	290	1		T218	7		T219	7		T221	4
all_values[4]	290	1		T218	7		T219	7		T221	4
all_values[5]	290	1		T218	7		T219	7		T221	4
all_values[6]	290	1		T218	7		T219	7		T221	4
all_values[7]	290	1		T218	7		T219	7		T221	4
all_values[8]	290	1		T218	7		T219	7		T221	4
all_values[9]	290	1		T218	7		T219	7		T221	4
all_values[10]	290	1		T218	7		T219	7		T221	4
all_values[11]	290	1		T218	7		T219	7		T221	4
all_values[12]	290	1		T218	7		T219	7		T221	4
all_values[13]	290	1		T218	7		T219	7		T221	4
all_values[14]	290	1		T218	7		T219	7		T221	4
all_values[15]	290	1		T218	7		T219	7		T221	4
all_values[16]	290	1		T218	7		T219	7		T221	4
all_values[17]	290	1		T218	7		T219	7		T221	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2797	1		T218	63		T219	70		T221	49
auto[1]	2423	1		T218	63		T219	56		T221	23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	927	1		T218	30		T219	18		T221	15
auto[1]	4293	1		T218	96		T219	108		T221	57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3088	1		T218	81		T219	75		T221	43
auto[1]	2132	1		T218	45		T219	51		T221	29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1		T218	4		T219	2		T220	2
all_values[0]	auto[0]	auto[0]	auto[1]	49	1		T219	1		T221	2		T294	1
all_values[0]	auto[0]	auto[1]	auto[0]	23	1		T218	1		T219	3		T220	2
all_values[0]	auto[0]	auto[1]	auto[1]	54	1		T218	1		T222	2		T294	1
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T219	1		T222	2		T295	1
all_values[0]	auto[1]	auto[1]	auto[1]	61	1		T218	1		T221	2		T222	3
all_values[1]	auto[0]	auto[0]	auto[0]	38	1		T219	1		T291	1		T296	1
all_values[1]	auto[0]	auto[0]	auto[1]	62	1		T218	2		T219	1		T221	1
all_values[1]	auto[0]	auto[1]	auto[0]	23	1		T219	1		T294	1		T290	2
all_values[1]	auto[0]	auto[1]	auto[1]	64	1		T218	2		T219	3		T221	1
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T218	1		T221	1		T220	2
all_values[1]	auto[1]	auto[1]	auto[1]	44	1		T218	2		T219	1		T221	1
all_values[2]	auto[0]	auto[0]	auto[0]	30	1		T222	1		T290	2		T291	3
all_values[2]	auto[0]	auto[0]	auto[1]	55	1		T218	3		T219	2		T221	2
all_values[2]	auto[0]	auto[1]	auto[0]	19	1		T218	1		T291	1		T292	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1		T218	1		T219	3		T222	1
all_values[2]	auto[1]	auto[0]	auto[1]	69	1		T219	1		T221	2		T220	3
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T218	2		T219	1		T222	2
all_values[3]	auto[0]	auto[0]	auto[0]	31	1		T219	1		T221	3		T222	1
all_values[3]	auto[0]	auto[0]	auto[1]	56	1		T218	4		T220	3		T222	2
all_values[3]	auto[0]	auto[1]	auto[0]	23	1		T219	1		T221	1		T222	2
all_values[3]	auto[0]	auto[1]	auto[1]	67	1		T218	2		T219	2		T295	1
all_values[3]	auto[1]	auto[0]	auto[1]	68	1		T219	1		T220	1		T222	1
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T218	1		T219	2		T222	1
all_values[4]	auto[0]	auto[0]	auto[0]	26	1		T222	1		T290	3		T298	1
all_values[4]	auto[0]	auto[0]	auto[1]	58	1		T219	1		T221	1		T220	2
all_values[4]	auto[0]	auto[1]	auto[0]	16	1		T294	1		T290	2		T299	1
all_values[4]	auto[0]	auto[1]	auto[1]	69	1		T218	1		T219	2		T220	1
all_values[4]	auto[1]	auto[0]	auto[1]	57	1		T219	2		T221	2		T220	1
all_values[4]	auto[1]	auto[1]	auto[1]	64	1		T218	6		T219	2		T221	1
all_values[5]	auto[0]	auto[0]	auto[0]	28	1		T220	1		T290	2		T296	4
all_values[5]	auto[0]	auto[0]	auto[1]	51	1		T218	1		T219	2		T295	1
all_values[5]	auto[0]	auto[1]	auto[0]	30	1		T218	3		T294	1		T298	1
all_values[5]	auto[0]	auto[1]	auto[1]	64	1		T218	1		T221	2		T220	2
all_values[5]	auto[1]	auto[0]	auto[1]	71	1		T218	1		T219	4		T220	1
all_values[5]	auto[1]	auto[1]	auto[1]	46	1		T218	1		T219	1		T221	2
all_values[6]	auto[0]	auto[0]	auto[0]	39	1		T218	5		T221	2		T220	1
all_values[6]	auto[0]	auto[0]	auto[1]	47	1		T220	1		T295	1		T291	1
all_values[6]	auto[0]	auto[1]	auto[0]	25	1		T218	2		T221	2		T294	2
all_values[6]	auto[0]	auto[1]	auto[1]	55	1		T219	2		T222	3		T295	3
all_values[6]	auto[1]	auto[0]	auto[1]	68	1		T219	2		T220	1		T222	1
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T219	3		T220	1		T222	2
all_values[7]	auto[0]	auto[0]	auto[0]	20	1		T218	2		T220	1		T295	1
all_values[7]	auto[0]	auto[0]	auto[1]	61	1		T218	2		T219	2		T221	3
all_values[7]	auto[0]	auto[1]	auto[0]	10	1		T294	1		T297	2		T301	1
all_values[7]	auto[0]	auto[1]	auto[1]	76	1		T219	2		T220	1		T222	2
all_values[7]	auto[1]	auto[0]	auto[1]	75	1		T218	3		T219	1		T221	1
all_values[7]	auto[1]	auto[1]	auto[1]	48	1		T219	2		T220	2		T295	1
all_values[8]	auto[0]	auto[0]	auto[0]	22	1		T219	1		T220	1		T290	3
all_values[8]	auto[0]	auto[0]	auto[1]	53	1		T218	1		T221	1		T222	2
all_values[8]	auto[0]	auto[1]	auto[0]	23	1		T218	3		T299	1		T302	3
all_values[8]	auto[0]	auto[1]	auto[1]	58	1		T218	1		T219	2		T221	1
all_values[8]	auto[1]	auto[0]	auto[1]	73	1		T218	1		T222	4		T294	1
all_values[8]	auto[1]	auto[1]	auto[1]	61	1		T218	1		T219	4		T221	2
all_values[9]	auto[0]	auto[0]	auto[0]	27	1		T222	2		T291	1		T292	2
all_values[9]	auto[0]	auto[0]	auto[1]	61	1		T218	2		T219	5		T221	1
all_values[9]	auto[0]	auto[1]	auto[0]	21	1		T221	1		T222	1		T292	2
all_values[9]	auto[0]	auto[1]	auto[1]	64	1		T218	1		T222	1		T294	1
all_values[9]	auto[1]	auto[0]	auto[1]	61	1		T218	1		T219	1		T221	1
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T218	3		T219	1		T221	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1		T220	1		T295	1		T290	5
all_values[10]	auto[0]	auto[0]	auto[1]	66	1		T218	1		T219	4		T220	1
all_values[10]	auto[0]	auto[1]	auto[0]	20	1		T218	2		T221	1		T290	2
all_values[10]	auto[0]	auto[1]	auto[1]	48	1		T218	2		T221	1		T220	1
all_values[10]	auto[1]	auto[0]	auto[1]	68	1		T219	1		T221	1		T222	2
all_values[10]	auto[1]	auto[1]	auto[1]	55	1		T218	2		T219	2		T221	1
all_values[11]	auto[0]	auto[0]	auto[0]	28	1		T219	1		T221	1		T291	1
all_values[11]	auto[0]	auto[0]	auto[1]	70	1		T218	4		T219	3		T221	1
all_values[11]	auto[0]	auto[1]	auto[0]	22	1		T290	1		T296	2		T297	2
all_values[11]	auto[0]	auto[1]	auto[1]	52	1		T219	2		T221	1		T220	1
all_values[11]	auto[1]	auto[0]	auto[1]	66	1		T218	1		T219	1		T221	1
all_values[11]	auto[1]	auto[1]	auto[1]	52	1		T218	2		T220	1		T294	1
all_values[12]	auto[0]	auto[0]	auto[0]	27	1		T219	1		T303	3		T296	2
all_values[12]	auto[0]	auto[0]	auto[1]	60	1		T218	3		T219	1		T221	1
all_values[12]	auto[0]	auto[1]	auto[0]	27	1		T218	2		T290	5		T296	2
all_values[12]	auto[0]	auto[1]	auto[1]	53	1		T219	1		T220	2		T222	2
all_values[12]	auto[1]	auto[0]	auto[1]	79	1		T218	2		T219	3		T221	3
all_values[12]	auto[1]	auto[1]	auto[1]	44	1		T219	1		T220	1		T294	3
all_values[13]	auto[0]	auto[0]	auto[0]	39	1		T221	1		T295	1		T290	2
all_values[13]	auto[0]	auto[0]	auto[1]	53	1		T219	4		T221	1		T220	1
all_values[13]	auto[0]	auto[1]	auto[0]	18	1		T295	1		T290	1		T303	2
all_values[13]	auto[0]	auto[1]	auto[1]	72	1		T218	3		T219	1		T220	2
all_values[13]	auto[1]	auto[0]	auto[1]	60	1		T218	2		T219	2		T221	2
all_values[13]	auto[1]	auto[1]	auto[1]	48	1		T218	2		T294	1		T295	1
all_values[14]	auto[0]	auto[0]	auto[0]	27	1		T221	2		T295	3		T292	1
all_values[14]	auto[0]	auto[0]	auto[1]	65	1		T218	4		T219	3		T221	1
all_values[14]	auto[0]	auto[1]	auto[0]	17	1		T292	3		T297	1		T304	1
all_values[14]	auto[0]	auto[1]	auto[1]	55	1		T220	2		T290	4		T303	1
all_values[14]	auto[1]	auto[0]	auto[1]	72	1		T218	3		T219	3		T220	1
all_values[14]	auto[1]	auto[1]	auto[1]	54	1		T219	1		T221	1		T294	1
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T218	2		T219	2		T222	3
all_values[15]	auto[0]	auto[0]	auto[1]	61	1		T218	2		T219	2		T221	2
all_values[15]	auto[0]	auto[1]	auto[0]	14	1		T299	1		T302	1		T305	2
all_values[15]	auto[0]	auto[1]	auto[1]	77	1		T218	1		T219	1		T220	2
all_values[15]	auto[1]	auto[0]	auto[1]	60	1		T218	2		T219	1		T221	2
all_values[15]	auto[1]	auto[1]	auto[1]	49	1		T219	1		T220	1		T222	1
all_values[16]	auto[0]	auto[0]	auto[0]	30	1		T222	1		T291	2		T292	1
all_values[16]	auto[0]	auto[0]	auto[1]	62	1		T219	1		T221	3		T220	1
all_values[16]	auto[0]	auto[1]	auto[0]	18	1		T291	2		T292	1		T306	1
all_values[16]	auto[0]	auto[1]	auto[1]	63	1		T218	4		T219	3		T222	2
all_values[16]	auto[1]	auto[0]	auto[1]	66	1		T218	1		T219	1		T221	1
all_values[16]	auto[1]	auto[1]	auto[1]	51	1		T218	2		T219	2		T220	2
all_values[17]	auto[0]	auto[0]	auto[0]	44	1		T218	2		T219	3		T221	1
all_values[17]	auto[0]	auto[0]	auto[1]	51	1		T221	1		T222	1		T294	2
all_values[17]	auto[0]	auto[1]	auto[0]	20	1		T218	1		T219	1		T222	1
all_values[17]	auto[0]	auto[1]	auto[1]	61	1		T218	2		T219	1		T221	1
all_values[17]	auto[1]	auto[0]	auto[1]	63	1		T218	1		T219	1		T221	1
all_values[17]	auto[1]	auto[1]	auto[1]	51	1		T218	1		T219	1		T222	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal