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LINE 9293
EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T34,T6,T36 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T255,T256,T25 |
LINE 9294
EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Covered | T236,T243,T245 |
1 | 1 | 1 | Covered | T25,T26,T27 |
LINE 9313
EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T210,T243,T245 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 9326
EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Covered | T210,T243,T245 |
1 | 1 | 1 | Covered | T7,T8,T9 |
LINE 9329
EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T38,T6,T36 |
1 | 1 | 0 | Covered | T210,T243,T245 |
1 | 1 | 1 | Covered | T38,T86,T96 |
LINE 9336
EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9337
EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Covered | T210,T236,T243 |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9350
EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9351
EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Covered | T210,T248,T249 |
1 | 1 | 1 | Covered | T238,T211,T212 |
LINE 9362
EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9363
EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Covered | T210,T243,T245 |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9368
EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9369
EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T36,T45 |
1 | 1 | 0 | Covered | T210,T245,T248 |
1 | 1 | 1 | Covered | T214,T238,T211 |
LINE 9881
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |