Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.36 97.82 93.83 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2807
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T2757 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1755226068 Jul 06 05:03:50 PM PDT 24 Jul 06 05:03:52 PM PDT 24 166574620 ps
T2758 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.766751026 Jul 06 05:04:12 PM PDT 24 Jul 06 05:04:14 PM PDT 24 66139987 ps
T2759 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3924209996 Jul 06 05:03:55 PM PDT 24 Jul 06 05:03:59 PM PDT 24 971796470 ps
T279 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2646413260 Jul 06 05:03:58 PM PDT 24 Jul 06 05:04:00 PM PDT 24 211673649 ps
T2760 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2115147824 Jul 06 05:04:21 PM PDT 24 Jul 06 05:04:23 PM PDT 24 68781872 ps
T2761 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2886336534 Jul 06 05:04:09 PM PDT 24 Jul 06 05:04:12 PM PDT 24 225101363 ps
T2762 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2593228083 Jul 06 05:03:55 PM PDT 24 Jul 06 05:03:57 PM PDT 24 113658637 ps
T2763 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.555381374 Jul 06 05:04:03 PM PDT 24 Jul 06 05:04:04 PM PDT 24 138648871 ps
T2764 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.526697475 Jul 06 05:03:50 PM PDT 24 Jul 06 05:03:51 PM PDT 24 93206860 ps
T2765 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2735761485 Jul 06 05:03:42 PM PDT 24 Jul 06 05:03:43 PM PDT 24 136837155 ps
T2766 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4154850219 Jul 06 05:03:56 PM PDT 24 Jul 06 05:03:57 PM PDT 24 84993133 ps
T315 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.254703668 Jul 06 05:03:57 PM PDT 24 Jul 06 05:04:00 PM PDT 24 341560089 ps
T312 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2854207140 Jul 06 05:03:49 PM PDT 24 Jul 06 05:03:52 PM PDT 24 801876584 ps
T317 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3781088589 Jul 06 05:04:17 PM PDT 24 Jul 06 05:04:20 PM PDT 24 545386082 ps
T2767 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4242055678 Jul 06 05:04:26 PM PDT 24 Jul 06 05:04:27 PM PDT 24 87179536 ps
T310 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2550643812 Jul 06 05:03:55 PM PDT 24 Jul 06 05:04:00 PM PDT 24 1006937882 ps
T2768 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1481680605 Jul 06 05:03:42 PM PDT 24 Jul 06 05:03:45 PM PDT 24 197520744 ps
T2769 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2330605097 Jul 06 05:03:56 PM PDT 24 Jul 06 05:03:57 PM PDT 24 169668090 ps
T2770 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.61061793 Jul 06 05:04:25 PM PDT 24 Jul 06 05:04:26 PM PDT 24 91909531 ps
T2771 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.399893100 Jul 06 05:04:12 PM PDT 24 Jul 06 05:04:13 PM PDT 24 64296169 ps
T2772 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2877952514 Jul 06 05:04:22 PM PDT 24 Jul 06 05:04:23 PM PDT 24 43423952 ps
T2773 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2775582388 Jul 06 05:04:08 PM PDT 24 Jul 06 05:04:09 PM PDT 24 88301461 ps
T2774 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.479281630 Jul 06 05:04:15 PM PDT 24 Jul 06 05:04:18 PM PDT 24 170278627 ps
T2775 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.975957936 Jul 06 05:03:49 PM PDT 24 Jul 06 05:03:52 PM PDT 24 107620668 ps
T2776 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.791764774 Jul 06 05:03:55 PM PDT 24 Jul 06 05:03:57 PM PDT 24 72682810 ps
T2777 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2984608250 Jul 06 05:04:21 PM PDT 24 Jul 06 05:04:23 PM PDT 24 91455106 ps
T313 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4133293461 Jul 06 05:04:16 PM PDT 24 Jul 06 05:04:23 PM PDT 24 1624824123 ps
T2778 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4050101218 Jul 06 05:04:15 PM PDT 24 Jul 06 05:04:17 PM PDT 24 182188855 ps
T2779 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4189753811 Jul 06 05:04:12 PM PDT 24 Jul 06 05:04:14 PM PDT 24 56830370 ps
T2780 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1380848868 Jul 06 05:04:07 PM PDT 24 Jul 06 05:04:08 PM PDT 24 36324774 ps
T2781 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2963763385 Jul 06 05:04:20 PM PDT 24 Jul 06 05:04:21 PM PDT 24 49257767 ps
T2782 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3041053370 Jul 06 05:04:04 PM PDT 24 Jul 06 05:04:05 PM PDT 24 50083216 ps
T2783 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3400063624 Jul 06 05:04:10 PM PDT 24 Jul 06 05:04:11 PM PDT 24 54476602 ps
T2784 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2554562301 Jul 06 05:04:04 PM PDT 24 Jul 06 05:04:05 PM PDT 24 131016724 ps
T2785 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2477289379 Jul 06 05:03:57 PM PDT 24 Jul 06 05:04:06 PM PDT 24 1677395580 ps
T2786 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1217798943 Jul 06 05:03:51 PM PDT 24 Jul 06 05:03:53 PM PDT 24 37789940 ps
T2787 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1938977777 Jul 06 05:05:01 PM PDT 24 Jul 06 05:05:03 PM PDT 24 70599870 ps
T2788 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4157233537 Jul 06 05:04:15 PM PDT 24 Jul 06 05:04:19 PM PDT 24 317715465 ps
T2789 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2761592028 Jul 06 05:04:13 PM PDT 24 Jul 06 05:04:15 PM PDT 24 201516433 ps
T2790 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.643835748 Jul 06 05:03:43 PM PDT 24 Jul 06 05:03:45 PM PDT 24 145871072 ps
T2791 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.471888902 Jul 06 05:04:18 PM PDT 24 Jul 06 05:04:19 PM PDT 24 118929036 ps
T2792 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.875645776 Jul 06 05:04:19 PM PDT 24 Jul 06 05:04:20 PM PDT 24 47236227 ps
T2793 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3501664772 Jul 06 05:03:55 PM PDT 24 Jul 06 05:03:59 PM PDT 24 135283598 ps
T2794 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4103061061 Jul 06 05:03:49 PM PDT 24 Jul 06 05:03:50 PM PDT 24 71180227 ps
T2795 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3171868110 Jul 06 05:04:15 PM PDT 24 Jul 06 05:04:16 PM PDT 24 45639130 ps
T2796 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1068326631 Jul 06 05:04:15 PM PDT 24 Jul 06 05:04:18 PM PDT 24 101038564 ps
T2797 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1598595188 Jul 06 05:04:18 PM PDT 24 Jul 06 05:04:19 PM PDT 24 40779721 ps
T2798 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3131646590 Jul 06 05:04:02 PM PDT 24 Jul 06 05:04:03 PM PDT 24 96377539 ps
T2799 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3078955045 Jul 06 05:04:15 PM PDT 24 Jul 06 05:04:17 PM PDT 24 110037035 ps
T2800 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1833681924 Jul 06 05:03:50 PM PDT 24 Jul 06 05:03:53 PM PDT 24 241272011 ps
T2801 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2922402459 Jul 06 05:03:51 PM PDT 24 Jul 06 05:03:53 PM PDT 24 195950184 ps
T2802 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3907429497 Jul 06 05:03:44 PM PDT 24 Jul 06 05:03:45 PM PDT 24 74371083 ps
T2803 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1663780846 Jul 06 05:04:20 PM PDT 24 Jul 06 05:04:21 PM PDT 24 85505334 ps
T2804 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3460870927 Jul 06 05:03:55 PM PDT 24 Jul 06 05:03:57 PM PDT 24 162796930 ps
T2805 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2669724485 Jul 06 05:04:09 PM PDT 24 Jul 06 05:04:13 PM PDT 24 240530532 ps
T2806 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3447515801 Jul 06 05:04:17 PM PDT 24 Jul 06 05:04:19 PM PDT 24 105406677 ps
T2807 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3131894152 Jul 06 05:03:57 PM PDT 24 Jul 06 05:03:58 PM PDT 24 80886404 ps

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3078926173
Short name T31
Test name
Test status
Simulation time 6657845764 ps
CPU time 14.58 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:23:07 PM PDT 24
Peak memory 206548 kb
Host smart-a2ec5344-ce0a-4d3a-8e7e-1a4efc9a0791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30789
26173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3078926173
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.4103579287
Short name T37
Test name
Test status
Simulation time 238110667 ps
CPU time 0.91 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:55 PM PDT 24
Peak memory 206204 kb
Host smart-5a753998-d0f6-41bc-9c95-5303e955bb8d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4103579287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.4103579287
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1083772547
Short name T295
Test name
Test status
Simulation time 32110173 ps
CPU time 0.67 seconds
Started Jul 06 05:04:21 PM PDT 24
Finished Jul 06 05:04:22 PM PDT 24
Peak memory 205808 kb
Host smart-745d30fa-73c9-4014-b836-89cf23d8ff37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1083772547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1083772547
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3375856159
Short name T9
Test name
Test status
Simulation time 23522776986 ps
CPU time 22.58 seconds
Started Jul 06 05:28:24 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206428 kb
Host smart-4ac1d9fb-1dd9-47ec-9422-4e0225b70a67
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3375856159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3375856159
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3089279202
Short name T212
Test name
Test status
Simulation time 404563534 ps
CPU time 2.73 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:47 PM PDT 24
Peak memory 205900 kb
Host smart-eabe5309-159c-4874-9876-4b454b25ac50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3089279202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3089279202
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3363357723
Short name T96
Test name
Test status
Simulation time 19054973488 ps
CPU time 36.45 seconds
Started Jul 06 05:23:07 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206536 kb
Host smart-fa6aed52-e166-4296-bcff-980128513e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
57723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3363357723
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3991015474
Short name T3
Test name
Test status
Simulation time 162974421 ps
CPU time 0.81 seconds
Started Jul 06 05:27:39 PM PDT 24
Finished Jul 06 05:27:40 PM PDT 24
Peak memory 206200 kb
Host smart-e8a91bb7-aacd-4996-9af5-37d393f0aa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39910
15474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3991015474
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.822829005
Short name T21
Test name
Test status
Simulation time 9788561639 ps
CPU time 45.16 seconds
Started Jul 06 05:23:04 PM PDT 24
Finished Jul 06 05:23:49 PM PDT 24
Peak memory 206508 kb
Host smart-2acad91f-a288-448d-8835-e7f687bd766e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=822829005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.822829005
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3583441276
Short name T43
Test name
Test status
Simulation time 143802950 ps
CPU time 0.78 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206160 kb
Host smart-c804d100-b6bd-4c0e-b198-2e6d90a64e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35834
41276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3583441276
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.99786299
Short name T112
Test name
Test status
Simulation time 199237385 ps
CPU time 0.88 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206220 kb
Host smart-589deb99-37bf-4552-a80b-8f1b56ee6b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99786
299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.99786299
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.97005973
Short name T290
Test name
Test status
Simulation time 67161849 ps
CPU time 0.72 seconds
Started Jul 06 05:03:56 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 205792 kb
Host smart-d288dc10-5654-40fe-b963-caf71e539f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=97005973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.97005973
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.525104232
Short name T24
Test name
Test status
Simulation time 413551448 ps
CPU time 1.33 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206172 kb
Host smart-1abfa156-0071-4522-b852-9fb865f2d7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52510
4232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.525104232
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3425621564
Short name T210
Test name
Test status
Simulation time 158708302 ps
CPU time 1.88 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 221952 kb
Host smart-2ca4fde5-02c5-4e75-90e4-e5e55b58b7bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3425621564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3425621564
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1692985387
Short name T207
Test name
Test status
Simulation time 987747657 ps
CPU time 1.88 seconds
Started Jul 06 05:23:16 PM PDT 24
Finished Jul 06 05:23:18 PM PDT 24
Peak memory 224020 kb
Host smart-1f9af52a-f95d-46d0-8978-79a5d63701d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1692985387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1692985387
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2667866995
Short name T136
Test name
Test status
Simulation time 211237752 ps
CPU time 0.86 seconds
Started Jul 06 05:22:22 PM PDT 24
Finished Jul 06 05:22:23 PM PDT 24
Peak memory 206172 kb
Host smart-ee415ab9-fccb-40e7-ac86-e89571c98401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26678
66995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2667866995
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.4126679301
Short name T730
Test name
Test status
Simulation time 13342660616 ps
CPU time 12.41 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:24:49 PM PDT 24
Peak memory 206248 kb
Host smart-2118d320-3f35-40a4-9871-f477b4324227
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4126679301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.4126679301
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1849261146
Short name T42
Test name
Test status
Simulation time 53424155 ps
CPU time 0.69 seconds
Started Jul 06 05:24:37 PM PDT 24
Finished Jul 06 05:24:38 PM PDT 24
Peak memory 206104 kb
Host smart-5ff4245e-1c7d-4d8f-b322-37340e911a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18492
61146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1849261146
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3120020345
Short name T304
Test name
Test status
Simulation time 101988222 ps
CPU time 0.77 seconds
Started Jul 06 05:04:21 PM PDT 24
Finished Jul 06 05:04:22 PM PDT 24
Peak memory 205720 kb
Host smart-820aa63e-d10e-4947-86a1-bc0b319a56ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3120020345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3120020345
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3313205953
Short name T83
Test name
Test status
Simulation time 323535137 ps
CPU time 1.02 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:22 PM PDT 24
Peak memory 206088 kb
Host smart-0e517e20-713e-4397-968f-3987ae7f1e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33132
05953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3313205953
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2563638315
Short name T51
Test name
Test status
Simulation time 20172550281 ps
CPU time 21.13 seconds
Started Jul 06 05:22:22 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206232 kb
Host smart-d7ed5fa8-8cea-4d20-9192-0484cf9f47f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25636
38315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2563638315
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2551011221
Short name T272
Test name
Test status
Simulation time 58402906 ps
CPU time 0.97 seconds
Started Jul 06 05:04:07 PM PDT 24
Finished Jul 06 05:04:08 PM PDT 24
Peak memory 205964 kb
Host smart-c5f6e306-f740-4d1e-a1b9-6b7cdc8ad934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2551011221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2551011221
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4071326501
Short name T306
Test name
Test status
Simulation time 57504622 ps
CPU time 0.71 seconds
Started Jul 06 05:04:08 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 205704 kb
Host smart-2a7a86dc-ca9a-42d8-9439-8d1427363fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4071326501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4071326501
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.756652916
Short name T414
Test name
Test status
Simulation time 180380591 ps
CPU time 0.82 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206180 kb
Host smart-ed6f00a7-6fd9-46be-b371-03142aca70c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75665
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.756652916
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2114183720
Short name T308
Test name
Test status
Simulation time 519222632 ps
CPU time 4.28 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:22 PM PDT 24
Peak memory 205944 kb
Host smart-d44dbd77-dc23-4b93-8111-4e5fabd01d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2114183720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2114183720
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.255890954
Short name T302
Test name
Test status
Simulation time 78646361 ps
CPU time 0.67 seconds
Started Jul 06 05:04:09 PM PDT 24
Finished Jul 06 05:04:11 PM PDT 24
Peak memory 205696 kb
Host smart-e0765289-4692-4c58-be8e-4405dc0b7208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=255890954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.255890954
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.361436861
Short name T261
Test name
Test status
Simulation time 162831375 ps
CPU time 0.8 seconds
Started Jul 06 05:22:23 PM PDT 24
Finished Jul 06 05:22:24 PM PDT 24
Peak memory 206180 kb
Host smart-31a3591d-396a-42fb-8115-aaf663045d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36143
6861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.361436861
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1433338672
Short name T92
Test name
Test status
Simulation time 192078160 ps
CPU time 0.81 seconds
Started Jul 06 05:22:14 PM PDT 24
Finished Jul 06 05:22:15 PM PDT 24
Peak memory 206192 kb
Host smart-012be9a1-d154-4ec0-b1ce-cf9a94b84ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14333
38672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1433338672
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.939741212
Short name T74
Test name
Test status
Simulation time 498258923 ps
CPU time 1.31 seconds
Started Jul 06 05:22:18 PM PDT 24
Finished Jul 06 05:22:20 PM PDT 24
Peak memory 206176 kb
Host smart-89b8422d-b990-4cff-9217-00dd400079b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93974
1212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.939741212
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2927353568
Short name T108
Test name
Test status
Simulation time 1014150036 ps
CPU time 2.25 seconds
Started Jul 06 05:26:14 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206388 kb
Host smart-4f0cbb5b-92c9-413c-9046-9ed89c08d02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29273
53568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2927353568
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.363084764
Short name T309
Test name
Test status
Simulation time 676700808 ps
CPU time 2.86 seconds
Started Jul 06 05:03:39 PM PDT 24
Finished Jul 06 05:03:42 PM PDT 24
Peak memory 205988 kb
Host smart-b6223e55-0f00-4636-a817-2e961475d614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=363084764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.363084764
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4133293461
Short name T313
Test name
Test status
Simulation time 1624824123 ps
CPU time 5.7 seconds
Started Jul 06 05:04:16 PM PDT 24
Finished Jul 06 05:04:23 PM PDT 24
Peak memory 205984 kb
Host smart-615c2631-a172-4ad9-be4c-d6fdabf3da0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4133293461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.4133293461
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.459841638
Short name T297
Test name
Test status
Simulation time 36535283 ps
CPU time 0.65 seconds
Started Jul 06 05:04:25 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 205808 kb
Host smart-60433d0e-c946-4eea-9c6d-dd5505b06b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=459841638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.459841638
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2401944
Short name T433
Test name
Test status
Simulation time 48357924 ps
CPU time 0.68 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:28 PM PDT 24
Peak memory 206220 kb
Host smart-551f9d04-10a4-419b-b6ae-1e4f81db2f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2401944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2401944
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.152415505
Short name T213
Test name
Test status
Simulation time 4370413209 ps
CPU time 4.79 seconds
Started Jul 06 05:22:27 PM PDT 24
Finished Jul 06 05:22:32 PM PDT 24
Peak memory 206228 kb
Host smart-2aa5c778-ab74-4f4b-a1ce-b241176ebad2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=152415505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.152415505
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2890756610
Short name T4
Test name
Test status
Simulation time 8888415815 ps
CPU time 82.42 seconds
Started Jul 06 05:25:53 PM PDT 24
Finished Jul 06 05:27:17 PM PDT 24
Peak memory 206476 kb
Host smart-923358bb-ca78-42b1-868e-4793603d658e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28907
56610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2890756610
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3997197062
Short name T184
Test name
Test status
Simulation time 14053553426 ps
CPU time 280.94 seconds
Started Jul 06 05:22:40 PM PDT 24
Finished Jul 06 05:27:22 PM PDT 24
Peak memory 206536 kb
Host smart-dd9f0e79-dcd0-433c-b818-7e3d58de5af0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3997197062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3997197062
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2854664249
Short name T59
Test name
Test status
Simulation time 286549137 ps
CPU time 1.11 seconds
Started Jul 06 05:22:24 PM PDT 24
Finished Jul 06 05:22:26 PM PDT 24
Peak memory 206156 kb
Host smart-1e98333e-159c-4f5b-88ff-6e5852c4d7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28546
64249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2854664249
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1232552602
Short name T247
Test name
Test status
Simulation time 11347312189 ps
CPU time 99.6 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:25:41 PM PDT 24
Peak memory 206384 kb
Host smart-4375fc41-df49-489f-b999-bf878573964b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12325
52602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1232552602
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2478812635
Short name T162
Test name
Test status
Simulation time 6352091964 ps
CPU time 39.88 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206512 kb
Host smart-9db8bc36-6103-456e-b338-3e9557057f21
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2478812635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2478812635
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1481680605
Short name T2768
Test name
Test status
Simulation time 197520744 ps
CPU time 2.58 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 222004 kb
Host smart-cf760f08-d4bc-40d9-9685-bdaf77ef923d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1481680605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1481680605
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3108267374
Short name T172
Test name
Test status
Simulation time 1334279564 ps
CPU time 3.41 seconds
Started Jul 06 05:27:15 PM PDT 24
Finished Jul 06 05:27:19 PM PDT 24
Peak memory 206428 kb
Host smart-b7d814cd-21ac-48bf-b2cb-b968ae1ce2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31082
67374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3108267374
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3756802709
Short name T156
Test name
Test status
Simulation time 13545580842 ps
CPU time 95.85 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206508 kb
Host smart-273e918e-2d05-429a-ad00-cc398243326d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37568
02709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3756802709
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3551783448
Short name T507
Test name
Test status
Simulation time 143001567 ps
CPU time 0.79 seconds
Started Jul 06 05:22:23 PM PDT 24
Finished Jul 06 05:22:24 PM PDT 24
Peak memory 206160 kb
Host smart-4196fd6b-799e-4871-8dea-5d50341488a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35517
83448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3551783448
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.589002272
Short name T203
Test name
Test status
Simulation time 23403175313 ps
CPU time 25.21 seconds
Started Jul 06 05:24:03 PM PDT 24
Finished Jul 06 05:24:29 PM PDT 24
Peak memory 206540 kb
Host smart-e4915ae2-15c2-4805-bdd1-93123c493d56
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=589002272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.589002272
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.231067557
Short name T236
Test name
Test status
Simulation time 206334808 ps
CPU time 2.9 seconds
Started Jul 06 05:04:09 PM PDT 24
Finished Jul 06 05:04:12 PM PDT 24
Peak memory 214196 kb
Host smart-fc003ac3-5c58-492c-b69a-e08539462128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231067557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.231067557
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1499021418
Short name T549
Test name
Test status
Simulation time 279877976 ps
CPU time 1.62 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206384 kb
Host smart-7dbaacf1-44fd-4429-aa97-f02581ac7fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
21418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1499021418
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2229090031
Short name T67
Test name
Test status
Simulation time 190853588 ps
CPU time 0.81 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206172 kb
Host smart-4de9b879-6bf9-48d5-a6b1-863e057b6597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22290
90031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2229090031
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.4283894943
Short name T57
Test name
Test status
Simulation time 156619534 ps
CPU time 0.77 seconds
Started Jul 06 05:22:12 PM PDT 24
Finished Jul 06 05:22:13 PM PDT 24
Peak memory 206160 kb
Host smart-4689de00-6193-4a12-8b8b-efd35507c410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42838
94943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.4283894943
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1862189967
Short name T70
Test name
Test status
Simulation time 4200442725 ps
CPU time 9.04 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:27 PM PDT 24
Peak memory 206444 kb
Host smart-20be645b-ebc4-4925-9ff5-e50e945e9561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18621
89967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1862189967
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3544903942
Short name T71
Test name
Test status
Simulation time 186418867 ps
CPU time 0.84 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:18 PM PDT 24
Peak memory 206220 kb
Host smart-7f65f6de-f7b2-457b-9051-aaa58e0dac0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35449
03942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3544903942
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2518967421
Short name T80
Test name
Test status
Simulation time 176266543 ps
CPU time 0.82 seconds
Started Jul 06 05:22:29 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 206188 kb
Host smart-71330b12-9f42-41e4-b187-4c3ba0765d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25189
67421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2518967421
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3425221879
Short name T242
Test name
Test status
Simulation time 16623941601 ps
CPU time 119.68 seconds
Started Jul 06 05:22:51 PM PDT 24
Finished Jul 06 05:24:51 PM PDT 24
Peak memory 206548 kb
Host smart-138294a5-c6ea-4d72-b94a-449c09d4be2a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3425221879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3425221879
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3005286786
Short name T696
Test name
Test status
Simulation time 42186761 ps
CPU time 0.66 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:20 PM PDT 24
Peak memory 206184 kb
Host smart-87f174ea-ffbc-4ee6-a412-476885b86ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
86786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3005286786
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3095026437
Short name T62
Test name
Test status
Simulation time 176792730 ps
CPU time 0.79 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:55 PM PDT 24
Peak memory 206156 kb
Host smart-7e3c6522-f16f-4530-8634-14d56057a572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30950
26437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3095026437
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1018786165
Short name T161
Test name
Test status
Simulation time 1234589018 ps
CPU time 2.62 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:36 PM PDT 24
Peak memory 206452 kb
Host smart-7be4954e-2981-4fd5-8f83-b333889ae322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
86165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1018786165
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2909326621
Short name T254
Test name
Test status
Simulation time 750588792 ps
CPU time 4.93 seconds
Started Jul 06 05:04:03 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 205952 kb
Host smart-c852ba3d-d4fd-4ca2-ae0e-9b75df274184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2909326621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2909326621
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3505481171
Short name T60
Test name
Test status
Simulation time 408940790 ps
CPU time 1.24 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 206200 kb
Host smart-d9bfcb5d-9514-48d8-b199-fd0a366e086c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
81171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3505481171
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3314574902
Short name T1774
Test name
Test status
Simulation time 231635510 ps
CPU time 0.9 seconds
Started Jul 06 05:22:34 PM PDT 24
Finished Jul 06 05:22:35 PM PDT 24
Peak memory 206200 kb
Host smart-64ea9d35-726b-49ba-a4af-68ecc20b3385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
74902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3314574902
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3464140543
Short name T139
Test name
Test status
Simulation time 197507552 ps
CPU time 0.86 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206084 kb
Host smart-235a5cc1-f2db-4e6c-bbf8-2009e60a59c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34641
40543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3464140543
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.170379718
Short name T93
Test name
Test status
Simulation time 6916898539 ps
CPU time 15.33 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:30 PM PDT 24
Peak memory 206732 kb
Host smart-20ed7507-b68d-413e-93f3-1ae45617af99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
9718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.170379718
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3242636275
Short name T2187
Test name
Test status
Simulation time 277051520 ps
CPU time 0.9 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206200 kb
Host smart-497a9807-721e-4504-baa8-1ce077f82db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32426
36275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3242636275
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.4083680574
Short name T2684
Test name
Test status
Simulation time 260522718 ps
CPU time 0.95 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206200 kb
Host smart-7fa9e0f5-da02-4da1-bd82-f8aaa9b82744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40836
80574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.4083680574
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.4203499275
Short name T146
Test name
Test status
Simulation time 213512601 ps
CPU time 0.82 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:32 PM PDT 24
Peak memory 206180 kb
Host smart-9abdeaa8-0c4c-4c14-b120-4a0be29a7974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
99275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.4203499275
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.853306675
Short name T235
Test name
Test status
Simulation time 6196272055 ps
CPU time 43.29 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:55 PM PDT 24
Peak memory 206424 kb
Host smart-8f3c3d67-66d8-4b3f-b54f-838dc01769dc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=853306675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.853306675
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2924516985
Short name T130
Test name
Test status
Simulation time 247142645 ps
CPU time 0.89 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206204 kb
Host smart-4d3b0828-1067-4032-a6b5-0f64f0686bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29245
16985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2924516985
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.238743106
Short name T124
Test name
Test status
Simulation time 217478384 ps
CPU time 0.89 seconds
Started Jul 06 05:25:22 PM PDT 24
Finished Jul 06 05:25:24 PM PDT 24
Peak memory 206220 kb
Host smart-8473b948-878b-4259-806a-b8cc3435b1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23874
3106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.238743106
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.463486218
Short name T129
Test name
Test status
Simulation time 238409296 ps
CPU time 1 seconds
Started Jul 06 05:22:50 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 206144 kb
Host smart-644d9037-a3d4-4682-bfe3-b6b45df70e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46348
6218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.463486218
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3246718496
Short name T125
Test name
Test status
Simulation time 197307231 ps
CPU time 0.83 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206012 kb
Host smart-122c5c2d-39f0-4e78-bee9-7f6f8cb08807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32467
18496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3246718496
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2142554753
Short name T195
Test name
Test status
Simulation time 677354399 ps
CPU time 1.76 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206352 kb
Host smart-61b5bdd2-25c1-4144-a53d-167d9ff2bcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
54753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2142554753
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2451819712
Short name T2676
Test name
Test status
Simulation time 170443064 ps
CPU time 0.83 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206164 kb
Host smart-62362848-f814-4e2d-a6c1-300807c0bb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24518
19712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2451819712
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.897592582
Short name T111
Test name
Test status
Simulation time 5201584853 ps
CPU time 35.96 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206444 kb
Host smart-cb9e8dc2-3c53-4870-8c5a-7f2f8d1bb31c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=897592582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.897592582
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1570454949
Short name T121
Test name
Test status
Simulation time 283575388 ps
CPU time 0.89 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206204 kb
Host smart-c575b59e-04ee-499f-b1de-179f84f0ffbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
54949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1570454949
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2645118814
Short name T269
Test name
Test status
Simulation time 140045806 ps
CPU time 2.12 seconds
Started Jul 06 05:03:44 PM PDT 24
Finished Jul 06 05:03:46 PM PDT 24
Peak memory 205856 kb
Host smart-32ea687c-6d4c-42b5-8333-5d678e693453
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2645118814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2645118814
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1601568989
Short name T278
Test name
Test status
Simulation time 821923121 ps
CPU time 7.33 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:51 PM PDT 24
Peak memory 205944 kb
Host smart-0e64b44d-83ba-406c-80e4-8124914c0953
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1601568989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1601568989
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.13158323
Short name T2750
Test name
Test status
Simulation time 82338530 ps
CPU time 0.79 seconds
Started Jul 06 05:03:44 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 205688 kb
Host smart-7bd28bd5-d2e9-4faf-a659-743bcdac340f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=13158323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.13158323
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.667671752
Short name T257
Test name
Test status
Simulation time 166516290 ps
CPU time 2 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:44 PM PDT 24
Peak memory 214168 kb
Host smart-b9dfdeb9-5b3c-4c39-96ed-31af95e4987f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667671752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.667671752
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2741670441
Short name T238
Test name
Test status
Simulation time 176571304 ps
CPU time 1.15 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:44 PM PDT 24
Peak memory 206272 kb
Host smart-767254cf-8f77-4fb7-adcd-9f1ae8df1505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2741670441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2741670441
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1612649806
Short name T218
Test name
Test status
Simulation time 43749435 ps
CPU time 0.67 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 205808 kb
Host smart-2be7832c-43b4-4fd6-ab4f-f71e2cbc6290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1612649806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1612649806
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.242804916
Short name T276
Test name
Test status
Simulation time 87606095 ps
CPU time 2.16 seconds
Started Jul 06 05:03:44 PM PDT 24
Finished Jul 06 05:03:47 PM PDT 24
Peak memory 214204 kb
Host smart-47023e5a-53a3-4de5-9529-a987ddb14945
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=242804916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.242804916
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2150133051
Short name T2755
Test name
Test status
Simulation time 96311908 ps
CPU time 2.51 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 205892 kb
Host smart-53854d1b-a8e8-4f4d-b19a-3e320f1d9311
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2150133051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2150133051
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.643835748
Short name T2790
Test name
Test status
Simulation time 145871072 ps
CPU time 1.41 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 205888 kb
Host smart-762d6054-497e-4cc5-835e-a067ffad2ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=643835748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.643835748
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3989221760
Short name T2707
Test name
Test status
Simulation time 188196525 ps
CPU time 2.1 seconds
Started Jul 06 05:03:52 PM PDT 24
Finished Jul 06 05:03:54 PM PDT 24
Peak memory 205988 kb
Host smart-9475e4ba-f597-4419-b7a7-e3b58a1bfef6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3989221760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3989221760
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.630758822
Short name T287
Test name
Test status
Simulation time 928895293 ps
CPU time 5.03 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:48 PM PDT 24
Peak memory 205992 kb
Host smart-fc99f66f-2580-4ebd-8fdc-1199b2fc9359
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=630758822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.630758822
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3907429497
Short name T2802
Test name
Test status
Simulation time 74371083 ps
CPU time 0.89 seconds
Started Jul 06 05:03:44 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 205704 kb
Host smart-c44fdc85-6972-4f50-acef-f496a7f3700c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3907429497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3907429497
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3071905471
Short name T2727
Test name
Test status
Simulation time 89676278 ps
CPU time 1.79 seconds
Started Jul 06 05:03:51 PM PDT 24
Finished Jul 06 05:03:54 PM PDT 24
Peak memory 214252 kb
Host smart-093101e4-36e1-415e-9ac3-bf8150d649fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071905471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3071905471
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2735761485
Short name T2765
Test name
Test status
Simulation time 136837155 ps
CPU time 1.08 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:43 PM PDT 24
Peak memory 206016 kb
Host smart-bd88038c-3008-42d2-af39-70e5598e2c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2735761485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2735761485
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2052283069
Short name T2729
Test name
Test status
Simulation time 42576233 ps
CPU time 0.69 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:44 PM PDT 24
Peak memory 205744 kb
Host smart-6a4b9452-d200-4113-91a1-ab2717ca31ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2052283069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2052283069
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1413543934
Short name T270
Test name
Test status
Simulation time 106660666 ps
CPU time 1.39 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 214200 kb
Host smart-abcfecb3-e655-4518-87ea-33f3ec323a59
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1413543934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1413543934
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4286509634
Short name T2705
Test name
Test status
Simulation time 483909356 ps
CPU time 4.1 seconds
Started Jul 06 05:03:43 PM PDT 24
Finished Jul 06 05:03:48 PM PDT 24
Peak memory 205896 kb
Host smart-55398ae1-dc43-490f-b9a1-f3a2932addd2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4286509634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4286509634
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3194309491
Short name T282
Test name
Test status
Simulation time 89842593 ps
CPU time 1.04 seconds
Started Jul 06 05:03:51 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 206004 kb
Host smart-806b2be1-75d9-410c-9eb5-8d593d0442fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3194309491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3194309491
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2775582388
Short name T2773
Test name
Test status
Simulation time 88301461 ps
CPU time 1.24 seconds
Started Jul 06 05:04:08 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 215784 kb
Host smart-e0051af7-4cf9-4c70-ae57-c3f5b25de6d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775582388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2775582388
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.665697005
Short name T284
Test name
Test status
Simulation time 117725464 ps
CPU time 1.31 seconds
Started Jul 06 05:04:06 PM PDT 24
Finished Jul 06 05:04:08 PM PDT 24
Peak memory 205916 kb
Host smart-68532945-8c70-4336-bd57-0169281e17a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=665697005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.665697005
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3102096223
Short name T2743
Test name
Test status
Simulation time 88837787 ps
CPU time 2.38 seconds
Started Jul 06 05:04:07 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 222084 kb
Host smart-ebbcdf22-92e0-482f-97a8-6aed2d213316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3102096223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3102096223
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.612704575
Short name T244
Test name
Test status
Simulation time 711565190 ps
CPU time 3.23 seconds
Started Jul 06 05:04:08 PM PDT 24
Finished Jul 06 05:04:12 PM PDT 24
Peak memory 205968 kb
Host smart-c4940fc4-c2b2-4564-95dd-8ad3678472e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=612704575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.612704575
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1380848868
Short name T2780
Test name
Test status
Simulation time 36324774 ps
CPU time 0.78 seconds
Started Jul 06 05:04:07 PM PDT 24
Finished Jul 06 05:04:08 PM PDT 24
Peak memory 205712 kb
Host smart-e8b01a62-29df-4836-a5e8-728894fc1e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1380848868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1380848868
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3124158742
Short name T219
Test name
Test status
Simulation time 36919940 ps
CPU time 0.68 seconds
Started Jul 06 05:04:08 PM PDT 24
Finished Jul 06 05:04:10 PM PDT 24
Peak memory 205744 kb
Host smart-85e55586-452a-4832-94cb-57f602ef37c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3124158742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3124158742
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2886336534
Short name T2761
Test name
Test status
Simulation time 225101363 ps
CPU time 1.6 seconds
Started Jul 06 05:04:09 PM PDT 24
Finished Jul 06 05:04:12 PM PDT 24
Peak memory 205876 kb
Host smart-fe1157b0-4a69-446a-a5c8-675419d2aac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2886336534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2886336534
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2669724485
Short name T2805
Test name
Test status
Simulation time 240530532 ps
CPU time 2.59 seconds
Started Jul 06 05:04:09 PM PDT 24
Finished Jul 06 05:04:13 PM PDT 24
Peak memory 214104 kb
Host smart-fad6ea2e-c6d9-4378-870c-f1196f8f750b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2669724485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2669724485
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4042363331
Short name T307
Test name
Test status
Simulation time 712022788 ps
CPU time 2.93 seconds
Started Jul 06 05:04:07 PM PDT 24
Finished Jul 06 05:04:11 PM PDT 24
Peak memory 205960 kb
Host smart-8c3f6d64-2963-4bef-9648-f9c8b4dcf896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4042363331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4042363331
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.209827374
Short name T2745
Test name
Test status
Simulation time 81836335 ps
CPU time 1.77 seconds
Started Jul 06 05:04:12 PM PDT 24
Finished Jul 06 05:04:15 PM PDT 24
Peak memory 214248 kb
Host smart-3142ccb8-1a4d-42e0-8df7-83a6f18b70d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209827374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.209827374
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.766751026
Short name T2758
Test name
Test status
Simulation time 66139987 ps
CPU time 0.88 seconds
Started Jul 06 05:04:12 PM PDT 24
Finished Jul 06 05:04:14 PM PDT 24
Peak memory 205808 kb
Host smart-a6e286f8-9ddc-462c-afcc-6ab2ccf83107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=766751026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.766751026
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.399893100
Short name T2771
Test name
Test status
Simulation time 64296169 ps
CPU time 0.69 seconds
Started Jul 06 05:04:12 PM PDT 24
Finished Jul 06 05:04:13 PM PDT 24
Peak memory 205808 kb
Host smart-d59bdeef-fdb8-4bf2-872a-7e650ef22002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=399893100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.399893100
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1823133161
Short name T285
Test name
Test status
Simulation time 110772629 ps
CPU time 1.11 seconds
Started Jul 06 05:04:22 PM PDT 24
Finished Jul 06 05:04:24 PM PDT 24
Peak memory 205816 kb
Host smart-34d27463-3108-4aa4-aae4-c82c201630d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1823133161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1823133161
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1733350409
Short name T249
Test name
Test status
Simulation time 160047038 ps
CPU time 2.9 seconds
Started Jul 06 05:04:10 PM PDT 24
Finished Jul 06 05:04:13 PM PDT 24
Peak memory 214268 kb
Host smart-f083d2e9-61a2-46f2-a88f-ef9fb98e0fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1733350409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1733350409
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1441824022
Short name T289
Test name
Test status
Simulation time 839275436 ps
CPU time 4.8 seconds
Started Jul 06 05:04:09 PM PDT 24
Finished Jul 06 05:04:14 PM PDT 24
Peak memory 205948 kb
Host smart-923aa83d-bbcd-43a1-8199-78929ac741f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1441824022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1441824022
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4050101218
Short name T2778
Test name
Test status
Simulation time 182188855 ps
CPU time 1.38 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:17 PM PDT 24
Peak memory 214212 kb
Host smart-3066aa67-8290-46bc-bffd-41ad3db98121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050101218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4050101218
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1158873098
Short name T286
Test name
Test status
Simulation time 50898353 ps
CPU time 0.77 seconds
Started Jul 06 05:04:13 PM PDT 24
Finished Jul 06 05:04:14 PM PDT 24
Peak memory 205688 kb
Host smart-900db90b-10ca-432b-a183-5fcaf7c15b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1158873098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1158873098
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.510114711
Short name T2725
Test name
Test status
Simulation time 52773041 ps
CPU time 0.69 seconds
Started Jul 06 05:04:16 PM PDT 24
Finished Jul 06 05:04:17 PM PDT 24
Peak memory 205768 kb
Host smart-2ba89de6-ee2c-40aa-acc9-e51f880ef9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=510114711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.510114711
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3447515801
Short name T2806
Test name
Test status
Simulation time 105406677 ps
CPU time 1.44 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 205968 kb
Host smart-4cd244e8-32a4-46ad-9aa4-5315a330700b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3447515801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3447515801
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4157233537
Short name T2788
Test name
Test status
Simulation time 317715465 ps
CPU time 3.01 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 214216 kb
Host smart-f9e44912-0184-4878-bbcd-b98b18c0a3bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4157233537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4157233537
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3355803138
Short name T314
Test name
Test status
Simulation time 814043244 ps
CPU time 3.12 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 206008 kb
Host smart-a9bda026-3a50-4a00-8ebc-dc849fdc0cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3355803138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3355803138
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2235182604
Short name T2709
Test name
Test status
Simulation time 116815356 ps
CPU time 2.34 seconds
Started Jul 06 05:04:23 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 214164 kb
Host smart-48034be3-0d26-4770-ab26-1d82ff2f352c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235182604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2235182604
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3990737990
Short name T277
Test name
Test status
Simulation time 127882773 ps
CPU time 1.05 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 205940 kb
Host smart-f6444328-d8f4-469f-bcda-25468103196b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3990737990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3990737990
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1985449305
Short name T2748
Test name
Test status
Simulation time 46675825 ps
CPU time 0.68 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:16 PM PDT 24
Peak memory 205808 kb
Host smart-deb66fa5-9104-4651-beaa-a21fbd40508b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985449305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1985449305
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4189753811
Short name T2779
Test name
Test status
Simulation time 56830370 ps
CPU time 1.03 seconds
Started Jul 06 05:04:12 PM PDT 24
Finished Jul 06 05:04:14 PM PDT 24
Peak memory 205848 kb
Host smart-b4061ae5-f033-4719-bd25-d83d4b215150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4189753811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4189753811
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3515694609
Short name T243
Test name
Test status
Simulation time 206190199 ps
CPU time 2.09 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 221716 kb
Host smart-c2314a86-2a44-4ec2-8149-26635fc39031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3515694609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3515694609
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3844535939
Short name T237
Test name
Test status
Simulation time 615994196 ps
CPU time 2.52 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205872 kb
Host smart-d820096f-2ef5-435d-a5f1-a7c9eb5db07c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3844535939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3844535939
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.479281630
Short name T2774
Test name
Test status
Simulation time 170278627 ps
CPU time 1.88 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 214560 kb
Host smart-53fe8935-29ea-4068-a533-a46c4f0eae4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479281630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.479281630
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.773908435
Short name T280
Test name
Test status
Simulation time 39121966 ps
CPU time 0.81 seconds
Started Jul 06 05:04:24 PM PDT 24
Finished Jul 06 05:04:25 PM PDT 24
Peak memory 205660 kb
Host smart-97b231b1-d9a9-4cdf-81e6-fbe809523de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=773908435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.773908435
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3171868110
Short name T2795
Test name
Test status
Simulation time 45639130 ps
CPU time 0.7 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:16 PM PDT 24
Peak memory 205744 kb
Host smart-e4316bb3-3e89-474e-b4ca-81078c7fdee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3171868110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3171868110
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.937084106
Short name T214
Test name
Test status
Simulation time 154870449 ps
CPU time 1.24 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 205960 kb
Host smart-671d61d8-53cc-499d-939e-78d4f434a196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=937084106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.937084106
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1068326631
Short name T2796
Test name
Test status
Simulation time 101038564 ps
CPU time 1.74 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 214492 kb
Host smart-5b0926a5-a177-47e3-854a-bd9fea3eb082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1068326631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1068326631
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1490069458
Short name T2713
Test name
Test status
Simulation time 404215343 ps
CPU time 2.91 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 205956 kb
Host smart-0f416a4d-15c2-4640-94ba-6fab1e7f6185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1490069458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1490069458
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3015600622
Short name T2740
Test name
Test status
Simulation time 98538798 ps
CPU time 2.4 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 214168 kb
Host smart-c5375ea7-e2d8-47fa-955a-1523f70e0f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015600622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3015600622
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.140487445
Short name T2728
Test name
Test status
Simulation time 63734430 ps
CPU time 0.82 seconds
Started Jul 06 05:04:14 PM PDT 24
Finished Jul 06 05:04:15 PM PDT 24
Peak memory 205804 kb
Host smart-f5cc1ad5-80ae-49d4-a02b-46b0a10e3837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=140487445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.140487445
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.644418445
Short name T2720
Test name
Test status
Simulation time 93269269 ps
CPU time 0.73 seconds
Started Jul 06 05:04:22 PM PDT 24
Finished Jul 06 05:04:24 PM PDT 24
Peak memory 205692 kb
Host smart-ac776df3-6ee5-4d37-a398-fcab0bdee321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=644418445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.644418445
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2761592028
Short name T2789
Test name
Test status
Simulation time 201516433 ps
CPU time 1.69 seconds
Started Jul 06 05:04:13 PM PDT 24
Finished Jul 06 05:04:15 PM PDT 24
Peak memory 205924 kb
Host smart-dd52a5dc-9bbc-4080-83fd-9d709dbf64d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2761592028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2761592028
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3680546473
Short name T2722
Test name
Test status
Simulation time 67359900 ps
CPU time 1.42 seconds
Started Jul 06 05:04:14 PM PDT 24
Finished Jul 06 05:04:15 PM PDT 24
Peak memory 214480 kb
Host smart-d3d8bb6e-54e4-44bf-832f-66bf216b2f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3680546473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3680546473
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1777313091
Short name T2708
Test name
Test status
Simulation time 87595162 ps
CPU time 1.22 seconds
Started Jul 06 05:04:16 PM PDT 24
Finished Jul 06 05:04:17 PM PDT 24
Peak memory 215792 kb
Host smart-522ce578-35e0-4dbf-8150-cd343c5be15e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777313091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1777313091
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1402541677
Short name T281
Test name
Test status
Simulation time 54733574 ps
CPU time 0.82 seconds
Started Jul 06 05:04:23 PM PDT 24
Finished Jul 06 05:04:24 PM PDT 24
Peak memory 205688 kb
Host smart-471b9308-c1c3-44bf-a8f9-f96bfad1a9d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1402541677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1402541677
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1527089023
Short name T2754
Test name
Test status
Simulation time 37077029 ps
CPU time 0.69 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:16 PM PDT 24
Peak memory 205808 kb
Host smart-7e206b98-b94d-4e32-a344-08f62fc89540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1527089023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1527089023
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3078955045
Short name T2799
Test name
Test status
Simulation time 110037035 ps
CPU time 1.28 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:17 PM PDT 24
Peak memory 205972 kb
Host smart-ab193f3f-1d0a-431a-8ab0-ceb007700a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3078955045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3078955045
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1694361440
Short name T251
Test name
Test status
Simulation time 182757015 ps
CPU time 2.2 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 221900 kb
Host smart-d28efa04-eefa-4541-926b-b8a7bbdc7b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1694361440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1694361440
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3781088589
Short name T317
Test name
Test status
Simulation time 545386082 ps
CPU time 2.77 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205944 kb
Host smart-14f0e302-ddd8-4ee8-8b34-e8bd0d9e5ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3781088589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3781088589
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.26005919
Short name T2752
Test name
Test status
Simulation time 68132911 ps
CPU time 1.45 seconds
Started Jul 06 05:04:19 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 214144 kb
Host smart-9c81db50-f914-4455-ac59-72ab8d92c8fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev
_csr_mem_rw_with_rand_reset.26005919
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.471888902
Short name T2791
Test name
Test status
Simulation time 118929036 ps
CPU time 0.85 seconds
Started Jul 06 05:04:18 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 205716 kb
Host smart-409248d2-a168-4d10-97cd-565140342e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=471888902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.471888902
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.741677580
Short name T2742
Test name
Test status
Simulation time 50450642 ps
CPU time 0.69 seconds
Started Jul 06 05:04:13 PM PDT 24
Finished Jul 06 05:04:14 PM PDT 24
Peak memory 205684 kb
Host smart-f4bc81bd-9db4-4309-99cc-71444394cdb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741677580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.741677580
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1938977777
Short name T2787
Test name
Test status
Simulation time 70599870 ps
CPU time 1.1 seconds
Started Jul 06 05:05:01 PM PDT 24
Finished Jul 06 05:05:03 PM PDT 24
Peak memory 205932 kb
Host smart-d8d8fcc1-3300-486a-b48d-4bd8b9976f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1938977777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1938977777
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3069247534
Short name T248
Test name
Test status
Simulation time 70234485 ps
CPU time 1.71 seconds
Started Jul 06 05:04:15 PM PDT 24
Finished Jul 06 05:04:17 PM PDT 24
Peak memory 221856 kb
Host smart-c84f3890-9e14-4d5e-acf9-ffd9b7475d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3069247534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3069247534
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2984608250
Short name T2777
Test name
Test status
Simulation time 91455106 ps
CPU time 1.27 seconds
Started Jul 06 05:04:21 PM PDT 24
Finished Jul 06 05:04:23 PM PDT 24
Peak memory 216052 kb
Host smart-7a73b5e3-275a-44fb-bed8-0412c8784aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984608250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2984608250
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2079684889
Short name T2706
Test name
Test status
Simulation time 44772996 ps
CPU time 0.79 seconds
Started Jul 06 05:04:19 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205772 kb
Host smart-d19862f4-4396-40d2-ae56-178063c30129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2079684889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2079684889
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1691256175
Short name T220
Test name
Test status
Simulation time 61121044 ps
CPU time 0.71 seconds
Started Jul 06 05:04:20 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 205804 kb
Host smart-ad223b53-de5c-4c11-9707-377036c82c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1691256175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1691256175
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2115147824
Short name T2760
Test name
Test status
Simulation time 68781872 ps
CPU time 1.13 seconds
Started Jul 06 05:04:21 PM PDT 24
Finished Jul 06 05:04:23 PM PDT 24
Peak memory 205896 kb
Host smart-a560322d-f0ce-4c2f-a578-f0b68597ddd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2115147824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2115147824
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1349204076
Short name T250
Test name
Test status
Simulation time 283490581 ps
CPU time 2.51 seconds
Started Jul 06 05:04:21 PM PDT 24
Finished Jul 06 05:04:24 PM PDT 24
Peak memory 222212 kb
Host smart-7339718d-7bd1-47a6-806b-7d0cc8b28dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1349204076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1349204076
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.766288547
Short name T2711
Test name
Test status
Simulation time 465718449 ps
CPU time 2.82 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:30 PM PDT 24
Peak memory 205840 kb
Host smart-bd0af479-1976-45b1-a2d3-4f7caa919eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=766288547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.766288547
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3888306524
Short name T273
Test name
Test status
Simulation time 79196765 ps
CPU time 1.97 seconds
Started Jul 06 05:03:49 PM PDT 24
Finished Jul 06 05:03:51 PM PDT 24
Peak memory 205868 kb
Host smart-a0746952-8b8c-46e3-b025-d5bbe6a44626
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3888306524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3888306524
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3903346029
Short name T2738
Test name
Test status
Simulation time 682280763 ps
CPU time 7.38 seconds
Started Jul 06 05:03:49 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 206032 kb
Host smart-2aa65384-b1de-40f6-887c-7957d0abb8e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3903346029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3903346029
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1822308825
Short name T274
Test name
Test status
Simulation time 69607238 ps
CPU time 0.79 seconds
Started Jul 06 05:03:49 PM PDT 24
Finished Jul 06 05:03:50 PM PDT 24
Peak memory 205836 kb
Host smart-06aa0b13-e322-4077-afb5-3446751c2519
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1822308825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1822308825
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1755226068
Short name T2757
Test name
Test status
Simulation time 166574620 ps
CPU time 1.83 seconds
Started Jul 06 05:03:50 PM PDT 24
Finished Jul 06 05:03:52 PM PDT 24
Peak memory 214176 kb
Host smart-c947a578-231c-4964-aebc-b145a110333e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755226068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1755226068
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.526697475
Short name T2764
Test name
Test status
Simulation time 93206860 ps
CPU time 0.86 seconds
Started Jul 06 05:03:50 PM PDT 24
Finished Jul 06 05:03:51 PM PDT 24
Peak memory 205752 kb
Host smart-eb271aea-cd27-4aab-bdfe-90ab41497a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=526697475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.526697475
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3283295443
Short name T222
Test name
Test status
Simulation time 39749765 ps
CPU time 0.69 seconds
Started Jul 06 05:03:50 PM PDT 24
Finished Jul 06 05:03:52 PM PDT 24
Peak memory 205716 kb
Host smart-5f8de90e-f9dc-45e7-aaea-3683470a5734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3283295443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3283295443
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4103061061
Short name T2794
Test name
Test status
Simulation time 71180227 ps
CPU time 1.41 seconds
Started Jul 06 05:03:49 PM PDT 24
Finished Jul 06 05:03:50 PM PDT 24
Peak memory 214148 kb
Host smart-f3af2a6d-e7b5-48bd-a391-fc5c06da8ef0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4103061061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4103061061
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.975957936
Short name T2775
Test name
Test status
Simulation time 107620668 ps
CPU time 2.36 seconds
Started Jul 06 05:03:49 PM PDT 24
Finished Jul 06 05:03:52 PM PDT 24
Peak memory 205892 kb
Host smart-cbef6e08-5457-4795-952f-f277241434d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=975957936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.975957936
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2834373603
Short name T2741
Test name
Test status
Simulation time 185915263 ps
CPU time 1.59 seconds
Started Jul 06 05:03:51 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 205984 kb
Host smart-bf84fbb0-6c38-4f16-b53e-a0dbe9918eb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2834373603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2834373603
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2922402459
Short name T2801
Test name
Test status
Simulation time 195950184 ps
CPU time 2.11 seconds
Started Jul 06 05:03:51 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 214180 kb
Host smart-8a2b3879-18c4-4bd3-9818-f584472d933f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2922402459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2922402459
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1833681924
Short name T2800
Test name
Test status
Simulation time 241272011 ps
CPU time 2.27 seconds
Started Jul 06 05:03:50 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 205924 kb
Host smart-4b872f7c-ce87-4e10-ba79-c5ae0e5d1f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1833681924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1833681924
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2877952514
Short name T2772
Test name
Test status
Simulation time 43423952 ps
CPU time 0.7 seconds
Started Jul 06 05:04:22 PM PDT 24
Finished Jul 06 05:04:23 PM PDT 24
Peak memory 205688 kb
Host smart-81b5d281-f005-4054-a8fc-708abb175c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2877952514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2877952514
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2068676506
Short name T221
Test name
Test status
Simulation time 68137758 ps
CPU time 0.68 seconds
Started Jul 06 05:04:18 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 205808 kb
Host smart-65cc9e06-c9de-4e8c-9d9d-328ba7a768eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068676506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2068676506
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1316364150
Short name T292
Test name
Test status
Simulation time 38000337 ps
CPU time 0.62 seconds
Started Jul 06 05:04:18 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 205724 kb
Host smart-dc1455cf-6fd4-4d0c-88b7-7dc3c7b147c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1316364150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1316364150
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1745067623
Short name T301
Test name
Test status
Simulation time 50337401 ps
CPU time 0.72 seconds
Started Jul 06 05:04:20 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 205748 kb
Host smart-eb44550f-2f63-408e-a508-f11e623f11c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1745067623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1745067623
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1598595188
Short name T2797
Test name
Test status
Simulation time 40779721 ps
CPU time 0.65 seconds
Started Jul 06 05:04:18 PM PDT 24
Finished Jul 06 05:04:19 PM PDT 24
Peak memory 205664 kb
Host smart-ab1e4c8b-2a15-423c-a522-16df40fa1798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1598595188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1598595188
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4143400845
Short name T2717
Test name
Test status
Simulation time 37014781 ps
CPU time 0.67 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 205680 kb
Host smart-f4cfabb7-0197-4040-a837-ee9ebf0fe778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4143400845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4143400845
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1663780846
Short name T2803
Test name
Test status
Simulation time 85505334 ps
CPU time 0.73 seconds
Started Jul 06 05:04:20 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 205768 kb
Host smart-1a82713f-e8e8-4c17-8bf5-fa651aa07e43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1663780846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1663780846
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1317410362
Short name T2746
Test name
Test status
Simulation time 47585587 ps
CPU time 0.7 seconds
Started Jul 06 05:04:17 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 205696 kb
Host smart-c7a2e7ec-3cc1-4352-af9b-a2ea319a775e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1317410362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1317410362
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1049885799
Short name T2723
Test name
Test status
Simulation time 55582947 ps
CPU time 0.68 seconds
Started Jul 06 05:04:20 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 205768 kb
Host smart-0930b139-0c57-4f14-9e85-5a632762a153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1049885799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1049885799
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.471490529
Short name T2733
Test name
Test status
Simulation time 47507305 ps
CPU time 0.67 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 205692 kb
Host smart-5ce95f74-b40a-42cb-b407-8c7f991087ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=471490529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.471490529
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2646413260
Short name T279
Test name
Test status
Simulation time 211673649 ps
CPU time 2.13 seconds
Started Jul 06 05:03:58 PM PDT 24
Finished Jul 06 05:04:00 PM PDT 24
Peak memory 205948 kb
Host smart-9c294598-f809-481a-951b-75c0d85561f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2646413260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2646413260
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3924209996
Short name T2759
Test name
Test status
Simulation time 971796470 ps
CPU time 4.36 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 205844 kb
Host smart-16dc046a-fcc5-4e36-9732-eedc979d8614
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3924209996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3924209996
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2297795699
Short name T2730
Test name
Test status
Simulation time 59814655 ps
CPU time 0.81 seconds
Started Jul 06 05:03:57 PM PDT 24
Finished Jul 06 05:03:58 PM PDT 24
Peak memory 205784 kb
Host smart-e1af6f51-cf58-4b5f-9169-f660f4fde8b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2297795699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2297795699
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2398890809
Short name T2712
Test name
Test status
Simulation time 75361764 ps
CPU time 1.77 seconds
Started Jul 06 05:03:57 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 214324 kb
Host smart-15f38d4a-c8ee-403b-9332-47013e4e2f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398890809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2398890809
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2330605097
Short name T2769
Test name
Test status
Simulation time 169668090 ps
CPU time 1.05 seconds
Started Jul 06 05:03:56 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 205916 kb
Host smart-d4e16dba-b5f4-4ca4-bb4b-6fa5312d90b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2330605097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2330605097
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1217798943
Short name T2786
Test name
Test status
Simulation time 37789940 ps
CPU time 0.69 seconds
Started Jul 06 05:03:51 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 205772 kb
Host smart-0cf82795-7ec2-4fb3-a760-a203ad7ee72b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1217798943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1217798943
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2593228083
Short name T2762
Test name
Test status
Simulation time 113658637 ps
CPU time 1.45 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 214188 kb
Host smart-28793aa9-6712-49c3-b41f-e2f57baf2e2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2593228083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2593228083
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3873473009
Short name T2704
Test name
Test status
Simulation time 254650283 ps
CPU time 2.53 seconds
Started Jul 06 05:03:50 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 205960 kb
Host smart-bee007eb-0ae5-4d71-a20b-3f17710d629d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3873473009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3873473009
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1880007584
Short name T283
Test name
Test status
Simulation time 498080742 ps
CPU time 2.31 seconds
Started Jul 06 05:03:56 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 205920 kb
Host smart-a17ff584-cc79-4d3a-87b1-17115f6dba38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1880007584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1880007584
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2067668695
Short name T2714
Test name
Test status
Simulation time 123359521 ps
CPU time 1.53 seconds
Started Jul 06 05:03:50 PM PDT 24
Finished Jul 06 05:03:52 PM PDT 24
Peak memory 221760 kb
Host smart-a9c48756-47e3-4d9b-8b83-2d3f05c66086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2067668695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2067668695
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2854207140
Short name T312
Test name
Test status
Simulation time 801876584 ps
CPU time 2.91 seconds
Started Jul 06 05:03:49 PM PDT 24
Finished Jul 06 05:03:52 PM PDT 24
Peak memory 206008 kb
Host smart-37afa140-e951-467b-aec9-4bfbcf4f3430
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2854207140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2854207140
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.875645776
Short name T2792
Test name
Test status
Simulation time 47236227 ps
CPU time 0.73 seconds
Started Jul 06 05:04:19 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205776 kb
Host smart-eaba0d75-e7c5-49f5-8819-028c5f594c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=875645776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.875645776
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2963763385
Short name T2781
Test name
Test status
Simulation time 49257767 ps
CPU time 0.73 seconds
Started Jul 06 05:04:20 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 205800 kb
Host smart-63b181ee-434c-4127-8fb5-c1acc98cbdd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2963763385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2963763385
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1521100801
Short name T291
Test name
Test status
Simulation time 110560838 ps
CPU time 0.75 seconds
Started Jul 06 05:04:19 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205776 kb
Host smart-12267faf-5160-4c9a-a87f-adbdc4549015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1521100801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1521100801
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1142901906
Short name T2726
Test name
Test status
Simulation time 32756579 ps
CPU time 0.69 seconds
Started Jul 06 05:04:22 PM PDT 24
Finished Jul 06 05:04:23 PM PDT 24
Peak memory 205700 kb
Host smart-49ac9c21-fad0-4340-833e-2cc1a1b69f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1142901906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1142901906
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1211723289
Short name T2744
Test name
Test status
Simulation time 45160283 ps
CPU time 0.72 seconds
Started Jul 06 05:04:21 PM PDT 24
Finished Jul 06 05:04:22 PM PDT 24
Peak memory 205808 kb
Host smart-1093d9cb-584e-46a0-93e7-ed7407674082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1211723289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1211723289
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.239506910
Short name T2731
Test name
Test status
Simulation time 49175479 ps
CPU time 0.7 seconds
Started Jul 06 05:04:18 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205800 kb
Host smart-537ae5dd-68db-4746-915a-587ffaa44e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=239506910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.239506910
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4121130637
Short name T299
Test name
Test status
Simulation time 48458065 ps
CPU time 0.66 seconds
Started Jul 06 05:04:20 PM PDT 24
Finished Jul 06 05:04:21 PM PDT 24
Peak memory 205712 kb
Host smart-2ab52552-40fb-430e-a098-d2b5f4388d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4121130637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4121130637
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2344969338
Short name T305
Test name
Test status
Simulation time 57685811 ps
CPU time 0.68 seconds
Started Jul 06 05:04:19 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205720 kb
Host smart-a9e08b14-fb5d-4554-8703-95073180bd99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2344969338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2344969338
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3501664772
Short name T2793
Test name
Test status
Simulation time 135283598 ps
CPU time 3.37 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 205900 kb
Host smart-59ca445b-b4be-4fea-92f7-5fc0923e0612
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3501664772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3501664772
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2477289379
Short name T2785
Test name
Test status
Simulation time 1677395580 ps
CPU time 9.34 seconds
Started Jul 06 05:03:57 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 206004 kb
Host smart-34550b16-e2ae-43f0-a9d0-cc95cba9896d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2477289379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2477289379
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3131894152
Short name T2807
Test name
Test status
Simulation time 80886404 ps
CPU time 0.82 seconds
Started Jul 06 05:03:57 PM PDT 24
Finished Jul 06 05:03:58 PM PDT 24
Peak memory 205808 kb
Host smart-ba5f81c2-217b-4f3d-8c36-835609c67d3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3131894152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3131894152
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1199389028
Short name T288
Test name
Test status
Simulation time 171123206 ps
CPU time 2.02 seconds
Started Jul 06 05:03:57 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 214168 kb
Host smart-69ebe712-42d2-4f36-84f4-65059ec4ee31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199389028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1199389028
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.791764774
Short name T2776
Test name
Test status
Simulation time 72682810 ps
CPU time 0.98 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 205972 kb
Host smart-6c1c8dfb-abb6-4d1f-b49d-08ce3a1da871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=791764774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.791764774
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2993691756
Short name T271
Test name
Test status
Simulation time 128652314 ps
CPU time 1.55 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 214200 kb
Host smart-fcbf7343-3851-4b73-b250-d6ebeec00ea0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2993691756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2993691756
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3653251846
Short name T2710
Test name
Test status
Simulation time 196120815 ps
CPU time 4.23 seconds
Started Jul 06 05:03:58 PM PDT 24
Finished Jul 06 05:04:03 PM PDT 24
Peak memory 205928 kb
Host smart-364a35e5-b4dd-4a2a-afd8-03bbd72e82cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3653251846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3653251846
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3641000140
Short name T2747
Test name
Test status
Simulation time 307875514 ps
CPU time 1.67 seconds
Started Jul 06 05:03:56 PM PDT 24
Finished Jul 06 05:03:58 PM PDT 24
Peak memory 205940 kb
Host smart-a8bba1c6-50ab-4452-9e0d-78e7b4b81146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3641000140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3641000140
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2699970567
Short name T2721
Test name
Test status
Simulation time 283004262 ps
CPU time 3.19 seconds
Started Jul 06 05:03:58 PM PDT 24
Finished Jul 06 05:04:01 PM PDT 24
Peak memory 214264 kb
Host smart-5ad3b3bf-155a-4387-9e5f-57871becee7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2699970567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2699970567
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2550643812
Short name T310
Test name
Test status
Simulation time 1006937882 ps
CPU time 4.98 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:04:00 PM PDT 24
Peak memory 205964 kb
Host smart-5a93ad9f-c1de-48dc-a68d-6999428221a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2550643812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2550643812
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3761094868
Short name T2718
Test name
Test status
Simulation time 41052760 ps
CPU time 0.67 seconds
Started Jul 06 05:04:18 PM PDT 24
Finished Jul 06 05:04:20 PM PDT 24
Peak memory 205780 kb
Host smart-484b0f32-8562-4bfd-b464-d793adb242d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3761094868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3761094868
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1818073968
Short name T296
Test name
Test status
Simulation time 90677665 ps
CPU time 0.72 seconds
Started Jul 06 05:04:25 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 205748 kb
Host smart-2bbabd49-c7b8-4eb1-aee3-729b0eb564d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818073968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1818073968
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.296402240
Short name T2735
Test name
Test status
Simulation time 62952270 ps
CPU time 0.68 seconds
Started Jul 06 05:04:25 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 205720 kb
Host smart-7739e121-c00f-4faf-bc97-b6b50d79efb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=296402240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.296402240
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3858106974
Short name T2736
Test name
Test status
Simulation time 71300684 ps
CPU time 0.74 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 205732 kb
Host smart-51f9afb5-94aa-47dd-8917-f2c166cbc2c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3858106974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3858106974
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.61061793
Short name T2770
Test name
Test status
Simulation time 91909531 ps
CPU time 0.72 seconds
Started Jul 06 05:04:25 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 205668 kb
Host smart-c6a67dfa-9e8c-4089-9ec6-c4672a8709b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=61061793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.61061793
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4242055678
Short name T2767
Test name
Test status
Simulation time 87179536 ps
CPU time 0.7 seconds
Started Jul 06 05:04:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 205776 kb
Host smart-c3730161-0d94-40be-ba75-5b185c491c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4242055678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4242055678
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2673357991
Short name T2716
Test name
Test status
Simulation time 63640240 ps
CPU time 0.68 seconds
Started Jul 06 05:04:24 PM PDT 24
Finished Jul 06 05:04:25 PM PDT 24
Peak memory 205744 kb
Host smart-1aed7b99-dce6-40ef-bc05-e3beb8d274cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2673357991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2673357991
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.358927028
Short name T294
Test name
Test status
Simulation time 36252627 ps
CPU time 0.66 seconds
Started Jul 06 05:04:25 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 205812 kb
Host smart-844650fd-b288-486f-b15e-d7277728dbde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=358927028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.358927028
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3788372538
Short name T298
Test name
Test status
Simulation time 35257806 ps
CPU time 0.69 seconds
Started Jul 06 05:04:25 PM PDT 24
Finished Jul 06 05:04:26 PM PDT 24
Peak memory 205808 kb
Host smart-ece0b7af-787c-473d-be7d-43e2501c3257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3788372538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3788372538
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3193241990
Short name T2739
Test name
Test status
Simulation time 191270732 ps
CPU time 1.8 seconds
Started Jul 06 05:04:02 PM PDT 24
Finished Jul 06 05:04:04 PM PDT 24
Peak memory 214208 kb
Host smart-bdb5a797-bb8b-4493-84a0-8aa418dfec77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193241990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.3193241990
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4154850219
Short name T2766
Test name
Test status
Simulation time 84993133 ps
CPU time 1 seconds
Started Jul 06 05:03:56 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 205912 kb
Host smart-ea9ee0a5-b849-4dab-8cee-cf16c7d8ec76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4154850219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.4154850219
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1488152243
Short name T2737
Test name
Test status
Simulation time 62005715 ps
CPU time 0.77 seconds
Started Jul 06 05:03:58 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 205808 kb
Host smart-5b403331-b4df-4166-9252-ee5fdd88e2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1488152243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1488152243
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.555381374
Short name T2763
Test name
Test status
Simulation time 138648871 ps
CPU time 1.17 seconds
Started Jul 06 05:04:03 PM PDT 24
Finished Jul 06 05:04:04 PM PDT 24
Peak memory 205948 kb
Host smart-2747dc6d-5cd4-4805-b375-8f837964cb6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=555381374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.555381374
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3460870927
Short name T2804
Test name
Test status
Simulation time 162796930 ps
CPU time 1.72 seconds
Started Jul 06 05:03:55 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 205964 kb
Host smart-ac4dfa66-8c66-4971-83e9-1c9b0d0048cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3460870927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3460870927
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.254703668
Short name T315
Test name
Test status
Simulation time 341560089 ps
CPU time 2.53 seconds
Started Jul 06 05:03:57 PM PDT 24
Finished Jul 06 05:04:00 PM PDT 24
Peak memory 205968 kb
Host smart-117ed247-8b10-4085-9261-2dfa17ebe1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=254703668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.254703668
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.267783115
Short name T2756
Test name
Test status
Simulation time 107725289 ps
CPU time 1.35 seconds
Started Jul 06 05:04:04 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 214232 kb
Host smart-c04156fd-69f5-40c1-86c4-8eb8ee0ab18f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267783115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.267783115
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3131646590
Short name T2798
Test name
Test status
Simulation time 96377539 ps
CPU time 1.04 seconds
Started Jul 06 05:04:02 PM PDT 24
Finished Jul 06 05:04:03 PM PDT 24
Peak memory 205924 kb
Host smart-146b281f-3fdd-462c-8f94-847a77c0d4a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3131646590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3131646590
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2445741777
Short name T303
Test name
Test status
Simulation time 30724934 ps
CPU time 0.65 seconds
Started Jul 06 05:04:05 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 205788 kb
Host smart-253d07d9-4ba9-4554-a253-87eda52d96e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2445741777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2445741777
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2554562301
Short name T2784
Test name
Test status
Simulation time 131016724 ps
CPU time 1.14 seconds
Started Jul 06 05:04:04 PM PDT 24
Finished Jul 06 05:04:05 PM PDT 24
Peak memory 205920 kb
Host smart-b76d9ee2-b586-4337-8c2d-7a4d8bdffa3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2554562301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2554562301
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2145160747
Short name T2749
Test name
Test status
Simulation time 269940610 ps
CPU time 2.34 seconds
Started Jul 06 05:04:03 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 221660 kb
Host smart-3d61e8d1-879d-4758-9216-8bbb105902d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2145160747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2145160747
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2123811381
Short name T2715
Test name
Test status
Simulation time 779045751 ps
CPU time 4.83 seconds
Started Jul 06 05:04:04 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 205928 kb
Host smart-3ea09ea8-c170-41ac-81d3-1d09625e5fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2123811381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2123811381
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3387190250
Short name T2751
Test name
Test status
Simulation time 210955277 ps
CPU time 2.07 seconds
Started Jul 06 05:04:02 PM PDT 24
Finished Jul 06 05:04:05 PM PDT 24
Peak memory 214204 kb
Host smart-73c7de14-45ab-4409-ad4b-d59d1ab65e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387190250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3387190250
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2033560650
Short name T293
Test name
Test status
Simulation time 71068501 ps
CPU time 0.95 seconds
Started Jul 06 05:04:01 PM PDT 24
Finished Jul 06 05:04:02 PM PDT 24
Peak memory 205708 kb
Host smart-0911fe78-1d8c-4a3b-a92e-d1441c7ea32d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2033560650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2033560650
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1754698662
Short name T2734
Test name
Test status
Simulation time 38320435 ps
CPU time 0.66 seconds
Started Jul 06 05:04:01 PM PDT 24
Finished Jul 06 05:04:02 PM PDT 24
Peak memory 205740 kb
Host smart-723e4423-192e-4eb3-b61d-a6f51bd95ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1754698662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1754698662
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.961553987
Short name T2732
Test name
Test status
Simulation time 102968150 ps
CPU time 1.12 seconds
Started Jul 06 05:04:01 PM PDT 24
Finished Jul 06 05:04:02 PM PDT 24
Peak memory 205932 kb
Host smart-b5e3d4ca-589e-4e55-99e3-a4c08d90e575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=961553987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.961553987
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1687459387
Short name T245
Test name
Test status
Simulation time 131569132 ps
CPU time 1.96 seconds
Started Jul 06 05:04:03 PM PDT 24
Finished Jul 06 05:04:05 PM PDT 24
Peak memory 221936 kb
Host smart-7f131a7e-2e6b-46a0-8185-84b95a2ac0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1687459387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1687459387
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.633443011
Short name T316
Test name
Test status
Simulation time 398502474 ps
CPU time 2.93 seconds
Started Jul 06 05:04:06 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 205940 kb
Host smart-12f5193c-dfca-4e06-9315-99b19fdb1137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=633443011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.633443011
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2118556357
Short name T211
Test name
Test status
Simulation time 220174383 ps
CPU time 1.78 seconds
Started Jul 06 05:04:04 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 214228 kb
Host smart-1e105eac-08dc-4bf0-a14e-f823f9e4fbb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118556357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2118556357
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.142338708
Short name T275
Test name
Test status
Simulation time 85519010 ps
CPU time 1.07 seconds
Started Jul 06 05:04:02 PM PDT 24
Finished Jul 06 05:04:04 PM PDT 24
Peak memory 205904 kb
Host smart-4d417cf2-be6c-4b86-bf42-aead3ce12eec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=142338708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.142338708
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3041053370
Short name T2782
Test name
Test status
Simulation time 50083216 ps
CPU time 0.69 seconds
Started Jul 06 05:04:04 PM PDT 24
Finished Jul 06 05:04:05 PM PDT 24
Peak memory 205780 kb
Host smart-108bc026-285b-49bb-aaa5-813d9a6982ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3041053370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3041053370
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3700554871
Short name T2724
Test name
Test status
Simulation time 91050487 ps
CPU time 1.09 seconds
Started Jul 06 05:04:02 PM PDT 24
Finished Jul 06 05:04:03 PM PDT 24
Peak memory 205848 kb
Host smart-9c094320-600d-4496-ab92-8df3e567eb6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3700554871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3700554871
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1171444778
Short name T2753
Test name
Test status
Simulation time 77048887 ps
CPU time 1.99 seconds
Started Jul 06 05:04:04 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 214300 kb
Host smart-c50f4690-22bb-43dd-94a2-0015d3bc546b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1171444778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1171444778
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.797304606
Short name T253
Test name
Test status
Simulation time 178797503 ps
CPU time 2.4 seconds
Started Jul 06 05:04:09 PM PDT 24
Finished Jul 06 05:04:12 PM PDT 24
Peak memory 214232 kb
Host smart-a45ae63d-565c-4448-b6a5-af9453a6cdc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797304606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.797304606
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3400063624
Short name T2783
Test name
Test status
Simulation time 54476602 ps
CPU time 0.88 seconds
Started Jul 06 05:04:10 PM PDT 24
Finished Jul 06 05:04:11 PM PDT 24
Peak memory 205692 kb
Host smart-9d35c9db-bb4a-449d-9398-85de1af3adca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3400063624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3400063624
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3454828641
Short name T2719
Test name
Test status
Simulation time 122353993 ps
CPU time 1.56 seconds
Started Jul 06 05:04:10 PM PDT 24
Finished Jul 06 05:04:12 PM PDT 24
Peak memory 205936 kb
Host smart-09b20f41-36a1-4ceb-8fc4-aa12e90b8776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3454828641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3454828641
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3260565371
Short name T252
Test name
Test status
Simulation time 135274824 ps
CPU time 3.05 seconds
Started Jul 06 05:04:05 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 214192 kb
Host smart-2ad35a3b-1933-48de-82c0-4c7e50c4c68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3260565371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3260565371
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1861765328
Short name T311
Test name
Test status
Simulation time 620127197 ps
CPU time 2.86 seconds
Started Jul 06 05:04:06 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 206020 kb
Host smart-8e2f6735-79eb-48db-b9cb-ec23a203d4f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1861765328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1861765328
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3158953662
Short name T1755
Test name
Test status
Simulation time 121605847 ps
CPU time 0.78 seconds
Started Jul 06 05:22:27 PM PDT 24
Finished Jul 06 05:22:28 PM PDT 24
Peak memory 206256 kb
Host smart-05aca965-598f-45d7-aae9-b922d3ed1782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3158953662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3158953662
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.431144214
Short name T1550
Test name
Test status
Simulation time 4077504156 ps
CPU time 4.94 seconds
Started Jul 06 05:22:14 PM PDT 24
Finished Jul 06 05:22:20 PM PDT 24
Peak memory 206376 kb
Host smart-9794625d-16fb-4be2-b6ba-a1d2f4ffa950
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=431144214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.431144214
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.4184363612
Short name T1088
Test name
Test status
Simulation time 13345943809 ps
CPU time 11.91 seconds
Started Jul 06 05:22:13 PM PDT 24
Finished Jul 06 05:22:25 PM PDT 24
Peak memory 206412 kb
Host smart-49c6fe09-a5a2-4efd-acb5-4afd68a1a6dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4184363612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.4184363612
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3465408657
Short name T840
Test name
Test status
Simulation time 23333800887 ps
CPU time 23.37 seconds
Started Jul 06 05:22:12 PM PDT 24
Finished Jul 06 05:22:36 PM PDT 24
Peak memory 206248 kb
Host smart-577c3e5e-96f6-40a8-b901-89ad0cfcd997
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3465408657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3465408657
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.956147134
Short name T351
Test name
Test status
Simulation time 158370332 ps
CPU time 0.85 seconds
Started Jul 06 05:22:15 PM PDT 24
Finished Jul 06 05:22:16 PM PDT 24
Peak memory 206128 kb
Host smart-eccd318e-11b3-4484-9c93-09a76194418d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95614
7134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.956147134
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2836946988
Short name T1754
Test name
Test status
Simulation time 165786752 ps
CPU time 0.75 seconds
Started Jul 06 05:22:12 PM PDT 24
Finished Jul 06 05:22:13 PM PDT 24
Peak memory 206200 kb
Host smart-8ec701c4-ad37-4b79-b40c-1f5c9d820d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
46988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2836946988
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3456202857
Short name T1715
Test name
Test status
Simulation time 208548407 ps
CPU time 0.86 seconds
Started Jul 06 05:22:15 PM PDT 24
Finished Jul 06 05:22:16 PM PDT 24
Peak memory 206108 kb
Host smart-772cfef3-ab1f-4d5c-8bd9-207c8ebed916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34562
02857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3456202857
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2823344185
Short name T188
Test name
Test status
Simulation time 582062866 ps
CPU time 1.45 seconds
Started Jul 06 05:22:13 PM PDT 24
Finished Jul 06 05:22:15 PM PDT 24
Peak memory 206208 kb
Host smart-4fcbe79d-c5be-4b16-a753-82029f8d1c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28233
44185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2823344185
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.246300771
Short name T2425
Test name
Test status
Simulation time 12061073892 ps
CPU time 25.3 seconds
Started Jul 06 05:22:13 PM PDT 24
Finished Jul 06 05:22:39 PM PDT 24
Peak memory 206420 kb
Host smart-f4dee554-b7e1-4ae3-82bd-61772c474916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24630
0771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.246300771
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.1910672094
Short name T2170
Test name
Test status
Simulation time 395725257 ps
CPU time 1.32 seconds
Started Jul 06 05:22:14 PM PDT 24
Finished Jul 06 05:22:15 PM PDT 24
Peak memory 206188 kb
Host smart-76aa640b-dce6-48c1-998a-334d8a0f4649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19106
72094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.1910672094
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1375802869
Short name T2322
Test name
Test status
Simulation time 146168256 ps
CPU time 0.83 seconds
Started Jul 06 05:22:12 PM PDT 24
Finished Jul 06 05:22:13 PM PDT 24
Peak memory 206192 kb
Host smart-cc88b18f-d954-4e97-b4ae-0852b4a0f705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13758
02869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1375802869
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2293473405
Short name T1476
Test name
Test status
Simulation time 5134131380 ps
CPU time 44.69 seconds
Started Jul 06 05:22:14 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206424 kb
Host smart-8b2d20fd-2cd2-4507-9596-c7cde471a775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22934
73405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2293473405
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1524958101
Short name T1987
Test name
Test status
Simulation time 53688214 ps
CPU time 0.64 seconds
Started Jul 06 05:22:12 PM PDT 24
Finished Jul 06 05:22:13 PM PDT 24
Peak memory 206200 kb
Host smart-13db8963-dcc1-433f-b5a8-755407194f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
58101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1524958101
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2076378734
Short name T750
Test name
Test status
Simulation time 936972212 ps
CPU time 2.18 seconds
Started Jul 06 05:22:13 PM PDT 24
Finished Jul 06 05:22:15 PM PDT 24
Peak memory 206404 kb
Host smart-2b7f3dd1-bb4f-4789-a10b-dad8bb91f469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20763
78734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2076378734
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1329003773
Short name T2136
Test name
Test status
Simulation time 188626723 ps
CPU time 1.58 seconds
Started Jul 06 05:22:10 PM PDT 24
Finished Jul 06 05:22:12 PM PDT 24
Peak memory 206464 kb
Host smart-19dfeafc-967f-4c2e-8cd0-3c348c3602b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13290
03773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1329003773
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.817386655
Short name T367
Test name
Test status
Simulation time 83178194307 ps
CPU time 123.65 seconds
Started Jul 06 05:22:12 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206452 kb
Host smart-c713f779-216f-44d0-b468-010c2468074b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=817386655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.817386655
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2917568764
Short name T2488
Test name
Test status
Simulation time 120163853487 ps
CPU time 179.73 seconds
Started Jul 06 05:22:11 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206432 kb
Host smart-c1cf8d8f-4767-44ba-9489-d2a841c8cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917568764 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2917568764
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.502487973
Short name T2100
Test name
Test status
Simulation time 102129883965 ps
CPU time 141.88 seconds
Started Jul 06 05:22:19 PM PDT 24
Finished Jul 06 05:24:42 PM PDT 24
Peak memory 206460 kb
Host smart-685f8f58-9720-403f-9de5-3d5fb88f729b
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=502487973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.502487973
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.705181118
Short name T2014
Test name
Test status
Simulation time 96110761047 ps
CPU time 127.2 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:24:28 PM PDT 24
Peak memory 206472 kb
Host smart-7c1be0cd-80f2-4c9c-9508-14298953386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705181118 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.705181118
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2512092675
Short name T2130
Test name
Test status
Simulation time 89185640169 ps
CPU time 119.35 seconds
Started Jul 06 05:22:19 PM PDT 24
Finished Jul 06 05:24:18 PM PDT 24
Peak memory 206368 kb
Host smart-2be29c84-f734-4254-82fd-f7b150e15aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25120
92675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2512092675
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2109060036
Short name T350
Test name
Test status
Simulation time 194365107 ps
CPU time 0.86 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:18 PM PDT 24
Peak memory 206180 kb
Host smart-3557636b-04ac-43b7-ba9d-a09628c97f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
60036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2109060036
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3905862283
Short name T2111
Test name
Test status
Simulation time 150435688 ps
CPU time 0.77 seconds
Started Jul 06 05:22:18 PM PDT 24
Finished Jul 06 05:22:19 PM PDT 24
Peak memory 206184 kb
Host smart-a184882c-e8d4-411a-9c54-d2cb458e8619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
62283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3905862283
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3410517601
Short name T1793
Test name
Test status
Simulation time 222258913 ps
CPU time 0.9 seconds
Started Jul 06 05:22:19 PM PDT 24
Finished Jul 06 05:22:21 PM PDT 24
Peak memory 206176 kb
Host smart-69804b47-3824-4194-9342-47906367c7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34105
17601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3410517601
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.791283490
Short name T2433
Test name
Test status
Simulation time 5660586133 ps
CPU time 40.86 seconds
Started Jul 06 05:22:19 PM PDT 24
Finished Jul 06 05:23:00 PM PDT 24
Peak memory 206492 kb
Host smart-88e99950-ffb4-42f1-8388-57884b42e324
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=791283490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.791283490
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2935837642
Short name T690
Test name
Test status
Simulation time 204479927 ps
CPU time 0.87 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:18 PM PDT 24
Peak memory 206208 kb
Host smart-ff0d2cc2-406a-4971-88da-ea6626e76dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29358
37642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2935837642
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.559976502
Short name T75
Test name
Test status
Simulation time 569222928 ps
CPU time 1.65 seconds
Started Jul 06 05:22:20 PM PDT 24
Finished Jul 06 05:22:22 PM PDT 24
Peak memory 206200 kb
Host smart-114e1cc5-178a-4fc5-9f8c-30adb61ca3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55997
6502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.559976502
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1904985757
Short name T672
Test name
Test status
Simulation time 23363623904 ps
CPU time 24.03 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:42 PM PDT 24
Peak memory 206236 kb
Host smart-4973c533-e3df-4b17-9dc6-bf25a7dc16a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19049
85757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1904985757
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3079678937
Short name T1856
Test name
Test status
Simulation time 3316858177 ps
CPU time 3.91 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:26 PM PDT 24
Peak memory 206264 kb
Host smart-b17841cb-baf6-46b6-8858-0ddf427aee0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
78937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3079678937
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3658318083
Short name T2429
Test name
Test status
Simulation time 13925251003 ps
CPU time 396.08 seconds
Started Jul 06 05:22:18 PM PDT 24
Finished Jul 06 05:28:54 PM PDT 24
Peak memory 206532 kb
Host smart-387b23d1-8063-4213-bb88-f8c7732b6aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36583
18083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3658318083
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1495937645
Short name T1783
Test name
Test status
Simulation time 5046519048 ps
CPU time 35.11 seconds
Started Jul 06 05:22:20 PM PDT 24
Finished Jul 06 05:22:55 PM PDT 24
Peak memory 206456 kb
Host smart-c9f292f5-295e-44ec-b13e-1906493e5cdb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1495937645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1495937645
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3596742845
Short name T2253
Test name
Test status
Simulation time 238642140 ps
CPU time 0.99 seconds
Started Jul 06 05:22:19 PM PDT 24
Finished Jul 06 05:22:20 PM PDT 24
Peak memory 206188 kb
Host smart-55f87ead-6868-448d-8e56-549c3ce847e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3596742845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3596742845
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3823195909
Short name T2634
Test name
Test status
Simulation time 288013690 ps
CPU time 0.99 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:18 PM PDT 24
Peak memory 206184 kb
Host smart-96f2a1e5-b5b5-4fee-b3be-53b4d571322e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38231
95909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3823195909
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3797855327
Short name T845
Test name
Test status
Simulation time 5397030827 ps
CPU time 149.43 seconds
Started Jul 06 05:22:18 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206492 kb
Host smart-befb077b-1509-49fe-ae40-64ed032e53e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
55327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3797855327
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.646683836
Short name T1058
Test name
Test status
Simulation time 3888991798 ps
CPU time 107.26 seconds
Started Jul 06 05:22:22 PM PDT 24
Finished Jul 06 05:24:09 PM PDT 24
Peak memory 206484 kb
Host smart-b990fe5b-2c04-48a1-9db4-6f718d0b9aa8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=646683836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.646683836
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1399542512
Short name T655
Test name
Test status
Simulation time 199057162 ps
CPU time 0.86 seconds
Started Jul 06 05:22:17 PM PDT 24
Finished Jul 06 05:22:18 PM PDT 24
Peak memory 206192 kb
Host smart-eff58f97-09f9-46ea-8e71-aedd796f2825
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1399542512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1399542512
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1143779041
Short name T332
Test name
Test status
Simulation time 164660155 ps
CPU time 0.78 seconds
Started Jul 06 05:22:18 PM PDT 24
Finished Jul 06 05:22:19 PM PDT 24
Peak memory 206112 kb
Host smart-a4b9da15-5e17-48a5-bd3d-f364c1ef6215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
79041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1143779041
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2109424621
Short name T73
Test name
Test status
Simulation time 534195119 ps
CPU time 1.34 seconds
Started Jul 06 05:22:18 PM PDT 24
Finished Jul 06 05:22:20 PM PDT 24
Peak memory 206184 kb
Host smart-4b34a029-111a-4b36-9147-822af6350b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
24621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2109424621
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3323601470
Short name T940
Test name
Test status
Simulation time 148160062 ps
CPU time 0.78 seconds
Started Jul 06 05:22:24 PM PDT 24
Finished Jul 06 05:22:25 PM PDT 24
Peak memory 206136 kb
Host smart-9c2a33a9-e440-4f5b-94fa-a97c89014903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
01470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3323601470
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1949573803
Short name T2564
Test name
Test status
Simulation time 215922480 ps
CPU time 0.94 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:23 PM PDT 24
Peak memory 206112 kb
Host smart-9e70fc9d-f7ca-4922-b9d8-51368798d4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
73803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1949573803
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2210713419
Short name T1657
Test name
Test status
Simulation time 151050331 ps
CPU time 0.81 seconds
Started Jul 06 05:22:23 PM PDT 24
Finished Jul 06 05:22:24 PM PDT 24
Peak memory 206140 kb
Host smart-c83ceaa9-9837-4407-a04c-a845ff21b0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22107
13419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2210713419
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3639735909
Short name T2532
Test name
Test status
Simulation time 155676192 ps
CPU time 0.79 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:22 PM PDT 24
Peak memory 206096 kb
Host smart-a1f03e32-e929-437b-9caa-baf9c07e4cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36397
35909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3639735909
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2395918157
Short name T356
Test name
Test status
Simulation time 181418182 ps
CPU time 0.83 seconds
Started Jul 06 05:22:24 PM PDT 24
Finished Jul 06 05:22:25 PM PDT 24
Peak memory 206172 kb
Host smart-e2e7bbbb-3941-4660-aa2b-337251ba2141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
18157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2395918157
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.41006244
Short name T2158
Test name
Test status
Simulation time 236527204 ps
CPU time 0.99 seconds
Started Jul 06 05:22:22 PM PDT 24
Finished Jul 06 05:22:23 PM PDT 24
Peak memory 206188 kb
Host smart-c1a19eae-bf7f-46f6-8f76-5aa0fdaeb5d5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=41006244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.41006244
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2493784115
Short name T1439
Test name
Test status
Simulation time 288069960 ps
CPU time 1 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:22 PM PDT 24
Peak memory 206132 kb
Host smart-cb769273-f0e8-4299-a5e0-2eb164a8c72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24937
84115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2493784115
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1924797748
Short name T1867
Test name
Test status
Simulation time 247828085 ps
CPU time 0.99 seconds
Started Jul 06 05:22:26 PM PDT 24
Finished Jul 06 05:22:27 PM PDT 24
Peak memory 206204 kb
Host smart-11e34b06-8e95-45ca-afcf-a23c66d619d1
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1924797748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1924797748
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3459371609
Short name T216
Test name
Test status
Simulation time 246508405 ps
CPU time 0.95 seconds
Started Jul 06 05:22:22 PM PDT 24
Finished Jul 06 05:22:23 PM PDT 24
Peak memory 206208 kb
Host smart-a32de55f-332e-4e34-895a-e7cbe41fdb3a
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3459371609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3459371609
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3324151761
Short name T1097
Test name
Test status
Simulation time 44457567 ps
CPU time 0.67 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:23 PM PDT 24
Peak memory 206200 kb
Host smart-e40496c2-12f3-4028-909b-c3343c2cd8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
51761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3324151761
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.419347081
Short name T2528
Test name
Test status
Simulation time 19902314706 ps
CPU time 42.38 seconds
Started Jul 06 05:22:23 PM PDT 24
Finished Jul 06 05:23:06 PM PDT 24
Peak memory 206556 kb
Host smart-ff7b15bc-d2ef-45bb-be0d-bafbcfcb7092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
7081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.419347081
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1330434929
Short name T758
Test name
Test status
Simulation time 232172788 ps
CPU time 0.88 seconds
Started Jul 06 05:22:24 PM PDT 24
Finished Jul 06 05:22:25 PM PDT 24
Peak memory 206200 kb
Host smart-fedc1bf4-bed8-4998-b335-5aacee524fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13304
34929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1330434929
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2171941208
Short name T175
Test name
Test status
Simulation time 7963723038 ps
CPU time 223.87 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206540 kb
Host smart-0d9db655-2130-4d0e-b47b-6225864bc6ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2171941208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2171941208
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1079579388
Short name T1811
Test name
Test status
Simulation time 5133031308 ps
CPU time 34.2 seconds
Started Jul 06 05:22:24 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206412 kb
Host smart-f34821e6-79ab-4a69-b241-d796897cca91
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1079579388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1079579388
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3441960748
Short name T1543
Test name
Test status
Simulation time 11462719539 ps
CPU time 203.46 seconds
Started Jul 06 05:22:22 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206548 kb
Host smart-25e7a2cd-5b52-4ec3-822d-66c5b84817a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3441960748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3441960748
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.4025382565
Short name T630
Test name
Test status
Simulation time 284525777 ps
CPU time 0.97 seconds
Started Jul 06 05:22:25 PM PDT 24
Finished Jul 06 05:22:26 PM PDT 24
Peak memory 206148 kb
Host smart-3d80f8e6-46d8-4f27-b6db-0dbc2ffdda2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
82565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.4025382565
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2983968951
Short name T1945
Test name
Test status
Simulation time 192856451 ps
CPU time 0.89 seconds
Started Jul 06 05:22:23 PM PDT 24
Finished Jul 06 05:22:24 PM PDT 24
Peak memory 206200 kb
Host smart-8f7fb953-e235-4224-b50b-13313f7d1e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29839
68951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2983968951
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.716267892
Short name T2617
Test name
Test status
Simulation time 147170427 ps
CPU time 0.8 seconds
Started Jul 06 05:22:21 PM PDT 24
Finished Jul 06 05:22:23 PM PDT 24
Peak memory 206188 kb
Host smart-dce4bce2-e198-4d4b-8e28-4fd4200e2305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71626
7892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.716267892
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1305396406
Short name T209
Test name
Test status
Simulation time 412515081 ps
CPU time 1.26 seconds
Started Jul 06 05:22:29 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 224076 kb
Host smart-e41f46f1-6e04-489a-8dd6-229843e610ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1305396406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1305396406
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.796103641
Short name T2060
Test name
Test status
Simulation time 308848897 ps
CPU time 1.07 seconds
Started Jul 06 05:22:26 PM PDT 24
Finished Jul 06 05:22:27 PM PDT 24
Peak memory 206200 kb
Host smart-a1b03831-acaf-4c44-a82c-4bf604574166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79610
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.796103641
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.722817331
Short name T1253
Test name
Test status
Simulation time 161932381 ps
CPU time 0.8 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:22:29 PM PDT 24
Peak memory 206204 kb
Host smart-0c360f6a-0116-4116-8335-2ab10674091d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72281
7331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.722817331
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3698912183
Short name T1506
Test name
Test status
Simulation time 149729688 ps
CPU time 0.76 seconds
Started Jul 06 05:22:31 PM PDT 24
Finished Jul 06 05:22:31 PM PDT 24
Peak memory 206100 kb
Host smart-a7e65292-c2dc-4bb4-81e8-3ee91dc454a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
12183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3698912183
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2694310393
Short name T999
Test name
Test status
Simulation time 235156090 ps
CPU time 0.96 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 206200 kb
Host smart-3049d5d0-e8f3-4fb9-bf64-913485a5c594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943
10393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2694310393
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.4246999317
Short name T524
Test name
Test status
Simulation time 5514759559 ps
CPU time 50.2 seconds
Started Jul 06 05:22:27 PM PDT 24
Finished Jul 06 05:23:18 PM PDT 24
Peak memory 206416 kb
Host smart-e6b3a3ce-78e1-4743-887c-8cd0385e4722
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4246999317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.4246999317
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.232302197
Short name T705
Test name
Test status
Simulation time 206381724 ps
CPU time 0.88 seconds
Started Jul 06 05:22:27 PM PDT 24
Finished Jul 06 05:22:28 PM PDT 24
Peak memory 206200 kb
Host smart-ffe23629-9c49-4890-ba13-25857f3de18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23230
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.232302197
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.683853454
Short name T1149
Test name
Test status
Simulation time 180226850 ps
CPU time 0.84 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:22:29 PM PDT 24
Peak memory 206204 kb
Host smart-18df4d3b-75ae-4762-9e90-6ec6a8376182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68385
3454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.683853454
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1022857633
Short name T322
Test name
Test status
Simulation time 1331388321 ps
CPU time 2.67 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:22:31 PM PDT 24
Peak memory 206364 kb
Host smart-c8d20ed2-433f-4cd6-bbb5-6b03e5220ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10228
57633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1022857633
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.383420826
Short name T1986
Test name
Test status
Simulation time 5856453898 ps
CPU time 39.9 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:23:08 PM PDT 24
Peak memory 206440 kb
Host smart-89782741-356c-4002-a21c-53befc45f32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38342
0826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.383420826
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2838533769
Short name T1010
Test name
Test status
Simulation time 12235359072 ps
CPU time 66.3 seconds
Started Jul 06 05:22:29 PM PDT 24
Finished Jul 06 05:23:36 PM PDT 24
Peak memory 206440 kb
Host smart-fd1c209a-210e-4777-948f-f6b4d5c1e5ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2838533769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2838533769
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1751379153
Short name T2516
Test name
Test status
Simulation time 66720105 ps
CPU time 0.76 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206212 kb
Host smart-c812b873-fd4c-4e9a-b942-4b42030d1091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1751379153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1751379153
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3170105607
Short name T778
Test name
Test status
Simulation time 13329505051 ps
CPU time 12.26 seconds
Started Jul 06 05:22:34 PM PDT 24
Finished Jul 06 05:22:47 PM PDT 24
Peak memory 206448 kb
Host smart-b3a1361d-4b14-4ef0-a3c7-b6c75d8f031e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3170105607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3170105607
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.54442377
Short name T2193
Test name
Test status
Simulation time 23344817419 ps
CPU time 22.81 seconds
Started Jul 06 05:22:28 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 206412 kb
Host smart-02e79ad8-b2ca-4617-bf60-69421432c3e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=54442377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.54442377
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3082221275
Short name T2522
Test name
Test status
Simulation time 166564409 ps
CPU time 0.78 seconds
Started Jul 06 05:22:31 PM PDT 24
Finished Jul 06 05:22:32 PM PDT 24
Peak memory 206176 kb
Host smart-0dfd6e15-0f4a-4e36-9410-320f7842dc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30822
21275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3082221275
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3567734799
Short name T1689
Test name
Test status
Simulation time 159540212 ps
CPU time 0.79 seconds
Started Jul 06 05:22:27 PM PDT 24
Finished Jul 06 05:22:28 PM PDT 24
Peak memory 206220 kb
Host smart-09e55306-9674-4f8f-a74a-41a3c5e2da7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35677
34799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3567734799
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.141982628
Short name T91
Test name
Test status
Simulation time 176279912 ps
CPU time 0.79 seconds
Started Jul 06 05:22:29 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 206156 kb
Host smart-e525c343-dfbf-4de1-adfc-56b94c03c11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14198
2628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.141982628
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1995393297
Short name T2436
Test name
Test status
Simulation time 161897983 ps
CPU time 0.81 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206168 kb
Host smart-712dac0f-688d-4364-8718-8927a382f390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
93297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1995393297
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1337088493
Short name T109
Test name
Test status
Simulation time 216043010 ps
CPU time 0.85 seconds
Started Jul 06 05:22:34 PM PDT 24
Finished Jul 06 05:22:35 PM PDT 24
Peak memory 206120 kb
Host smart-68705f0a-8835-49fa-a835-224271647495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13370
88493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1337088493
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.886513193
Short name T1759
Test name
Test status
Simulation time 1102476749 ps
CPU time 2.38 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:22:36 PM PDT 24
Peak memory 206364 kb
Host smart-4297ca4d-cb79-4daf-8725-81393d13290a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88651
3193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.886513193
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.110115885
Short name T554
Test name
Test status
Simulation time 9044259848 ps
CPU time 18.17 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:53 PM PDT 24
Peak memory 206472 kb
Host smart-a6d3bb1a-7425-4eaf-b539-ee1ac98d771a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
5885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.110115885
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1113324149
Short name T1175
Test name
Test status
Simulation time 492656121 ps
CPU time 1.36 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:22:38 PM PDT 24
Peak memory 206180 kb
Host smart-4bdd979f-bafc-4247-9e28-fcfd5b0d95b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11133
24149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1113324149
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1083292383
Short name T762
Test name
Test status
Simulation time 136470645 ps
CPU time 0.76 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206076 kb
Host smart-94e5f773-75b3-4d7b-a1f7-b0d7fe49af9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10832
92383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1083292383
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.583677910
Short name T1841
Test name
Test status
Simulation time 52437067 ps
CPU time 0.65 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:22:34 PM PDT 24
Peak memory 206196 kb
Host smart-2e7869f4-bbaa-40cf-b554-cd220d95eb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58367
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.583677910
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.666131376
Short name T2600
Test name
Test status
Simulation time 854639575 ps
CPU time 2.32 seconds
Started Jul 06 05:22:38 PM PDT 24
Finished Jul 06 05:22:41 PM PDT 24
Peak memory 206444 kb
Host smart-15c633e9-99f1-4fa0-990a-3cde2da6880c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66613
1376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.666131376
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1327960195
Short name T1264
Test name
Test status
Simulation time 116192044383 ps
CPU time 181.88 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:25:37 PM PDT 24
Peak memory 206444 kb
Host smart-443fe6d5-2b5a-4ec3-ab6f-bd6c2ab3a8c1
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1327960195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1327960195
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.974934617
Short name T1979
Test name
Test status
Simulation time 104433710879 ps
CPU time 142.08 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:24:57 PM PDT 24
Peak memory 206424 kb
Host smart-45113e68-a645-416e-b05c-d29a64686e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974934617 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.974934617
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2480524760
Short name T674
Test name
Test status
Simulation time 87136656584 ps
CPU time 124.93 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:24:38 PM PDT 24
Peak memory 206432 kb
Host smart-c01f3356-9aee-4ff1-89a9-7a4ce20578f7
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2480524760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2480524760
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.531067807
Short name T2662
Test name
Test status
Simulation time 106068400056 ps
CPU time 135.85 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:24:52 PM PDT 24
Peak memory 206444 kb
Host smart-a784436c-43c5-4ebf-b5a3-4c80a10fa496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531067807 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.531067807
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3726235769
Short name T2566
Test name
Test status
Simulation time 88162365688 ps
CPU time 126.64 seconds
Started Jul 06 05:22:38 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206460 kb
Host smart-95319fc8-9065-45fb-ae97-d86ca2e2d15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37262
35769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3726235769
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.747039903
Short name T2338
Test name
Test status
Simulation time 170448526 ps
CPU time 0.8 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206176 kb
Host smart-e9f8766d-458d-4752-bf74-df4aaf89b209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74703
9903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.747039903
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3174596859
Short name T1330
Test name
Test status
Simulation time 165259859 ps
CPU time 0.87 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:22:34 PM PDT 24
Peak memory 206160 kb
Host smart-fbceb98a-d565-4308-9175-e176d3a3fcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31745
96859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3174596859
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.675016052
Short name T1805
Test name
Test status
Simulation time 228097626 ps
CPU time 1 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:22:34 PM PDT 24
Peak memory 206176 kb
Host smart-0a563846-5879-4974-9aae-0e52b19b50b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67501
6052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.675016052
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3265854255
Short name T2282
Test name
Test status
Simulation time 5310479028 ps
CPU time 50.64 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:23:24 PM PDT 24
Peak memory 206460 kb
Host smart-908c12e2-d1ad-4931-84cd-d0a6c6964a21
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3265854255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3265854255
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.159974296
Short name T1230
Test name
Test status
Simulation time 210708839 ps
CPU time 0.82 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206204 kb
Host smart-68e9f4f4-4106-477c-87d4-69efb1134098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15997
4296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.159974296
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2812630987
Short name T990
Test name
Test status
Simulation time 23280865809 ps
CPU time 22.51 seconds
Started Jul 06 05:22:40 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206264 kb
Host smart-f8c16b42-6848-455a-b15a-ef17190c054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28126
30987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2812630987
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.978539802
Short name T1168
Test name
Test status
Simulation time 3292012693 ps
CPU time 3.72 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206188 kb
Host smart-7c291fbc-41b5-4f9e-979c-6143f7e08646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97853
9802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.978539802
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3738698499
Short name T1272
Test name
Test status
Simulation time 11136894414 ps
CPU time 312.13 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:27:49 PM PDT 24
Peak memory 205984 kb
Host smart-6c9b6c55-c6ed-428b-9b26-c12dc315a310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
98499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3738698499
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2996706782
Short name T1375
Test name
Test status
Simulation time 3312123454 ps
CPU time 91.23 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 206428 kb
Host smart-1d33ff53-8bba-4f63-b795-6e1547a25e39
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2996706782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2996706782
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2531801061
Short name T578
Test name
Test status
Simulation time 249334997 ps
CPU time 0.92 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:22:38 PM PDT 24
Peak memory 206072 kb
Host smart-dbd79d5e-6e02-483c-bab1-04cfb0988ed5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2531801061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2531801061
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.245073177
Short name T2259
Test name
Test status
Simulation time 195299105 ps
CPU time 0.88 seconds
Started Jul 06 05:22:32 PM PDT 24
Finished Jul 06 05:22:33 PM PDT 24
Peak memory 206040 kb
Host smart-72841b78-110d-44d3-889b-2505371f4362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24507
3177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.245073177
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3500868918
Short name T1409
Test name
Test status
Simulation time 5729466770 ps
CPU time 166.75 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:25:22 PM PDT 24
Peak memory 206460 kb
Host smart-6fa50031-1a23-4f25-9053-3998a5148cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35008
68918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3500868918
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.4093544507
Short name T1561
Test name
Test status
Simulation time 4131377813 ps
CPU time 30.21 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:23:06 PM PDT 24
Peak memory 206416 kb
Host smart-36ff774f-990a-4330-a4af-3b39ad85f1a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4093544507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.4093544507
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.435477566
Short name T360
Test name
Test status
Simulation time 175001381 ps
CPU time 0.8 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:36 PM PDT 24
Peak memory 206144 kb
Host smart-604c23de-f6b6-448e-a6b4-442bf35b770a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=435477566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.435477566
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2387170830
Short name T1448
Test name
Test status
Simulation time 166981466 ps
CPU time 0.86 seconds
Started Jul 06 05:22:38 PM PDT 24
Finished Jul 06 05:22:40 PM PDT 24
Peak memory 206176 kb
Host smart-d722216b-06e8-4889-a3fd-a759c04777d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23871
70830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2387170830
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2374660498
Short name T1086
Test name
Test status
Simulation time 178181539 ps
CPU time 0.83 seconds
Started Jul 06 05:22:34 PM PDT 24
Finished Jul 06 05:22:35 PM PDT 24
Peak memory 206184 kb
Host smart-98542d69-2d8d-4152-990a-7ac947f47c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
60498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2374660498
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3259783011
Short name T1737
Test name
Test status
Simulation time 155406648 ps
CPU time 0.8 seconds
Started Jul 06 05:22:37 PM PDT 24
Finished Jul 06 05:22:38 PM PDT 24
Peak memory 206200 kb
Host smart-e79bb662-db7f-4f93-b4cf-81bc12d07bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
83011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3259783011
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3542178913
Short name T1446
Test name
Test status
Simulation time 182441048 ps
CPU time 0.84 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:36 PM PDT 24
Peak memory 206112 kb
Host smart-22c5a76d-e73d-4d1b-9c9e-82266f615abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35421
78913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3542178913
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3661592030
Short name T1578
Test name
Test status
Simulation time 241888435 ps
CPU time 0.85 seconds
Started Jul 06 05:22:32 PM PDT 24
Finished Jul 06 05:22:33 PM PDT 24
Peak memory 206136 kb
Host smart-bd27a80c-dcf2-462d-97f8-8ffe6650bf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
92030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3661592030
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2685191628
Short name T1574
Test name
Test status
Simulation time 213064208 ps
CPU time 0.88 seconds
Started Jul 06 05:22:37 PM PDT 24
Finished Jul 06 05:22:38 PM PDT 24
Peak memory 206208 kb
Host smart-ffad6988-1e42-4d9e-9e83-51ca9051504c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2685191628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2685191628
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2462647395
Short name T215
Test name
Test status
Simulation time 178747028 ps
CPU time 0.82 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:36 PM PDT 24
Peak memory 206196 kb
Host smart-c8abc343-8617-4f59-822b-d099941806cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
47395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2462647395
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1121490065
Short name T1169
Test name
Test status
Simulation time 153948758 ps
CPU time 0.76 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:22:46 PM PDT 24
Peak memory 206180 kb
Host smart-2e77a753-a4b5-41f9-8729-13df2979d835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
90065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1121490065
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2086148148
Short name T1158
Test name
Test status
Simulation time 40011914 ps
CPU time 0.65 seconds
Started Jul 06 05:22:38 PM PDT 24
Finished Jul 06 05:22:39 PM PDT 24
Peak memory 206192 kb
Host smart-5de3c33b-b62a-4310-b128-e6eb10d3159d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
48148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2086148148
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1143091516
Short name T1787
Test name
Test status
Simulation time 13033980590 ps
CPU time 29.63 seconds
Started Jul 06 05:22:36 PM PDT 24
Finished Jul 06 05:23:06 PM PDT 24
Peak memory 206028 kb
Host smart-9a4fc1b7-6953-4335-949b-3da10ffdb0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11430
91516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1143091516
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.402980845
Short name T1597
Test name
Test status
Simulation time 178635605 ps
CPU time 0.83 seconds
Started Jul 06 05:22:33 PM PDT 24
Finished Jul 06 05:22:34 PM PDT 24
Peak memory 206200 kb
Host smart-543c0700-1b3a-42c2-a0a7-bfdf40cfe1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298
0845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.402980845
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2609881614
Short name T2109
Test name
Test status
Simulation time 159691845 ps
CPU time 0.81 seconds
Started Jul 06 05:22:35 PM PDT 24
Finished Jul 06 05:22:37 PM PDT 24
Peak memory 206176 kb
Host smart-939f6ca5-9e12-40cc-b42c-638d39d32dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
81614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2609881614
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3021787598
Short name T1040
Test name
Test status
Simulation time 23567305896 ps
CPU time 575.77 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:32:18 PM PDT 24
Peak memory 206444 kb
Host smart-52e704ba-fb0a-4b88-8baf-1d95f1759ad6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3021787598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3021787598
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3305088385
Short name T1732
Test name
Test status
Simulation time 244560715 ps
CPU time 0.87 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:22:44 PM PDT 24
Peak memory 206200 kb
Host smart-ba42ce38-f8ee-4507-bd31-390349e7e008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33050
88385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3305088385
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1796274859
Short name T629
Test name
Test status
Simulation time 245493696 ps
CPU time 0.89 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:22:45 PM PDT 24
Peak memory 206124 kb
Host smart-fcb2d9db-394a-43aa-b251-19bc597920b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17962
74859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1796274859
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3347365502
Short name T752
Test name
Test status
Simulation time 175698294 ps
CPU time 0.79 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206204 kb
Host smart-8985c4e5-1847-4695-a00c-27589078353b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
65502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3347365502
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.209018683
Short name T82
Test name
Test status
Simulation time 197369524 ps
CPU time 0.86 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:42 PM PDT 24
Peak memory 206200 kb
Host smart-a76b238f-fa6f-4499-ba8b-711cf05f8b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20901
8683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.209018683
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1841383973
Short name T223
Test name
Test status
Simulation time 256470717 ps
CPU time 1.12 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 224036 kb
Host smart-defcc588-ec7b-49fd-a8b9-f2b15188ce6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1841383973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1841383973
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.3612017495
Short name T1420
Test name
Test status
Simulation time 391226869 ps
CPU time 1.23 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206200 kb
Host smart-497306f7-ccda-4993-aa54-00b0330def88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
17495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.3612017495
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.67556568
Short name T1922
Test name
Test status
Simulation time 315946005 ps
CPU time 1 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:42 PM PDT 24
Peak memory 206128 kb
Host smart-63711435-ab7b-42a5-8b24-ca01c68c8f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67556
568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.67556568
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.970763560
Short name T2315
Test name
Test status
Simulation time 206665087 ps
CPU time 0.8 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:22:44 PM PDT 24
Peak memory 206224 kb
Host smart-d12a46fa-6e75-4478-951f-f10d427aa0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97076
3560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.970763560
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.147175117
Short name T2345
Test name
Test status
Simulation time 182752670 ps
CPU time 0.82 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206148 kb
Host smart-dca81724-be9e-4d92-a7d5-40974c15f7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14717
5117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.147175117
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.512229967
Short name T396
Test name
Test status
Simulation time 222063286 ps
CPU time 0.93 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 206200 kb
Host smart-f96d2a3e-622e-4d85-893c-b8c664ebf4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51222
9967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.512229967
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.4245829110
Short name T1527
Test name
Test status
Simulation time 6076962205 ps
CPU time 40.95 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:23:22 PM PDT 24
Peak memory 206424 kb
Host smart-e23a6728-d9f5-418b-b8bc-2241e26538d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4245829110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.4245829110
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1512136087
Short name T490
Test name
Test status
Simulation time 198122332 ps
CPU time 0.84 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:22:45 PM PDT 24
Peak memory 206180 kb
Host smart-0591b1eb-5b4a-4385-95be-6981be833a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15121
36087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1512136087
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3189080587
Short name T716
Test name
Test status
Simulation time 160616829 ps
CPU time 0.82 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:22:44 PM PDT 24
Peak memory 206168 kb
Host smart-377f9b6b-52d8-4b99-9062-2c491da3029d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890
80587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3189080587
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3887128945
Short name T2030
Test name
Test status
Simulation time 199834591 ps
CPU time 0.9 seconds
Started Jul 06 05:22:40 PM PDT 24
Finished Jul 06 05:22:41 PM PDT 24
Peak memory 206196 kb
Host smart-5ef53d26-487e-4f47-b54c-df90dfd613d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
28945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3887128945
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4025762162
Short name T1419
Test name
Test status
Simulation time 3981837757 ps
CPU time 36.79 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:23:19 PM PDT 24
Peak memory 206420 kb
Host smart-28bd3485-b0e1-49aa-907a-52febf6b0182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40257
62162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4025762162
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3401840521
Short name T163
Test name
Test status
Simulation time 17201540228 ps
CPU time 132.31 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:24:55 PM PDT 24
Peak memory 206552 kb
Host smart-b9bc3209-adb6-4aeb-b7b1-4f7cbdc163cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3401840521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3401840521
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3315945666
Short name T746
Test name
Test status
Simulation time 44632057 ps
CPU time 0.73 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206284 kb
Host smart-65b93c83-72c1-4b2f-afdc-b815f94a124d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3315945666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3315945666
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1076548815
Short name T1849
Test name
Test status
Simulation time 3922567685 ps
CPU time 4.4 seconds
Started Jul 06 05:24:04 PM PDT 24
Finished Jul 06 05:24:09 PM PDT 24
Peak memory 206176 kb
Host smart-38e7a450-369f-4cb4-83d7-b22bc34a03b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1076548815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1076548815
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.850629391
Short name T13
Test name
Test status
Simulation time 13387183851 ps
CPU time 12.63 seconds
Started Jul 06 05:24:04 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206424 kb
Host smart-ac355370-cb58-428a-94a8-2fd1fe94db83
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=850629391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.850629391
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3078777281
Short name T434
Test name
Test status
Simulation time 181805826 ps
CPU time 0.87 seconds
Started Jul 06 05:24:06 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 206200 kb
Host smart-9c505688-11d9-4b0d-ae17-084fc34c6ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30787
77281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3078777281
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1203791569
Short name T66
Test name
Test status
Simulation time 137109655 ps
CPU time 0.83 seconds
Started Jul 06 05:24:06 PM PDT 24
Finished Jul 06 05:24:08 PM PDT 24
Peak memory 206200 kb
Host smart-04c60155-904e-4d6a-9c4b-f9f8a8f5d2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
91569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1203791569
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.714065999
Short name T193
Test name
Test status
Simulation time 252574750 ps
CPU time 1.03 seconds
Started Jul 06 05:24:06 PM PDT 24
Finished Jul 06 05:24:08 PM PDT 24
Peak memory 206156 kb
Host smart-f2e10ab1-1a30-49ba-b45e-13e6c633c40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71406
5999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.714065999
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3012312596
Short name T1736
Test name
Test status
Simulation time 1084959450 ps
CPU time 2.35 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206368 kb
Host smart-ff74ef6e-4cf7-45eb-82d3-beff88b13684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30123
12596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3012312596
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.876201422
Short name T1034
Test name
Test status
Simulation time 12599487755 ps
CPU time 26.9 seconds
Started Jul 06 05:24:06 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206460 kb
Host smart-6ce2c75b-3f43-4aac-8c56-6b0b252a97e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87620
1422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.876201422
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.83715672
Short name T1723
Test name
Test status
Simulation time 324425852 ps
CPU time 1.18 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206180 kb
Host smart-56d82484-aa7a-433a-b2e3-9ab590813e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83715
672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.83715672
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2130935860
Short name T1719
Test name
Test status
Simulation time 161029677 ps
CPU time 0.78 seconds
Started Jul 06 05:24:05 PM PDT 24
Finished Jul 06 05:24:06 PM PDT 24
Peak memory 206192 kb
Host smart-a405046b-8b28-45b8-8e6b-10781e7b67ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
35860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2130935860
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2406580144
Short name T591
Test name
Test status
Simulation time 50766966 ps
CPU time 0.71 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206164 kb
Host smart-ac4eee9d-8b61-40d3-b887-ae9d0ab4310d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24065
80144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2406580144
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.210571478
Short name T1278
Test name
Test status
Simulation time 799205822 ps
CPU time 2.11 seconds
Started Jul 06 05:24:09 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206388 kb
Host smart-d66674e4-4857-45a7-9b87-6ea1a48670a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
1478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.210571478
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3674697187
Short name T198
Test name
Test status
Simulation time 161917877 ps
CPU time 1.17 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206292 kb
Host smart-f19143be-828f-4bca-8a43-d04186eadee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
97187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3674697187
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2915203219
Short name T555
Test name
Test status
Simulation time 221274731 ps
CPU time 0.83 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206184 kb
Host smart-59b8ccd7-131b-4bec-a4e6-7b5925526372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152
03219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2915203219
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.821364505
Short name T113
Test name
Test status
Simulation time 188536033 ps
CPU time 0.82 seconds
Started Jul 06 05:24:06 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 206200 kb
Host smart-015af17b-3b64-4e51-9d6c-f5b5a48bfe7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82136
4505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.821364505
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.341291781
Short name T2066
Test name
Test status
Simulation time 178253073 ps
CPU time 0.8 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206160 kb
Host smart-85626b32-dbb3-4e0d-90ec-d8b8be50ebf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34129
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.341291781
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3153287685
Short name T1254
Test name
Test status
Simulation time 216796041 ps
CPU time 0.93 seconds
Started Jul 06 05:24:09 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206176 kb
Host smart-f12b516b-64db-495b-9c7b-659c3a028b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
87685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3153287685
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3008045448
Short name T1184
Test name
Test status
Simulation time 23289342282 ps
CPU time 23.91 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206152 kb
Host smart-1e59bbfb-d7ff-4a8a-8c0b-59c0c2092a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30080
45448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3008045448
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.346906262
Short name T228
Test name
Test status
Simulation time 3287561574 ps
CPU time 3.5 seconds
Started Jul 06 05:24:09 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206228 kb
Host smart-b4eb1275-c11e-4839-a7f8-abe253f4be50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
6262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.346906262
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2811463544
Short name T1513
Test name
Test status
Simulation time 10578339359 ps
CPU time 100.14 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206444 kb
Host smart-0dcef798-1bcc-4a64-a602-ed21fdb256d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
63544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2811463544
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.4029755765
Short name T386
Test name
Test status
Simulation time 7524479800 ps
CPU time 54.57 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206376 kb
Host smart-d8a5d40d-1294-4ea3-bcaa-f218dba803e9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4029755765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.4029755765
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.3786155653
Short name T1611
Test name
Test status
Simulation time 258282166 ps
CPU time 0.9 seconds
Started Jul 06 05:24:08 PM PDT 24
Finished Jul 06 05:24:09 PM PDT 24
Peak memory 206180 kb
Host smart-a368ffe4-d2ef-467e-b510-75b5e3244bdf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3786155653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.3786155653
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2871335962
Short name T569
Test name
Test status
Simulation time 181792352 ps
CPU time 0.79 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206184 kb
Host smart-95e7dd08-cc29-40be-af8e-622c01ecaffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
35962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2871335962
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2554022196
Short name T23
Test name
Test status
Simulation time 5803205974 ps
CPU time 40.33 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:54 PM PDT 24
Peak memory 206756 kb
Host smart-8c4aa8f1-9041-47c1-9808-3b6e61a05d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25540
22196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2554022196
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2987291982
Short name T1258
Test name
Test status
Simulation time 3464979214 ps
CPU time 23.98 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206392 kb
Host smart-f26218c6-43b9-4503-94f8-e5e6d91d0db5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2987291982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2987291982
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.4177660891
Short name T2204
Test name
Test status
Simulation time 152346337 ps
CPU time 0.8 seconds
Started Jul 06 05:24:09 PM PDT 24
Finished Jul 06 05:24:10 PM PDT 24
Peak memory 206176 kb
Host smart-88d1932d-635b-4511-ad5a-3acdead57b21
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4177660891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.4177660891
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3863297424
Short name T2171
Test name
Test status
Simulation time 158280744 ps
CPU time 0.8 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206160 kb
Host smart-60a83042-3b84-4b7f-a18d-a96923306073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632
97424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3863297424
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2651317762
Short name T1333
Test name
Test status
Simulation time 144930344 ps
CPU time 0.76 seconds
Started Jul 06 05:24:09 PM PDT 24
Finished Jul 06 05:24:10 PM PDT 24
Peak memory 206124 kb
Host smart-274c9d68-2033-4693-9123-63889643ae36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26513
17762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2651317762
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.484991338
Short name T1293
Test name
Test status
Simulation time 143915698 ps
CPU time 0.74 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206200 kb
Host smart-bd967727-87ce-4bec-8965-15ccc56c579d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48499
1338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.484991338
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1577231136
Short name T452
Test name
Test status
Simulation time 181758499 ps
CPU time 0.87 seconds
Started Jul 06 05:24:08 PM PDT 24
Finished Jul 06 05:24:09 PM PDT 24
Peak memory 206172 kb
Host smart-89f25d5e-1623-4dfa-bbd3-06fa2c58390a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772
31136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1577231136
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.493124089
Short name T1833
Test name
Test status
Simulation time 160698894 ps
CPU time 0.8 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206180 kb
Host smart-6b0de34a-fefc-4b93-9210-4f79896722fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49312
4089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.493124089
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.95982950
Short name T84
Test name
Test status
Simulation time 211734049 ps
CPU time 0.96 seconds
Started Jul 06 05:24:11 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206188 kb
Host smart-5a7dfdc3-376b-4962-86ca-7921d3e221b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=95982950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.95982950
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2937106091
Short name T2543
Test name
Test status
Simulation time 167337806 ps
CPU time 0.84 seconds
Started Jul 06 05:24:08 PM PDT 24
Finished Jul 06 05:24:09 PM PDT 24
Peak memory 206184 kb
Host smart-65594b8f-bc24-4ce6-8b00-9ccb56e44383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
06091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2937106091
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1205740199
Short name T2581
Test name
Test status
Simulation time 40219967 ps
CPU time 0.69 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206164 kb
Host smart-07da4010-c0f7-4797-9cc6-42250177db42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057
40199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1205740199
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3769775148
Short name T1463
Test name
Test status
Simulation time 148008585 ps
CPU time 0.78 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206200 kb
Host smart-04c8c225-61d3-4ea8-b33a-c24326456445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697
75148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3769775148
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3358469736
Short name T1851
Test name
Test status
Simulation time 218185613 ps
CPU time 0.9 seconds
Started Jul 06 05:24:11 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206096 kb
Host smart-a922312d-1755-4199-9867-1a38262a3374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584
69736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3358469736
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2318686550
Short name T1618
Test name
Test status
Simulation time 199926472 ps
CPU time 0.9 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206184 kb
Host smart-4665bf6e-3b81-477b-b888-2db6b0a085c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
86550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2318686550
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2864920697
Short name T468
Test name
Test status
Simulation time 207918209 ps
CPU time 0.83 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206128 kb
Host smart-5f490bac-26ba-41b2-a7fd-5160bd0980c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28649
20697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2864920697
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2516061666
Short name T1703
Test name
Test status
Simulation time 170766953 ps
CPU time 0.75 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:15 PM PDT 24
Peak memory 206204 kb
Host smart-e169d6c9-370e-4cf0-ab57-1834013cf406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
61666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2516061666
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3238978721
Short name T444
Test name
Test status
Simulation time 154423834 ps
CPU time 0.83 seconds
Started Jul 06 05:24:10 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206180 kb
Host smart-0ef3bd79-11e6-48ca-832c-91df7884469b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32389
78721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3238978721
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1800688411
Short name T916
Test name
Test status
Simulation time 149487052 ps
CPU time 0.74 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:15 PM PDT 24
Peak memory 206440 kb
Host smart-201a7e57-2c97-4742-9e38-d4c3132efda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
88411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1800688411
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.258889882
Short name T364
Test name
Test status
Simulation time 264495691 ps
CPU time 0.99 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206440 kb
Host smart-c58864c1-a206-4026-b176-adecedf4ce6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25888
9882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.258889882
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2981509188
Short name T1428
Test name
Test status
Simulation time 4324379237 ps
CPU time 38.68 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:52 PM PDT 24
Peak memory 206792 kb
Host smart-74972eb7-28a7-4204-ae57-d76a44f6da61
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2981509188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2981509188
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2682608230
Short name T1669
Test name
Test status
Simulation time 235047636 ps
CPU time 0.94 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206088 kb
Host smart-66a33138-39fd-4045-924f-f2e86dc43d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826
08230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2682608230
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3369801433
Short name T2249
Test name
Test status
Simulation time 229373528 ps
CPU time 0.9 seconds
Started Jul 06 05:24:09 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206176 kb
Host smart-79c04952-75c8-4981-8280-345217fbc0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33698
01433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3369801433
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1121681893
Short name T425
Test name
Test status
Simulation time 436554149 ps
CPU time 1.26 seconds
Started Jul 06 05:24:11 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206152 kb
Host smart-113f5c4a-428f-4e93-b132-9f0190e23777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
81893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1121681893
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1108416380
Short name T1364
Test name
Test status
Simulation time 6282783746 ps
CPU time 169.42 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206512 kb
Host smart-3f898083-06a6-4585-8084-c4d950fa1fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11084
16380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1108416380
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.190342833
Short name T1342
Test name
Test status
Simulation time 79305162 ps
CPU time 0.71 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:24:18 PM PDT 24
Peak memory 206212 kb
Host smart-6ac6a0de-7b28-423e-b74a-59c32f2ec914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=190342833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.190342833
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1861114736
Short name T1953
Test name
Test status
Simulation time 4153685795 ps
CPU time 4.76 seconds
Started Jul 06 05:24:16 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206248 kb
Host smart-e32fef30-06d0-44ae-be9b-e2b5d4964f58
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1861114736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1861114736
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1931209118
Short name T1236
Test name
Test status
Simulation time 13366331268 ps
CPU time 12.88 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:24:30 PM PDT 24
Peak memory 206516 kb
Host smart-7cfbe390-4038-465c-a553-5a8b2ea28ba8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1931209118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1931209118
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1083973176
Short name T2556
Test name
Test status
Simulation time 23448878142 ps
CPU time 23.84 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206436 kb
Host smart-6534eb0e-c322-4fa6-ba37-5cd00572d61a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1083973176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1083973176
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1346505014
Short name T562
Test name
Test status
Simulation time 201533061 ps
CPU time 0.84 seconds
Started Jul 06 05:24:16 PM PDT 24
Finished Jul 06 05:24:18 PM PDT 24
Peak memory 206184 kb
Host smart-fe53671a-330c-4c1a-ba10-22b3aa4ac7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13465
05014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1346505014
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.450939717
Short name T2270
Test name
Test status
Simulation time 210303058 ps
CPU time 0.79 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206164 kb
Host smart-2e76961c-2825-46b7-81b0-9bbe4d2fc990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45093
9717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.450939717
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.125913075
Short name T1462
Test name
Test status
Simulation time 190425061 ps
CPU time 0.9 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 205452 kb
Host smart-ca1ed4f3-e61b-4603-af83-ed1fc274424a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12591
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.125913075
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2731751578
Short name T1932
Test name
Test status
Simulation time 1088885618 ps
CPU time 2.43 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:34 PM PDT 24
Peak memory 205708 kb
Host smart-4c7fe049-e645-45c2-aa21-fd13a3c63ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27317
51578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2731751578
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1905494090
Short name T2567
Test name
Test status
Simulation time 14697737272 ps
CPU time 31.05 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:47 PM PDT 24
Peak memory 206428 kb
Host smart-9fe46eb0-c1ea-4892-9bf0-18d84daf677f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19054
94090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1905494090
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1252935599
Short name T1458
Test name
Test status
Simulation time 432521517 ps
CPU time 1.37 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206144 kb
Host smart-82ea4cee-36ab-46d3-8eb4-43fec9f2dd0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12529
35599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1252935599
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2843898602
Short name T1880
Test name
Test status
Simulation time 157451850 ps
CPU time 0.76 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206004 kb
Host smart-69137a6a-1a68-4f67-b133-d4bf2527783f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
98602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2843898602
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2391620965
Short name T1879
Test name
Test status
Simulation time 46642279 ps
CPU time 0.68 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:15 PM PDT 24
Peak memory 206180 kb
Host smart-d5d77ff1-8aa9-426e-bdce-cb0e541c0f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23916
20965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2391620965
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.577009003
Short name T1478
Test name
Test status
Simulation time 932839312 ps
CPU time 2.27 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206348 kb
Host smart-02fec1ff-b47e-4306-b7c5-4ca8bbe2a6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57700
9003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.577009003
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1192799210
Short name T700
Test name
Test status
Simulation time 172494156 ps
CPU time 1.51 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206240 kb
Host smart-bc97ee60-2de2-4ce1-a822-13cef64b1902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11927
99210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1192799210
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.405306135
Short name T352
Test name
Test status
Simulation time 281143553 ps
CPU time 0.93 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206196 kb
Host smart-aaabddbe-4d36-4416-9e4c-9612a5dd35e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
6135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.405306135
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.4007287536
Short name T1190
Test name
Test status
Simulation time 140460895 ps
CPU time 0.79 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:31 PM PDT 24
Peak memory 205992 kb
Host smart-ec77b1d5-6ac6-4f49-8c58-ac54cae72e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40072
87536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.4007287536
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1609629102
Short name T1276
Test name
Test status
Simulation time 264826357 ps
CPU time 0.91 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206200 kb
Host smart-ace5c82c-822a-4d22-8265-5c063206aedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16096
29102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1609629102
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.919904948
Short name T2416
Test name
Test status
Simulation time 157883681 ps
CPU time 0.83 seconds
Started Jul 06 05:24:19 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206200 kb
Host smart-3740204e-4226-483e-9560-1b95612185c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91990
4948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.919904948
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1732373821
Short name T770
Test name
Test status
Simulation time 23260995385 ps
CPU time 21.6 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206236 kb
Host smart-db306138-c570-45cd-9a0f-a3b632d4a9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17323
73821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1732373821
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.970738574
Short name T1433
Test name
Test status
Simulation time 3282453946 ps
CPU time 4.49 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:24:18 PM PDT 24
Peak memory 206264 kb
Host smart-f0c73c15-fd0c-42ed-8c34-6027fd01ee62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97073
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.970738574
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1505089616
Short name T1241
Test name
Test status
Simulation time 13389270177 ps
CPU time 380.38 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 206552 kb
Host smart-1cd8ecd8-6836-4c4f-a6b0-ded8b0f5e489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15050
89616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1505089616
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3222777288
Short name T157
Test name
Test status
Simulation time 3341366403 ps
CPU time 29.68 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206480 kb
Host smart-c49c8b70-ca2c-4459-be4c-01ed5013c52c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3222777288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3222777288
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3132896236
Short name T2128
Test name
Test status
Simulation time 237455762 ps
CPU time 0.9 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206124 kb
Host smart-7eebd829-d984-4480-856a-f224943cda61
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3132896236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3132896236
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1269626530
Short name T2236
Test name
Test status
Simulation time 206316926 ps
CPU time 0.86 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206168 kb
Host smart-8ae39b24-af0b-42bd-9375-6de735bf1c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12696
26530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1269626530
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2039577755
Short name T2368
Test name
Test status
Simulation time 5233687384 ps
CPU time 46.96 seconds
Started Jul 06 05:24:13 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206488 kb
Host smart-4a3b7fa0-d5f1-4ac6-9da7-08a34efc2a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20395
77755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2039577755
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3567211912
Short name T944
Test name
Test status
Simulation time 6198043538 ps
CPU time 47.08 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206436 kb
Host smart-4d540ecd-9ab4-4a2e-a4cd-f3edfaf15ef3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3567211912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3567211912
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3196142459
Short name T2222
Test name
Test status
Simulation time 151916598 ps
CPU time 0.83 seconds
Started Jul 06 05:24:15 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206204 kb
Host smart-fdde2eeb-9c4a-405c-912d-6f59cec5da57
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3196142459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3196142459
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2163833128
Short name T464
Test name
Test status
Simulation time 153180509 ps
CPU time 0.77 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206156 kb
Host smart-a78e74f0-864c-4680-9f8a-932aa2364a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21638
33128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2163833128
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2120162571
Short name T2339
Test name
Test status
Simulation time 158062414 ps
CPU time 0.82 seconds
Started Jul 06 05:24:16 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206204 kb
Host smart-160c4bd3-5e5a-42f7-aee8-bc68f469ef83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201
62571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2120162571
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.370283194
Short name T792
Test name
Test status
Simulation time 161157441 ps
CPU time 0.82 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206124 kb
Host smart-5d31212e-3b0b-4507-a755-35cfb012c61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37028
3194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.370283194
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4117389207
Short name T1306
Test name
Test status
Simulation time 231004270 ps
CPU time 0.89 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:31 PM PDT 24
Peak memory 206012 kb
Host smart-ef03b6db-4587-47d0-a0db-59324fba07d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41173
89207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4117389207
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1939671389
Short name T1201
Test name
Test status
Simulation time 177432853 ps
CPU time 0.88 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206172 kb
Host smart-3f2210a6-7b8a-4bce-82e7-2ae68a62ece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
71389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1939671389
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.4123259610
Short name T1656
Test name
Test status
Simulation time 230490482 ps
CPU time 0.92 seconds
Started Jul 06 05:24:14 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206128 kb
Host smart-fbd59212-ba23-4c9b-b2c9-37ad12ed8cf5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4123259610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.4123259610
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3663402103
Short name T2562
Test name
Test status
Simulation time 166375620 ps
CPU time 0.77 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:24:22 PM PDT 24
Peak memory 206172 kb
Host smart-41d8ffc7-ad59-432c-892c-8c2ad9417f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
02103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3663402103
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3065323476
Short name T868
Test name
Test status
Simulation time 67088030 ps
CPU time 0.69 seconds
Started Jul 06 05:24:22 PM PDT 24
Finished Jul 06 05:24:23 PM PDT 24
Peak memory 206172 kb
Host smart-964198fd-d3af-4e0e-86fa-1be8ca36afcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30653
23476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3065323476
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3211342555
Short name T1916
Test name
Test status
Simulation time 8913901275 ps
CPU time 18.59 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:51 PM PDT 24
Peak memory 206336 kb
Host smart-8d89667b-2cd0-4bd2-a81b-ed2f5f9efc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32113
42555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3211342555
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2826374237
Short name T2309
Test name
Test status
Simulation time 250456770 ps
CPU time 0.91 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:19 PM PDT 24
Peak memory 206204 kb
Host smart-2835b9d1-53a9-454e-bced-4f1e29222579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263
74237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2826374237
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.871254337
Short name T2101
Test name
Test status
Simulation time 227713684 ps
CPU time 0.93 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206200 kb
Host smart-5e4332d8-8cc4-4d7b-bea7-c2268fdd76d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87125
4337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.871254337
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.621763712
Short name T384
Test name
Test status
Simulation time 232156879 ps
CPU time 0.89 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:24:22 PM PDT 24
Peak memory 206100 kb
Host smart-b0b010ee-d243-4a35-bc3c-46d0eda23cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62176
3712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.621763712
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.4104324115
Short name T2283
Test name
Test status
Simulation time 237964767 ps
CPU time 0.88 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206168 kb
Host smart-f60d94d3-906c-4fb6-9cde-5247ee787083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41043
24115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.4104324115
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3745341884
Short name T1713
Test name
Test status
Simulation time 154159514 ps
CPU time 0.8 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206140 kb
Host smart-36b9226d-1a64-4119-8d2a-c047926d79a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37453
41884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3745341884
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3100484571
Short name T865
Test name
Test status
Simulation time 156522714 ps
CPU time 0.79 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206112 kb
Host smart-5a41a056-d239-46cc-8e63-69e70e3a953f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31004
84571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3100484571
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1480822110
Short name T18
Test name
Test status
Simulation time 151896654 ps
CPU time 0.79 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:24:18 PM PDT 24
Peak memory 206184 kb
Host smart-678a5f23-9251-4c0f-b824-da8953ad6975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14808
22110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1480822110
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2665201713
Short name T1824
Test name
Test status
Simulation time 217253934 ps
CPU time 0.93 seconds
Started Jul 06 05:24:19 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206184 kb
Host smart-f9d6dfec-6b5b-4c35-9d85-8cc295339f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26652
01713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2665201713
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.111480092
Short name T2574
Test name
Test status
Simulation time 3255065501 ps
CPU time 86.43 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 206464 kb
Host smart-222ded25-8918-445b-acfe-4de998c76353
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=111480092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.111480092
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3760263690
Short name T1602
Test name
Test status
Simulation time 231802944 ps
CPU time 0.88 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:24:19 PM PDT 24
Peak memory 206156 kb
Host smart-01620f12-c017-4940-a72c-3c778df97cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37602
63690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3760263690
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3190313459
Short name T1571
Test name
Test status
Simulation time 176704539 ps
CPU time 0.79 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:24 PM PDT 24
Peak memory 206204 kb
Host smart-132dafb8-f466-4b6e-91f6-c42521b226e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31903
13459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3190313459
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1182613211
Short name T594
Test name
Test status
Simulation time 522616299 ps
CPU time 1.33 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:22 PM PDT 24
Peak memory 206196 kb
Host smart-4c66d878-de01-44be-ac89-a154b0eda7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11826
13211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1182613211
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.426517613
Short name T864
Test name
Test status
Simulation time 4798782616 ps
CPU time 45.29 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206488 kb
Host smart-d5e32575-9355-45c5-bcce-04f09f99d47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42651
7613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.426517613
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2595552704
Short name T1835
Test name
Test status
Simulation time 36968751 ps
CPU time 0.72 seconds
Started Jul 06 05:24:33 PM PDT 24
Finished Jul 06 05:24:34 PM PDT 24
Peak memory 206260 kb
Host smart-1c51e125-b7ee-45fa-b8e5-b24c47cb4629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2595552704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2595552704
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1363287403
Short name T1441
Test name
Test status
Simulation time 3413792966 ps
CPU time 4.18 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206500 kb
Host smart-651e3110-5335-4e45-ac62-32f264c4d603
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1363287403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1363287403
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4157877385
Short name T1007
Test name
Test status
Simulation time 13384059457 ps
CPU time 13.16 seconds
Started Jul 06 05:24:22 PM PDT 24
Finished Jul 06 05:24:35 PM PDT 24
Peak memory 206264 kb
Host smart-89f71c7f-c01f-4d66-af02-947624816951
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4157877385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4157877385
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.4023549323
Short name T239
Test name
Test status
Simulation time 23351646523 ps
CPU time 22.26 seconds
Started Jul 06 05:24:22 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206460 kb
Host smart-c9bf4c93-d70e-45b8-a9d9-132dab5f80b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4023549323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.4023549323
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.4122593862
Short name T1553
Test name
Test status
Simulation time 151203202 ps
CPU time 0.8 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:24 PM PDT 24
Peak memory 206200 kb
Host smart-d77e66ca-e406-4443-82d2-86c5435a6bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41225
93862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.4122593862
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3292559512
Short name T498
Test name
Test status
Simulation time 171340771 ps
CPU time 0.79 seconds
Started Jul 06 05:24:19 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206100 kb
Host smart-843c5ec5-1ab4-47fe-b3af-99280270ffb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32925
59512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3292559512
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3859432930
Short name T2439
Test name
Test status
Simulation time 347054615 ps
CPU time 1.17 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:19 PM PDT 24
Peak memory 206188 kb
Host smart-7c901e1f-c743-4c44-b7fc-4662341f33f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
32930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3859432930
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2659193492
Short name T714
Test name
Test status
Simulation time 340442254 ps
CPU time 1.08 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:24:23 PM PDT 24
Peak memory 206148 kb
Host smart-1325b42a-07ca-4cb1-87bf-d345e3ebfe05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
93492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2659193492
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.717184710
Short name T2174
Test name
Test status
Simulation time 10029413042 ps
CPU time 18.08 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:38 PM PDT 24
Peak memory 206368 kb
Host smart-cc8fd68a-e645-4a0f-b844-576ef6b08f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71718
4710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.717184710
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.24152430
Short name T509
Test name
Test status
Simulation time 405828633 ps
CPU time 1.2 seconds
Started Jul 06 05:24:16 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206204 kb
Host smart-aa2fa56c-38d5-40d2-a8d8-ecaf3c959c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.24152430
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2196010213
Short name T2631
Test name
Test status
Simulation time 138382864 ps
CPU time 0.73 seconds
Started Jul 06 05:24:19 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206156 kb
Host smart-4c050684-a545-4787-83e7-005f1a2f1207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
10213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2196010213
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.402940042
Short name T2307
Test name
Test status
Simulation time 38028729 ps
CPU time 0.69 seconds
Started Jul 06 05:24:16 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 206032 kb
Host smart-e88817e7-be50-4fd9-88bb-781bd9163d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40294
0042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.402940042
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1889645308
Short name T650
Test name
Test status
Simulation time 913322415 ps
CPU time 2.07 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206396 kb
Host smart-3808def5-f455-4f7b-971d-ed26758ec2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18896
45308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1889645308
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.4178195186
Short name T488
Test name
Test status
Simulation time 180119176 ps
CPU time 1.65 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:24:23 PM PDT 24
Peak memory 206388 kb
Host smart-a3b846b2-2ef4-43d7-b4a3-f70168c82f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
95186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.4178195186
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.308861437
Short name T35
Test name
Test status
Simulation time 219782035 ps
CPU time 0.9 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:24:22 PM PDT 24
Peak memory 206196 kb
Host smart-68b6cce1-ce57-4d43-96ac-830312828dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30886
1437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.308861437
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1329658831
Short name T2217
Test name
Test status
Simulation time 142282954 ps
CPU time 0.78 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206172 kb
Host smart-9772d8e8-40d1-46f9-b7a3-b42a1a85e0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13296
58831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1329658831
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2925169949
Short name T816
Test name
Test status
Simulation time 185002402 ps
CPU time 0.89 seconds
Started Jul 06 05:24:17 PM PDT 24
Finished Jul 06 05:24:19 PM PDT 24
Peak memory 206208 kb
Host smart-d4d2b226-0fa1-46d4-8f3c-c0e4fe4434b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
69949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2925169949
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.4283823555
Short name T1941
Test name
Test status
Simulation time 234861596 ps
CPU time 0.85 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:24:23 PM PDT 24
Peak memory 206148 kb
Host smart-1a9de9a3-e093-4afc-8f65-9a35909deb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42838
23555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.4283823555
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3939643781
Short name T17
Test name
Test status
Simulation time 23340624185 ps
CPU time 26.15 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:47 PM PDT 24
Peak memory 206244 kb
Host smart-51536b5e-8320-4061-aaaa-40a201a84b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39396
43781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3939643781
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1713374023
Short name T1746
Test name
Test status
Simulation time 3327928720 ps
CPU time 4.34 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:28 PM PDT 24
Peak memory 206264 kb
Host smart-3f695840-9cab-44b2-adeb-e032bb0a2391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17133
74023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1713374023
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.965094754
Short name T643
Test name
Test status
Simulation time 7637199383 ps
CPU time 55.54 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206524 kb
Host smart-b6e41c5c-ebe1-4f0e-ac4f-5003d7bd256f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96509
4754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.965094754
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1591872904
Short name T1684
Test name
Test status
Simulation time 5865644136 ps
CPU time 52.7 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 206484 kb
Host smart-a50249d7-6e89-401d-b430-7061b160b090
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1591872904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1591872904
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.799677435
Short name T1089
Test name
Test status
Simulation time 254957610 ps
CPU time 0.9 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:19 PM PDT 24
Peak memory 206204 kb
Host smart-40f24722-f8d2-48ee-9350-aa7ead61873b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=799677435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.799677435
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4133802800
Short name T2686
Test name
Test status
Simulation time 215574105 ps
CPU time 0.86 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206180 kb
Host smart-2341d0b7-6820-4ad1-adca-83db126dd08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41338
02800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4133802800
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2430518253
Short name T2677
Test name
Test status
Simulation time 4646380781 ps
CPU time 128.42 seconds
Started Jul 06 05:24:21 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206440 kb
Host smart-30fb029e-2cc0-47ce-b5d7-5b6b1842d32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305
18253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2430518253
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.584297988
Short name T2105
Test name
Test status
Simulation time 6179783854 ps
CPU time 43.54 seconds
Started Jul 06 05:24:20 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206448 kb
Host smart-550ba11b-840f-49fb-91ea-4c2c94b0901e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=584297988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.584297988
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3200497603
Short name T2081
Test name
Test status
Simulation time 200830812 ps
CPU time 0.82 seconds
Started Jul 06 05:24:18 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206144 kb
Host smart-2f51cea4-232d-4837-a905-ca5918e8c392
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3200497603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3200497603
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.4098709730
Short name T1973
Test name
Test status
Simulation time 139354413 ps
CPU time 0.79 seconds
Started Jul 06 05:24:19 PM PDT 24
Finished Jul 06 05:24:21 PM PDT 24
Peak memory 206192 kb
Host smart-4236d2c7-c7a2-4db5-99ad-90179eaeaf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987
09730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.4098709730
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1586168706
Short name T2313
Test name
Test status
Simulation time 184065698 ps
CPU time 0.87 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:26 PM PDT 24
Peak memory 206200 kb
Host smart-bade2b9e-a4fd-41b3-b62f-b8cd1c2e06ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
68706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1586168706
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.4020335749
Short name T1096
Test name
Test status
Simulation time 180606361 ps
CPU time 0.79 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206208 kb
Host smart-f57bc47c-c4c2-4c5a-83ef-de62d9dc46ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
35749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.4020335749
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2927272559
Short name T1226
Test name
Test status
Simulation time 160343002 ps
CPU time 0.86 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:26 PM PDT 24
Peak memory 206208 kb
Host smart-8f464ad7-949f-474c-bf3a-4c5dfcbc76ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272
72559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2927272559
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1351122877
Short name T520
Test name
Test status
Simulation time 175548379 ps
CPU time 0.77 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:24 PM PDT 24
Peak memory 206168 kb
Host smart-a93c2cb5-63ab-4f6e-99e6-a45ee20adf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
22877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1351122877
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3456289498
Short name T1239
Test name
Test status
Simulation time 241891808 ps
CPU time 1.03 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206200 kb
Host smart-f6a38baa-fd69-4a25-a106-ae79a537cfbe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3456289498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3456289498
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2858371816
Short name T2389
Test name
Test status
Simulation time 142256208 ps
CPU time 0.74 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:26 PM PDT 24
Peak memory 206160 kb
Host smart-e97aecb0-1b35-4c64-a964-a22eea2c43dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
71816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2858371816
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.361919414
Short name T2316
Test name
Test status
Simulation time 41542015 ps
CPU time 0.75 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206148 kb
Host smart-ea42e8c3-33e2-4b55-acea-7ea3b9a97397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36191
9414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.361919414
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3344305570
Short name T2349
Test name
Test status
Simulation time 21089017923 ps
CPU time 45.08 seconds
Started Jul 06 05:24:27 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206544 kb
Host smart-5b88d5b5-9f18-418e-a5e4-d845ce690760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33443
05570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3344305570
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2451799697
Short name T955
Test name
Test status
Simulation time 164481398 ps
CPU time 0.8 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206184 kb
Host smart-7bc321c0-5fd2-49b7-a392-3004337af9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
99697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2451799697
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3958780375
Short name T2077
Test name
Test status
Simulation time 171483984 ps
CPU time 0.9 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:27 PM PDT 24
Peak memory 206204 kb
Host smart-fb8819cf-c71e-40d8-b9c4-f901d213d05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39587
80375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3958780375
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2159697903
Short name T1712
Test name
Test status
Simulation time 193808418 ps
CPU time 0.85 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206144 kb
Host smart-2ab5a246-151d-4442-999c-442348abc90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21596
97903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2159697903
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.212922392
Short name T1969
Test name
Test status
Simulation time 168881194 ps
CPU time 0.84 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:26 PM PDT 24
Peak memory 206108 kb
Host smart-39536578-df6e-43db-a1f0-a039a9f16767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21292
2392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.212922392
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2969247142
Short name T1901
Test name
Test status
Simulation time 161639795 ps
CPU time 0.78 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:26 PM PDT 24
Peak memory 206120 kb
Host smart-130879f0-8227-45b3-be14-81ba798be784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
47142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2969247142
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.4184726699
Short name T2583
Test name
Test status
Simulation time 165494304 ps
CPU time 0.85 seconds
Started Jul 06 05:24:25 PM PDT 24
Finished Jul 06 05:24:26 PM PDT 24
Peak memory 206188 kb
Host smart-ed5001de-fec5-4208-89b5-584c2e8b3bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
26699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.4184726699
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2219291267
Short name T832
Test name
Test status
Simulation time 143159511 ps
CPU time 0.76 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206180 kb
Host smart-c5eeca96-7723-4d76-a6b1-cdcb2409244e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
91267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2219291267
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2863683301
Short name T870
Test name
Test status
Simulation time 246979544 ps
CPU time 0.99 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:24 PM PDT 24
Peak memory 206112 kb
Host smart-971e099f-52c7-434f-8b83-3ad919e12ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28636
83301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2863683301
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.4243150150
Short name T148
Test name
Test status
Simulation time 4006993596 ps
CPU time 111.84 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206516 kb
Host smart-7e6036cd-9136-4263-9a17-5715fecb0788
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4243150150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.4243150150
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2690460329
Short name T1547
Test name
Test status
Simulation time 207209498 ps
CPU time 0.88 seconds
Started Jul 06 05:24:23 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206204 kb
Host smart-82ff4700-8ac8-4dc3-93fb-e164b40cea77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26904
60329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2690460329
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1469899642
Short name T646
Test name
Test status
Simulation time 179536119 ps
CPU time 0.78 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206204 kb
Host smart-7e69ae7d-8bf2-4404-8f33-14cd100f5267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14698
99642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1469899642
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3574416
Short name T1877
Test name
Test status
Simulation time 633253359 ps
CPU time 1.62 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206176 kb
Host smart-06f4987d-01a1-4d05-8f16-95cf863ca631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35744
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3574416
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2423680786
Short name T2200
Test name
Test status
Simulation time 3213060160 ps
CPU time 21.93 seconds
Started Jul 06 05:24:24 PM PDT 24
Finished Jul 06 05:24:46 PM PDT 24
Peak memory 206512 kb
Host smart-cd0d85c6-f119-4f52-9c2a-3c1daf6ee661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24236
80786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2423680786
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3341959379
Short name T1552
Test name
Test status
Simulation time 35613398 ps
CPU time 0.66 seconds
Started Jul 06 05:24:39 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206256 kb
Host smart-c1ae5a0d-310f-452b-bab6-8d031ce0f8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3341959379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3341959379
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3418674492
Short name T1221
Test name
Test status
Simulation time 3911742002 ps
CPU time 4.55 seconds
Started Jul 06 05:24:34 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206240 kb
Host smart-b0719318-3662-4ebd-a60f-06f7863aa50f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3418674492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3418674492
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.4101166897
Short name T638
Test name
Test status
Simulation time 13360593959 ps
CPU time 12.74 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206244 kb
Host smart-a4753653-7ce8-4072-be2b-e28da8613023
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4101166897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.4101166897
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.394412545
Short name T2087
Test name
Test status
Simulation time 23383282788 ps
CPU time 25.82 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:24:58 PM PDT 24
Peak memory 206524 kb
Host smart-613d04ca-9e91-4e25-941b-c78099343898
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=394412545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.394412545
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3619009145
Short name T1118
Test name
Test status
Simulation time 148737038 ps
CPU time 0.88 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206200 kb
Host smart-9551ba11-6e35-4ac7-93a0-40f39e59be44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36190
09145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3619009145
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1952651198
Short name T1767
Test name
Test status
Simulation time 152960743 ps
CPU time 0.76 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:31 PM PDT 24
Peak memory 206164 kb
Host smart-faf0e7ae-2a17-4257-b84a-a267ee8e4a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19526
51198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1952651198
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3988973155
Short name T813
Test name
Test status
Simulation time 155384012 ps
CPU time 0.81 seconds
Started Jul 06 05:24:29 PM PDT 24
Finished Jul 06 05:24:30 PM PDT 24
Peak memory 206204 kb
Host smart-2c120fd4-8f96-4785-ab37-a48868064cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39889
73155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3988973155
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1813753275
Short name T170
Test name
Test status
Simulation time 580458259 ps
CPU time 1.41 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:32 PM PDT 24
Peak memory 206200 kb
Host smart-c5851368-0d09-4fa2-9ffd-32a0312298d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18137
53275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1813753275
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3034574729
Short name T962
Test name
Test status
Simulation time 15956580527 ps
CPU time 28.52 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206452 kb
Host smart-d01763e3-3ade-46f2-95d9-f231ad6895f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
74729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3034574729
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1905650631
Short name T787
Test name
Test status
Simulation time 357811386 ps
CPU time 1.13 seconds
Started Jul 06 05:24:33 PM PDT 24
Finished Jul 06 05:24:35 PM PDT 24
Peak memory 206160 kb
Host smart-67729427-6f75-4064-b191-af5bdbd5c089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19056
50631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1905650631
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.4240992456
Short name T983
Test name
Test status
Simulation time 147000862 ps
CPU time 0.81 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206124 kb
Host smart-6d4fff45-6268-4a2d-8898-79a503d83370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
92456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.4240992456
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2962507633
Short name T1339
Test name
Test status
Simulation time 36408398 ps
CPU time 0.67 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206108 kb
Host smart-73b5c284-db89-479e-b4de-32367592f551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29625
07633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2962507633
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2548880325
Short name T662
Test name
Test status
Simulation time 940019693 ps
CPU time 2.23 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:34 PM PDT 24
Peak memory 206392 kb
Host smart-a0d5392a-bea9-4b3a-9eb8-1fe5a5554ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25488
80325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2548880325
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2818442714
Short name T1858
Test name
Test status
Simulation time 186683144 ps
CPU time 2 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:24:34 PM PDT 24
Peak memory 206396 kb
Host smart-1f3088f1-3648-454c-add5-5e194bc998e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
42714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2818442714
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.244869675
Short name T859
Test name
Test status
Simulation time 212612456 ps
CPU time 0.87 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:31 PM PDT 24
Peak memory 206176 kb
Host smart-d7ced2e0-783e-4069-a60f-7787a7950ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24486
9675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.244869675
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.189694007
Short name T2489
Test name
Test status
Simulation time 137051230 ps
CPU time 0.76 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206164 kb
Host smart-bda3796d-aec4-4e3c-8b7d-b38a2ccb141b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18969
4007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.189694007
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.189712947
Short name T894
Test name
Test status
Simulation time 223476908 ps
CPU time 0.91 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:32 PM PDT 24
Peak memory 206200 kb
Host smart-4f25565d-c667-4d47-8e55-aa01f3b234d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18971
2947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.189712947
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2242474953
Short name T1720
Test name
Test status
Simulation time 163368980 ps
CPU time 0.8 seconds
Started Jul 06 05:24:38 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206108 kb
Host smart-fb1f8a2f-6399-432f-b979-c35d3decc5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22424
74953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2242474953
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3406755990
Short name T2011
Test name
Test status
Simulation time 23392919921 ps
CPU time 28.54 seconds
Started Jul 06 05:24:35 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206268 kb
Host smart-88d9fdac-f07d-4c45-82db-3def0891020c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
55990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3406755990
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2905194040
Short name T556
Test name
Test status
Simulation time 3317782103 ps
CPU time 4.05 seconds
Started Jul 06 05:24:35 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206280 kb
Host smart-f5392496-4a0d-4972-9fd1-bbdf35219518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29051
94040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2905194040
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2009139959
Short name T1185
Test name
Test status
Simulation time 12127302784 ps
CPU time 92.74 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206488 kb
Host smart-b6b1818e-26e0-4552-8a28-377e0c6003f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20091
39959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2009139959
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1147269702
Short name T2336
Test name
Test status
Simulation time 7588861992 ps
CPU time 218.43 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:28:15 PM PDT 24
Peak memory 206404 kb
Host smart-9aadf91f-7988-4847-8218-e82cbf2e36f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1147269702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1147269702
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1262006600
Short name T686
Test name
Test status
Simulation time 245870216 ps
CPU time 0.91 seconds
Started Jul 06 05:24:34 PM PDT 24
Finished Jul 06 05:24:36 PM PDT 24
Peak memory 206176 kb
Host smart-90f76c96-7ea3-410e-b439-cae6db769189
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1262006600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1262006600
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.615368134
Short name T2038
Test name
Test status
Simulation time 223734060 ps
CPU time 0.92 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:32 PM PDT 24
Peak memory 206208 kb
Host smart-3d6da5fd-c3d9-4912-b381-3a07f8a45a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61536
8134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.615368134
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.69412514
Short name T2073
Test name
Test status
Simulation time 4780503976 ps
CPU time 45.02 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206496 kb
Host smart-a884e2d9-5b5f-48a7-9eee-5d0cf683d15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69412
514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.69412514
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3826089764
Short name T532
Test name
Test status
Simulation time 5120894461 ps
CPU time 47.99 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:25:20 PM PDT 24
Peak memory 206436 kb
Host smart-c88a433b-2426-4c1a-84da-4a69eb79c5a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3826089764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3826089764
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2353886308
Short name T1215
Test name
Test status
Simulation time 194696113 ps
CPU time 0.83 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206192 kb
Host smart-baa10148-0168-44db-9330-be1bf688b5c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2353886308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2353886308
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1032751304
Short name T2400
Test name
Test status
Simulation time 160448006 ps
CPU time 0.79 seconds
Started Jul 06 05:24:33 PM PDT 24
Finished Jul 06 05:24:34 PM PDT 24
Peak memory 206204 kb
Host smart-79e020d6-eb88-4c41-830b-3529f20a0ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10327
51304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1032751304
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2942650043
Short name T1951
Test name
Test status
Simulation time 176707697 ps
CPU time 0.83 seconds
Started Jul 06 05:24:31 PM PDT 24
Finished Jul 06 05:24:32 PM PDT 24
Peak memory 206172 kb
Host smart-c56fa5fc-9aa0-4de5-9e0f-90ea0570df83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426
50043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2942650043
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3447282576
Short name T893
Test name
Test status
Simulation time 186889119 ps
CPU time 0.81 seconds
Started Jul 06 05:24:32 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206176 kb
Host smart-3524141b-e0be-4797-b631-078feb599f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34472
82576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3447282576
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4207517298
Short name T2659
Test name
Test status
Simulation time 188741977 ps
CPU time 0.87 seconds
Started Jul 06 05:24:30 PM PDT 24
Finished Jul 06 05:24:31 PM PDT 24
Peak memory 206184 kb
Host smart-2fb37635-495b-4a37-8331-7916bb2470b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42075
17298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4207517298
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1081175685
Short name T153
Test name
Test status
Simulation time 165673143 ps
CPU time 0.86 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206172 kb
Host smart-e967490f-b816-4eb4-864f-aafdfe06ecd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
75685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1081175685
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.4158591601
Short name T817
Test name
Test status
Simulation time 247680562 ps
CPU time 0.97 seconds
Started Jul 06 05:24:39 PM PDT 24
Finished Jul 06 05:24:41 PM PDT 24
Peak memory 206208 kb
Host smart-5e00a9c7-b7bd-412e-b9dd-59bc024b1859
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4158591601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.4158591601
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1611594885
Short name T2300
Test name
Test status
Simulation time 152197390 ps
CPU time 0.79 seconds
Started Jul 06 05:24:37 PM PDT 24
Finished Jul 06 05:24:38 PM PDT 24
Peak memory 206144 kb
Host smart-9e33d55a-3fb5-48cc-a5d7-dbb1d3d5ec76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16115
94885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1611594885
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1938600184
Short name T2242
Test name
Test status
Simulation time 6920754590 ps
CPU time 14.82 seconds
Started Jul 06 05:24:45 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206452 kb
Host smart-a9e3842f-53d8-4c42-894f-bca3cfbc9965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19386
00184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1938600184
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1419829543
Short name T1059
Test name
Test status
Simulation time 176557880 ps
CPU time 0.86 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206156 kb
Host smart-837d5f44-b881-427e-b01c-1029181a5ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14198
29543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1419829543
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3972558597
Short name T1589
Test name
Test status
Simulation time 167876450 ps
CPU time 0.91 seconds
Started Jul 06 05:24:38 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206100 kb
Host smart-ec4d8c32-e575-4bdf-b768-e935dea666a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
58597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3972558597
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.596548974
Short name T525
Test name
Test status
Simulation time 256402546 ps
CPU time 0.89 seconds
Started Jul 06 05:24:45 PM PDT 24
Finished Jul 06 05:24:46 PM PDT 24
Peak memory 206156 kb
Host smart-632bb5da-42dc-4351-b5ec-1cc2c3f95700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59654
8974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.596548974
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1000370662
Short name T2314
Test name
Test status
Simulation time 167189097 ps
CPU time 0.82 seconds
Started Jul 06 05:24:34 PM PDT 24
Finished Jul 06 05:24:35 PM PDT 24
Peak memory 206196 kb
Host smart-c2875440-6dae-4f2a-aab2-b304bfb67712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10003
70662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1000370662
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3468908757
Short name T1536
Test name
Test status
Simulation time 143574826 ps
CPU time 0.75 seconds
Started Jul 06 05:24:41 PM PDT 24
Finished Jul 06 05:24:42 PM PDT 24
Peak memory 206104 kb
Host smart-87d5b455-2e39-47d6-8d1a-0466a713ad54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34689
08757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3468908757
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2792380043
Short name T623
Test name
Test status
Simulation time 185808855 ps
CPU time 0.83 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206204 kb
Host smart-9529cac7-cd24-41fe-900a-7ffa3850dcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
80043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2792380043
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.210180805
Short name T2422
Test name
Test status
Simulation time 148253097 ps
CPU time 0.79 seconds
Started Jul 06 05:24:38 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206208 kb
Host smart-abe0b3f8-ddb5-4c61-9e12-8e77c906449b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21018
0805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.210180805
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4039245790
Short name T1864
Test name
Test status
Simulation time 215254183 ps
CPU time 1 seconds
Started Jul 06 05:24:39 PM PDT 24
Finished Jul 06 05:24:41 PM PDT 24
Peak memory 206172 kb
Host smart-98598a4f-fbca-4f1b-8783-0d89dba445a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40392
45790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4039245790
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.454428118
Short name T1406
Test name
Test status
Simulation time 4311706551 ps
CPU time 113.21 seconds
Started Jul 06 05:24:45 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206472 kb
Host smart-42d9730c-cab2-48d9-8beb-69825e4844ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=454428118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.454428118
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1562848215
Short name T1095
Test name
Test status
Simulation time 195556801 ps
CPU time 0.85 seconds
Started Jul 06 05:24:38 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206172 kb
Host smart-3bfa8d15-b503-4f94-81ea-72cb0c33906e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
48215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1562848215
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.549620135
Short name T1472
Test name
Test status
Simulation time 171677105 ps
CPU time 0.81 seconds
Started Jul 06 05:24:45 PM PDT 24
Finished Jul 06 05:24:46 PM PDT 24
Peak memory 206160 kb
Host smart-473f7744-7dd4-4ea5-9cff-c0ddba087f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54962
0135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.549620135
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1508050524
Short name T417
Test name
Test status
Simulation time 1146903070 ps
CPU time 2.36 seconds
Started Jul 06 05:24:37 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206404 kb
Host smart-309bc445-a4c0-487b-947b-9e402dceae28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080
50524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1508050524
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.4197773648
Short name T2490
Test name
Test status
Simulation time 3054693496 ps
CPU time 27.53 seconds
Started Jul 06 05:24:34 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206516 kb
Host smart-f1f76662-574d-495f-aed1-21ae1160c658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41977
73648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.4197773648
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1497898268
Short name T1257
Test name
Test status
Simulation time 35022785 ps
CPU time 0.67 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206260 kb
Host smart-f8634c66-c597-40b7-ab2b-b8dabf85750c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1497898268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1497898268
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.4171679465
Short name T2083
Test name
Test status
Simulation time 3419429223 ps
CPU time 5.01 seconds
Started Jul 06 05:24:42 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206184 kb
Host smart-2afd0b44-6e9f-4dc8-a1d6-59d8eb5b7361
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4171679465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.4171679465
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3115662518
Short name T803
Test name
Test status
Simulation time 23420871181 ps
CPU time 28.4 seconds
Started Jul 06 05:24:36 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206236 kb
Host smart-a8d9e683-9169-4ca0-85ce-be359b386378
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3115662518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3115662518
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2904906432
Short name T2434
Test name
Test status
Simulation time 198502414 ps
CPU time 0.88 seconds
Started Jul 06 05:24:37 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206100 kb
Host smart-a6875467-eb78-4c35-b38b-752420af75cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
06432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2904906432
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.826053044
Short name T1251
Test name
Test status
Simulation time 169463944 ps
CPU time 0.84 seconds
Started Jul 06 05:24:35 PM PDT 24
Finished Jul 06 05:24:36 PM PDT 24
Peak memory 206120 kb
Host smart-bf3e4eb9-1a10-4a69-abd6-11a44594b63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82605
3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.826053044
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.575718284
Short name T2481
Test name
Test status
Simulation time 160548904 ps
CPU time 0.77 seconds
Started Jul 06 05:24:38 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206152 kb
Host smart-b05dc1f2-74ed-4e76-b8b0-d49aca9580bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57571
8284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.575718284
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3974789932
Short name T2017
Test name
Test status
Simulation time 486066067 ps
CPU time 1.33 seconds
Started Jul 06 05:24:40 PM PDT 24
Finished Jul 06 05:24:42 PM PDT 24
Peak memory 206116 kb
Host smart-020babc1-c6a7-47b3-a0f8-6edf0f34a9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39747
89932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3974789932
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.4109022034
Short name T1460
Test name
Test status
Simulation time 17612911060 ps
CPU time 37.02 seconds
Started Jul 06 05:24:41 PM PDT 24
Finished Jul 06 05:25:19 PM PDT 24
Peak memory 206428 kb
Host smart-beb6bb6e-9532-41be-b2b3-d443824d3139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41090
22034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.4109022034
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.706194309
Short name T1147
Test name
Test status
Simulation time 351050130 ps
CPU time 1.13 seconds
Started Jul 06 05:24:37 PM PDT 24
Finished Jul 06 05:24:38 PM PDT 24
Peak memory 206144 kb
Host smart-94992553-e857-4bcf-9c61-d88575e5997a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70619
4309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.706194309
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2018397135
Short name T1314
Test name
Test status
Simulation time 166493446 ps
CPU time 0.79 seconds
Started Jul 06 05:24:41 PM PDT 24
Finished Jul 06 05:24:42 PM PDT 24
Peak memory 206120 kb
Host smart-1fa3576f-ebff-4af0-9584-41fa6bd2e17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20183
97135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2018397135
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1019751872
Short name T584
Test name
Test status
Simulation time 86590890 ps
CPU time 0.73 seconds
Started Jul 06 05:24:35 PM PDT 24
Finished Jul 06 05:24:36 PM PDT 24
Peak memory 206176 kb
Host smart-39b42170-0ea7-435c-809e-8b6ffe0b9cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10197
51872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1019751872
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2289458983
Short name T1507
Test name
Test status
Simulation time 874058875 ps
CPU time 2.04 seconds
Started Jul 06 05:24:37 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206368 kb
Host smart-7f7cadac-abd7-44c5-b6c9-84a21353e22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22894
58983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2289458983
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4162777505
Short name T985
Test name
Test status
Simulation time 164573225 ps
CPU time 1.43 seconds
Started Jul 06 05:24:38 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206412 kb
Host smart-2c1740e8-5923-4985-98ff-b61b3d735119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627
77505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4162777505
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1365774805
Short name T1457
Test name
Test status
Simulation time 182929686 ps
CPU time 0.83 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206160 kb
Host smart-84ceedb3-97a5-467b-9a97-5df63de38dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
74805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1365774805
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2650214828
Short name T765
Test name
Test status
Simulation time 148377819 ps
CPU time 0.79 seconds
Started Jul 06 05:24:42 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206112 kb
Host smart-40fc7425-9acb-41d8-a055-2ee30424cc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
14828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2650214828
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1038299964
Short name T1171
Test name
Test status
Simulation time 227965398 ps
CPU time 0.94 seconds
Started Jul 06 05:24:47 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206164 kb
Host smart-ba12db99-8e8d-4901-ac71-edd4742dad58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382
99964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1038299964
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3927129172
Short name T104
Test name
Test status
Simulation time 9526495028 ps
CPU time 86.02 seconds
Started Jul 06 05:24:45 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206372 kb
Host smart-e269fa7a-9ede-43d4-aba9-d5a82f3ffd91
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3927129172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3927129172
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2554181815
Short name T644
Test name
Test status
Simulation time 189200893 ps
CPU time 0.84 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206180 kb
Host smart-74728797-cf54-4469-861e-2e5a1d7643c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25541
81815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2554181815
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1707957513
Short name T229
Test name
Test status
Simulation time 23284473861 ps
CPU time 30.86 seconds
Started Jul 06 05:24:43 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 206152 kb
Host smart-6ed7fced-2047-4493-8cfd-99c30e315018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17079
57513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1707957513
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3044749188
Short name T1942
Test name
Test status
Simulation time 3331791797 ps
CPU time 3.82 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206216 kb
Host smart-7162e8f5-5cd8-4446-8c3f-780f1ef5d93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
49188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3044749188
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3115402675
Short name T2069
Test name
Test status
Simulation time 12534972230 ps
CPU time 120.2 seconds
Started Jul 06 05:24:47 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206488 kb
Host smart-90ddeb08-1c77-4c88-8ab4-2f46c823bca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31154
02675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3115402675
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2419746663
Short name T1413
Test name
Test status
Simulation time 7091539319 ps
CPU time 196.16 seconds
Started Jul 06 05:24:42 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206452 kb
Host smart-1df708d6-1de9-4292-88c6-0fa77d35bb46
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2419746663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2419746663
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1325193840
Short name T747
Test name
Test status
Simulation time 246647753 ps
CPU time 0.97 seconds
Started Jul 06 05:24:42 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206040 kb
Host smart-c83330a7-cba5-43eb-a886-b29d4820ef08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1325193840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1325193840
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1030856678
Short name T2392
Test name
Test status
Simulation time 208601897 ps
CPU time 0.86 seconds
Started Jul 06 05:24:47 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206204 kb
Host smart-2b65e553-852e-481f-90bc-8b68e4ca1940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308
56678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1030856678
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3639409429
Short name T1540
Test name
Test status
Simulation time 5385790364 ps
CPU time 49.46 seconds
Started Jul 06 05:24:45 PM PDT 24
Finished Jul 06 05:25:35 PM PDT 24
Peak memory 206508 kb
Host smart-f7ac8f2b-1219-42b6-b79d-3190488bcfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36394
09429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3639409429
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2353343016
Short name T1929
Test name
Test status
Simulation time 7529058650 ps
CPU time 57.65 seconds
Started Jul 06 05:24:43 PM PDT 24
Finished Jul 06 05:25:41 PM PDT 24
Peak memory 206436 kb
Host smart-b363ae71-1049-4368-a9a3-6a6ddfc0eaf8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2353343016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2353343016
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3922679763
Short name T709
Test name
Test status
Simulation time 155415972 ps
CPU time 0.78 seconds
Started Jul 06 05:24:43 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206168 kb
Host smart-53f37f22-eb23-4bff-8894-834bb09f9712
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3922679763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3922679763
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3953148855
Short name T342
Test name
Test status
Simulation time 143215102 ps
CPU time 0.82 seconds
Started Jul 06 05:24:46 PM PDT 24
Finished Jul 06 05:24:47 PM PDT 24
Peak memory 206100 kb
Host smart-b6591737-d562-4d7c-82eb-85fedb22e3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531
48855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3953148855
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2074676830
Short name T142
Test name
Test status
Simulation time 222139674 ps
CPU time 0.86 seconds
Started Jul 06 05:24:50 PM PDT 24
Finished Jul 06 05:24:51 PM PDT 24
Peak memory 205996 kb
Host smart-8fcfaf0d-37b8-4951-afab-61e309446c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
76830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2074676830
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.481358608
Short name T100
Test name
Test status
Simulation time 181884621 ps
CPU time 0.86 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206188 kb
Host smart-4866f772-3b7f-4c4e-8aee-ef064a62db1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48135
8608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.481358608
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3576290865
Short name T1809
Test name
Test status
Simulation time 150753793 ps
CPU time 0.82 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206192 kb
Host smart-23ed3ab9-084c-429f-b191-24cdae233d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35762
90865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3576290865
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3595549561
Short name T1825
Test name
Test status
Simulation time 152428412 ps
CPU time 0.83 seconds
Started Jul 06 05:24:42 PM PDT 24
Finished Jul 06 05:24:43 PM PDT 24
Peak memory 206204 kb
Host smart-457a0351-b0a1-4d87-b40c-16323f9f547e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35955
49561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3595549561
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1139704340
Short name T164
Test name
Test status
Simulation time 164645079 ps
CPU time 0.81 seconds
Started Jul 06 05:24:46 PM PDT 24
Finished Jul 06 05:24:47 PM PDT 24
Peak memory 206184 kb
Host smart-cfb2a281-545a-47a0-9451-5cd6e5fdf5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
04340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1139704340
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3403425328
Short name T421
Test name
Test status
Simulation time 252800248 ps
CPU time 0.97 seconds
Started Jul 06 05:24:43 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206188 kb
Host smart-b9a1cef0-03be-42c1-830c-3d8edbc4fdbe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3403425328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3403425328
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3957344620
Short name T2376
Test name
Test status
Simulation time 143721112 ps
CPU time 0.79 seconds
Started Jul 06 05:24:47 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206144 kb
Host smart-7c14cb76-4a5c-4f6f-88b2-488e15616e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
44620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3957344620
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3265884615
Short name T431
Test name
Test status
Simulation time 68912602 ps
CPU time 0.72 seconds
Started Jul 06 05:24:44 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206180 kb
Host smart-b23fc6a3-097f-49b5-b29b-07d3e2178b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32658
84615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3265884615
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2670942578
Short name T2443
Test name
Test status
Simulation time 8402844382 ps
CPU time 20.5 seconds
Started Jul 06 05:24:48 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206404 kb
Host smart-6156bfac-a3c1-45e1-9f9e-8099a9965a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
42578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2670942578
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3620216012
Short name T2146
Test name
Test status
Simulation time 170032829 ps
CPU time 0.83 seconds
Started Jul 06 05:24:46 PM PDT 24
Finished Jul 06 05:24:47 PM PDT 24
Peak memory 206204 kb
Host smart-d4bfbbc7-8187-4cfc-931d-ea0ddf52d9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36202
16012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3620216012
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1973600980
Short name T807
Test name
Test status
Simulation time 172586522 ps
CPU time 0.75 seconds
Started Jul 06 05:24:49 PM PDT 24
Finished Jul 06 05:24:50 PM PDT 24
Peak memory 205996 kb
Host smart-e00248fa-e8d8-46f1-86d9-684fd386de28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19736
00980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1973600980
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2046266192
Short name T1081
Test name
Test status
Simulation time 212490106 ps
CPU time 0.91 seconds
Started Jul 06 05:24:43 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206128 kb
Host smart-613e4c90-8054-4144-b156-6a08f18e5f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20462
66192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2046266192
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1113564305
Short name T2319
Test name
Test status
Simulation time 174413329 ps
CPU time 0.87 seconds
Started Jul 06 05:24:48 PM PDT 24
Finished Jul 06 05:24:49 PM PDT 24
Peak memory 206036 kb
Host smart-cff93938-3c5f-4eed-ae16-4e0ec4f102fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
64305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1113564305
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2661510933
Short name T1348
Test name
Test status
Simulation time 195323305 ps
CPU time 0.88 seconds
Started Jul 06 05:24:46 PM PDT 24
Finished Jul 06 05:24:48 PM PDT 24
Peak memory 206156 kb
Host smart-0405cfb7-1ef8-49d8-b065-31be43f1dd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26615
10933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2661510933
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2872086417
Short name T1772
Test name
Test status
Simulation time 167839598 ps
CPU time 0.8 seconds
Started Jul 06 05:24:43 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206124 kb
Host smart-136b3eaa-27e6-46ce-a26b-095bea39d273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28720
86417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2872086417
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3991927857
Short name T1304
Test name
Test status
Simulation time 199363863 ps
CPU time 0.92 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206100 kb
Host smart-64c065a1-df3c-4bef-be64-51c22f344098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39919
27857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3991927857
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2431808731
Short name T1150
Test name
Test status
Simulation time 4457395011 ps
CPU time 31.04 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:36 PM PDT 24
Peak memory 206436 kb
Host smart-9711b73b-0905-4b2f-b119-9e07f4afb92e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2431808731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2431808731
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2351017588
Short name T1038
Test name
Test status
Simulation time 195412669 ps
CPU time 0.81 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206204 kb
Host smart-24d1abde-55cc-4f41-99ef-e4f0ab4398d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23510
17588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2351017588
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1686973472
Short name T1009
Test name
Test status
Simulation time 191720474 ps
CPU time 0.87 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206176 kb
Host smart-ab03f231-7a99-42e3-93f4-12e083ce4867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
73472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1686973472
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.281126237
Short name T1991
Test name
Test status
Simulation time 203576112 ps
CPU time 0.97 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206084 kb
Host smart-a5bbde31-bc9d-449a-99a2-0480afa6a55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
6237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.281126237
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3790040326
Short name T1846
Test name
Test status
Simulation time 3479973135 ps
CPU time 33.33 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:31 PM PDT 24
Peak memory 206424 kb
Host smart-1b5ea902-a432-4940-88b5-0da78f774c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37900
40326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3790040326
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.1675167952
Short name T1977
Test name
Test status
Simulation time 80673362 ps
CPU time 0.76 seconds
Started Jul 06 05:24:56 PM PDT 24
Finished Jul 06 05:24:57 PM PDT 24
Peak memory 206224 kb
Host smart-fbee6eba-c08c-4b41-961a-df7e6428cc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1675167952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.1675167952
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.357716342
Short name T850
Test name
Test status
Simulation time 3525269140 ps
CPU time 4.23 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206264 kb
Host smart-d7e96c0d-f65f-4c13-8040-27318ce958c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=357716342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.357716342
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.947549581
Short name T735
Test name
Test status
Simulation time 13348525191 ps
CPU time 13.01 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206268 kb
Host smart-20401989-a05c-4ad1-b56a-97393c232613
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=947549581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.947549581
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3511971869
Short name T659
Test name
Test status
Simulation time 23408077607 ps
CPU time 23.22 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206424 kb
Host smart-12964f20-eddc-425b-b04e-4369d8483324
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3511971869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3511971869
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.153009269
Short name T2227
Test name
Test status
Simulation time 147359058 ps
CPU time 0.81 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:01 PM PDT 24
Peak memory 206204 kb
Host smart-3cb0da21-fae8-4b6e-a0f1-cf5330e53e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15300
9269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.153009269
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.52747499
Short name T2501
Test name
Test status
Simulation time 142026756 ps
CPU time 0.8 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206164 kb
Host smart-2cc2aeaf-7816-4b27-a189-68fe03db1969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52747
499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.52747499
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2264914396
Short name T2279
Test name
Test status
Simulation time 520080665 ps
CPU time 1.58 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206348 kb
Host smart-36da09da-2750-49da-a61a-c2c25ef19a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22649
14396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2264914396
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.837104869
Short name T1152
Test name
Test status
Simulation time 339368025 ps
CPU time 0.98 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206120 kb
Host smart-5b18ba6b-c82e-478d-8a94-633679b54155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83710
4869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.837104869
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.688554354
Short name T2523
Test name
Test status
Simulation time 6844055151 ps
CPU time 13.14 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206460 kb
Host smart-aa8504c0-d736-4a5b-89b7-43bb9a3078cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68855
4354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.688554354
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.4164476640
Short name T1516
Test name
Test status
Simulation time 383188402 ps
CPU time 1.27 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:01 PM PDT 24
Peak memory 206164 kb
Host smart-b6110200-4171-4197-8f42-6c4cf31ac491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41644
76640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.4164476640
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3889755598
Short name T951
Test name
Test status
Simulation time 144356177 ps
CPU time 0.77 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206116 kb
Host smart-6e723f02-5948-44ee-a695-c40f8e91ee7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
55598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3889755598
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2407907344
Short name T1237
Test name
Test status
Simulation time 45353325 ps
CPU time 0.66 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206088 kb
Host smart-9165a6c2-4c00-4b38-8740-56f9e27aaab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24079
07344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2407907344
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1519531651
Short name T1694
Test name
Test status
Simulation time 969348055 ps
CPU time 2.32 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206376 kb
Host smart-cae15da5-96ae-4c1d-ad33-b9391ec48a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15195
31651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1519531651
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1250527819
Short name T883
Test name
Test status
Simulation time 394144172 ps
CPU time 2.3 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206448 kb
Host smart-47461f25-e7f9-4844-a0e2-0733d2b5314f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
27819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1250527819
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2131967235
Short name T1538
Test name
Test status
Simulation time 187968648 ps
CPU time 0.84 seconds
Started Jul 06 05:24:56 PM PDT 24
Finished Jul 06 05:24:58 PM PDT 24
Peak memory 206152 kb
Host smart-03c5e617-35cf-4774-b2e9-c3e9fe4c95f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21319
67235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2131967235
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1814604501
Short name T2643
Test name
Test status
Simulation time 141094400 ps
CPU time 0.77 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206200 kb
Host smart-2a121f76-7a65-44c0-9f94-a585d4dfc64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18146
04501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1814604501
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4126663553
Short name T577
Test name
Test status
Simulation time 210060812 ps
CPU time 0.89 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206184 kb
Host smart-62eb676b-6294-4992-ad10-809914e8b38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
63553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4126663553
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.859667573
Short name T424
Test name
Test status
Simulation time 205775351 ps
CPU time 0.9 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206156 kb
Host smart-3b881199-6b4a-442b-a7da-9e0bd382f5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85966
7573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.859667573
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.236076245
Short name T915
Test name
Test status
Simulation time 23316231226 ps
CPU time 23.09 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206252 kb
Host smart-0d8e5df6-ca98-442a-ada1-021e39468f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23607
6245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.236076245
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3043004016
Short name T1284
Test name
Test status
Simulation time 3325911412 ps
CPU time 3.79 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206260 kb
Host smart-8bdf073c-4fad-40cd-b2f6-31949015b6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
04016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3043004016
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.4136523871
Short name T246
Test name
Test status
Simulation time 6381815549 ps
CPU time 167.92 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:27:48 PM PDT 24
Peak memory 206436 kb
Host smart-01da7768-ee38-42cb-8ebd-73746e9975f8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4136523871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.4136523871
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3697880083
Short name T1376
Test name
Test status
Simulation time 270542099 ps
CPU time 0.96 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206180 kb
Host smart-2b6a84e7-2917-48c7-bd5b-b2ebe9dddb0f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3697880083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3697880083
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1431041401
Short name T2678
Test name
Test status
Simulation time 205262637 ps
CPU time 0.91 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 206092 kb
Host smart-24845cab-2de6-4905-a240-0ef3983307e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14310
41401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1431041401
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.194132632
Short name T2108
Test name
Test status
Simulation time 4220402093 ps
CPU time 39.19 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206460 kb
Host smart-433d31b7-9648-48ab-92df-8a4df7c69f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19413
2632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.194132632
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3423228920
Short name T1329
Test name
Test status
Simulation time 4136184803 ps
CPU time 115.95 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:26:58 PM PDT 24
Peak memory 206404 kb
Host smart-30af66e6-2c3e-4729-8ddc-7c2e78fcc72c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3423228920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3423228920
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.4123516385
Short name T2405
Test name
Test status
Simulation time 156631545 ps
CPU time 0.77 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206008 kb
Host smart-00ca5641-db2b-4eb0-8cf9-c81709acfb76
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4123516385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.4123516385
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2859208075
Short name T1488
Test name
Test status
Simulation time 144272542 ps
CPU time 0.84 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206136 kb
Host smart-cfb23d00-d8d3-40fb-9307-544998588d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28592
08075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2859208075
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.734521022
Short name T1299
Test name
Test status
Simulation time 204580074 ps
CPU time 0.93 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206164 kb
Host smart-a2ddc22b-d3c1-42a7-b3dd-c23a809fa37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73452
1022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.734521022
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3716205293
Short name T1762
Test name
Test status
Simulation time 216064695 ps
CPU time 0.86 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:24:58 PM PDT 24
Peak memory 206172 kb
Host smart-02527376-f87f-40d1-8a4d-586a58b140e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
05293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3716205293
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4111768931
Short name T2632
Test name
Test status
Simulation time 147656241 ps
CPU time 0.8 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206084 kb
Host smart-a0562f36-d981-4fc0-b977-5c454c1686f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
68931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4111768931
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2677612981
Short name T1099
Test name
Test status
Simulation time 155103157 ps
CPU time 0.78 seconds
Started Jul 06 05:24:55 PM PDT 24
Finished Jul 06 05:24:56 PM PDT 24
Peak memory 206040 kb
Host smart-a3d53ed0-c8a4-4bd5-8161-24cd6fe60a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
12981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2677612981
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.934918260
Short name T1909
Test name
Test status
Simulation time 161879041 ps
CPU time 0.81 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 205696 kb
Host smart-1a6074b4-dc84-4e9d-b402-5f4988c9d7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93491
8260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.934918260
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2656426859
Short name T1806
Test name
Test status
Simulation time 226150802 ps
CPU time 0.96 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206160 kb
Host smart-3d312388-7fd1-4b4c-8bae-4bc9c59096bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2656426859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2656426859
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1163481699
Short name T2197
Test name
Test status
Simulation time 144613430 ps
CPU time 0.78 seconds
Started Jul 06 05:24:56 PM PDT 24
Finished Jul 06 05:24:57 PM PDT 24
Peak memory 206180 kb
Host smart-318343a8-28d5-4a2a-b68d-06658d55c678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11634
81699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1163481699
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1430487294
Short name T1668
Test name
Test status
Simulation time 66993885 ps
CPU time 0.69 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206156 kb
Host smart-17b4803f-59ba-4443-8596-a5d9249e997a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14304
87294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1430487294
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1767452557
Short name T262
Test name
Test status
Simulation time 19224577453 ps
CPU time 47.42 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206460 kb
Host smart-04109b76-8dd8-4472-bdf1-7b6eb81be087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17674
52557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1767452557
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3170047321
Short name T2151
Test name
Test status
Simulation time 191298154 ps
CPU time 0.86 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206208 kb
Host smart-2efc06ab-ed65-4d5f-ac54-58bc22483705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700
47321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3170047321
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.336132670
Short name T2381
Test name
Test status
Simulation time 235035405 ps
CPU time 0.92 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206208 kb
Host smart-60d3d867-e689-4d41-81fb-6272e3312867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613
2670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.336132670
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3433922043
Short name T2093
Test name
Test status
Simulation time 221125908 ps
CPU time 0.95 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206204 kb
Host smart-7121b6b5-a20e-4bc3-a547-58cade572d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34339
22043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3433922043
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2201752231
Short name T510
Test name
Test status
Simulation time 204484939 ps
CPU time 0.88 seconds
Started Jul 06 05:24:56 PM PDT 24
Finished Jul 06 05:24:57 PM PDT 24
Peak memory 206128 kb
Host smart-7ee1672c-d5a8-46d7-819c-d98f26c8d334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22017
52231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2201752231
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3329169035
Short name T2084
Test name
Test status
Simulation time 141444927 ps
CPU time 0.8 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206180 kb
Host smart-1c00c630-63e3-4d3d-8148-abe5ff65c188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33291
69035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3329169035
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1914932093
Short name T385
Test name
Test status
Simulation time 187844898 ps
CPU time 0.84 seconds
Started Jul 06 05:24:56 PM PDT 24
Finished Jul 06 05:24:57 PM PDT 24
Peak memory 206164 kb
Host smart-9886b9ce-9c9b-45bb-9b3a-748f77d8b66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19149
32093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1914932093
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1773364444
Short name T2541
Test name
Test status
Simulation time 144810056 ps
CPU time 0.82 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206224 kb
Host smart-72112b71-3bf6-492e-aa17-5879ae50b065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17733
64444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1773364444
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1426812434
Short name T1240
Test name
Test status
Simulation time 258447491 ps
CPU time 1.01 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206196 kb
Host smart-14aa389c-b708-47c7-bf0c-27e72cd00cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14268
12434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1426812434
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.238994544
Short name T986
Test name
Test status
Simulation time 3475639253 ps
CPU time 31.36 seconds
Started Jul 06 05:24:56 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206528 kb
Host smart-054072c5-95c1-4404-a942-6c24bb4e215b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=238994544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.238994544
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1585170367
Short name T882
Test name
Test status
Simulation time 189620439 ps
CPU time 0.81 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206112 kb
Host smart-5febaeed-a24b-4d03-aef1-4365b551888d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15851
70367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1585170367
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2557644584
Short name T749
Test name
Test status
Simulation time 158062303 ps
CPU time 0.78 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206120 kb
Host smart-10183001-5961-42fd-a45c-1c3ae193552b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25576
44584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2557644584
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3351259817
Short name T1100
Test name
Test status
Simulation time 1085715702 ps
CPU time 2.47 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206372 kb
Host smart-71379ee3-31eb-4254-89dc-2fcea76dda21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33512
59817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3351259817
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1032889957
Short name T2327
Test name
Test status
Simulation time 4654516931 ps
CPU time 127.8 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206512 kb
Host smart-a9967a9d-f26d-404d-af72-9847d317865a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10328
89957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1032889957
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.943350536
Short name T2029
Test name
Test status
Simulation time 39029032 ps
CPU time 0.73 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206232 kb
Host smart-6ddca22c-331c-46bb-8fc6-525ecea4b7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=943350536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.943350536
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2315440497
Short name T1046
Test name
Test status
Simulation time 3968091701 ps
CPU time 5.12 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206508 kb
Host smart-ef034281-7781-4b06-ae14-453da65d7e12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2315440497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2315440497
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3423390939
Short name T2059
Test name
Test status
Simulation time 13376531347 ps
CPU time 13.2 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206248 kb
Host smart-3649ec9d-7553-4d78-a599-58613216c0bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3423390939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3423390939
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2418605972
Short name T1212
Test name
Test status
Simulation time 23484122235 ps
CPU time 24.16 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206424 kb
Host smart-910524eb-ff4a-4980-b518-8a12e044d693
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2418605972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2418605972
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2504479176
Short name T1857
Test name
Test status
Simulation time 155412755 ps
CPU time 0.79 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:01 PM PDT 24
Peak memory 206116 kb
Host smart-6ae7aa03-3ad5-4863-a294-c85d88b38d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25044
79176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2504479176
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.329694570
Short name T2134
Test name
Test status
Simulation time 163078164 ps
CPU time 0.86 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206080 kb
Host smart-e6841b5a-e25f-4d57-99aa-fd5713913f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
4570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.329694570
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.358132636
Short name T348
Test name
Test status
Simulation time 152455448 ps
CPU time 0.83 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206136 kb
Host smart-e0c1c3c5-f4ef-4da3-839e-f31f062558d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
2636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.358132636
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1115220487
Short name T165
Test name
Test status
Simulation time 1197340705 ps
CPU time 2.65 seconds
Started Jul 06 05:24:55 PM PDT 24
Finished Jul 06 05:24:57 PM PDT 24
Peak memory 206368 kb
Host smart-9974eb7e-bd76-4370-97c8-c994b26c8125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11152
20487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1115220487
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3282935842
Short name T900
Test name
Test status
Simulation time 13661750650 ps
CPU time 25.84 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:31 PM PDT 24
Peak memory 206476 kb
Host smart-8fb7e23c-ab5d-4b55-a30c-d73174c815c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
35842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3282935842
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1803067672
Short name T988
Test name
Test status
Simulation time 446025967 ps
CPU time 1.35 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:01 PM PDT 24
Peak memory 206180 kb
Host smart-1c1d7d38-78f4-4270-b207-c716f23225b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
67672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1803067672
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3184088647
Short name T614
Test name
Test status
Simulation time 151304670 ps
CPU time 0.79 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206184 kb
Host smart-4e19c8c7-1bd0-4456-8742-9d00103ccded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
88647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3184088647
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.378321817
Short name T461
Test name
Test status
Simulation time 86753991 ps
CPU time 0.71 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206168 kb
Host smart-fcf1ebce-c3c3-4060-a0ee-3ff736e88be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37832
1817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.378321817
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2419973828
Short name T2061
Test name
Test status
Simulation time 878609546 ps
CPU time 1.96 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206048 kb
Host smart-56f794e8-9a95-49ad-9969-d775687a7386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24199
73828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2419973828
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2466033136
Short name T2691
Test name
Test status
Simulation time 160090279 ps
CPU time 1.55 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206368 kb
Host smart-a409b35e-20a1-4edf-9dd9-e3404bfe6399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24660
33136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2466033136
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1869396039
Short name T2177
Test name
Test status
Simulation time 200513287 ps
CPU time 0.83 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206180 kb
Host smart-3326a88c-f46b-47a0-80e8-8c786d39a38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18693
96039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1869396039
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3652908314
Short name T755
Test name
Test status
Simulation time 156835976 ps
CPU time 0.78 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206188 kb
Host smart-84b34aeb-7167-4f9f-b77f-cad6d8b764c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36529
08314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3652908314
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.929317179
Short name T445
Test name
Test status
Simulation time 264005880 ps
CPU time 0.91 seconds
Started Jul 06 05:24:58 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206200 kb
Host smart-ef5980ab-2d0e-4acb-af3d-c87387b2cb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92931
7179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.929317179
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.4158132526
Short name T2557
Test name
Test status
Simulation time 9638256446 ps
CPU time 72.17 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:26:10 PM PDT 24
Peak memory 206460 kb
Host smart-d1349277-4e35-46ea-a2c6-cec168ca7ab6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4158132526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.4158132526
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3478176546
Short name T2337
Test name
Test status
Simulation time 157814897 ps
CPU time 0.81 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206204 kb
Host smart-4f9d5fe8-81af-4d32-b129-33dc12f332a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34781
76546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3478176546
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.2386891949
Short name T1730
Test name
Test status
Simulation time 23314298418 ps
CPU time 24.56 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:22 PM PDT 24
Peak memory 206220 kb
Host smart-740dcf85-d188-4b04-af01-704a5c42b437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23868
91949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2386891949
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.4059722114
Short name T1307
Test name
Test status
Simulation time 3330558404 ps
CPU time 4.08 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 205964 kb
Host smart-205c2694-d02e-4d1b-a1eb-8e17a8b7e599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40597
22114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.4059722114
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.875218041
Short name T1893
Test name
Test status
Simulation time 9748987595 ps
CPU time 68.65 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206000 kb
Host smart-412634a4-ded1-4922-96d8-fbd4136f1ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87521
8041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.875218041
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1720568531
Short name T1112
Test name
Test status
Simulation time 6031057065 ps
CPU time 43.45 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:25:41 PM PDT 24
Peak memory 206432 kb
Host smart-d238bd96-9a7f-4897-81e8-6d04e5ffb525
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1720568531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1720568531
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3929776516
Short name T380
Test name
Test status
Simulation time 306662583 ps
CPU time 0.93 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206120 kb
Host smart-b53e8f7b-d8fd-4bd3-b35b-ba9dd8df73fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3929776516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3929776516
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1928248277
Short name T1863
Test name
Test status
Simulation time 283788374 ps
CPU time 0.96 seconds
Started Jul 06 05:24:57 PM PDT 24
Finished Jul 06 05:24:59 PM PDT 24
Peak memory 206132 kb
Host smart-21a0cefd-1360-4f8a-baa2-2fc755041fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
48277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1928248277
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1550271370
Short name T582
Test name
Test status
Simulation time 2676585194 ps
CPU time 24.16 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:25 PM PDT 24
Peak memory 206528 kb
Host smart-9e031dfa-80e1-4469-aa74-5c03dc6ee84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1550271370
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3052744325
Short name T668
Test name
Test status
Simulation time 4575362220 ps
CPU time 44.05 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206420 kb
Host smart-2afdabac-6da3-425b-ae45-9b6562ae84f0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3052744325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3052744325
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3963155862
Short name T32
Test name
Test status
Simulation time 160905161 ps
CPU time 0.84 seconds
Started Jul 06 05:24:59 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206144 kb
Host smart-d9245e93-c798-4e12-8203-19bc5ae3bdd7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3963155862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3963155862
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.929539332
Short name T992
Test name
Test status
Simulation time 144303778 ps
CPU time 0.88 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206048 kb
Host smart-a55b044f-0218-4760-9b09-ee2131802783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92953
9332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.929539332
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3433608700
Short name T128
Test name
Test status
Simulation time 222111435 ps
CPU time 0.87 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206200 kb
Host smart-bb033365-c555-4e0f-91fc-76db730a2839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34336
08700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3433608700
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3518597726
Short name T1949
Test name
Test status
Simulation time 195810664 ps
CPU time 0.81 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 205940 kb
Host smart-584219e6-79ee-4f85-a0b6-df192b226505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
97726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3518597726
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4231721259
Short name T539
Test name
Test status
Simulation time 199526968 ps
CPU time 0.81 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206192 kb
Host smart-1646b6a7-489b-4ce3-a161-febc9a156726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
21259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4231721259
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3289222467
Short name T1616
Test name
Test status
Simulation time 151162943 ps
CPU time 0.83 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206200 kb
Host smart-99b3c68c-16ef-49f3-a56f-294a2383e3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
22467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3289222467
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.137808886
Short name T2071
Test name
Test status
Simulation time 151151436 ps
CPU time 0.86 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206144 kb
Host smart-0c7e1786-8ed3-43de-8ed5-dd4cceab35cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13780
8886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.137808886
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.464516565
Short name T1092
Test name
Test status
Simulation time 194533809 ps
CPU time 0.85 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206196 kb
Host smart-cf09cdf3-60a2-4dbe-b32c-36993b87a87a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=464516565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.464516565
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.209289125
Short name T1286
Test name
Test status
Simulation time 149975058 ps
CPU time 0.84 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206156 kb
Host smart-61b4210a-57e3-4f93-89ed-28c453585aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20928
9125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.209289125
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1354061319
Short name T826
Test name
Test status
Simulation time 68012427 ps
CPU time 0.66 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206108 kb
Host smart-3b3e4372-8c61-4dd9-b43f-6ec487c8d780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13540
61319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1354061319
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3529828509
Short name T1091
Test name
Test status
Simulation time 16489630925 ps
CPU time 39.29 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206412 kb
Host smart-2f9c0aab-070f-4439-9811-05cbf749c22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
28509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3529828509
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1141556611
Short name T440
Test name
Test status
Simulation time 245025875 ps
CPU time 0.88 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206180 kb
Host smart-5c4f8986-c215-450b-9ab5-cdbeec967c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11415
56611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1141556611
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.4240310607
Short name T1273
Test name
Test status
Simulation time 289799884 ps
CPU time 0.96 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206200 kb
Host smart-38608c81-bacd-4306-90a6-1c98fd165a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
10607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.4240310607
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.873831083
Short name T1361
Test name
Test status
Simulation time 309947372 ps
CPU time 1 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206184 kb
Host smart-5e987115-2d9d-4d76-baf8-29aab51064a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87383
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.873831083
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3346312675
Short name T355
Test name
Test status
Simulation time 188797489 ps
CPU time 0.85 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206200 kb
Host smart-d2296808-0c94-48c2-86bf-c5188c10f326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
12675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3346312675
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4045738456
Short name T1981
Test name
Test status
Simulation time 230587129 ps
CPU time 0.9 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206204 kb
Host smart-0d4674d1-101c-4a75-87df-18b141b1d1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
38456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4045738456
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2499382116
Short name T877
Test name
Test status
Simulation time 147130768 ps
CPU time 0.77 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206140 kb
Host smart-d2554487-5a79-4ff8-ba9d-206c77d110d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24993
82116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2499382116
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1408003045
Short name T843
Test name
Test status
Simulation time 158397168 ps
CPU time 0.74 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206164 kb
Host smart-052b39f5-3baf-4ade-a600-30fd5862b41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14080
03045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1408003045
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3761034865
Short name T2681
Test name
Test status
Simulation time 223821902 ps
CPU time 0.96 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206200 kb
Host smart-797271ab-e1ae-46b6-8a3a-82d18cfa709f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
34865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3761034865
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1614832566
Short name T1122
Test name
Test status
Simulation time 3996095724 ps
CPU time 109.46 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206516 kb
Host smart-44e84611-6347-4e1b-91b2-68d673f65ca1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1614832566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1614832566
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2576749481
Short name T809
Test name
Test status
Simulation time 154611282 ps
CPU time 0.76 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206144 kb
Host smart-e5752a25-eed7-44ab-9ee9-3827907789b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25767
49481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2576749481
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1725737340
Short name T729
Test name
Test status
Simulation time 201705985 ps
CPU time 0.84 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206180 kb
Host smart-38053f6a-7c63-4f9e-b0fa-1d6a176a3aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17257
37340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1725737340
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.596177607
Short name T1180
Test name
Test status
Simulation time 840580335 ps
CPU time 1.93 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206356 kb
Host smart-e7da18ad-0c77-401c-a6be-285273f45b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59617
7607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.596177607
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.639356130
Short name T1870
Test name
Test status
Simulation time 5042870891 ps
CPU time 37.83 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:42 PM PDT 24
Peak memory 206500 kb
Host smart-472f9cb4-be77-4f2c-a55d-05c0ee9422f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63935
6130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.639356130
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.935307268
Short name T1546
Test name
Test status
Simulation time 31326153 ps
CPU time 0.68 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206216 kb
Host smart-66b28bff-a81e-4df3-9767-77f98ad56c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=935307268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.935307268
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1530965865
Short name T2166
Test name
Test status
Simulation time 3415035271 ps
CPU time 4.11 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206508 kb
Host smart-c2c5ff6b-7310-44ba-8e9d-f1afdd37e595
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1530965865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1530965865
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.529097494
Short name T1537
Test name
Test status
Simulation time 13349275200 ps
CPU time 12.8 seconds
Started Jul 06 05:25:06 PM PDT 24
Finished Jul 06 05:25:20 PM PDT 24
Peak memory 206456 kb
Host smart-139b04f0-c77c-4c61-a4cd-f3589fc19563
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=529097494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.529097494
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3528257908
Short name T1069
Test name
Test status
Simulation time 23387392768 ps
CPU time 30.23 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:34 PM PDT 24
Peak memory 206260 kb
Host smart-902f0b10-e84a-49ab-abaa-6514a0d76886
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3528257908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3528257908
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.765322473
Short name T2673
Test name
Test status
Simulation time 155776598 ps
CPU time 0.82 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206196 kb
Host smart-6ceedea1-107f-4dff-b4d1-aea3330f4384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76532
2473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.765322473
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1254402057
Short name T588
Test name
Test status
Simulation time 158506207 ps
CPU time 0.84 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206148 kb
Host smart-88ee4687-3f39-4e57-9530-66719e2262b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544
02057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1254402057
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.588924960
Short name T2656
Test name
Test status
Simulation time 213642400 ps
CPU time 0.97 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:03 PM PDT 24
Peak memory 206192 kb
Host smart-4ff7245d-f60e-4ed7-8b50-a905f15fe878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58892
4960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.588924960
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2633370856
Short name T2169
Test name
Test status
Simulation time 1282917854 ps
CPU time 2.76 seconds
Started Jul 06 05:25:00 PM PDT 24
Finished Jul 06 05:25:05 PM PDT 24
Peak memory 206432 kb
Host smart-02845d24-b5e5-4f43-96f0-4e6eed754219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26333
70856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2633370856
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2977363969
Short name T190
Test name
Test status
Simulation time 16796066788 ps
CPU time 32.55 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206460 kb
Host smart-75d87818-5e79-4dd8-b308-5b60abfaee29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29773
63969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2977363969
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.469197025
Short name T2263
Test name
Test status
Simulation time 478248235 ps
CPU time 1.41 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206148 kb
Host smart-44cfc82a-c050-4053-ad0d-32064a696ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46919
7025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.469197025
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2154257613
Short name T526
Test name
Test status
Simulation time 137744340 ps
CPU time 0.79 seconds
Started Jul 06 05:25:03 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206200 kb
Host smart-8c473bd4-c581-4c31-93dd-0ce01efa96a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21542
57613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2154257613
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.649143828
Short name T1936
Test name
Test status
Simulation time 79983111 ps
CPU time 0.72 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206172 kb
Host smart-a33b980f-c33c-4f1f-b010-4887956004f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64914
3828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.649143828
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.280732155
Short name T1716
Test name
Test status
Simulation time 927981966 ps
CPU time 2.1 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 206400 kb
Host smart-ed0498d2-9488-4262-8e6e-aba082dbfe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28073
2155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.280732155
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1558194746
Short name T2125
Test name
Test status
Simulation time 299812621 ps
CPU time 2.36 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206404 kb
Host smart-422e992e-6c70-4c75-bed7-41a5f17b1eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15581
94746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1558194746
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.495533044
Short name T406
Test name
Test status
Simulation time 229595611 ps
CPU time 0.86 seconds
Started Jul 06 05:25:09 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206160 kb
Host smart-ad27a554-c42b-4f0d-842c-60e90d659096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49553
3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.495533044
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3345666720
Short name T1962
Test name
Test status
Simulation time 190278567 ps
CPU time 0.8 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206172 kb
Host smart-9f570176-caa6-4fee-94e4-6e531f47056b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33456
66720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3345666720
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3862160343
Short name T994
Test name
Test status
Simulation time 265106591 ps
CPU time 1.02 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206164 kb
Host smart-96cc4986-a997-4789-9b7e-9b81821211f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38621
60343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3862160343
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2189191865
Short name T1247
Test name
Test status
Simulation time 156157209 ps
CPU time 0.83 seconds
Started Jul 06 05:25:01 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206120 kb
Host smart-9812b544-9bfc-4504-b1b7-a564f41b6ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21891
91865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2189191865
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2111971023
Short name T1153
Test name
Test status
Simulation time 23337085526 ps
CPU time 28.65 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:37 PM PDT 24
Peak memory 206180 kb
Host smart-a2034ecb-be3e-4373-822b-fa96d2f0fb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21119
71023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2111971023
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3080704418
Short name T713
Test name
Test status
Simulation time 3377109935 ps
CPU time 4.55 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 206228 kb
Host smart-8f9025d7-7439-4f20-8ff7-9e5ee0416f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30807
04418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3080704418
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1545900525
Short name T1528
Test name
Test status
Simulation time 6260769442 ps
CPU time 174.81 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206488 kb
Host smart-0abefc99-2f43-40c0-b72e-b15b630ebb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15459
00525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1545900525
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.157149122
Short name T1750
Test name
Test status
Simulation time 4448755683 ps
CPU time 121.55 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:27:06 PM PDT 24
Peak memory 206396 kb
Host smart-8b198483-7ff4-4012-bc12-e52931cb01a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=157149122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.157149122
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3202903607
Short name T2344
Test name
Test status
Simulation time 236162684 ps
CPU time 0.9 seconds
Started Jul 06 05:25:02 PM PDT 24
Finished Jul 06 05:25:04 PM PDT 24
Peak memory 206100 kb
Host smart-0bfc2cad-6325-421d-93f7-607efb5956bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3202903607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3202903607
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3687694641
Short name T259
Test name
Test status
Simulation time 195552254 ps
CPU time 0.86 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206148 kb
Host smart-dc0c70cd-32c3-4879-a117-3f68b7118927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876
94641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3687694641
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.329208251
Short name T1821
Test name
Test status
Simulation time 4407302001 ps
CPU time 42.53 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206424 kb
Host smart-537a4b62-e543-41c9-8558-576c2e8b48cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920
8251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.329208251
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2769591057
Short name T936
Test name
Test status
Simulation time 6334316836 ps
CPU time 45.28 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:52 PM PDT 24
Peak memory 206452 kb
Host smart-b3e2e3e9-a93c-4742-8ba1-ed1e799fd043
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2769591057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2769591057
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.4077655736
Short name T1395
Test name
Test status
Simulation time 147842504 ps
CPU time 0.76 seconds
Started Jul 06 05:25:09 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206160 kb
Host smart-2c914ae7-27ea-49e8-a732-a50b9be83375
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4077655736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.4077655736
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1080138540
Short name T2096
Test name
Test status
Simulation time 148711033 ps
CPU time 0.75 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 205940 kb
Host smart-f05f4df5-d6ab-42b6-886e-739b1b66d7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10801
38540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1080138540
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1001714374
Short name T1322
Test name
Test status
Simulation time 311874970 ps
CPU time 0.99 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206136 kb
Host smart-551fa985-1fbb-4ea3-be90-f91bdaf105e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10017
14374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1001714374
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.755180413
Short name T1259
Test name
Test status
Simulation time 191905261 ps
CPU time 0.97 seconds
Started Jul 06 05:25:06 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 206188 kb
Host smart-03c6ca75-ff32-4c77-a5d2-415b8cb28478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75518
0413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.755180413
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1163326971
Short name T2027
Test name
Test status
Simulation time 184543601 ps
CPU time 0.77 seconds
Started Jul 06 05:25:06 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 206084 kb
Host smart-9bca56ad-6935-4b11-9e23-d23ef6080505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633
26971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1163326971
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1047380309
Short name T1402
Test name
Test status
Simulation time 144344052 ps
CPU time 0.76 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206208 kb
Host smart-c0afac75-2e75-407a-89af-914c9368b6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10473
80309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1047380309
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1461758117
Short name T641
Test name
Test status
Simulation time 150905751 ps
CPU time 0.78 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206188 kb
Host smart-476a671c-0b9b-43e1-83d4-4bf1acaaa222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14617
58117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1461758117
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.411665378
Short name T973
Test name
Test status
Simulation time 224487457 ps
CPU time 0.93 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206184 kb
Host smart-1f0cac75-3561-4d29-a10b-f08962bbe917
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=411665378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.411665378
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3263608145
Short name T846
Test name
Test status
Simulation time 139532404 ps
CPU time 0.76 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206096 kb
Host smart-556289d9-baea-4e61-8478-6b6f9c7c23fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636
08145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3263608145
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.251661227
Short name T1435
Test name
Test status
Simulation time 48163557 ps
CPU time 0.73 seconds
Started Jul 06 05:25:12 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206168 kb
Host smart-c9975341-a1c2-4a2f-b82f-8bc1b0db98c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
1227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.251661227
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2829288827
Short name T2260
Test name
Test status
Simulation time 6242418948 ps
CPU time 14.33 seconds
Started Jul 06 05:25:04 PM PDT 24
Finished Jul 06 05:25:20 PM PDT 24
Peak memory 206540 kb
Host smart-253536f9-f30b-4dfa-85f2-d679a3d95f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
88827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2829288827
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1448414693
Short name T1930
Test name
Test status
Simulation time 198228293 ps
CPU time 0.83 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206176 kb
Host smart-c3b87a59-f4bd-4755-bce2-0a77bd948bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484
14693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1448414693
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2188780205
Short name T684
Test name
Test status
Simulation time 205273206 ps
CPU time 0.82 seconds
Started Jul 06 05:25:09 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206144 kb
Host smart-ff6de637-23a5-4b55-82a2-9ddad8a9d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887
80205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2188780205
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.803992519
Short name T1011
Test name
Test status
Simulation time 215953256 ps
CPU time 0.88 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206200 kb
Host smart-ee0d87c3-6d50-46af-8bc6-9ad0cb95182a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80399
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.803992519
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2510446119
Short name T904
Test name
Test status
Simulation time 184091355 ps
CPU time 0.86 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206200 kb
Host smart-1480aba0-587a-4126-bbce-a2a65128ea5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25104
46119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2510446119
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1157971560
Short name T1515
Test name
Test status
Simulation time 210007064 ps
CPU time 0.88 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 206200 kb
Host smart-c9738aeb-0a0a-4551-9341-15ec952da7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
71560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1157971560
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.913574274
Short name T1726
Test name
Test status
Simulation time 159384326 ps
CPU time 0.85 seconds
Started Jul 06 05:25:08 PM PDT 24
Finished Jul 06 05:25:10 PM PDT 24
Peak memory 206108 kb
Host smart-073f5883-5f57-42fb-8b62-913319ed9343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91357
4274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.913574274
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2286509162
Short name T1629
Test name
Test status
Simulation time 155921925 ps
CPU time 0.8 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206172 kb
Host smart-b3dbb2e4-2b2c-44c9-8e51-a88c84f5e1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
09162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2286509162
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1829510193
Short name T2568
Test name
Test status
Simulation time 218045172 ps
CPU time 0.95 seconds
Started Jul 06 05:25:06 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206200 kb
Host smart-7bceecaa-9d7b-4d1b-b29b-5514bccf9843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18295
10193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1829510193
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2514497737
Short name T2419
Test name
Test status
Simulation time 3557121424 ps
CPU time 98.63 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:26:45 PM PDT 24
Peak memory 206516 kb
Host smart-36e65c7e-a92f-4ac6-9cce-f3e1fa85d31a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2514497737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2514497737
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1890324502
Short name T518
Test name
Test status
Simulation time 200412717 ps
CPU time 0.83 seconds
Started Jul 06 05:25:06 PM PDT 24
Finished Jul 06 05:25:08 PM PDT 24
Peak memory 206196 kb
Host smart-eb8ac4d4-6b1b-4b1e-af8b-b5529a26ba3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18903
24502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1890324502
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1130703597
Short name T571
Test name
Test status
Simulation time 172259334 ps
CPU time 0.8 seconds
Started Jul 06 05:25:12 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206176 kb
Host smart-98643907-f767-4c7e-9d7b-7f00fcce1fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
03597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1130703597
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3972567241
Short name T1497
Test name
Test status
Simulation time 940277354 ps
CPU time 2.09 seconds
Started Jul 06 05:25:09 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206452 kb
Host smart-0ccceed1-8dc2-42af-a693-6fd69015d51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
67241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3972567241
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.586847803
Short name T392
Test name
Test status
Simulation time 3880088339 ps
CPU time 29.22 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:36 PM PDT 24
Peak memory 206460 kb
Host smart-2ded226b-a96f-4ebc-8777-388ba593de09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58684
7803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.586847803
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1548089856
Short name T2141
Test name
Test status
Simulation time 30037939 ps
CPU time 0.67 seconds
Started Jul 06 05:25:14 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 206264 kb
Host smart-51440dbf-cbfc-4b5c-b970-0cc0913077bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1548089856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1548089856
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.858793014
Short name T1751
Test name
Test status
Simulation time 4233422763 ps
CPU time 5.8 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206180 kb
Host smart-d6f0f705-fecc-4132-9d70-d65982f02938
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=858793014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.858793014
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3430398684
Short name T2432
Test name
Test status
Simulation time 13402948770 ps
CPU time 12.02 seconds
Started Jul 06 05:25:05 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206460 kb
Host smart-f9c47d97-7bd5-419d-b94c-b7ef27b53977
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3430398684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3430398684
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.265577114
Short name T15
Test name
Test status
Simulation time 23363022312 ps
CPU time 27.7 seconds
Started Jul 06 05:25:07 PM PDT 24
Finished Jul 06 05:25:36 PM PDT 24
Peak memory 206180 kb
Host smart-9a80e843-ce3a-433d-96fe-6537f776df27
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=265577114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.265577114
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.877217310
Short name T964
Test name
Test status
Simulation time 187022674 ps
CPU time 0.9 seconds
Started Jul 06 05:25:12 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206204 kb
Host smart-2f1daa53-6e81-4393-85b4-a9999fa8a0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87721
7310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.877217310
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.781156002
Short name T2471
Test name
Test status
Simulation time 159920966 ps
CPU time 0.78 seconds
Started Jul 06 05:25:17 PM PDT 24
Finished Jul 06 05:25:19 PM PDT 24
Peak memory 206188 kb
Host smart-59e81c24-3bdd-4197-9451-767d979e550f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78115
6002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.781156002
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1177759083
Short name T702
Test name
Test status
Simulation time 422540758 ps
CPU time 1.42 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206168 kb
Host smart-27ab5584-f744-479c-8097-0b3b5a61b4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777
59083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1177759083
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.502859182
Short name T171
Test name
Test status
Simulation time 1209143017 ps
CPU time 3.09 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:17 PM PDT 24
Peak memory 206424 kb
Host smart-62ade4e4-afa9-4a4e-bf86-9e6e7738f353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50285
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.502859182
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.327768846
Short name T187
Test name
Test status
Simulation time 21639870210 ps
CPU time 41.61 seconds
Started Jul 06 05:25:12 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206492 kb
Host smart-29065031-d4d9-4243-8278-ce3945962ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32776
8846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.327768846
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3838571102
Short name T1791
Test name
Test status
Simulation time 405847791 ps
CPU time 1.2 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206172 kb
Host smart-9ddea421-30a5-4a8c-909b-e1f7547a91cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38385
71102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3838571102
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3471339304
Short name T48
Test name
Test status
Simulation time 140110013 ps
CPU time 0.74 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206188 kb
Host smart-d348beaf-0979-4676-8d35-fb44440ef89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
39304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3471339304
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2073275929
Short name T590
Test name
Test status
Simulation time 111917588 ps
CPU time 0.73 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 206148 kb
Host smart-0ce31018-4cac-4976-9df1-7cecaecfe28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
75929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2073275929
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2821981444
Short name T1255
Test name
Test status
Simulation time 999588302 ps
CPU time 2.44 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206452 kb
Host smart-923bfb5a-bdf5-47c8-96a4-451fb042d0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219
81444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2821981444
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1180987175
Short name T1475
Test name
Test status
Simulation time 303555812 ps
CPU time 2.18 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206392 kb
Host smart-daab1bdd-8630-4477-a269-ee96bd75d439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
87175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1180987175
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2825430175
Short name T1013
Test name
Test status
Simulation time 233691982 ps
CPU time 0.87 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206184 kb
Host smart-6f7e6ca0-6aa7-4e0b-bb0d-781477d96447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28254
30175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2825430175
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1646012968
Short name T1391
Test name
Test status
Simulation time 144282972 ps
CPU time 0.79 seconds
Started Jul 06 05:25:12 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206216 kb
Host smart-6ef82b02-d411-4ef1-a272-d18c024c7e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16460
12968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1646012968
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3311551449
Short name T346
Test name
Test status
Simulation time 200616863 ps
CPU time 0.88 seconds
Started Jul 06 05:25:14 PM PDT 24
Finished Jul 06 05:25:16 PM PDT 24
Peak memory 206200 kb
Host smart-9a5d6181-de42-4281-b763-16b170d3e687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
51449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3311551449
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.305590040
Short name T1822
Test name
Test status
Simulation time 8884129725 ps
CPU time 236.97 seconds
Started Jul 06 05:25:12 PM PDT 24
Finished Jul 06 05:29:10 PM PDT 24
Peak memory 206488 kb
Host smart-b861c7f5-a25d-468b-ab79-74f4b3c46562
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=305590040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.305590040
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.611814899
Short name T924
Test name
Test status
Simulation time 198152170 ps
CPU time 0.86 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206208 kb
Host smart-2bafcc4d-5b74-412a-8d86-5816237c675d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61181
4899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.611814899
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1388525167
Short name T491
Test name
Test status
Simulation time 23302006279 ps
CPU time 23.22 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:37 PM PDT 24
Peak memory 206248 kb
Host smart-a0cb1d1a-764f-4e60-8028-9f4d693eecfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13885
25167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1388525167
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3178728529
Short name T1432
Test name
Test status
Simulation time 3275534220 ps
CPU time 3.68 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206232 kb
Host smart-c9100fc1-dd53-45ec-9ca3-45bd647b2e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31787
28529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3178728529
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.149024627
Short name T625
Test name
Test status
Simulation time 10681357684 ps
CPU time 289.7 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:30:01 PM PDT 24
Peak memory 206496 kb
Host smart-3e8dd24f-7f9c-4986-a837-73a50adc0108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14902
4627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.149024627
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2713218418
Short name T2041
Test name
Test status
Simulation time 6862140098 ps
CPU time 189.29 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:28:21 PM PDT 24
Peak memory 206460 kb
Host smart-d17ea827-84f9-4280-b329-4bf522af98d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2713218418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2713218418
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.566501531
Short name T327
Test name
Test status
Simulation time 253090050 ps
CPU time 0.95 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206176 kb
Host smart-1956622b-73d4-4e15-a08c-750262d90cae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=566501531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.566501531
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.293246239
Short name T2192
Test name
Test status
Simulation time 193551773 ps
CPU time 0.86 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206124 kb
Host smart-82a434a5-89a7-4265-928a-b88acd91e283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
6239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.293246239
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.347563668
Short name T2592
Test name
Test status
Simulation time 5387078278 ps
CPU time 37.25 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206480 kb
Host smart-f03ce87c-baa3-4325-b3f1-763c33029136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.347563668
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2336949585
Short name T1874
Test name
Test status
Simulation time 2893625808 ps
CPU time 82.17 seconds
Started Jul 06 05:25:17 PM PDT 24
Finished Jul 06 05:26:40 PM PDT 24
Peak memory 206468 kb
Host smart-133812e3-1ede-40d4-93fb-a2ec5d3debbb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2336949585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2336949585
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2712902345
Short name T1651
Test name
Test status
Simulation time 201225711 ps
CPU time 0.8 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206204 kb
Host smart-e2a32572-4157-41d2-8cfc-a3a927e18284
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2712902345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2712902345
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1561513860
Short name T358
Test name
Test status
Simulation time 168009111 ps
CPU time 0.8 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:14 PM PDT 24
Peak memory 206164 kb
Host smart-6aa9546d-a1aa-46ea-bc4d-8353ffcb8420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15615
13860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1561513860
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2498841179
Short name T1894
Test name
Test status
Simulation time 179862651 ps
CPU time 0.85 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 205856 kb
Host smart-cf75d3ca-5ddd-49ac-9712-10a299b93426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24988
41179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2498841179
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3826042590
Short name T1673
Test name
Test status
Simulation time 185868825 ps
CPU time 0.87 seconds
Started Jul 06 05:25:14 PM PDT 24
Finished Jul 06 05:25:16 PM PDT 24
Peak memory 206200 kb
Host smart-6ef08c8a-fb5b-4ac9-81b2-b58161eddd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38260
42590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3826042590
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3402641535
Short name T397
Test name
Test status
Simulation time 165096760 ps
CPU time 0.83 seconds
Started Jul 06 05:26:39 PM PDT 24
Finished Jul 06 05:26:40 PM PDT 24
Peak memory 206204 kb
Host smart-3b243d0f-c0e1-4b60-b5c8-14ea113ca7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
41535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3402641535
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1327557069
Short name T173
Test name
Test status
Simulation time 166309007 ps
CPU time 0.82 seconds
Started Jul 06 05:25:11 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206164 kb
Host smart-7d38cc8c-5ecb-4cf5-880d-3234507b0ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13275
57069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1327557069
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2816446010
Short name T2091
Test name
Test status
Simulation time 233952420 ps
CPU time 0.88 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206180 kb
Host smart-e3927f4c-5a99-4fe8-894e-07f44a923a48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2816446010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2816446010
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1730500362
Short name T2650
Test name
Test status
Simulation time 176324425 ps
CPU time 0.82 seconds
Started Jul 06 05:25:10 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206136 kb
Host smart-be9e4044-aa37-413b-b019-c3850ffac2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17305
00362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1730500362
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3723129263
Short name T1840
Test name
Test status
Simulation time 57702741 ps
CPU time 0.67 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 205912 kb
Host smart-78e83654-b595-457d-8438-ddd050d74d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37231
29263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3723129263
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2837539595
Short name T1270
Test name
Test status
Simulation time 8823728595 ps
CPU time 18.15 seconds
Started Jul 06 05:25:34 PM PDT 24
Finished Jul 06 05:25:52 PM PDT 24
Peak memory 206512 kb
Host smart-d736c014-a7f3-419e-a40d-0151c2bfc032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28375
39595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2837539595
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.127778771
Short name T53
Test name
Test status
Simulation time 176715855 ps
CPU time 0.85 seconds
Started Jul 06 05:25:15 PM PDT 24
Finished Jul 06 05:25:16 PM PDT 24
Peak memory 206156 kb
Host smart-bac17978-f9e0-4cc4-a5f0-a4ebe499f7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12777
8771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.127778771
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4142780425
Short name T1923
Test name
Test status
Simulation time 189707987 ps
CPU time 0.83 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:17 PM PDT 24
Peak memory 206176 kb
Host smart-094796ac-3436-43d7-b25e-d7e20c4105c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427
80425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4142780425
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2892552607
Short name T835
Test name
Test status
Simulation time 149987233 ps
CPU time 0.75 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206196 kb
Host smart-2b626698-afda-4ee2-9adf-042c3a9773ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28925
52607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2892552607
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2441406956
Short name T2499
Test name
Test status
Simulation time 190337594 ps
CPU time 0.88 seconds
Started Jul 06 05:25:15 PM PDT 24
Finished Jul 06 05:25:16 PM PDT 24
Peak memory 206156 kb
Host smart-d0652f6f-41d3-4149-b1db-1ccd40874304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24414
06956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2441406956
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1605979129
Short name T564
Test name
Test status
Simulation time 172918159 ps
CPU time 0.79 seconds
Started Jul 06 05:25:17 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206084 kb
Host smart-65779840-2fef-4627-b9d6-4fea5910f454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16059
79129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1605979129
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1266305053
Short name T531
Test name
Test status
Simulation time 157924049 ps
CPU time 0.81 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206100 kb
Host smart-b2961f64-fedd-40fb-b0bd-8ba7353a42b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12663
05053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1266305053
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2866123521
Short name T2377
Test name
Test status
Simulation time 153813938 ps
CPU time 0.8 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:17 PM PDT 24
Peak memory 206120 kb
Host smart-9f8e8de9-28b8-41f8-8ad0-1b69b07a24c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28661
23521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2866123521
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1331623006
Short name T2364
Test name
Test status
Simulation time 221334405 ps
CPU time 0.9 seconds
Started Jul 06 05:25:25 PM PDT 24
Finished Jul 06 05:25:26 PM PDT 24
Peak memory 206176 kb
Host smart-9c27b490-6366-481e-8571-092bec00cde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13316
23006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1331623006
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1075490330
Short name T1661
Test name
Test status
Simulation time 5850745388 ps
CPU time 53.96 seconds
Started Jul 06 05:25:17 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206464 kb
Host smart-bb534346-6a25-4677-a186-1e05c8b6a81e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1075490330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1075490330
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1157362955
Short name T708
Test name
Test status
Simulation time 201532155 ps
CPU time 0.86 seconds
Started Jul 06 05:25:40 PM PDT 24
Finished Jul 06 05:25:41 PM PDT 24
Peak memory 206160 kb
Host smart-25622b2f-0db6-4bbb-9d40-0ae340df8768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11573
62955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1157362955
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3769721509
Short name T1186
Test name
Test status
Simulation time 191440249 ps
CPU time 0.82 seconds
Started Jul 06 05:25:30 PM PDT 24
Finished Jul 06 05:25:32 PM PDT 24
Peak memory 206196 kb
Host smart-06c6c3c1-c210-43fd-935b-8db7d8859d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697
21509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3769721509
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.528498417
Short name T413
Test name
Test status
Simulation time 402726709 ps
CPU time 1.16 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206156 kb
Host smart-01bf9aa9-7f6e-4183-8402-ba2a5e407f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52849
8417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.528498417
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1409530765
Short name T2068
Test name
Test status
Simulation time 3497184792 ps
CPU time 93.7 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:26:56 PM PDT 24
Peak memory 206460 kb
Host smart-66a5c4c6-ba68-416e-ac2e-9ba95b22c5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14095
30765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1409530765
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2253101725
Short name T2243
Test name
Test status
Simulation time 3585626191 ps
CPU time 4.23 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:25:25 PM PDT 24
Peak memory 206144 kb
Host smart-358a1588-fe83-4062-ab72-e574a426f15e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2253101725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2253101725
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3245773632
Short name T2078
Test name
Test status
Simulation time 13370169652 ps
CPU time 12.18 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206420 kb
Host smart-a1dc1919-9daa-4626-bba2-b85817d15f64
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3245773632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3245773632
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1880519293
Short name T1001
Test name
Test status
Simulation time 23326153266 ps
CPU time 25.39 seconds
Started Jul 06 05:25:14 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206448 kb
Host smart-03ea391b-8a61-449d-93c9-2fa4ddc6352a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1880519293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1880519293
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3927537231
Short name T349
Test name
Test status
Simulation time 177236451 ps
CPU time 0.83 seconds
Started Jul 06 05:25:22 PM PDT 24
Finished Jul 06 05:25:23 PM PDT 24
Peak memory 206200 kb
Host smart-ebe05c30-58b2-485b-82b3-f3aa320e0ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
37231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3927537231
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3718366062
Short name T1349
Test name
Test status
Simulation time 155573643 ps
CPU time 0.76 seconds
Started Jul 06 05:25:17 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206164 kb
Host smart-74170168-6800-42c4-89c8-88ef82898913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37183
66062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3718366062
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1168086126
Short name T2207
Test name
Test status
Simulation time 165144056 ps
CPU time 0.82 seconds
Started Jul 06 05:25:36 PM PDT 24
Finished Jul 06 05:25:37 PM PDT 24
Peak memory 206160 kb
Host smart-7a31de04-1964-4764-be75-2dd2d52568b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11680
86126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1168086126
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3880240005
Short name T2056
Test name
Test status
Simulation time 1217346849 ps
CPU time 2.62 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206356 kb
Host smart-cfbab69b-7e5b-4361-9eac-1b2e00a1f6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
40005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3880240005
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.231632743
Short name T2257
Test name
Test status
Simulation time 21202437442 ps
CPU time 42.47 seconds
Started Jul 06 05:25:15 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206488 kb
Host smart-92150399-2ab1-485c-8258-185481283d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
2743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.231632743
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3850888058
Short name T1852
Test name
Test status
Simulation time 326930800 ps
CPU time 1.19 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206140 kb
Host smart-85396a2c-9500-434b-8a1b-f4788b8363a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
88058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3850888058
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.317423568
Short name T542
Test name
Test status
Simulation time 135944938 ps
CPU time 0.75 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:25:22 PM PDT 24
Peak memory 206088 kb
Host smart-c73d3dc8-a241-4624-9360-a5ba7801d91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31742
3568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.317423568
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1558793264
Short name T400
Test name
Test status
Simulation time 44555685 ps
CPU time 0.67 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206156 kb
Host smart-7c698821-1cb2-4f2d-b500-a91b4d24e2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15587
93264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1558793264
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3173996134
Short name T1139
Test name
Test status
Simulation time 776935977 ps
CPU time 1.86 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:25:23 PM PDT 24
Peak memory 206436 kb
Host smart-672be266-2906-40f7-8d55-dc94c8bfe2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31739
96134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3173996134
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.242935057
Short name T2558
Test name
Test status
Simulation time 300472638 ps
CPU time 2.17 seconds
Started Jul 06 05:25:22 PM PDT 24
Finished Jul 06 05:25:25 PM PDT 24
Peak memory 206392 kb
Host smart-68b34aea-c439-4764-b891-98f1678acc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24293
5057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.242935057
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2259898920
Short name T2036
Test name
Test status
Simulation time 154747695 ps
CPU time 0.8 seconds
Started Jul 06 05:25:14 PM PDT 24
Finished Jul 06 05:25:16 PM PDT 24
Peak memory 206184 kb
Host smart-00f14de2-cfa4-430d-8f9d-2fd23756274c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
98920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2259898920
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.4039643619
Short name T1896
Test name
Test status
Simulation time 204593861 ps
CPU time 0.82 seconds
Started Jul 06 05:25:23 PM PDT 24
Finished Jul 06 05:25:24 PM PDT 24
Peak memory 206200 kb
Host smart-d1278d44-20f7-4147-81aa-f9bea36edef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
43619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.4039643619
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.4007499409
Short name T837
Test name
Test status
Simulation time 249182362 ps
CPU time 0.97 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206156 kb
Host smart-73b350f4-26e7-4941-8286-3b449137fa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40074
99409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4007499409
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1996233751
Short name T712
Test name
Test status
Simulation time 236416469 ps
CPU time 0.93 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206120 kb
Host smart-de2ecd74-328a-4c1a-acd4-df61f45f9c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19962
33751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1996233751
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3714621340
Short name T842
Test name
Test status
Simulation time 23289787443 ps
CPU time 24.25 seconds
Started Jul 06 05:25:36 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206224 kb
Host smart-75b42073-490f-4371-a47d-8775cee7a94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37146
21340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3714621340
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3233729719
Short name T1800
Test name
Test status
Simulation time 3282619820 ps
CPU time 3.97 seconds
Started Jul 06 05:25:13 PM PDT 24
Finished Jul 06 05:25:17 PM PDT 24
Peak memory 206500 kb
Host smart-4e4d8f62-cf02-4a36-8a31-3335d7a9e08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32337
29719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3233729719
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.449231155
Short name T1866
Test name
Test status
Simulation time 8942439246 ps
CPU time 258.03 seconds
Started Jul 06 05:25:16 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 206532 kb
Host smart-13bded7f-478c-46e7-9cff-43ec473d51c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44923
1155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.449231155
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2212088303
Short name T1605
Test name
Test status
Simulation time 3133589094 ps
CPU time 84.96 seconds
Started Jul 06 05:25:22 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206420 kb
Host smart-b81a4328-04c2-45d2-8982-da5123b98fa2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2212088303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2212088303
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2660564273
Short name T763
Test name
Test status
Simulation time 253254412 ps
CPU time 0.94 seconds
Started Jul 06 05:25:24 PM PDT 24
Finished Jul 06 05:25:26 PM PDT 24
Peak memory 206164 kb
Host smart-314f3501-d7fa-4242-a0c7-dd674871783f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2660564273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2660564273
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4118202400
Short name T560
Test name
Test status
Simulation time 266669822 ps
CPU time 0.95 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:28 PM PDT 24
Peak memory 206160 kb
Host smart-da723d0c-b236-4c86-b352-ecbdd58763ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41182
02400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4118202400
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1922242493
Short name T1380
Test name
Test status
Simulation time 5402255970 ps
CPU time 144.49 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206484 kb
Host smart-41884eed-a9dd-4f56-936f-d79ed008decb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19222
42493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1922242493
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.262364548
Short name T1952
Test name
Test status
Simulation time 6847121067 ps
CPU time 195.06 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206456 kb
Host smart-77bf22ff-0c42-4780-a886-f16ce14a827d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=262364548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.262364548
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1722787787
Short name T2047
Test name
Test status
Simulation time 186198266 ps
CPU time 0.82 seconds
Started Jul 06 05:25:23 PM PDT 24
Finished Jul 06 05:25:24 PM PDT 24
Peak memory 206108 kb
Host smart-796a40d8-1755-475a-8fcd-501f1aaf7045
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1722787787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1722787787
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2398816899
Short name T1323
Test name
Test status
Simulation time 147868416 ps
CPU time 0.83 seconds
Started Jul 06 05:25:23 PM PDT 24
Finished Jul 06 05:25:24 PM PDT 24
Peak memory 206148 kb
Host smart-b9bb0413-d9ba-48fa-b617-ad3bdc345106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23988
16899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2398816899
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1094090860
Short name T1886
Test name
Test status
Simulation time 162525959 ps
CPU time 0.79 seconds
Started Jul 06 05:25:33 PM PDT 24
Finished Jul 06 05:25:34 PM PDT 24
Peak memory 206176 kb
Host smart-c23e9c97-d583-41de-8f3c-9b3380e525e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
90860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1094090860
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3277223096
Short name T2470
Test name
Test status
Simulation time 183071386 ps
CPU time 0.93 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:25:22 PM PDT 24
Peak memory 206084 kb
Host smart-cf214667-6e4b-4873-9ed9-6a10f72182b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32772
23096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3277223096
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2962382094
Short name T2699
Test name
Test status
Simulation time 155231066 ps
CPU time 0.82 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206168 kb
Host smart-51bbdf03-b792-4dc9-98be-8b85c1126312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29623
82094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2962382094
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1286447032
Short name T1933
Test name
Test status
Simulation time 169517827 ps
CPU time 0.81 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206152 kb
Host smart-c4edc0d1-b26b-4aa4-a138-efdec80816ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12864
47032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1286447032
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.776738815
Short name T740
Test name
Test status
Simulation time 231854734 ps
CPU time 0.92 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206176 kb
Host smart-4a90e725-6b6d-497c-bf8b-0649bbdef7d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=776738815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.776738815
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.138916015
Short name T2269
Test name
Test status
Simulation time 185106075 ps
CPU time 0.84 seconds
Started Jul 06 05:25:23 PM PDT 24
Finished Jul 06 05:25:24 PM PDT 24
Peak memory 206096 kb
Host smart-aca24c7a-0f30-417b-8941-3a9d40bad935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
6015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.138916015
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1016925479
Short name T2326
Test name
Test status
Simulation time 49966784 ps
CPU time 0.66 seconds
Started Jul 06 05:25:24 PM PDT 24
Finished Jul 06 05:25:25 PM PDT 24
Peak memory 206184 kb
Host smart-d4d71743-545e-4445-bdab-01001bdff631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10169
25479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1016925479
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.322062269
Short name T264
Test name
Test status
Simulation time 17056956274 ps
CPU time 36.3 seconds
Started Jul 06 05:25:30 PM PDT 24
Finished Jul 06 05:26:07 PM PDT 24
Peak memory 206460 kb
Host smart-90ba1eb2-48e2-4d48-a38d-c4bff6d05c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32206
2269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.322062269
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2394602568
Short name T966
Test name
Test status
Simulation time 165623609 ps
CPU time 0.86 seconds
Started Jul 06 05:25:22 PM PDT 24
Finished Jul 06 05:25:23 PM PDT 24
Peak memory 206192 kb
Host smart-19ded3be-e5f1-4cc1-b88a-41eac4e33ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23946
02568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2394602568
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2294450144
Short name T2247
Test name
Test status
Simulation time 259151363 ps
CPU time 0.97 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206204 kb
Host smart-5e0dd2f6-e8df-41e9-80fa-229e2d42d0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22944
50144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2294450144
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1431499714
Short name T1593
Test name
Test status
Simulation time 253176870 ps
CPU time 0.88 seconds
Started Jul 06 05:25:21 PM PDT 24
Finished Jul 06 05:25:22 PM PDT 24
Peak memory 206104 kb
Host smart-667f6451-ac40-4fe1-a048-5c5996e0564c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314
99714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1431499714
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1675728512
Short name T1154
Test name
Test status
Simulation time 193333096 ps
CPU time 0.93 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206204 kb
Host smart-7863f565-da19-4a49-8090-d8591492bce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16757
28512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1675728512
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3858131492
Short name T2502
Test name
Test status
Simulation time 166545363 ps
CPU time 0.78 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206156 kb
Host smart-15d367e1-08a8-4acc-959b-dc71efffa927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38581
31492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3858131492
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2843018067
Short name T1434
Test name
Test status
Simulation time 157404418 ps
CPU time 0.81 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206112 kb
Host smart-8501102d-6069-4373-8bb6-9d2d4c153c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28430
18067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2843018067
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2925005710
Short name T515
Test name
Test status
Simulation time 145314347 ps
CPU time 0.8 seconds
Started Jul 06 05:25:29 PM PDT 24
Finished Jul 06 05:25:30 PM PDT 24
Peak memory 206148 kb
Host smart-899d9103-51b7-464d-b6eb-92e6202324b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29250
05710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2925005710
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.652035719
Short name T548
Test name
Test status
Simulation time 244068658 ps
CPU time 1.06 seconds
Started Jul 06 05:25:22 PM PDT 24
Finished Jul 06 05:25:23 PM PDT 24
Peak memory 206200 kb
Host smart-a0fbd019-0e2c-4988-8985-a5a5e5fcb7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65203
5719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.652035719
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.662009517
Short name T2612
Test name
Test status
Simulation time 6460031414 ps
CPU time 179.48 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:28:27 PM PDT 24
Peak memory 206360 kb
Host smart-64787fe8-379a-4df6-afb0-647970045272
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=662009517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.662009517
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3044805841
Short name T1607
Test name
Test status
Simulation time 157025296 ps
CPU time 0.85 seconds
Started Jul 06 05:25:38 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206176 kb
Host smart-5c8dad36-9122-4d31-bde8-a14a9cbc3156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
05841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3044805841
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3230254843
Short name T2241
Test name
Test status
Simulation time 170091706 ps
CPU time 0.85 seconds
Started Jul 06 05:25:35 PM PDT 24
Finished Jul 06 05:25:36 PM PDT 24
Peak memory 206180 kb
Host smart-ed93522c-c9fa-41aa-84e6-3725fcb0e6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32302
54843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3230254843
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3799336135
Short name T839
Test name
Test status
Simulation time 1087574739 ps
CPU time 2.29 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206452 kb
Host smart-1e462456-5baa-4e83-b6ae-92bfac23c37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37993
36135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3799336135
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.349114158
Short name T2373
Test name
Test status
Simulation time 3812523693 ps
CPU time 26.54 seconds
Started Jul 06 05:25:31 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206436 kb
Host smart-8eb81808-c3a7-4200-b1bb-974d0c0c957f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34911
4158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.349114158
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.1469917744
Short name T2399
Test name
Test status
Simulation time 43897270 ps
CPU time 0.67 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206232 kb
Host smart-dea1be4d-a6fd-465e-8359-e25c34a5cada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1469917744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1469917744
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.690661847
Short name T913
Test name
Test status
Simulation time 4076859536 ps
CPU time 5.19 seconds
Started Jul 06 05:22:43 PM PDT 24
Finished Jul 06 05:22:49 PM PDT 24
Peak memory 206192 kb
Host smart-395933b7-3323-423f-b753-9b6af9b8fa29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=690661847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.690661847
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.767179174
Short name T8
Test name
Test status
Simulation time 13357889324 ps
CPU time 13.42 seconds
Started Jul 06 05:22:40 PM PDT 24
Finished Jul 06 05:22:53 PM PDT 24
Peak memory 206268 kb
Host smart-72f6d9d0-b687-4aa6-8a49-78c4392f6cda
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=767179174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.767179174
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.4169831724
Short name T1143
Test name
Test status
Simulation time 23334923918 ps
CPU time 23.9 seconds
Started Jul 06 05:22:42 PM PDT 24
Finished Jul 06 05:23:06 PM PDT 24
Peak memory 206268 kb
Host smart-8745561c-9a1c-4032-8072-294937aa38eb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4169831724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.4169831724
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3792540382
Short name T942
Test name
Test status
Simulation time 191175231 ps
CPU time 0.93 seconds
Started Jul 06 05:22:43 PM PDT 24
Finished Jul 06 05:22:44 PM PDT 24
Peak memory 206100 kb
Host smart-406bcebe-b168-4239-bcb0-bd5c4132ac33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
40382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3792540382
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2741249807
Short name T56
Test name
Test status
Simulation time 150769964 ps
CPU time 0.8 seconds
Started Jul 06 05:22:40 PM PDT 24
Finished Jul 06 05:22:41 PM PDT 24
Peak memory 206192 kb
Host smart-4de32a31-cd2e-49e5-a990-dcb2fe90ad97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27412
49807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2741249807
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1499639798
Short name T2623
Test name
Test status
Simulation time 178974376 ps
CPU time 0.77 seconds
Started Jul 06 05:22:41 PM PDT 24
Finished Jul 06 05:22:42 PM PDT 24
Peak memory 206200 kb
Host smart-d6e2783e-d69c-411c-a4b1-758b844abebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14996
39798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1499639798
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.63644858
Short name T186
Test name
Test status
Simulation time 229137883 ps
CPU time 1.05 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:22:46 PM PDT 24
Peak memory 206156 kb
Host smart-5aeabdb8-d864-45fb-bffe-d54dd99af1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63644
858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.63644858
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3954901930
Short name T1625
Test name
Test status
Simulation time 1255745919 ps
CPU time 2.82 seconds
Started Jul 06 05:22:46 PM PDT 24
Finished Jul 06 05:22:49 PM PDT 24
Peak memory 206396 kb
Host smart-0c6d2368-2b65-4d36-9de5-1ef05885314a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39549
01930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3954901930
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3269554813
Short name T1129
Test name
Test status
Simulation time 11745301388 ps
CPU time 22.85 seconds
Started Jul 06 05:22:47 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 206436 kb
Host smart-3ef1b47e-98c3-4602-b527-6e0b0fb9b16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
54813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3269554813
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2575529314
Short name T1555
Test name
Test status
Simulation time 427976639 ps
CPU time 1.28 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:22:47 PM PDT 24
Peak memory 206148 kb
Host smart-0087d692-280e-42e1-bb33-475e51b33766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25755
29314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2575529314
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2403787403
Short name T2113
Test name
Test status
Simulation time 172474548 ps
CPU time 0.8 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:22:46 PM PDT 24
Peak memory 206168 kb
Host smart-ca21a36a-8c75-42ad-b498-9d395d935df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
87403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2403787403
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.4237499129
Short name T960
Test name
Test status
Simulation time 40017364 ps
CPU time 0.67 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:22:54 PM PDT 24
Peak memory 206172 kb
Host smart-2f5dd2b5-3cc6-479c-b142-3f4633261fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42374
99129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4237499129
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1657440092
Short name T453
Test name
Test status
Simulation time 871973146 ps
CPU time 2.11 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:22:48 PM PDT 24
Peak memory 206316 kb
Host smart-a132e507-a2dd-4b3d-8ebc-891b9588d804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16574
40092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1657440092
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.559746411
Short name T485
Test name
Test status
Simulation time 163547130 ps
CPU time 1.57 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:22:47 PM PDT 24
Peak memory 206396 kb
Host smart-ebec1f79-b65b-4d5f-a1dc-ff64b7b9b546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55974
6411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.559746411
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.2562160152
Short name T36
Test name
Test status
Simulation time 111186835241 ps
CPU time 144.7 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 206460 kb
Host smart-f12dcf19-98ec-464f-9b43-3b58a3f251eb
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2562160152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.2562160152
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1809917115
Short name T1072
Test name
Test status
Simulation time 98172373477 ps
CPU time 122.11 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:24:47 PM PDT 24
Peak memory 206472 kb
Host smart-f0f5f24f-871c-4326-ae17-ce314273b85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809917115 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1809917115
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1970992539
Short name T1994
Test name
Test status
Simulation time 107141303038 ps
CPU time 151.05 seconds
Started Jul 06 05:22:47 PM PDT 24
Finished Jul 06 05:25:18 PM PDT 24
Peak memory 206376 kb
Host smart-f58337d2-b568-448d-8d46-57500448fe5f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1970992539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1970992539
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2080103348
Short name T1637
Test name
Test status
Simulation time 98085961721 ps
CPU time 161.46 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:25:26 PM PDT 24
Peak memory 206448 kb
Host smart-d825f164-4a27-4d90-bf6e-a8a46b8a6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080103348 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2080103348
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.881476190
Short name T230
Test name
Test status
Simulation time 119173834022 ps
CPU time 166.62 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:25:31 PM PDT 24
Peak memory 206412 kb
Host smart-24ec5fa9-9657-42a9-b1b4-175b9dfeb331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88147
6190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.881476190
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3916205225
Short name T1530
Test name
Test status
Simulation time 183523475 ps
CPU time 0.89 seconds
Started Jul 06 05:22:46 PM PDT 24
Finished Jul 06 05:22:47 PM PDT 24
Peak memory 206180 kb
Host smart-6deb683e-98bb-4f93-a099-17a06967acda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39162
05225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3916205225
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1020660827
Short name T466
Test name
Test status
Simulation time 146773979 ps
CPU time 0.74 seconds
Started Jul 06 05:22:43 PM PDT 24
Finished Jul 06 05:22:44 PM PDT 24
Peak memory 206172 kb
Host smart-8c588cfd-fd8d-4c61-80ef-751181fd9ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
60827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1020660827
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.274195566
Short name T1887
Test name
Test status
Simulation time 184617733 ps
CPU time 0.83 seconds
Started Jul 06 05:22:43 PM PDT 24
Finished Jul 06 05:22:45 PM PDT 24
Peak memory 206204 kb
Host smart-9c7732a4-3ba7-4d8e-85aa-acf9a16ccc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27419
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.274195566
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.528681797
Short name T1115
Test name
Test status
Simulation time 235687089 ps
CPU time 0.88 seconds
Started Jul 06 05:22:44 PM PDT 24
Finished Jul 06 05:22:45 PM PDT 24
Peak memory 206160 kb
Host smart-6bb38bee-da90-4d62-9342-a3e3195c3293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52868
1797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.528681797
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.606171552
Short name T1575
Test name
Test status
Simulation time 23338950437 ps
CPU time 23.98 seconds
Started Jul 06 05:22:46 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 206268 kb
Host smart-3d90eb18-a790-4ad1-b153-c3b6a4c016d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60617
1552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.606171552
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.278458595
Short name T2630
Test name
Test status
Simulation time 3284416409 ps
CPU time 3.9 seconds
Started Jul 06 05:22:46 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 206264 kb
Host smart-9dc0db8d-dc8d-4578-b588-f213ba53d8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27845
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.278458595
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.692624520
Short name T2454
Test name
Test status
Simulation time 10193555950 ps
CPU time 92.56 seconds
Started Jul 06 05:22:51 PM PDT 24
Finished Jul 06 05:24:24 PM PDT 24
Peak memory 206472 kb
Host smart-99d563ac-a47d-424b-ad93-2d79bea8545c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69262
4520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.692624520
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1118507982
Short name T1290
Test name
Test status
Simulation time 4985702989 ps
CPU time 43.83 seconds
Started Jul 06 05:22:45 PM PDT 24
Finished Jul 06 05:23:30 PM PDT 24
Peak memory 206480 kb
Host smart-94dfba43-d092-45b5-961f-fb2f4cfc0080
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1118507982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1118507982
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1755408797
Short name T2255
Test name
Test status
Simulation time 275894069 ps
CPU time 0.93 seconds
Started Jul 06 05:22:47 PM PDT 24
Finished Jul 06 05:22:48 PM PDT 24
Peak memory 206204 kb
Host smart-f3f57079-5d3c-474b-8873-264ea237f8f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1755408797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1755408797
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1309033040
Short name T516
Test name
Test status
Simulation time 204438023 ps
CPU time 0.91 seconds
Started Jul 06 05:22:47 PM PDT 24
Finished Jul 06 05:22:48 PM PDT 24
Peak memory 206120 kb
Host smart-17180909-c332-42e7-a353-c1fba3817990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13090
33040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1309033040
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1822134939
Short name T1133
Test name
Test status
Simulation time 3918988926 ps
CPU time 102.97 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:24:35 PM PDT 24
Peak memory 206412 kb
Host smart-c6558d73-336b-4655-b0e3-306214ba5a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18221
34939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1822134939
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3430081959
Short name T1195
Test name
Test status
Simulation time 3241038588 ps
CPU time 24.03 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:23:16 PM PDT 24
Peak memory 206452 kb
Host smart-5a4f5acd-e6c6-4b12-8385-47b7050a3304
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3430081959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3430081959
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.4224829159
Short name T1151
Test name
Test status
Simulation time 173898141 ps
CPU time 0.81 seconds
Started Jul 06 05:22:47 PM PDT 24
Finished Jul 06 05:22:49 PM PDT 24
Peak memory 206176 kb
Host smart-3c717d1d-239a-4e51-9b22-65361e138643
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4224829159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.4224829159
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3075337114
Short name T2050
Test name
Test status
Simulation time 160562525 ps
CPU time 0.79 seconds
Started Jul 06 05:22:50 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 206148 kb
Host smart-d285cc0a-d145-46e5-b44d-fcb1aa498f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
37114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3075337114
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2463025665
Short name T443
Test name
Test status
Simulation time 205534754 ps
CPU time 0.83 seconds
Started Jul 06 05:22:47 PM PDT 24
Finished Jul 06 05:22:48 PM PDT 24
Peak memory 206436 kb
Host smart-e6be7b92-5293-44d7-968c-c947b89124a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24630
25665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2463025665
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1692232324
Short name T411
Test name
Test status
Simulation time 196213664 ps
CPU time 0.83 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:22:50 PM PDT 24
Peak memory 206204 kb
Host smart-f18abcdb-b81e-481e-8a7a-cca8f2d09777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16922
32324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1692232324
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2535358733
Short name T1076
Test name
Test status
Simulation time 187912613 ps
CPU time 0.8 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:22:50 PM PDT 24
Peak memory 206168 kb
Host smart-f16c4eef-c00d-4e89-a39a-ec6ab6102d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
58733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2535358733
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1101952490
Short name T176
Test name
Test status
Simulation time 150771009 ps
CPU time 0.79 seconds
Started Jul 06 05:22:50 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 206164 kb
Host smart-bfef3fac-79e1-4073-a888-fe28022b3636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019
52490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1101952490
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.404997271
Short name T150
Test name
Test status
Simulation time 207027999 ps
CPU time 0.98 seconds
Started Jul 06 05:22:51 PM PDT 24
Finished Jul 06 05:22:53 PM PDT 24
Peak memory 206204 kb
Host smart-f4d56f5f-d665-45da-9534-9e6a0c6010fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40499
7271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.404997271
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2390098139
Short name T1265
Test name
Test status
Simulation time 145128773 ps
CPU time 0.84 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:22:53 PM PDT 24
Peak memory 206176 kb
Host smart-bcac2963-e87a-4e08-a57f-c5ec8ae645dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900
98139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2390098139
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2070203246
Short name T1826
Test name
Test status
Simulation time 36259640 ps
CPU time 0.65 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206184 kb
Host smart-50baa781-d06b-403c-9749-24aa007f8fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
03246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2070203246
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.352337100
Short name T2531
Test name
Test status
Simulation time 183577034 ps
CPU time 0.91 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:22:50 PM PDT 24
Peak memory 206200 kb
Host smart-dfa3a524-7ff3-49a6-a5df-7cca06fdf3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.352337100
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1498399905
Short name T1427
Test name
Test status
Simulation time 229640803 ps
CPU time 0.94 seconds
Started Jul 06 05:22:50 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 206200 kb
Host smart-5fe01ed5-2cb2-4324-a172-319fcb4272de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14983
99905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1498399905
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1561765891
Short name T167
Test name
Test status
Simulation time 10306666285 ps
CPU time 283.64 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206520 kb
Host smart-b6d02b44-a2de-4831-9c31-d3db4d6aae5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1561765891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1561765891
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.4228318549
Short name T2654
Test name
Test status
Simulation time 7282130331 ps
CPU time 38.29 seconds
Started Jul 06 05:22:50 PM PDT 24
Finished Jul 06 05:23:28 PM PDT 24
Peak memory 206380 kb
Host smart-e9ffb96b-78cc-435a-bf5b-6213fee7d841
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4228318549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.4228318549
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2651842395
Short name T1399
Test name
Test status
Simulation time 12675197758 ps
CPU time 249.49 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:27:07 PM PDT 24
Peak memory 206320 kb
Host smart-d98ac4a7-eab8-4e5f-81c2-7d5fa7b3f7fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2651842395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2651842395
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2104073087
Short name T575
Test name
Test status
Simulation time 286082798 ps
CPU time 1.01 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206204 kb
Host smart-d71f9b0f-2892-48fc-af55-46dd5ce72fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21040
73087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2104073087
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.653853203
Short name T1028
Test name
Test status
Simulation time 166424210 ps
CPU time 0.84 seconds
Started Jul 06 05:22:46 PM PDT 24
Finished Jul 06 05:22:47 PM PDT 24
Peak memory 206160 kb
Host smart-d229785e-e15d-4019-8fed-b21365e79896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65385
3203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.653853203
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3744361242
Short name T972
Test name
Test status
Simulation time 180969729 ps
CPU time 0.79 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206192 kb
Host smart-36e26cf5-faaa-458e-a5a6-ed1904b0c636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37443
61242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3744361242
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2647670823
Short name T81
Test name
Test status
Simulation time 167313832 ps
CPU time 0.81 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:22:54 PM PDT 24
Peak memory 206200 kb
Host smart-ada4d9c6-15ab-4703-9aa7-91433913ba0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
70823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2647670823
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.715523119
Short name T208
Test name
Test status
Simulation time 693864540 ps
CPU time 1.66 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 225076 kb
Host smart-104abb5c-e402-4dfd-bbdd-52d258a00592
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=715523119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.715523119
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1779432259
Short name T61
Test name
Test status
Simulation time 420976121 ps
CPU time 1.27 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206188 kb
Host smart-41be7f97-af61-4cbd-b4a7-f21c086d8c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17794
32259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1779432259
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3789366309
Short name T1414
Test name
Test status
Simulation time 180424714 ps
CPU time 0.92 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:58 PM PDT 24
Peak memory 205976 kb
Host smart-bd75bcc3-3003-4a90-83df-edaff3eac87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37893
66309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3789366309
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3801461171
Short name T2010
Test name
Test status
Simulation time 184143170 ps
CPU time 0.85 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:22:50 PM PDT 24
Peak memory 206160 kb
Host smart-9edf6b7a-33bf-4c8f-a3f3-c2f1d7ca6c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38014
61171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3801461171
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2009605842
Short name T2
Test name
Test status
Simulation time 153781199 ps
CPU time 0.73 seconds
Started Jul 06 05:22:48 PM PDT 24
Finished Jul 06 05:22:49 PM PDT 24
Peak memory 206436 kb
Host smart-321557e3-cfe3-49d3-9d3f-41641f38fd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20096
05842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2009605842
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.397314367
Short name T669
Test name
Test status
Simulation time 206758555 ps
CPU time 0.9 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:58 PM PDT 24
Peak memory 206208 kb
Host smart-09191753-b9d4-4274-9eed-bb66f2992b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39731
4367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.397314367
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.4059417358
Short name T1480
Test name
Test status
Simulation time 3203054707 ps
CPU time 28.78 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:23:21 PM PDT 24
Peak memory 206520 kb
Host smart-7c09e214-27e6-425d-8921-c48ca75ebf41
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4059417358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4059417358
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2717568668
Short name T527
Test name
Test status
Simulation time 205225075 ps
CPU time 0.97 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:22:54 PM PDT 24
Peak memory 206156 kb
Host smart-0a8160ab-7c2c-413e-9e35-c1633566f936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27175
68668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2717568668
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.641294011
Short name T2285
Test name
Test status
Simulation time 170042074 ps
CPU time 0.79 seconds
Started Jul 06 05:22:51 PM PDT 24
Finished Jul 06 05:22:52 PM PDT 24
Peak memory 206204 kb
Host smart-7b6ec9fb-3d53-4b1d-8b57-cf00c7399a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64129
4011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.641294011
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2323110868
Short name T326
Test name
Test status
Simulation time 374407259 ps
CPU time 1.13 seconds
Started Jul 06 05:22:49 PM PDT 24
Finished Jul 06 05:22:50 PM PDT 24
Peak memory 206192 kb
Host smart-577353a1-f2db-4e10-8f45-33573f352730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
10868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2323110868
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1724803706
Short name T2378
Test name
Test status
Simulation time 6728310222 ps
CPU time 179.63 seconds
Started Jul 06 05:22:48 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206448 kb
Host smart-50e37845-a074-48bf-b82b-058e7c4996c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
03706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1724803706
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3577901155
Short name T801
Test name
Test status
Simulation time 39402212 ps
CPU time 0.67 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:59 PM PDT 24
Peak memory 206100 kb
Host smart-eca4d57c-1f55-45b2-8af6-eb737a7166ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3577901155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3577901155
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3867169896
Short name T1006
Test name
Test status
Simulation time 3593390040 ps
CPU time 4.09 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:31 PM PDT 24
Peak memory 206248 kb
Host smart-80daf646-b312-4181-bb49-91deea848e7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3867169896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3867169896
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.289827264
Short name T2043
Test name
Test status
Simulation time 13323042540 ps
CPU time 12.69 seconds
Started Jul 06 05:25:32 PM PDT 24
Finished Jul 06 05:25:45 PM PDT 24
Peak memory 206540 kb
Host smart-bdc94161-b062-45fc-892b-8d3f79c3c4e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=289827264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.289827264
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1347799201
Short name T679
Test name
Test status
Simulation time 23521440625 ps
CPU time 30.21 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206384 kb
Host smart-d7180bf3-4aec-46cc-acc0-b89d80414dc1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1347799201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1347799201
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1043181540
Short name T2265
Test name
Test status
Simulation time 184195911 ps
CPU time 0.89 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206192 kb
Host smart-c70008d0-9218-4517-9e59-190bca2cbef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
81540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1043181540
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.19692138
Short name T2473
Test name
Test status
Simulation time 152039221 ps
CPU time 0.83 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:25:38 PM PDT 24
Peak memory 206204 kb
Host smart-d7211091-8054-40b0-95fa-610d6aa3da91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19692
138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.19692138
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.4085836629
Short name T174
Test name
Test status
Simulation time 532164580 ps
CPU time 1.54 seconds
Started Jul 06 05:25:24 PM PDT 24
Finished Jul 06 05:25:26 PM PDT 24
Peak memory 206384 kb
Host smart-92e75c55-17b1-4dc2-a29b-bc236e7d0860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40858
36629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.4085836629
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.781728203
Short name T194
Test name
Test status
Simulation time 1376262081 ps
CPU time 3.21 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206492 kb
Host smart-b9903225-4dc6-45bd-9118-94be0bf937db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78172
8203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.781728203
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3480462116
Short name T1041
Test name
Test status
Simulation time 22581630695 ps
CPU time 44.13 seconds
Started Jul 06 05:25:29 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206376 kb
Host smart-cc5dc963-65e1-434a-bc6d-4f597ed15bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34804
62116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3480462116
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1591298884
Short name T602
Test name
Test status
Simulation time 463822417 ps
CPU time 1.38 seconds
Started Jul 06 05:25:28 PM PDT 24
Finished Jul 06 05:25:30 PM PDT 24
Peak memory 206140 kb
Host smart-23f4a6f8-58ef-4b14-acc2-adabc155bc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15912
98884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1591298884
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.4150790085
Short name T1563
Test name
Test status
Simulation time 139439300 ps
CPU time 0.75 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:28 PM PDT 24
Peak memory 206196 kb
Host smart-c35e4dee-de55-4b2b-bfd9-bf281c9147d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41507
90085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.4150790085
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1441618962
Short name T256
Test name
Test status
Simulation time 49789091 ps
CPU time 0.7 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:27 PM PDT 24
Peak memory 206184 kb
Host smart-f58acd03-4d82-4350-8166-0f7e4dc03a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14416
18962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1441618962
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.662492372
Short name T1
Test name
Test status
Simulation time 909458545 ps
CPU time 2.11 seconds
Started Jul 06 05:25:26 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206344 kb
Host smart-5ba88367-9a40-4b58-ab31-4ba00b0d5d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66249
2372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.662492372
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1572844931
Short name T2161
Test name
Test status
Simulation time 181842360 ps
CPU time 1.75 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:30 PM PDT 24
Peak memory 206356 kb
Host smart-aa4c6819-ce5b-46e7-99c3-cd034f0f347a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15728
44931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1572844931
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3308160891
Short name T382
Test name
Test status
Simulation time 277925824 ps
CPU time 1.06 seconds
Started Jul 06 05:25:32 PM PDT 24
Finished Jul 06 05:25:33 PM PDT 24
Peak memory 206128 kb
Host smart-f3a73e3d-81b2-4f0d-8dc3-8a0c99dbe1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33081
60891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3308160891
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2597471044
Short name T1174
Test name
Test status
Simulation time 162335697 ps
CPU time 0.77 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:28 PM PDT 24
Peak memory 206176 kb
Host smart-346fdcd8-8921-4c01-861c-50720885e7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
71044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2597471044
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1975176680
Short name T1844
Test name
Test status
Simulation time 180445466 ps
CPU time 0.95 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:29 PM PDT 24
Peak memory 206124 kb
Host smart-40dd6f7a-8406-4f2a-8279-d923a1bfe268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
76680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1975176680
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3566564040
Short name T1479
Test name
Test status
Simulation time 218232054 ps
CPU time 0.96 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:28 PM PDT 24
Peak memory 206184 kb
Host smart-4ca408ff-0968-498d-8555-ed6b871b823a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35665
64040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3566564040
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.571039684
Short name T2575
Test name
Test status
Simulation time 23290995845 ps
CPU time 22.64 seconds
Started Jul 06 05:25:27 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206248 kb
Host smart-63678d7c-2fae-4660-b7a6-bc4a50d3d004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57103
9684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.571039684
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2510692081
Short name T467
Test name
Test status
Simulation time 3303479133 ps
CPU time 3.77 seconds
Started Jul 06 05:25:33 PM PDT 24
Finished Jul 06 05:25:37 PM PDT 24
Peak memory 206240 kb
Host smart-f7c8712d-2ace-445a-8dec-0107091d7947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106
92081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2510692081
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.457106840
Short name T508
Test name
Test status
Simulation time 10393677225 ps
CPU time 94.77 seconds
Started Jul 06 05:25:28 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206456 kb
Host smart-4c256720-6f5b-41be-857c-6cfc6bbafca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45710
6840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.457106840
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2624002795
Short name T685
Test name
Test status
Simulation time 6293795243 ps
CPU time 58.21 seconds
Started Jul 06 05:25:32 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206436 kb
Host smart-09e8abd9-849d-4ab6-bc16-d70d2b6764e3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2624002795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2624002795
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2725976553
Short name T1854
Test name
Test status
Simulation time 267197742 ps
CPU time 1.02 seconds
Started Jul 06 05:25:32 PM PDT 24
Finished Jul 06 05:25:33 PM PDT 24
Peak memory 206184 kb
Host smart-ed314792-e846-4ac5-a03d-37ef370f1097
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2725976553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2725976553
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.436196499
Short name T347
Test name
Test status
Simulation time 191084727 ps
CPU time 0.89 seconds
Started Jul 06 05:25:33 PM PDT 24
Finished Jul 06 05:25:34 PM PDT 24
Peak memory 206148 kb
Host smart-5341d05e-a394-4131-9cc6-db8263912fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43619
6499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.436196499
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.2600010718
Short name T1943
Test name
Test status
Simulation time 3531644408 ps
CPU time 24.94 seconds
Started Jul 06 05:25:41 PM PDT 24
Finished Jul 06 05:26:06 PM PDT 24
Peak memory 206464 kb
Host smart-a6b23a45-f15f-4877-ad4b-081681d6b0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26000
10718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.2600010718
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.933190236
Short name T378
Test name
Test status
Simulation time 4281952531 ps
CPU time 30.91 seconds
Started Jul 06 05:25:31 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206432 kb
Host smart-1f0ba214-168a-4651-9b02-79129763ab76
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=933190236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.933190236
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3865649715
Short name T2653
Test name
Test status
Simulation time 155949732 ps
CPU time 0.77 seconds
Started Jul 06 05:25:30 PM PDT 24
Finished Jul 06 05:25:31 PM PDT 24
Peak memory 206200 kb
Host smart-8034b550-b0dc-44b7-ba10-6d470a3a6e91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3865649715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3865649715
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.321846187
Short name T544
Test name
Test status
Simulation time 151253273 ps
CPU time 0.8 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206156 kb
Host smart-5e82429a-f333-4562-99cd-897975707e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32184
6187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.321846187
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3907768552
Short name T134
Test name
Test status
Simulation time 273376595 ps
CPU time 0.94 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:25:52 PM PDT 24
Peak memory 206176 kb
Host smart-8f52a5f8-e1c0-4c28-9128-45cb2354be11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39077
68552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3907768552
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3249804978
Short name T642
Test name
Test status
Simulation time 152883719 ps
CPU time 0.82 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206176 kb
Host smart-3dd4a7bd-fe97-45d9-8f53-8733e5420c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498
04978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3249804978
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2123851786
Short name T1964
Test name
Test status
Simulation time 155786963 ps
CPU time 0.78 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206176 kb
Host smart-af875946-208f-4c24-a560-5afd5635399d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
51786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2123851786
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2318824504
Short name T600
Test name
Test status
Simulation time 192685144 ps
CPU time 0.82 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 206180 kb
Host smart-fa1cd2bd-a326-41d6-8717-9667560c1d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23188
24504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2318824504
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3025243088
Short name T22
Test name
Test status
Simulation time 154453532 ps
CPU time 0.83 seconds
Started Jul 06 05:25:31 PM PDT 24
Finished Jul 06 05:25:32 PM PDT 24
Peak memory 206180 kb
Host smart-eb574d26-ba81-4f8f-84f2-b3aebce5275d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30252
43088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3025243088
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.436384781
Short name T2015
Test name
Test status
Simulation time 209263540 ps
CPU time 0.94 seconds
Started Jul 06 05:25:31 PM PDT 24
Finished Jul 06 05:25:32 PM PDT 24
Peak memory 206204 kb
Host smart-c9a8165e-3779-432d-925d-4902968ff2e7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=436384781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.436384781
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.242662732
Short name T1471
Test name
Test status
Simulation time 145332809 ps
CPU time 0.77 seconds
Started Jul 06 05:25:56 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206112 kb
Host smart-37897d11-703b-4fbf-b071-f55bc9e36dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
2732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.242662732
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.808286826
Short name T1194
Test name
Test status
Simulation time 29476730 ps
CPU time 0.65 seconds
Started Jul 06 05:25:36 PM PDT 24
Finished Jul 06 05:25:37 PM PDT 24
Peak memory 206172 kb
Host smart-e4432b67-87f0-45ed-ab3b-489476525e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80828
6826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.808286826
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1863725190
Short name T1567
Test name
Test status
Simulation time 18601832180 ps
CPU time 43.03 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206508 kb
Host smart-42702c1e-9a77-47bd-b3bb-da14c8f10843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18637
25190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1863725190
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3254163271
Short name T1807
Test name
Test status
Simulation time 161168054 ps
CPU time 0.83 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206084 kb
Host smart-c6a42cfe-40e4-4ad9-8ac8-d001c1c3624a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32541
63271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3254163271
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1595542173
Short name T2353
Test name
Test status
Simulation time 263566438 ps
CPU time 0.9 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206200 kb
Host smart-c7e25178-63f0-4b64-87c5-fc0018fc057c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15955
42173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1595542173
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.867792660
Short name T1477
Test name
Test status
Simulation time 273400593 ps
CPU time 0.94 seconds
Started Jul 06 05:25:38 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206116 kb
Host smart-ddd971b4-0008-46cd-9c53-c75c318ad539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86779
2660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.867792660
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.492768587
Short name T479
Test name
Test status
Simulation time 185768769 ps
CPU time 0.89 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 206204 kb
Host smart-1da4e0a8-5650-436d-bbfc-005d595242e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49276
8587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.492768587
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.4232046725
Short name T639
Test name
Test status
Simulation time 142940229 ps
CPU time 0.73 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:41 PM PDT 24
Peak memory 206208 kb
Host smart-e15d913a-cdc5-4fdf-809a-a5851165d113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
46725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.4232046725
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2980689227
Short name T2277
Test name
Test status
Simulation time 188450546 ps
CPU time 0.85 seconds
Started Jul 06 05:25:56 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206164 kb
Host smart-0ab8ad4a-1dc3-4353-a045-e6f0ee9118aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
89227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2980689227
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.781769693
Short name T369
Test name
Test status
Simulation time 159942605 ps
CPU time 0.78 seconds
Started Jul 06 05:25:44 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206132 kb
Host smart-f98c469b-4084-4c48-a1e5-745365c2b63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78176
9693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.781769693
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.4012148755
Short name T1802
Test name
Test status
Simulation time 206185367 ps
CPU time 0.95 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206124 kb
Host smart-b4bef344-519c-4983-ace8-cdc1fb822bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
48755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4012148755
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3065288825
Short name T1653
Test name
Test status
Simulation time 6177767095 ps
CPU time 44.93 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:26:41 PM PDT 24
Peak memory 206496 kb
Host smart-75aca695-8346-4ac8-93b4-9f1c11490cbb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3065288825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3065288825
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.9366805
Short name T1487
Test name
Test status
Simulation time 183853844 ps
CPU time 0.84 seconds
Started Jul 06 05:25:38 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206204 kb
Host smart-b65093da-9fea-430b-89e4-1183f21c1ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93668
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.9366805
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2898179889
Short name T2157
Test name
Test status
Simulation time 202809815 ps
CPU time 0.88 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:25:38 PM PDT 24
Peak memory 206204 kb
Host smart-717f206f-0cc1-4a01-b750-c3b4cbbb2000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981
79889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2898179889
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2826507393
Short name T1899
Test name
Test status
Simulation time 1028957788 ps
CPU time 2.24 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 206460 kb
Host smart-5247ba99-ddee-4b87-a395-21739112da63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28265
07393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2826507393
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2915982172
Short name T1155
Test name
Test status
Simulation time 4674561912 ps
CPU time 42.95 seconds
Started Jul 06 05:25:40 PM PDT 24
Finished Jul 06 05:26:24 PM PDT 24
Peak memory 206512 kb
Host smart-e24bf990-c0db-4503-b233-b2e97921921d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29159
82172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2915982172
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.385356050
Short name T606
Test name
Test status
Simulation time 57351728 ps
CPU time 0.71 seconds
Started Jul 06 05:25:44 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206172 kb
Host smart-00359220-8e53-417c-95a3-dcc262b97e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=385356050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.385356050
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2155385057
Short name T2355
Test name
Test status
Simulation time 3881595964 ps
CPU time 4.49 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206452 kb
Host smart-f047d22d-63c2-41e5-a80a-da5f0f21c11a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2155385057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2155385057
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1490343484
Short name T2545
Test name
Test status
Simulation time 13287209298 ps
CPU time 13.08 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206272 kb
Host smart-4fd7d99a-63e8-456f-8fbb-93c018500716
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1490343484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1490343484
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.404071086
Short name T836
Test name
Test status
Simulation time 23350912035 ps
CPU time 24.48 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:26:12 PM PDT 24
Peak memory 206464 kb
Host smart-aec282f5-0311-4471-b21c-24822e95aac1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=404071086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.404071086
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.4222816395
Short name T2301
Test name
Test status
Simulation time 155859282 ps
CPU time 0.84 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206172 kb
Host smart-892d377c-302a-47a9-8b36-6b43de761568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
16395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.4222816395
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.8853901
Short name T895
Test name
Test status
Simulation time 146367373 ps
CPU time 0.82 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:25:38 PM PDT 24
Peak memory 206172 kb
Host smart-43319b8d-bd4d-4386-bcad-a05c544663cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88539
01 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.8853901
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1572284001
Short name T786
Test name
Test status
Simulation time 366772044 ps
CPU time 1.27 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:55 PM PDT 24
Peak memory 206168 kb
Host smart-b078b356-e330-43e8-8d30-6c160f56939a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15722
84001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1572284001
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3104920846
Short name T1181
Test name
Test status
Simulation time 1095267536 ps
CPU time 2.75 seconds
Started Jul 06 05:25:41 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206396 kb
Host smart-70705ae4-7f3b-4d9d-a118-1dbe41b596c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31049
20846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3104920846
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3486458337
Short name T2237
Test name
Test status
Simulation time 6416583668 ps
CPU time 12.35 seconds
Started Jul 06 05:25:40 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206532 kb
Host smart-c1c50ce8-cb8e-4d6a-8398-863af5bde040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34864
58337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3486458337
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1088599976
Short name T1162
Test name
Test status
Simulation time 348224706 ps
CPU time 1.16 seconds
Started Jul 06 05:25:41 PM PDT 24
Finished Jul 06 05:25:42 PM PDT 24
Peak memory 206096 kb
Host smart-da3a54b2-e612-49db-bd32-cfff176a242d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885
99976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1088599976
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2054336188
Short name T741
Test name
Test status
Simulation time 150133225 ps
CPU time 0.75 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206204 kb
Host smart-0d3d6b79-d3b3-420c-ba1b-3f5d5a064a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20543
36188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2054336188
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3113258567
Short name T1648
Test name
Test status
Simulation time 65780096 ps
CPU time 0.69 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206176 kb
Host smart-e269d00b-2d62-4963-b3f3-31766fdb42fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
58567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3113258567
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3553307821
Short name T2599
Test name
Test status
Simulation time 928875419 ps
CPU time 1.99 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206240 kb
Host smart-d7e09500-b05a-4f7e-bb8e-b0340e2447ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35533
07821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3553307821
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1419104153
Short name T2206
Test name
Test status
Simulation time 147459341 ps
CPU time 1.17 seconds
Started Jul 06 05:25:41 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206308 kb
Host smart-ddf30f89-798b-47a5-a7cd-a070e5e46527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191
04153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1419104153
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.4009177076
Short name T1581
Test name
Test status
Simulation time 206860109 ps
CPU time 0.87 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:25:38 PM PDT 24
Peak memory 206156 kb
Host smart-b4038f8a-3df0-462e-8213-88ed06689c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
77076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.4009177076
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1235630301
Short name T2221
Test name
Test status
Simulation time 142091621 ps
CPU time 0.75 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206172 kb
Host smart-53f8b461-d722-4656-88bb-cfe8895a2478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12356
30301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1235630301
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.515862453
Short name T1999
Test name
Test status
Simulation time 186460819 ps
CPU time 0.83 seconds
Started Jul 06 05:25:38 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206200 kb
Host smart-cf049357-ff7f-447d-8d8d-6fe685bab394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51586
2453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.515862453
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.4174976396
Short name T2145
Test name
Test status
Simulation time 7579505080 ps
CPU time 209.68 seconds
Started Jul 06 05:25:46 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 206448 kb
Host smart-871d6c14-0291-4796-9491-eed89898077e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4174976396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.4174976396
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.970957401
Short name T1274
Test name
Test status
Simulation time 167691134 ps
CPU time 0.82 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206120 kb
Host smart-ab7aaf66-b94d-44b6-862d-70305b7ce0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97095
7401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.970957401
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3278301335
Short name T1980
Test name
Test status
Simulation time 23294805658 ps
CPU time 22.55 seconds
Started Jul 06 05:25:37 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206268 kb
Host smart-9474e233-d88e-4387-b2d1-cdbc66e4bf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32783
01335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3278301335
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2097022592
Short name T2537
Test name
Test status
Simulation time 3343534835 ps
CPU time 3.77 seconds
Started Jul 06 05:25:49 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206236 kb
Host smart-d047b34e-9e2d-4b70-bcac-f7ee2a37ef51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20970
22592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2097022592
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.794796370
Short name T2627
Test name
Test status
Simulation time 6719513062 ps
CPU time 47.24 seconds
Started Jul 06 05:25:40 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206492 kb
Host smart-04e28048-6112-456a-b349-ba629542ec8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79479
6370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.794796370
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4222524210
Short name T1442
Test name
Test status
Simulation time 5446056701 ps
CPU time 147.72 seconds
Started Jul 06 05:25:43 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206416 kb
Host smart-2317952c-b5ed-4aee-9afe-ab9777efb921
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4222524210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4222524210
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3649068883
Short name T1074
Test name
Test status
Simulation time 241554837 ps
CPU time 0.95 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206100 kb
Host smart-68437756-42a5-40ac-a874-84b786f4b20e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3649068883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3649068883
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.873504013
Short name T1645
Test name
Test status
Simulation time 209088355 ps
CPU time 0.89 seconds
Started Jul 06 05:25:53 PM PDT 24
Finished Jul 06 05:25:55 PM PDT 24
Peak memory 206132 kb
Host smart-98a33cdd-e71b-4fa6-ad4b-46bd42995f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87350
4013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.873504013
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.4222540350
Short name T481
Test name
Test status
Simulation time 3827846822 ps
CPU time 104.09 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:27:24 PM PDT 24
Peak memory 206528 kb
Host smart-46b684f5-7bdb-488c-841a-2d40b2249a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42225
40350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.4222540350
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2469312789
Short name T1316
Test name
Test status
Simulation time 5084346543 ps
CPU time 139.87 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:28:19 PM PDT 24
Peak memory 206428 kb
Host smart-0dc14d67-c3b7-46f6-ae9b-ff1ca8e8d0c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2469312789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2469312789
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1790830388
Short name T892
Test name
Test status
Simulation time 153710578 ps
CPU time 0.78 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206204 kb
Host smart-58f257b6-de74-4bc6-b84f-0f70d767b0dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1790830388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1790830388
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1563708314
Short name T1928
Test name
Test status
Simulation time 149070820 ps
CPU time 0.75 seconds
Started Jul 06 05:25:38 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206184 kb
Host smart-0fbe54e2-ddbf-45af-8192-3f0aa668a8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15637
08314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1563708314
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2936026015
Short name T115
Test name
Test status
Simulation time 219171142 ps
CPU time 0.9 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206112 kb
Host smart-f81a4d3d-8c03-4cb2-beae-c13eed5da85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29360
26015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2936026015
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3905106322
Short name T2469
Test name
Test status
Simulation time 176793453 ps
CPU time 0.88 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206176 kb
Host smart-bb221f67-9287-4876-a67c-5b4d6c18079a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39051
06322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3905106322
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4126766319
Short name T1456
Test name
Test status
Simulation time 245061954 ps
CPU time 0.92 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206084 kb
Host smart-7cbe367f-a640-40a8-bbe1-51b2e522e246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41267
66319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4126766319
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3650478375
Short name T2118
Test name
Test status
Simulation time 165240221 ps
CPU time 0.77 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206204 kb
Host smart-f4c126bf-dae0-4ec5-bae8-51bb370c1d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504
78375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3650478375
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1998522320
Short name T1498
Test name
Test status
Simulation time 153896101 ps
CPU time 0.84 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:59 PM PDT 24
Peak memory 206160 kb
Host smart-075a8ee6-3622-4889-b0a4-71665f4dce3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19985
22320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1998522320
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2398372088
Short name T2394
Test name
Test status
Simulation time 188720277 ps
CPU time 0.87 seconds
Started Jul 06 05:25:43 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206132 kb
Host smart-377ee073-7a49-4b8b-bfe3-2154f5b72e18
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2398372088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2398372088
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1847983565
Short name T1872
Test name
Test status
Simulation time 161889146 ps
CPU time 0.82 seconds
Started Jul 06 05:25:43 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206180 kb
Host smart-7ecb9eaa-b2af-400c-8cec-2836f2649ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18479
83565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1847983565
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3813092273
Short name T665
Test name
Test status
Simulation time 33759556 ps
CPU time 0.66 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:25:59 PM PDT 24
Peak memory 206200 kb
Host smart-000ab603-ee18-4659-add8-2f46af27f26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38130
92273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3813092273
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.627267665
Short name T1784
Test name
Test status
Simulation time 10641292587 ps
CPU time 24.15 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:26:13 PM PDT 24
Peak memory 206568 kb
Host smart-93b7d2ff-fc7a-4961-b7a4-45e70a10c128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62726
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.627267665
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2760096615
Short name T2116
Test name
Test status
Simulation time 221022095 ps
CPU time 0.91 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206156 kb
Host smart-b5d10ce6-20cb-4658-b137-fea6f237cef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
96615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2760096615
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1407425105
Short name T1216
Test name
Test status
Simulation time 161426003 ps
CPU time 0.79 seconds
Started Jul 06 05:25:43 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206148 kb
Host smart-d4c6e048-dcca-442b-a3a1-8a8b9a92bd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
25105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1407425105
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1222495768
Short name T2312
Test name
Test status
Simulation time 238151913 ps
CPU time 0.86 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206120 kb
Host smart-0f4588cd-f986-4d2e-a5b1-d35a94a8f48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12224
95768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1222495768
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.711404463
Short name T1067
Test name
Test status
Simulation time 203186138 ps
CPU time 0.87 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206040 kb
Host smart-7208d219-a615-4f6a-8941-f84fd3a7419b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71140
4463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.711404463
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2351205255
Short name T52
Test name
Test status
Simulation time 191039907 ps
CPU time 0.84 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206204 kb
Host smart-4c259d4d-6725-4790-b4ee-e581747e8cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
05255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2351205255
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.929982765
Short name T1883
Test name
Test status
Simulation time 169182560 ps
CPU time 0.81 seconds
Started Jul 06 05:26:00 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206208 kb
Host smart-5f51fee3-6f17-47f8-b85f-f001e4d8148b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92998
2765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.929982765
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2959594113
Short name T551
Test name
Test status
Simulation time 211323863 ps
CPU time 0.82 seconds
Started Jul 06 05:25:41 PM PDT 24
Finished Jul 06 05:25:42 PM PDT 24
Peak memory 206192 kb
Host smart-8a0cceb7-1791-4197-bc96-cd29b05cfe2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
94113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2959594113
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.415068887
Short name T2372
Test name
Test status
Simulation time 221929845 ps
CPU time 1.01 seconds
Started Jul 06 05:25:41 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206164 kb
Host smart-2a4c3bb0-daed-4f62-8720-52a214c80b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
8887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.415068887
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.982546594
Short name T1785
Test name
Test status
Simulation time 4760204767 ps
CPU time 129.91 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206520 kb
Host smart-f35a51d4-ba8e-4079-bcbb-69f755f3a87b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=982546594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.982546594
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3789623253
Short name T736
Test name
Test status
Simulation time 244456560 ps
CPU time 0.87 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:57 PM PDT 24
Peak memory 206212 kb
Host smart-b29a9c86-fdb9-460e-bb07-5d41a443e530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37896
23253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3789623253
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3874027390
Short name T2168
Test name
Test status
Simulation time 162738866 ps
CPU time 0.8 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206180 kb
Host smart-2d5f072d-e4b9-43dd-9cd6-f10f441a7402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38740
27390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3874027390
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3627931391
Short name T1357
Test name
Test status
Simulation time 789027509 ps
CPU time 1.84 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:45 PM PDT 24
Peak memory 206452 kb
Host smart-e511b84b-3244-4a3d-924a-67e438ebbc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
31391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3627931391
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.4066985284
Short name T2544
Test name
Test status
Simulation time 5874654259 ps
CPU time 164.72 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206496 kb
Host smart-61f4190d-6a00-4b2a-bc34-dedee5b50550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40669
85284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.4066985284
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.492363050
Short name T1697
Test name
Test status
Simulation time 50477187 ps
CPU time 0.74 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 206148 kb
Host smart-dcf26273-3d48-49fd-8a78-b0ad396c4542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=492363050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.492363050
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1823071703
Short name T2115
Test name
Test status
Simulation time 3672259373 ps
CPU time 5.06 seconds
Started Jul 06 05:25:44 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206464 kb
Host smart-f9d942f4-1375-4208-9176-21dc2d46e6f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1823071703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1823071703
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1449542229
Short name T1050
Test name
Test status
Simulation time 13402293238 ps
CPU time 13.92 seconds
Started Jul 06 05:25:40 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206456 kb
Host smart-448b6032-9373-40b0-8ade-d289a4f1a51e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1449542229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1449542229
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3026867873
Short name T901
Test name
Test status
Simulation time 23376671134 ps
CPU time 22.03 seconds
Started Jul 06 05:25:44 PM PDT 24
Finished Jul 06 05:26:07 PM PDT 24
Peak memory 206520 kb
Host smart-c336fb80-40ac-44f0-af0c-63f99563f206
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026867873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.3026867873
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1956642733
Short name T506
Test name
Test status
Simulation time 151401053 ps
CPU time 0.81 seconds
Started Jul 06 05:25:39 PM PDT 24
Finished Jul 06 05:25:40 PM PDT 24
Peak memory 206200 kb
Host smart-5a41ebee-91fe-421f-af9c-5355edd6ee03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19566
42733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1956642733
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2910971476
Short name T2074
Test name
Test status
Simulation time 137314696 ps
CPU time 0.75 seconds
Started Jul 06 05:25:43 PM PDT 24
Finished Jul 06 05:25:44 PM PDT 24
Peak memory 206200 kb
Host smart-e1703ea7-a70e-4db7-a963-7f8da7da5157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29109
71476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2910971476
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1541478552
Short name T2154
Test name
Test status
Simulation time 229135603 ps
CPU time 0.92 seconds
Started Jul 06 05:25:53 PM PDT 24
Finished Jul 06 05:25:55 PM PDT 24
Peak memory 206204 kb
Host smart-851ac498-64eb-43b8-b051-b7675eddcb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
78552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1541478552
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2741215686
Short name T1627
Test name
Test status
Simulation time 971467374 ps
CPU time 2.47 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 206380 kb
Host smart-d63ef639-b6ab-4083-a489-845c7c170fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27412
15686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2741215686
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1259148244
Short name T2412
Test name
Test status
Simulation time 11979204854 ps
CPU time 22.21 seconds
Started Jul 06 05:25:53 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206468 kb
Host smart-97569914-5a2e-412b-bf6d-13c80d8d7340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12591
48244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1259148244
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2052699178
Short name T1875
Test name
Test status
Simulation time 425395727 ps
CPU time 1.24 seconds
Started Jul 06 05:25:56 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206188 kb
Host smart-aa10b4b7-bdca-4048-8c0f-9d45e7fd6309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20526
99178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2052699178
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.480536269
Short name T2199
Test name
Test status
Simulation time 149468523 ps
CPU time 0.78 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206084 kb
Host smart-4410d7b9-3c3f-4270-bd9e-6241338d2498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48053
6269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.480536269
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3895904269
Short name T1895
Test name
Test status
Simulation time 34147336 ps
CPU time 0.65 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206176 kb
Host smart-6aa165a2-9afd-439b-a2c9-feee20bab757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38959
04269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3895904269
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.192722751
Short name T2294
Test name
Test status
Simulation time 883211587 ps
CPU time 2.13 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206404 kb
Host smart-93efcd77-9eb6-4ca0-9b2d-59b6427aa921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19272
2751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.192722751
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3861825873
Short name T2571
Test name
Test status
Simulation time 168295578 ps
CPU time 1.85 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206360 kb
Host smart-4b2bf9d0-780a-4712-a9d2-5bb685ee5728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38618
25873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3861825873
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.4194169610
Short name T876
Test name
Test status
Simulation time 240864833 ps
CPU time 0.94 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206128 kb
Host smart-795becba-b6e8-43d2-af6a-48d00d3f70e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41941
69610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.4194169610
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3828085809
Short name T1208
Test name
Test status
Simulation time 148367425 ps
CPU time 0.79 seconds
Started Jul 06 05:25:42 PM PDT 24
Finished Jul 06 05:25:43 PM PDT 24
Peak memory 206196 kb
Host smart-3897b84e-6bb3-4860-a167-5e856ea9adb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38280
85809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3828085809
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.5223938
Short name T1227
Test name
Test status
Simulation time 259652870 ps
CPU time 0.97 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206144 kb
Host smart-2e3f7b45-f2bf-4589-b362-26700fa9f1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52239
38 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.5223938
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2244614054
Short name T918
Test name
Test status
Simulation time 201812526 ps
CPU time 0.82 seconds
Started Jul 06 05:25:40 PM PDT 24
Finished Jul 06 05:25:41 PM PDT 24
Peak memory 206184 kb
Host smart-f171901a-fb73-46ef-ad57-3d1da870895f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
14054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2244614054
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.832071266
Short name T1524
Test name
Test status
Simulation time 23277266099 ps
CPU time 27.06 seconds
Started Jul 06 05:25:44 PM PDT 24
Finished Jul 06 05:26:12 PM PDT 24
Peak memory 206164 kb
Host smart-a3b98962-0eaa-496b-83cf-28c7c230b3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83207
1266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.832071266
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2498472261
Short name T536
Test name
Test status
Simulation time 3254316546 ps
CPU time 4.54 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206184 kb
Host smart-c395b409-0cb0-4b7f-b25f-6ae69f22b241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24984
72261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2498472261
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1932804571
Short name T1136
Test name
Test status
Simulation time 4046354273 ps
CPU time 28.6 seconds
Started Jul 06 05:25:43 PM PDT 24
Finished Jul 06 05:26:12 PM PDT 24
Peak memory 206372 kb
Host smart-7d1bb95d-ef3c-4d43-90f8-edcca27200ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1932804571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1932804571
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2136773836
Short name T2694
Test name
Test status
Simulation time 248289314 ps
CPU time 0.92 seconds
Started Jul 06 05:25:59 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206116 kb
Host smart-be658685-58b0-4021-ae81-8b6436f0fd31
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2136773836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2136773836
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2914345454
Short name T814
Test name
Test status
Simulation time 211506102 ps
CPU time 0.87 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206168 kb
Host smart-b3099400-0e45-41c8-8367-24b1d5d5cb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29143
45454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2914345454
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3047160704
Short name T982
Test name
Test status
Simulation time 3161743508 ps
CPU time 20.71 seconds
Started Jul 06 05:26:02 PM PDT 24
Finished Jul 06 05:26:23 PM PDT 24
Peak memory 206332 kb
Host smart-c71418f7-4945-40e5-9670-45c788f7672a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30471
60704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3047160704
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2109075983
Short name T2037
Test name
Test status
Simulation time 6788333203 ps
CPU time 62.9 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:27:01 PM PDT 24
Peak memory 206452 kb
Host smart-bc16b0d6-020a-42b0-8a10-06a78dee685e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2109075983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2109075983
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1254681767
Short name T2185
Test name
Test status
Simulation time 152609537 ps
CPU time 0.81 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206192 kb
Host smart-8d3e9a7b-03b0-4f8d-b26f-492da249e188
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254681767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1254681767
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.787088495
Short name T2424
Test name
Test status
Simulation time 140249803 ps
CPU time 0.8 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206132 kb
Host smart-aa987355-d148-42d9-80d7-9d97f9818d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78708
8495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.787088495
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3408444011
Short name T633
Test name
Test status
Simulation time 172911408 ps
CPU time 0.78 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206432 kb
Host smart-61c83225-d068-4451-b2a9-dcb3959bea4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
44011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3408444011
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1910086587
Short name T1256
Test name
Test status
Simulation time 192701205 ps
CPU time 0.85 seconds
Started Jul 06 05:25:46 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 206200 kb
Host smart-b3321124-8a40-4906-a109-e86aedfddfcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19100
86587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1910086587
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1628777917
Short name T938
Test name
Test status
Simulation time 178698149 ps
CPU time 0.83 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206172 kb
Host smart-3bc17648-2c9b-4be7-802c-d00a9ccb3d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287
77917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1628777917
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2780694002
Short name T1279
Test name
Test status
Simulation time 153428836 ps
CPU time 0.76 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206436 kb
Host smart-c70ae441-ddb7-463d-a69e-a35519d13df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27806
94002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2780694002
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.624394508
Short name T1378
Test name
Test status
Simulation time 224419707 ps
CPU time 0.94 seconds
Started Jul 06 05:25:56 PM PDT 24
Finished Jul 06 05:25:57 PM PDT 24
Peak memory 206180 kb
Host smart-433e09f2-82f4-437d-bf3e-405943be6ceb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=624394508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.624394508
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.453387603
Short name T206
Test name
Test status
Simulation time 142153344 ps
CPU time 0.8 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:25:52 PM PDT 24
Peak memory 206156 kb
Host smart-ba568c8f-f77e-4c90-aa64-a5256287b2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45338
7603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.453387603
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3541728449
Short name T27
Test name
Test status
Simulation time 38521634 ps
CPU time 0.67 seconds
Started Jul 06 05:26:03 PM PDT 24
Finished Jul 06 05:26:04 PM PDT 24
Peak memory 206004 kb
Host smart-3b44169d-4966-4a15-a97d-69dc5736294b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
28449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3541728449
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.914529023
Short name T268
Test name
Test status
Simulation time 13771550451 ps
CPU time 34.89 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206416 kb
Host smart-75e5e27a-e914-42e9-a720-9e4f15ed26cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91452
9023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.914529023
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.25753404
Short name T534
Test name
Test status
Simulation time 160082862 ps
CPU time 0.85 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 206184 kb
Host smart-d25fc291-e17d-4b3d-94d6-5bc30b646d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753
404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.25753404
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2804884790
Short name T1576
Test name
Test status
Simulation time 245409820 ps
CPU time 0.89 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206156 kb
Host smart-61926ef5-abc2-421d-a3df-69fe9dc5fdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28048
84790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2804884790
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.567499069
Short name T1548
Test name
Test status
Simulation time 229734081 ps
CPU time 0.87 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206172 kb
Host smart-512b4136-5e07-4e57-9f2d-95ef2c0c323e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56749
9069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.567499069
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2317498095
Short name T1588
Test name
Test status
Simulation time 179141244 ps
CPU time 0.86 seconds
Started Jul 06 05:25:46 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 206200 kb
Host smart-57b0c953-a6ee-4e1a-8b69-2bf97a03ec83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23174
98095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2317498095
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1667643836
Short name T896
Test name
Test status
Simulation time 158258945 ps
CPU time 0.8 seconds
Started Jul 06 05:25:46 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 206204 kb
Host smart-800ef04e-948b-4263-8038-400ce24139d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16676
43836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1667643836
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2475415110
Short name T2308
Test name
Test status
Simulation time 194310584 ps
CPU time 0.77 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206012 kb
Host smart-7dd2f140-ee7a-4cc4-8067-d7814874eea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
15110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2475415110
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2371114415
Short name T1768
Test name
Test status
Simulation time 152096315 ps
CPU time 0.77 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206012 kb
Host smart-a7ea8b01-95e4-4036-88b9-b343eba3e7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23711
14415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2371114415
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4157427944
Short name T1362
Test name
Test status
Simulation time 261131465 ps
CPU time 1.01 seconds
Started Jul 06 05:25:59 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206172 kb
Host smart-8720ee22-170c-4fac-8096-a98229f2fc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
27944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4157427944
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3992615437
Short name T1426
Test name
Test status
Simulation time 6104673768 ps
CPU time 56.27 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:26:45 PM PDT 24
Peak memory 206404 kb
Host smart-08b80675-c161-4b19-99d6-f1cc8377178d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3992615437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3992615437
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1029526034
Short name T2682
Test name
Test status
Simulation time 178623293 ps
CPU time 0.83 seconds
Started Jul 06 05:25:45 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 206172 kb
Host smart-dc7ead24-4315-403f-bbef-5dc699401a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10295
26034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1029526034
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2468941003
Short name T912
Test name
Test status
Simulation time 180246757 ps
CPU time 0.82 seconds
Started Jul 06 05:25:49 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206180 kb
Host smart-7fb23c65-9be5-4cfb-9872-21cfa53e8506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24689
41003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2468941003
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3300088804
Short name T2164
Test name
Test status
Simulation time 996948818 ps
CPU time 2.08 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206416 kb
Host smart-929f032c-c311-4dbe-bdc0-426491440e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
88804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3300088804
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3214767912
Short name T2374
Test name
Test status
Simulation time 5429201779 ps
CPU time 49.68 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206432 kb
Host smart-a4bc51ef-c050-4223-a8a8-1f2141e9e6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
67912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3214767912
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.666295427
Short name T2679
Test name
Test status
Simulation time 38614084 ps
CPU time 0.66 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206248 kb
Host smart-81a14d6f-a05a-41a1-9494-275af60af5cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=666295427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.666295427
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3096900609
Short name T2165
Test name
Test status
Simulation time 3776123651 ps
CPU time 4.61 seconds
Started Jul 06 05:25:46 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206268 kb
Host smart-52bd374e-fe59-4076-9437-7c0e3c36b3b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3096900609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3096900609
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.806002646
Short name T1492
Test name
Test status
Simulation time 13458532500 ps
CPU time 15.97 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206512 kb
Host smart-865f8c18-736b-4fdb-a428-97aa516d3137
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=806002646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.806002646
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1608120714
Short name T1643
Test name
Test status
Simulation time 23385945978 ps
CPU time 23.81 seconds
Started Jul 06 05:25:44 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206268 kb
Host smart-4b4a08b7-9f27-4025-a1cd-4d93f37d4b64
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1608120714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1608120714
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.60628719
Short name T987
Test name
Test status
Simulation time 165652141 ps
CPU time 0.82 seconds
Started Jul 06 05:25:56 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206204 kb
Host smart-206d9373-5512-4371-9990-270338451994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60628
719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.60628719
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2876682732
Short name T595
Test name
Test status
Simulation time 149343600 ps
CPU time 0.76 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:57 PM PDT 24
Peak memory 206176 kb
Host smart-0b7704b6-b2ab-4ebb-92e9-08000a475c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766
82732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2876682732
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2410088822
Short name T166
Test name
Test status
Simulation time 494588931 ps
CPU time 1.45 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206704 kb
Host smart-f50ebf0e-ff5a-492e-bdff-9bd1aa74582d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24100
88822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2410088822
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_device_address.3002552609
Short name T1529
Test name
Test status
Simulation time 12910705006 ps
CPU time 25.41 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206512 kb
Host smart-18c16fb9-ced0-49a0-9d96-76406b0fb9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30025
52609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3002552609
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2219667933
Short name T2305
Test name
Test status
Simulation time 302988508 ps
CPU time 1.12 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206172 kb
Host smart-6731e53d-8933-487f-a295-479fa9fbada9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22196
67933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2219667933
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1810809536
Short name T2256
Test name
Test status
Simulation time 135251164 ps
CPU time 0.78 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206184 kb
Host smart-57a1fee0-70eb-44cd-9cb0-4e6baf6da50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108
09536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1810809536
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1169990206
Short name T1667
Test name
Test status
Simulation time 34112167 ps
CPU time 0.64 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 205988 kb
Host smart-54e934dc-ecde-4f59-aadf-6b64516476e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11699
90206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1169990206
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4208889794
Short name T2552
Test name
Test status
Simulation time 813770242 ps
CPU time 2.01 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:10 PM PDT 24
Peak memory 206372 kb
Host smart-fe3fb835-cd2e-4845-902c-dbd051a3378d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42088
89794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4208889794
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3595220182
Short name T1756
Test name
Test status
Simulation time 228513779 ps
CPU time 1.58 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206360 kb
Host smart-ed75e4d8-67d0-4280-bfc6-d5c41f699e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35952
20182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3595220182
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1670319834
Short name T887
Test name
Test status
Simulation time 277278261 ps
CPU time 0.94 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 205996 kb
Host smart-f85dd883-d9b0-415e-a6c8-fb2607bd28d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16703
19834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1670319834
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.4141937948
Short name T2476
Test name
Test status
Simulation time 157602668 ps
CPU time 0.76 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206196 kb
Host smart-c6673015-de66-47a1-a0ea-6f5488e76557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
37948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.4141937948
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2077124198
Short name T2231
Test name
Test status
Simulation time 236838384 ps
CPU time 0.94 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206012 kb
Host smart-c4499a22-e5d2-48e6-9d24-6d2dcf907602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20771
24198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2077124198
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.517607345
Short name T2114
Test name
Test status
Simulation time 210573022 ps
CPU time 0.85 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206216 kb
Host smart-fd6e80a1-12f9-454e-b006-0efd1a03e03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51760
7345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.517607345
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2289604557
Short name T1612
Test name
Test status
Simulation time 23324135803 ps
CPU time 23.91 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206080 kb
Host smart-fcf023b8-68b8-47f1-9251-96bb384ce871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22896
04557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2289604557
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3400798542
Short name T1773
Test name
Test status
Simulation time 3271333254 ps
CPU time 4.29 seconds
Started Jul 06 05:25:46 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206264 kb
Host smart-de70a90d-3627-4fba-91fa-9e653fd52d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34007
98542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3400798542
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1998303836
Short name T1915
Test name
Test status
Simulation time 12697383354 ps
CPU time 359.99 seconds
Started Jul 06 05:25:47 PM PDT 24
Finished Jul 06 05:31:47 PM PDT 24
Peak memory 206524 kb
Host smart-417c024c-af98-466c-920c-574be6205511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983
03836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1998303836
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.330022565
Short name T769
Test name
Test status
Simulation time 6760906396 ps
CPU time 63.21 seconds
Started Jul 06 05:26:05 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206520 kb
Host smart-bbbd8dee-d859-43f5-9b24-91205a8870b5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=330022565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.330022565
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.421156204
Short name T1985
Test name
Test status
Simulation time 242235889 ps
CPU time 0.94 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206172 kb
Host smart-cae32f7d-2403-43ac-af60-e925b2debcdb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=421156204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.421156204
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3469874547
Short name T2549
Test name
Test status
Simulation time 186395612 ps
CPU time 0.89 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206176 kb
Host smart-6ef73569-027e-45b6-9963-057a2babd405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34698
74547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3469874547
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.4045240371
Short name T470
Test name
Test status
Simulation time 4863175883 ps
CPU time 46.42 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:26:40 PM PDT 24
Peak memory 206436 kb
Host smart-426c067c-e9d5-4eac-bda4-ec03767e63d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452
40371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.4045240371
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.4249993061
Short name T616
Test name
Test status
Simulation time 6880443161 ps
CPU time 52.43 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:26:44 PM PDT 24
Peak memory 206516 kb
Host smart-40207a59-3fb1-4059-be5b-52aa4b716e65
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4249993061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.4249993061
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2908955278
Short name T2325
Test name
Test status
Simulation time 158635064 ps
CPU time 0.78 seconds
Started Jul 06 05:26:03 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206180 kb
Host smart-ddc591a3-9c98-45bf-bbc3-767da51bd34b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2908955278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2908955278
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2264382486
Short name T619
Test name
Test status
Simulation time 142869073 ps
CPU time 0.73 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206184 kb
Host smart-b8475809-88c8-4f3f-81a4-5ff8cb1bbdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
82486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2264382486
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1653496720
Short name T2293
Test name
Test status
Simulation time 184690661 ps
CPU time 0.88 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206188 kb
Host smart-50d77a42-16b6-4952-9fbd-e65e27a0b633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
96720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1653496720
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1824287713
Short name T631
Test name
Test status
Simulation time 189435855 ps
CPU time 0.9 seconds
Started Jul 06 05:25:49 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206164 kb
Host smart-84cb2a85-c5e7-4380-9bda-02a59440e25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
87713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1824287713
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.979876447
Short name T465
Test name
Test status
Simulation time 165215949 ps
CPU time 0.78 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206112 kb
Host smart-570dd6d3-81dc-4941-a9eb-b537ef86b841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97987
6447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.979876447
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3217093315
Short name T2519
Test name
Test status
Simulation time 178075167 ps
CPU time 0.79 seconds
Started Jul 06 05:25:48 PM PDT 24
Finished Jul 06 05:25:49 PM PDT 24
Peak memory 206204 kb
Host smart-b1cba34c-8ddf-4d7b-96b8-1840478319a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32170
93315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3217093315
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2377906504
Short name T1664
Test name
Test status
Simulation time 172400932 ps
CPU time 0.83 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:25:52 PM PDT 24
Peak memory 206164 kb
Host smart-fc6a7836-eb84-4e73-aa9b-0bbc82e4a122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
06504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2377906504
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.681024039
Short name T2299
Test name
Test status
Simulation time 189281634 ps
CPU time 0.93 seconds
Started Jul 06 05:25:49 PM PDT 24
Finished Jul 06 05:25:50 PM PDT 24
Peak memory 206204 kb
Host smart-fbc57beb-6d5c-4215-93f8-2c6218ea60b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=681024039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.681024039
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3633340937
Short name T720
Test name
Test status
Simulation time 151736594 ps
CPU time 0.85 seconds
Started Jul 06 05:26:00 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206176 kb
Host smart-abcd139e-a570-43b4-95c1-75775681b631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36333
40937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3633340937
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2892851886
Short name T502
Test name
Test status
Simulation time 42896826 ps
CPU time 0.67 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206172 kb
Host smart-e5bafa47-9582-45b4-a8de-665d97e67552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28928
51886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2892851886
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.999603563
Short name T914
Test name
Test status
Simulation time 6657188980 ps
CPU time 14.46 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:26 PM PDT 24
Peak memory 206492 kb
Host smart-822fcec5-c79b-4e48-b2cb-258cd4763772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99960
3563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.999603563
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1374607019
Short name T1019
Test name
Test status
Simulation time 160238162 ps
CPU time 0.86 seconds
Started Jul 06 05:26:05 PM PDT 24
Finished Jul 06 05:26:06 PM PDT 24
Peak memory 206204 kb
Host smart-d3d18a29-f9c9-4c8c-9434-b735835bb11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
07019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1374607019
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2456120462
Short name T2642
Test name
Test status
Simulation time 165735568 ps
CPU time 0.79 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206160 kb
Host smart-fcff2d6f-47dc-4814-846e-601830bb962d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24561
20462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2456120462
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4090009074
Short name T362
Test name
Test status
Simulation time 197632743 ps
CPU time 0.91 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:25:55 PM PDT 24
Peak memory 206204 kb
Host smart-8905e513-7745-42b9-aa2a-9b95bcd29e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40900
09074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4090009074
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.570183916
Short name T321
Test name
Test status
Simulation time 190449524 ps
CPU time 0.85 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206164 kb
Host smart-5f16d8c7-aec1-49dc-a884-74d000175cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57018
3916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.570183916
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.468354400
Short name T1110
Test name
Test status
Simulation time 203374643 ps
CPU time 0.82 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206164 kb
Host smart-bbe63f55-56e4-4871-8807-b7789be58ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46835
4400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.468354400
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2231186503
Short name T2570
Test name
Test status
Simulation time 159438937 ps
CPU time 0.77 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206192 kb
Host smart-47b0bb34-e98c-4427-bb7b-08d755ef5d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
86503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2231186503
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3623847386
Short name T2577
Test name
Test status
Simulation time 182704593 ps
CPU time 0.81 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206124 kb
Host smart-97cfc91a-5436-4f83-9bf8-53144961e153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
47386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3623847386
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.30387655
Short name T323
Test name
Test status
Simulation time 215141780 ps
CPU time 0.93 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206152 kb
Host smart-b2889da3-867e-4e64-b18b-49e3bc383a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30387
655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.30387655
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3315355480
Short name T2334
Test name
Test status
Simulation time 3336950376 ps
CPU time 89.51 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:27:25 PM PDT 24
Peak memory 206516 kb
Host smart-aade0447-bb11-40d2-978e-d270a3e46b76
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3315355480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3315355480
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.669623701
Short name T1831
Test name
Test status
Simulation time 187937374 ps
CPU time 0.83 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206084 kb
Host smart-517349fa-054e-4c61-9c52-e9f768da3197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66962
3701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.669623701
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.468850049
Short name T2652
Test name
Test status
Simulation time 185330714 ps
CPU time 0.86 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206224 kb
Host smart-0985a16e-fca3-4026-9ac1-08fa0f696a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46885
0049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.468850049
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3324921809
Short name T1913
Test name
Test status
Simulation time 501486542 ps
CPU time 1.5 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:57 PM PDT 24
Peak memory 206200 kb
Host smart-d0575564-b5c0-4a58-a81d-ff2052cb2421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33249
21809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3324921809
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3800989107
Short name T1687
Test name
Test status
Simulation time 7263758334 ps
CPU time 52.04 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206512 kb
Host smart-7ebd0bd4-07cd-4ad0-a1f8-1b5373f88c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
89107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3800989107
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1798807265
Short name T2506
Test name
Test status
Simulation time 126082129 ps
CPU time 0.73 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206240 kb
Host smart-9445c751-406c-444e-9b31-a00330e4e3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1798807265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1798807265
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.9249583
Short name T1633
Test name
Test status
Simulation time 3669353626 ps
CPU time 5.18 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206240 kb
Host smart-137727a4-8392-4c09-a92f-9983f415abd5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=9249583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.9249583
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.858733527
Short name T2644
Test name
Test status
Simulation time 13375827141 ps
CPU time 13.75 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206512 kb
Host smart-44d754e3-59f2-4c1f-8e2e-44719580ee93
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=858733527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.858733527
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1479797682
Short name T2147
Test name
Test status
Simulation time 23318192797 ps
CPU time 24.77 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:40 PM PDT 24
Peak memory 206280 kb
Host smart-96197f13-27a8-424c-9b8f-132285128536
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1479797682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1479797682
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3720245194
Short name T760
Test name
Test status
Simulation time 204390957 ps
CPU time 0.82 seconds
Started Jul 06 05:26:00 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206168 kb
Host smart-63101ca5-208e-4ffb-8d44-62cb6bb8d86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37202
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3720245194
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2106331074
Short name T1026
Test name
Test status
Simulation time 150780653 ps
CPU time 0.78 seconds
Started Jul 06 05:26:00 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206208 kb
Host smart-201668f2-f88a-4285-8f40-c031ecb5244a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21063
31074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2106331074
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2165018761
Short name T1781
Test name
Test status
Simulation time 318166543 ps
CPU time 1.1 seconds
Started Jul 06 05:26:10 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206208 kb
Host smart-6302938c-7cf1-4226-9f66-fbbae62feedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
18761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2165018761
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.201453659
Short name T1686
Test name
Test status
Simulation time 1020035233 ps
CPU time 2.57 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206376 kb
Host smart-39fe6157-caa7-436b-830c-ed1cf0a86499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20145
3659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.201453659
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.387115625
Short name T721
Test name
Test status
Simulation time 19314942915 ps
CPU time 33.28 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:26:25 PM PDT 24
Peak memory 206436 kb
Host smart-4809dcf4-f7e6-40e7-ad2c-7e13ee9fa46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
5625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.387115625
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3246451803
Short name T1055
Test name
Test status
Simulation time 466665091 ps
CPU time 1.32 seconds
Started Jul 06 05:25:51 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206180 kb
Host smart-9744a924-74aa-4479-9e9f-cca2beb563ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32464
51803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3246451803
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1548169751
Short name T517
Test name
Test status
Simulation time 149163195 ps
CPU time 0.77 seconds
Started Jul 06 05:25:50 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206188 kb
Host smart-562f8988-4da6-43a2-b1c7-880ce41fc698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
69751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1548169751
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2420746547
Short name T1630
Test name
Test status
Simulation time 42333589 ps
CPU time 0.73 seconds
Started Jul 06 05:26:06 PM PDT 24
Finished Jul 06 05:26:07 PM PDT 24
Peak memory 206180 kb
Host smart-84166304-bb64-420c-8cab-20b95090343e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24207
46547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2420746547
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1999524477
Short name T1502
Test name
Test status
Simulation time 862789935 ps
CPU time 2.11 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206360 kb
Host smart-8a828db3-fcbf-4a17-bd34-8be68ba72275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
24477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1999524477
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1253529085
Short name T2063
Test name
Test status
Simulation time 274822357 ps
CPU time 1.92 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206444 kb
Host smart-a22cf9ad-f702-4c75-9d13-d956b242f059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12535
29085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1253529085
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1975971608
Short name T1289
Test name
Test status
Simulation time 224689327 ps
CPU time 0.9 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206184 kb
Host smart-595b0ed4-906f-426b-b1b1-f8debb6d5c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
71608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1975971608
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3149686516
Short name T2698
Test name
Test status
Simulation time 136950104 ps
CPU time 0.75 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:25:59 PM PDT 24
Peak memory 206172 kb
Host smart-b8e89201-07b0-4a07-b5c4-8e887760c3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31496
86516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3149686516
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3646818948
Short name T2690
Test name
Test status
Simulation time 202344112 ps
CPU time 0.87 seconds
Started Jul 06 05:25:52 PM PDT 24
Finished Jul 06 05:25:54 PM PDT 24
Peak memory 206184 kb
Host smart-fd0d3118-3439-427d-889a-c67010fd76e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36468
18948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3646818948
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1939377201
Short name T971
Test name
Test status
Simulation time 8446110564 ps
CPU time 235.1 seconds
Started Jul 06 05:25:49 PM PDT 24
Finished Jul 06 05:29:45 PM PDT 24
Peak memory 206520 kb
Host smart-0809313b-fbb6-4a9d-9f92-16270337938c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1939377201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1939377201
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3556525844
Short name T1764
Test name
Test status
Simulation time 231015155 ps
CPU time 0.93 seconds
Started Jul 06 05:26:00 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206208 kb
Host smart-2d05b6f1-e720-46c9-bd4a-f3845012d7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35565
25844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3556525844
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1619840635
Short name T1907
Test name
Test status
Simulation time 23358081474 ps
CPU time 23.8 seconds
Started Jul 06 05:25:56 PM PDT 24
Finished Jul 06 05:26:20 PM PDT 24
Peak memory 206264 kb
Host smart-28719d57-8863-446e-985f-eaa6b9bf29bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
40635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1619840635
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3872697193
Short name T1900
Test name
Test status
Simulation time 3263208218 ps
CPU time 4.27 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:03 PM PDT 24
Peak memory 206188 kb
Host smart-a09ed86f-2975-4d50-a3af-e9c03d20ab13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38726
97193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3872697193
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2705022257
Short name T1232
Test name
Test status
Simulation time 8684240141 ps
CPU time 233.96 seconds
Started Jul 06 05:26:00 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 206480 kb
Host smart-6464b7b8-2067-422c-badb-0f92d5490df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27050
22257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2705022257
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3543716952
Short name T2535
Test name
Test status
Simulation time 5904469488 ps
CPU time 171.54 seconds
Started Jul 06 05:26:05 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206408 kb
Host smart-31c0d749-142b-418f-9297-27b13f70bacb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3543716952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3543716952
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1896177746
Short name T357
Test name
Test status
Simulation time 294747727 ps
CPU time 0.92 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206220 kb
Host smart-a4c571c9-201d-45f3-8f6c-94f09ecd47b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1896177746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1896177746
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2828607652
Short name T2089
Test name
Test status
Simulation time 198873034 ps
CPU time 0.91 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206184 kb
Host smart-662913fb-2169-4169-b2a7-6362fc89cc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
07652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2828607652
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.4284723495
Short name T428
Test name
Test status
Simulation time 5210832768 ps
CPU time 147.7 seconds
Started Jul 06 05:25:55 PM PDT 24
Finished Jul 06 05:28:24 PM PDT 24
Peak memory 206456 kb
Host smart-6961b6a4-770e-4d23-b999-a88a7bcff180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42847
23495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.4284723495
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2040895312
Short name T454
Test name
Test status
Simulation time 4663635059 ps
CPU time 36.05 seconds
Started Jul 06 05:25:53 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206516 kb
Host smart-cf735c73-2fff-4930-8f86-f4411b7b9c55
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2040895312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2040895312
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3902277824
Short name T1002
Test name
Test status
Simulation time 160838769 ps
CPU time 0.79 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:06 PM PDT 24
Peak memory 206156 kb
Host smart-96647960-68e5-4588-97fc-00d9ab52328b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3902277824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3902277824
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2287775917
Short name T372
Test name
Test status
Simulation time 166244524 ps
CPU time 0.78 seconds
Started Jul 06 05:26:06 PM PDT 24
Finished Jul 06 05:26:07 PM PDT 24
Peak memory 206180 kb
Host smart-a2fb4425-406f-4b57-b3ef-c81367ad5929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
75917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2287775917
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.295825447
Short name T1452
Test name
Test status
Simulation time 205225623 ps
CPU time 0.86 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:06 PM PDT 24
Peak memory 206196 kb
Host smart-c63dba26-2d95-473e-951c-7bc4fceac01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
5447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.295825447
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2683309204
Short name T945
Test name
Test status
Simulation time 184222857 ps
CPU time 0.82 seconds
Started Jul 06 05:25:58 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206084 kb
Host smart-5f53a7bd-c557-4b90-9404-d6fd84dc85fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26833
09204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2683309204
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.359052787
Short name T2016
Test name
Test status
Simulation time 160123843 ps
CPU time 0.85 seconds
Started Jul 06 05:25:54 PM PDT 24
Finished Jul 06 05:25:56 PM PDT 24
Peak memory 206200 kb
Host smart-005e3a8d-0041-4ec2-967b-afb4b7e32c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
2787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.359052787
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2929241377
Short name T1141
Test name
Test status
Simulation time 186667955 ps
CPU time 0.85 seconds
Started Jul 06 05:26:09 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206196 kb
Host smart-e5d3e806-ab81-4ec1-8895-3452f700f11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
41377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2929241377
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2114810309
Short name T2095
Test name
Test status
Simulation time 171460844 ps
CPU time 0.81 seconds
Started Jul 06 05:25:57 PM PDT 24
Finished Jul 06 05:25:58 PM PDT 24
Peak memory 206180 kb
Host smart-076fd5ca-ba80-4c6b-8ada-05d0a5f2f714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148
10309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2114810309
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3094258157
Short name T1132
Test name
Test status
Simulation time 262791222 ps
CPU time 1.03 seconds
Started Jul 06 05:26:03 PM PDT 24
Finished Jul 06 05:26:04 PM PDT 24
Peak memory 206204 kb
Host smart-f3b79374-47bf-4cbe-8349-6dc3214d87c2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3094258157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3094258157
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3654278856
Short name T1950
Test name
Test status
Simulation time 153336504 ps
CPU time 0.75 seconds
Started Jul 06 05:25:59 PM PDT 24
Finished Jul 06 05:26:00 PM PDT 24
Peak memory 206064 kb
Host smart-e03a4907-51c4-4d7f-84a4-b8444a3fb93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
78856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3654278856
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1470633483
Short name T39
Test name
Test status
Simulation time 64768283 ps
CPU time 0.7 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206168 kb
Host smart-da1033c3-40df-4bd2-908a-2d62e0e1445f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14706
33483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1470633483
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3622625990
Short name T1263
Test name
Test status
Simulation time 8146941376 ps
CPU time 18.17 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:32 PM PDT 24
Peak memory 206544 kb
Host smart-a0419b39-8dfc-4ced-85b1-5c6222cdf164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
25990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3622625990
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1193327674
Short name T711
Test name
Test status
Simulation time 153314434 ps
CPU time 0.88 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206184 kb
Host smart-eea071fd-73a2-4079-822c-47f6ac563ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11933
27674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1193327674
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.49141053
Short name T1698
Test name
Test status
Simulation time 177304648 ps
CPU time 0.8 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206180 kb
Host smart-710dfccc-375f-45f9-9b0e-8a52605376db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49141
053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.49141053
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1838669963
Short name T2561
Test name
Test status
Simulation time 221556725 ps
CPU time 0.87 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206172 kb
Host smart-29f6cc12-beab-4c58-9f3c-7ec034686689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18386
69963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1838669963
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2587879139
Short name T343
Test name
Test status
Simulation time 164888546 ps
CPU time 0.86 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206200 kb
Host smart-55161f99-c5a1-48d9-945c-0bbb145a6c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25878
79139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2587879139
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.669330679
Short name T647
Test name
Test status
Simulation time 137134335 ps
CPU time 0.77 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206160 kb
Host smart-7336eea3-45ec-4132-b286-1950ca9268a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66933
0679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.669330679
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1189005011
Short name T661
Test name
Test status
Simulation time 152982267 ps
CPU time 0.79 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:12 PM PDT 24
Peak memory 206112 kb
Host smart-8aa8eb46-5b1e-40c6-a2c1-0e907e5bc0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
05011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1189005011
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.135103943
Short name T2607
Test name
Test status
Simulation time 149281797 ps
CPU time 0.77 seconds
Started Jul 06 05:26:16 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206208 kb
Host smart-10766de4-f382-4049-b0c0-e4eb648f1479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510
3943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.135103943
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1438829995
Short name T2228
Test name
Test status
Simulation time 234272341 ps
CPU time 0.98 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:02 PM PDT 24
Peak memory 206200 kb
Host smart-3befd6f4-92ed-4463-97b0-f8850ed2c698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
29995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1438829995
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1609090614
Short name T158
Test name
Test status
Simulation time 5605728212 ps
CPU time 41.57 seconds
Started Jul 06 05:26:02 PM PDT 24
Finished Jul 06 05:26:44 PM PDT 24
Peak memory 206348 kb
Host smart-f23a4219-d07a-4508-bbc9-cdee409ea002
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1609090614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1609090614
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4143236977
Short name T2297
Test name
Test status
Simulation time 237793954 ps
CPU time 0.9 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206164 kb
Host smart-55e55946-db47-42bb-a56f-2517eab037c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
36977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4143236977
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.96045385
Short name T1522
Test name
Test status
Simulation time 224989687 ps
CPU time 0.83 seconds
Started Jul 06 05:26:12 PM PDT 24
Finished Jul 06 05:26:13 PM PDT 24
Peak memory 206176 kb
Host smart-bff8f36a-bf47-43dd-ac09-c47122171b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96045
385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.96045385
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.2730168547
Short name T2310
Test name
Test status
Simulation time 1296969488 ps
CPU time 2.96 seconds
Started Jul 06 05:26:02 PM PDT 24
Finished Jul 06 05:26:06 PM PDT 24
Peak memory 206448 kb
Host smart-41af7e09-48dd-4523-9a84-9d35f5e4e921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
68547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.2730168547
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.422593694
Short name T1766
Test name
Test status
Simulation time 5020423110 ps
CPU time 130.9 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:28:28 PM PDT 24
Peak memory 206456 kb
Host smart-2876b1a0-fddf-407a-a003-6ed7ddd849c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
3694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.422593694
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2729672569
Short name T1161
Test name
Test status
Simulation time 52820667 ps
CPU time 0.69 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206252 kb
Host smart-82741771-ee90-492e-8f21-8629f1966c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2729672569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2729672569
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2843275274
Short name T14
Test name
Test status
Simulation time 4124392863 ps
CPU time 4.76 seconds
Started Jul 06 05:26:03 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206252 kb
Host smart-422f71b8-90a8-4a71-85b2-f37e30b2d108
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2843275274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2843275274
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3322022108
Short name T2466
Test name
Test status
Simulation time 13354474446 ps
CPU time 12.43 seconds
Started Jul 06 05:26:01 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206412 kb
Host smart-e5c863ac-c5b8-415d-9161-1b7a037059f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3322022108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3322022108
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2378421260
Short name T1075
Test name
Test status
Simulation time 23322266118 ps
CPU time 22.56 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206240 kb
Host smart-55c90639-f662-4733-b165-66b4871749e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2378421260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2378421260
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.442346642
Short name T152
Test name
Test status
Simulation time 175746575 ps
CPU time 0.79 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206180 kb
Host smart-a8374fb1-23dd-4d7d-b6fb-c75a34a6c5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44234
6642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.442346642
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.122255270
Short name T415
Test name
Test status
Simulation time 149760049 ps
CPU time 0.79 seconds
Started Jul 06 05:26:02 PM PDT 24
Finished Jul 06 05:26:04 PM PDT 24
Peak memory 206164 kb
Host smart-865fb503-2216-4d71-9fda-b18a201eca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12225
5270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.122255270
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.617275276
Short name T1626
Test name
Test status
Simulation time 375807466 ps
CPU time 1.26 seconds
Started Jul 06 05:25:59 PM PDT 24
Finished Jul 06 05:26:01 PM PDT 24
Peak memory 206204 kb
Host smart-3f4d1412-0060-4b89-90e3-0d2aa8d399e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61727
5276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.617275276
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2411619016
Short name T1525
Test name
Test status
Simulation time 847306898 ps
CPU time 1.95 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:13 PM PDT 24
Peak memory 206400 kb
Host smart-d48a5c8e-4c8a-471e-ace5-5c6370773586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24116
19016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2411619016
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1516767835
Short name T181
Test name
Test status
Simulation time 11588843796 ps
CPU time 21.74 seconds
Started Jul 06 05:26:02 PM PDT 24
Finished Jul 06 05:26:24 PM PDT 24
Peak memory 206416 kb
Host smart-5eece769-b299-4864-b7f7-41509bdbaee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
67835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1516767835
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.301945848
Short name T2613
Test name
Test status
Simulation time 321670254 ps
CPU time 1.08 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206124 kb
Host smart-4c7a3083-923d-4bc9-902c-0df5a2f0fd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194
5848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.301945848
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4214649446
Short name T889
Test name
Test status
Simulation time 145519627 ps
CPU time 0.76 seconds
Started Jul 06 05:26:14 PM PDT 24
Finished Jul 06 05:26:15 PM PDT 24
Peak memory 206168 kb
Host smart-2318ab25-c055-41f8-a9b0-b96afe4d88e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
49446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4214649446
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1573559115
Short name T2214
Test name
Test status
Simulation time 36014794 ps
CPU time 0.67 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:12 PM PDT 24
Peak memory 206180 kb
Host smart-9864395c-0f76-406c-978d-05fe59e8301e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735
59115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1573559115
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.938812757
Short name T1444
Test name
Test status
Simulation time 770092812 ps
CPU time 1.84 seconds
Started Jul 06 05:26:14 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206420 kb
Host smart-1b4517d4-5f6b-4c10-bfe8-f8f103a14b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93881
2757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.938812757
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.365159900
Short name T1288
Test name
Test status
Simulation time 321264495 ps
CPU time 1.91 seconds
Started Jul 06 05:26:09 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206356 kb
Host smart-77ca08ce-301b-4e50-85ab-ee0c7cc0c857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
9900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.365159900
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3063549424
Short name T432
Test name
Test status
Simulation time 157869871 ps
CPU time 0.82 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206096 kb
Host smart-d553eae5-aafc-44e1-805d-0c69bf826d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
49424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3063549424
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3901079124
Short name T723
Test name
Test status
Simulation time 175722494 ps
CPU time 0.81 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206196 kb
Host smart-292c9ff6-57c1-42cc-a16e-01c98479cf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39010
79124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3901079124
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3308466092
Short name T2271
Test name
Test status
Simulation time 219051765 ps
CPU time 0.9 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206160 kb
Host smart-f87f5cd3-8bb4-4c1b-954b-5049517cf1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084
66092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3308466092
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2596055421
Short name T2335
Test name
Test status
Simulation time 6880465418 ps
CPU time 45.39 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:57 PM PDT 24
Peak memory 206420 kb
Host smart-afa68a57-9c22-4ea2-8324-8800c8a112c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2596055421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2596055421
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1700424421
Short name T105
Test name
Test status
Simulation time 207076011 ps
CPU time 0.88 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206104 kb
Host smart-d8fb5a3d-e8ea-4183-89bf-ddd73f17bba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17004
24421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1700424421
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3113034247
Short name T487
Test name
Test status
Simulation time 23338691513 ps
CPU time 25.48 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:32 PM PDT 24
Peak memory 206228 kb
Host smart-41da0c32-19ce-492a-be09-74f4473e1edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31130
34247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3113034247
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2701448224
Short name T1243
Test name
Test status
Simulation time 3314199654 ps
CPU time 4.27 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206228 kb
Host smart-780c0da1-090e-463d-baf8-99e5fc013ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27014
48224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2701448224
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.768129686
Short name T1321
Test name
Test status
Simulation time 7559621787 ps
CPU time 210.44 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:29:42 PM PDT 24
Peak memory 206452 kb
Host smart-34123ec0-38a9-472c-9b26-6d07f187fdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76812
9686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.768129686
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1847131861
Short name T2121
Test name
Test status
Simulation time 4659494620 ps
CPU time 44.06 seconds
Started Jul 06 05:26:16 PM PDT 24
Finished Jul 06 05:27:01 PM PDT 24
Peak memory 206364 kb
Host smart-0dca92e7-4f09-4638-abe7-0a82e1f1bf7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1847131861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1847131861
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1494810581
Short name T1381
Test name
Test status
Simulation time 249610770 ps
CPU time 0.9 seconds
Started Jul 06 05:26:03 PM PDT 24
Finished Jul 06 05:26:04 PM PDT 24
Peak memory 206184 kb
Host smart-23692a20-d08c-4522-b8c4-eb46026ce092
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1494810581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1494810581
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.866588246
Short name T87
Test name
Test status
Simulation time 199422512 ps
CPU time 0.94 seconds
Started Jul 06 05:26:06 PM PDT 24
Finished Jul 06 05:26:07 PM PDT 24
Peak memory 206120 kb
Host smart-e5344914-9179-489b-9c09-9836f14fa2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86658
8246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.866588246
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3834957287
Short name T2235
Test name
Test status
Simulation time 6323509181 ps
CPU time 45.46 seconds
Started Jul 06 05:26:05 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206432 kb
Host smart-841efff1-aa4d-4277-a494-dbcebfc444ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38349
57287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3834957287
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1199425046
Short name T2072
Test name
Test status
Simulation time 3632601664 ps
CPU time 35.09 seconds
Started Jul 06 05:26:05 PM PDT 24
Finished Jul 06 05:26:41 PM PDT 24
Peak memory 206480 kb
Host smart-c286dd0e-5c2b-4827-8283-13981eeb77a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1199425046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1199425046
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2538465827
Short name T1672
Test name
Test status
Simulation time 169892082 ps
CPU time 0.79 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:20 PM PDT 24
Peak memory 206172 kb
Host smart-f7b56a75-0d3d-4c0c-8d97-ad6933c137bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2538465827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2538465827
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2799493106
Short name T1873
Test name
Test status
Simulation time 182597606 ps
CPU time 0.87 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206184 kb
Host smart-0fc98adb-2295-4415-949b-7beae097caa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
93106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2799493106
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3023669287
Short name T138
Test name
Test status
Simulation time 230717283 ps
CPU time 0.87 seconds
Started Jul 06 05:26:02 PM PDT 24
Finished Jul 06 05:26:03 PM PDT 24
Peak memory 206116 kb
Host smart-3789a62d-0476-4169-80d0-2f6d9f20faa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30236
69287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3023669287
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3738109496
Short name T728
Test name
Test status
Simulation time 158434429 ps
CPU time 0.89 seconds
Started Jul 06 05:26:04 PM PDT 24
Finished Jul 06 05:26:05 PM PDT 24
Peak memory 206192 kb
Host smart-161c502e-ef2a-40f0-a1cd-6b07e66c493f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37381
09496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3738109496
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3543966196
Short name T426
Test name
Test status
Simulation time 172117150 ps
CPU time 0.81 seconds
Started Jul 06 05:26:06 PM PDT 24
Finished Jul 06 05:26:07 PM PDT 24
Peak memory 206180 kb
Host smart-3038cc86-285a-416e-bf08-a10f1c9200c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
66196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3543966196
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2916476540
Short name T2226
Test name
Test status
Simulation time 191643882 ps
CPU time 0.83 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206180 kb
Host smart-2792c7ff-3734-4bbd-a51d-1a1c207d4e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29164
76540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2916476540
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3240552703
Short name T1690
Test name
Test status
Simulation time 235846535 ps
CPU time 0.87 seconds
Started Jul 06 05:26:08 PM PDT 24
Finished Jul 06 05:26:09 PM PDT 24
Peak memory 206120 kb
Host smart-b5a65162-39f4-420f-9a3e-31444f3d3165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32405
52703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3240552703
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3452987418
Short name T761
Test name
Test status
Simulation time 257168201 ps
CPU time 0.99 seconds
Started Jul 06 05:26:18 PM PDT 24
Finished Jul 06 05:26:20 PM PDT 24
Peak memory 206164 kb
Host smart-c920e211-317d-450c-a68a-660703eed6b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3452987418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3452987418
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2482820427
Short name T869
Test name
Test status
Simulation time 216787996 ps
CPU time 0.85 seconds
Started Jul 06 05:26:07 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206144 kb
Host smart-dc54d34e-48df-4a97-be57-5db3d8815413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
20427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2482820427
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2444930684
Short name T1188
Test name
Test status
Simulation time 95874522 ps
CPU time 0.71 seconds
Started Jul 06 05:26:10 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206108 kb
Host smart-a5d7cf8c-f7c0-4f31-846b-c74483ed9fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24449
30684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2444930684
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.211772691
Short name T258
Test name
Test status
Simulation time 20798147181 ps
CPU time 45.65 seconds
Started Jul 06 05:26:06 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206516 kb
Host smart-88895e7d-2c79-4982-a692-d51dfda047ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21177
2691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.211772691
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3537348274
Short name T1309
Test name
Test status
Simulation time 194536317 ps
CPU time 0.81 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206180 kb
Host smart-501d0208-9930-4c46-9c61-dece36578181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35373
48274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3537348274
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2246893687
Short name T1068
Test name
Test status
Simulation time 211105918 ps
CPU time 0.84 seconds
Started Jul 06 05:26:14 PM PDT 24
Finished Jul 06 05:26:15 PM PDT 24
Peak memory 206208 kb
Host smart-0d776253-0ca0-430a-81dd-8f9b8039c631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
93687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2246893687
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3248090240
Short name T1438
Test name
Test status
Simulation time 247362456 ps
CPU time 0.89 seconds
Started Jul 06 05:26:14 PM PDT 24
Finished Jul 06 05:26:15 PM PDT 24
Peak memory 206432 kb
Host smart-e8fdbb22-9ae5-47ff-8519-53eb7a41301e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480
90240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3248090240
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.4241179746
Short name T632
Test name
Test status
Simulation time 177670339 ps
CPU time 0.86 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206180 kb
Host smart-63e2d5ff-b42a-4fcc-90a9-be8463b52aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42411
79746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.4241179746
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.36833309
Short name T2672
Test name
Test status
Simulation time 195082343 ps
CPU time 0.84 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:13 PM PDT 24
Peak memory 206160 kb
Host smart-b2428a47-5e17-4c5a-bb02-2938697f7cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.36833309
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2154834454
Short name T1277
Test name
Test status
Simulation time 157227372 ps
CPU time 0.81 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206108 kb
Host smart-fc035578-eb35-4aba-b3ce-a848ecb1a01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21548
34454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2154834454
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2390336139
Short name T2550
Test name
Test status
Simulation time 188689975 ps
CPU time 0.78 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206160 kb
Host smart-77bf2278-5fc3-4f67-bbc8-daa32e51f96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23903
36139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2390336139
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2050014733
Short name T1914
Test name
Test status
Simulation time 222263590 ps
CPU time 0.93 seconds
Started Jul 06 05:26:12 PM PDT 24
Finished Jul 06 05:26:13 PM PDT 24
Peak memory 206180 kb
Host smart-fb79f058-cd8a-4ed0-b02e-85a82a4bda3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
14733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2050014733
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2307055287
Short name T1437
Test name
Test status
Simulation time 4648580360 ps
CPU time 44.98 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:56 PM PDT 24
Peak memory 206520 kb
Host smart-c9bdab3e-4530-4794-8a8d-349b9a70be56
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2307055287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2307055287
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3760891682
Short name T1262
Test name
Test status
Simulation time 185847314 ps
CPU time 0.79 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206044 kb
Host smart-40db57f9-f4f0-4a4a-abec-bbeae14fc4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37608
91682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3760891682
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3462093995
Short name T1109
Test name
Test status
Simulation time 199016577 ps
CPU time 0.93 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:13 PM PDT 24
Peak memory 206188 kb
Host smart-0293f93e-bf26-41a6-aab9-f97e4cdcf62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620
93995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3462093995
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1243493578
Short name T1300
Test name
Test status
Simulation time 329133283 ps
CPU time 1.11 seconds
Started Jul 06 05:26:10 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206176 kb
Host smart-c1f0d93a-cace-4987-b65b-2cc58c02b59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
93578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1243493578
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3532981295
Short name T634
Test name
Test status
Simulation time 4152188369 ps
CPU time 113.48 seconds
Started Jul 06 05:26:16 PM PDT 24
Finished Jul 06 05:28:09 PM PDT 24
Peak memory 206516 kb
Host smart-108ead1f-8c09-40ac-9f0e-924bc39f67c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329
81295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3532981295
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.3457406272
Short name T1126
Test name
Test status
Simulation time 45832804 ps
CPU time 0.68 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:44 PM PDT 24
Peak memory 206240 kb
Host smart-6a453b47-743b-4c6f-a18b-88309249129c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3457406272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.3457406272
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.4219056962
Short name T1451
Test name
Test status
Simulation time 4181358627 ps
CPU time 5.69 seconds
Started Jul 06 05:26:10 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206516 kb
Host smart-ccc6a16b-bd2e-431c-8e81-71a98681af78
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4219056962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.4219056962
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.376304531
Short name T827
Test name
Test status
Simulation time 13398313686 ps
CPU time 12.41 seconds
Started Jul 06 05:26:16 PM PDT 24
Finished Jul 06 05:26:29 PM PDT 24
Peak memory 206224 kb
Host smart-1bda8c07-4bc3-4b3a-bfac-6b687f0ce8c4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=376304531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.376304531
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.4174763248
Short name T1182
Test name
Test status
Simulation time 23323912168 ps
CPU time 23.91 seconds
Started Jul 06 05:26:09 PM PDT 24
Finished Jul 06 05:26:33 PM PDT 24
Peak memory 206192 kb
Host smart-cd5f0aa2-26b5-43ce-98a9-e084ca4a218a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4174763248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.4174763248
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2980706284
Short name T1937
Test name
Test status
Simulation time 215736606 ps
CPU time 0.89 seconds
Started Jul 06 05:26:10 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206140 kb
Host smart-ac93e5ef-7600-4b22-b7f4-369f59a3012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
06284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2980706284
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2846071033
Short name T2565
Test name
Test status
Simulation time 142967923 ps
CPU time 0.82 seconds
Started Jul 06 05:26:10 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 206200 kb
Host smart-d261e4b3-7167-4dc8-bcd7-a01b59aeee85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28460
71033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2846071033
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2115679271
Short name T2540
Test name
Test status
Simulation time 375505130 ps
CPU time 1.31 seconds
Started Jul 06 05:26:13 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 206204 kb
Host smart-eae1a3b1-3964-4231-ba71-9ec503548989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21156
79271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2115679271
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_device_address.664235357
Short name T448
Test name
Test status
Simulation time 19888894899 ps
CPU time 38.78 seconds
Started Jul 06 05:26:11 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206444 kb
Host smart-98219efa-7b65-4d22-a4e6-bd1a2f6f6c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66423
5357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.664235357
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3804979154
Short name T401
Test name
Test status
Simulation time 545688778 ps
CPU time 1.42 seconds
Started Jul 06 05:26:16 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206192 kb
Host smart-af4fd8bb-09b8-4225-b7e3-1a6304d0f4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049
79154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3804979154
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.4079344906
Short name T2383
Test name
Test status
Simulation time 148490601 ps
CPU time 0.79 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206120 kb
Host smart-967dacaa-fde0-4405-b572-6e37e1f5cf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
44906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.4079344906
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1450652239
Short name T1283
Test name
Test status
Simulation time 44124180 ps
CPU time 0.68 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:17 PM PDT 24
Peak memory 206172 kb
Host smart-a7aa42a2-a17d-4a48-96ce-41b1545cf13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506
52239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1450652239
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.575337270
Short name T341
Test name
Test status
Simulation time 986900987 ps
CPU time 2.17 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206352 kb
Host smart-0cc8dfaa-c89a-4f59-adda-a131b0d0fbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57533
7270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.575337270
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2534836825
Short name T1287
Test name
Test status
Simulation time 327661131 ps
CPU time 2.21 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206304 kb
Host smart-1a8d3005-52f1-431c-8943-fd5ba794cfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25348
36825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2534836825
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2096996191
Short name T227
Test name
Test status
Simulation time 288440868 ps
CPU time 0.92 seconds
Started Jul 06 05:26:31 PM PDT 24
Finished Jul 06 05:26:32 PM PDT 24
Peak memory 206168 kb
Host smart-8694098e-453a-4182-8c6a-51b8528f0d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20969
96191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2096996191
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1822107303
Short name T1613
Test name
Test status
Simulation time 146209421 ps
CPU time 0.74 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206176 kb
Host smart-68a9b04b-2166-4fa3-bef2-d7ea0891b30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18221
07303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1822107303
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1628290081
Short name T849
Test name
Test status
Simulation time 289938624 ps
CPU time 0.93 seconds
Started Jul 06 05:26:28 PM PDT 24
Finished Jul 06 05:26:29 PM PDT 24
Peak memory 206156 kb
Host smart-c9b052b7-4a80-4e1d-b4e1-a54e17fbba50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16282
90081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1628290081
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.664625903
Short name T2584
Test name
Test status
Simulation time 227558589 ps
CPU time 0.91 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206180 kb
Host smart-9af6069d-57a1-4035-9ef9-d3551e69f984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66462
5903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.664625903
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1245939003
Short name T852
Test name
Test status
Simulation time 23316865387 ps
CPU time 26.29 seconds
Started Jul 06 05:26:42 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206228 kb
Host smart-628e4791-ebaa-431e-8eff-5506b91b31da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12459
39003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1245939003
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2884952843
Short name T1382
Test name
Test status
Simulation time 3264634190 ps
CPU time 3.81 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206232 kb
Host smart-d143ac7f-6143-4a70-848a-c697d2e569df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28849
52843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2884952843
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2799499047
Short name T1467
Test name
Test status
Simulation time 10137226252 ps
CPU time 93.92 seconds
Started Jul 06 05:26:18 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206496 kb
Host smart-5b9af2bf-943d-4d59-af2b-0db860d28a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
99047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2799499047
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3376932838
Short name T1685
Test name
Test status
Simulation time 4844095773 ps
CPU time 46.17 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:27:06 PM PDT 24
Peak memory 206512 kb
Host smart-ba666640-dc9e-4d7f-a581-188129dd5463
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3376932838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3376932838
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.4264918365
Short name T2611
Test name
Test status
Simulation time 243031736 ps
CPU time 0.99 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206200 kb
Host smart-62de99cf-a668-481b-a88f-3cdd228dde5d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4264918365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.4264918365
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1063036042
Short name T2175
Test name
Test status
Simulation time 198019445 ps
CPU time 0.89 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206184 kb
Host smart-20a7e646-7898-46a1-b488-e67bea91bc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
36042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1063036042
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1555137598
Short name T1119
Test name
Test status
Simulation time 3702603120 ps
CPU time 26.83 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206460 kb
Host smart-b2d6c6e1-f778-4310-87bc-22950ec933d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15551
37598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1555137598
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1307460162
Short name T463
Test name
Test status
Simulation time 6826986065 ps
CPU time 187.84 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:29:25 PM PDT 24
Peak memory 206452 kb
Host smart-496c91da-2927-4afa-b906-d347af9ff0e3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1307460162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1307460162
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3654294775
Short name T408
Test name
Test status
Simulation time 155741173 ps
CPU time 0.81 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:26:34 PM PDT 24
Peak memory 206176 kb
Host smart-cfbf5d73-a225-472a-b45d-5515d1a771d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3654294775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3654294775
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3674212997
Short name T2467
Test name
Test status
Simulation time 144932023 ps
CPU time 0.81 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:26:16 PM PDT 24
Peak memory 206176 kb
Host smart-ff391982-fd13-46b6-a2c5-3403c5f37ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
12997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3674212997
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3011022603
Short name T145
Test name
Test status
Simulation time 210954169 ps
CPU time 0.87 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 206184 kb
Host smart-f47ef07b-e154-457e-9a3f-3203c5d8774c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
22603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3011022603
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.785232389
Short name T2449
Test name
Test status
Simulation time 160934995 ps
CPU time 0.85 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206188 kb
Host smart-5938faab-979a-4a1a-90ef-e4b14b1e4987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78523
2389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.785232389
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1503236022
Short name T2040
Test name
Test status
Simulation time 197275434 ps
CPU time 0.84 seconds
Started Jul 06 05:26:17 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206144 kb
Host smart-6afb720b-e656-4db0-a2e9-8648d027c7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15032
36022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1503236022
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1436051610
Short name T2340
Test name
Test status
Simulation time 199757428 ps
CPU time 0.77 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:19 PM PDT 24
Peak memory 206160 kb
Host smart-448a0326-e8e4-45ad-a151-bcb0daef285d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14360
51610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1436051610
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3249085650
Short name T2695
Test name
Test status
Simulation time 151834140 ps
CPU time 0.79 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206192 kb
Host smart-ead94092-f6b7-4875-bcf2-932ef3e41877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32490
85650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3249085650
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1016916513
Short name T1128
Test name
Test status
Simulation time 255522002 ps
CPU time 1.02 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:22 PM PDT 24
Peak memory 206176 kb
Host smart-9587e385-82bb-444d-bdf7-0768e1e3f0af
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1016916513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1016916513
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1200432087
Short name T1107
Test name
Test status
Simulation time 147757092 ps
CPU time 0.8 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206128 kb
Host smart-d7cba4b4-4a6c-4fee-994f-e7b6b9b3737a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12004
32087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1200432087
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4086226035
Short name T1570
Test name
Test status
Simulation time 14183825462 ps
CPU time 31.05 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206500 kb
Host smart-965d7d9e-af7c-45ad-9e44-e740f3d89139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
26035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4086226035
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2476943332
Short name T1813
Test name
Test status
Simulation time 167279081 ps
CPU time 0.83 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:20 PM PDT 24
Peak memory 206180 kb
Host smart-dee42cb4-6c49-4332-9a89-61214698ec3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24769
43332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2476943332
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2164516773
Short name T420
Test name
Test status
Simulation time 297437415 ps
CPU time 1.01 seconds
Started Jul 06 05:26:19 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206200 kb
Host smart-256860e1-f2ea-43ba-80f1-1cf2df10b21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21645
16773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2164516773
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2538506383
Short name T2033
Test name
Test status
Simulation time 238948057 ps
CPU time 0.88 seconds
Started Jul 06 05:26:18 PM PDT 24
Finished Jul 06 05:26:19 PM PDT 24
Peak memory 206204 kb
Host smart-d85c37b8-1e86-48ce-95c8-11daaea5b53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25385
06383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2538506383
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1144101614
Short name T2198
Test name
Test status
Simulation time 195662205 ps
CPU time 0.85 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:21 PM PDT 24
Peak memory 206172 kb
Host smart-1f9b1cc4-e243-4321-b366-f76f66ad4f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11441
01614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1144101614
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.488926483
Short name T76
Test name
Test status
Simulation time 138273866 ps
CPU time 0.8 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206200 kb
Host smart-392582cb-43af-4ab6-a5a4-5029f79e0b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48892
6483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.488926483
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3413080409
Short name T1211
Test name
Test status
Simulation time 148911020 ps
CPU time 0.77 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:26:45 PM PDT 24
Peak memory 206176 kb
Host smart-487af04e-8832-4dff-8776-e6bc551efbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34130
80409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3413080409
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.584747786
Short name T2703
Test name
Test status
Simulation time 179830110 ps
CPU time 0.79 seconds
Started Jul 06 05:26:18 PM PDT 24
Finished Jul 06 05:26:19 PM PDT 24
Peak memory 206172 kb
Host smart-88b6e91b-a685-4bbc-94a9-020ca24c2b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58474
7786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.584747786
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.669269585
Short name T1386
Test name
Test status
Simulation time 273596002 ps
CPU time 1.04 seconds
Started Jul 06 05:26:18 PM PDT 24
Finished Jul 06 05:26:20 PM PDT 24
Peak memory 206168 kb
Host smart-c81e306b-0119-4614-a67a-69106d013676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66926
9585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.669269585
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2540474362
Short name T2098
Test name
Test status
Simulation time 5315628644 ps
CPU time 151.28 seconds
Started Jul 06 05:26:15 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206508 kb
Host smart-6eed3095-298a-48db-b5b9-40ae4fde8234
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2540474362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2540474362
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2093451139
Short name T1995
Test name
Test status
Simulation time 151558309 ps
CPU time 0.86 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206160 kb
Host smart-418185e6-94a2-494a-9c38-49f3b9838219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20934
51139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2093451139
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1627981969
Short name T103
Test name
Test status
Simulation time 194328856 ps
CPU time 0.81 seconds
Started Jul 06 05:26:26 PM PDT 24
Finished Jul 06 05:26:27 PM PDT 24
Peak memory 206180 kb
Host smart-d79a4151-e6c6-4cc1-b158-3a13f77618a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279
81969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1627981969
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2408813535
Short name T1904
Test name
Test status
Simulation time 1315351427 ps
CPU time 2.63 seconds
Started Jul 06 05:26:22 PM PDT 24
Finished Jul 06 05:26:25 PM PDT 24
Peak memory 206380 kb
Host smart-795da4dd-fed6-4dfd-9466-eb3dcd55e9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
13535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2408813535
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1555002351
Short name T2639
Test name
Test status
Simulation time 7397291301 ps
CPU time 68.87 seconds
Started Jul 06 05:26:21 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206508 kb
Host smart-a11cc545-4fa6-46fc-b9d4-62369b45f6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15550
02351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1555002351
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2981205020
Short name T2099
Test name
Test status
Simulation time 86742856 ps
CPU time 0.73 seconds
Started Jul 06 05:26:45 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206216 kb
Host smart-48fa4909-e94a-40f5-b9c0-ccdb0cd118b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2981205020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2981205020
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1502073833
Short name T1280
Test name
Test status
Simulation time 3819469684 ps
CPU time 4.53 seconds
Started Jul 06 05:26:32 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206248 kb
Host smart-90d20d73-ae85-4a68-8c77-08359f89d852
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1502073833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1502073833
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.183666490
Short name T573
Test name
Test status
Simulation time 13339857720 ps
CPU time 12.44 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:33 PM PDT 24
Peak memory 206236 kb
Host smart-1fb32e25-51f0-448f-a197-663964c8ccdd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=183666490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.183666490
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1807186450
Short name T1087
Test name
Test status
Simulation time 23372922959 ps
CPU time 22.35 seconds
Started Jul 06 05:26:21 PM PDT 24
Finished Jul 06 05:26:43 PM PDT 24
Peak memory 206524 kb
Host smart-6656de3c-a021-41cb-9b49-14f1c7034f1e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1807186450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1807186450
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.326841870
Short name T819
Test name
Test status
Simulation time 175453582 ps
CPU time 0.82 seconds
Started Jul 06 05:26:22 PM PDT 24
Finished Jul 06 05:26:23 PM PDT 24
Peak memory 206124 kb
Host smart-2453b393-af22-49eb-833a-28fb1b1d6a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
1870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.326841870
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2584799085
Short name T1587
Test name
Test status
Simulation time 146905600 ps
CPU time 0.76 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:24 PM PDT 24
Peak memory 206184 kb
Host smart-88696a80-859e-40d7-a88c-f6140dc29818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25847
99085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2584799085
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2784093109
Short name T2123
Test name
Test status
Simulation time 306443498 ps
CPU time 1.15 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206224 kb
Host smart-03154a26-4f13-4bef-abeb-48ac63e6ce09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27840
93109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2784093109
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2594147449
Short name T860
Test name
Test status
Simulation time 566597837 ps
CPU time 1.58 seconds
Started Jul 06 05:26:26 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206200 kb
Host smart-8dab91a9-c9ea-41a9-a286-d79fb65c5857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25941
47449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2594147449
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3820115009
Short name T2328
Test name
Test status
Simulation time 6684784914 ps
CPU time 14.24 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:35 PM PDT 24
Peak memory 206436 kb
Host smart-798db049-aeca-4e14-8c03-fb3bcae18e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38201
15009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3820115009
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3508431334
Short name T409
Test name
Test status
Simulation time 393704150 ps
CPU time 1.39 seconds
Started Jul 06 05:26:22 PM PDT 24
Finished Jul 06 05:26:23 PM PDT 24
Peak memory 206156 kb
Host smart-f3ab45ca-7227-404a-8b4a-0e0bc88dcc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35084
31334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3508431334
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2243725178
Short name T1336
Test name
Test status
Simulation time 147637896 ps
CPU time 0.75 seconds
Started Jul 06 05:26:27 PM PDT 24
Finished Jul 06 05:26:27 PM PDT 24
Peak memory 206160 kb
Host smart-e2ecfb41-d06a-427c-91a1-3b897de07dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
25178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2243725178
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1236272296
Short name T1711
Test name
Test status
Simulation time 64591508 ps
CPU time 0.69 seconds
Started Jul 06 05:26:27 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206176 kb
Host smart-7cdd331c-264c-4b05-97c7-bad7443f1a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362
72296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1236272296
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2673902795
Short name T2234
Test name
Test status
Simulation time 816896669 ps
CPU time 1.9 seconds
Started Jul 06 05:26:34 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206400 kb
Host smart-df12cbb0-34f3-4358-8935-3cc7debf0f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26739
02795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2673902795
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4111528922
Short name T1308
Test name
Test status
Simulation time 258102009 ps
CPU time 1.46 seconds
Started Jul 06 05:26:25 PM PDT 24
Finished Jul 06 05:26:26 PM PDT 24
Peak memory 206408 kb
Host smart-3f896e80-85e2-4bd1-9b7f-21f7694ea019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41115
28922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4111528922
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1949989201
Short name T493
Test name
Test status
Simulation time 210333107 ps
CPU time 0.92 seconds
Started Jul 06 05:26:26 PM PDT 24
Finished Jul 06 05:26:27 PM PDT 24
Peak memory 206184 kb
Host smart-48ecfd65-720f-4dd1-ba40-284eede66a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19499
89201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1949989201
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2490828326
Short name T1677
Test name
Test status
Simulation time 178008632 ps
CPU time 0.86 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206160 kb
Host smart-fcccd858-a32a-404f-b0e2-aae6ff878b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24908
28326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2490828326
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.296253905
Short name T1839
Test name
Test status
Simulation time 230702391 ps
CPU time 0.92 seconds
Started Jul 06 05:26:34 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206128 kb
Host smart-079eee32-054b-481f-8232-db92ffb0ee07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29625
3905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.296253905
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3415968007
Short name T234
Test name
Test status
Simulation time 8874731637 ps
CPU time 62.07 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206468 kb
Host smart-99913b63-6cd3-4e90-ab98-ded54ccc6817
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3415968007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3415968007
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.4278520525
Short name T1678
Test name
Test status
Simulation time 220213699 ps
CPU time 0.9 seconds
Started Jul 06 05:26:37 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206200 kb
Host smart-2d2b6d85-95ae-40a0-a361-32849f15bc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42785
20525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.4278520525
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.903920377
Short name T2240
Test name
Test status
Simulation time 23346544335 ps
CPU time 25.56 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206168 kb
Host smart-c04a2299-5316-4a1b-9f30-c68101a2d745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90392
0377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.903920377
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2036312582
Short name T1331
Test name
Test status
Simulation time 3310783941 ps
CPU time 3.73 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206240 kb
Host smart-ec4a6b11-7961-4e25-b1f2-948b97992193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20363
12582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2036312582
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.4126287480
Short name T1036
Test name
Test status
Simulation time 10526426211 ps
CPU time 287.8 seconds
Started Jul 06 05:26:42 PM PDT 24
Finished Jul 06 05:31:30 PM PDT 24
Peak memory 206464 kb
Host smart-838908ec-bb09-4582-9dbe-4fa141dbff2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41262
87480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.4126287480
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.4048683156
Short name T353
Test name
Test status
Simulation time 7222347518 ps
CPU time 202.44 seconds
Started Jul 06 05:26:41 PM PDT 24
Finished Jul 06 05:30:04 PM PDT 24
Peak memory 206408 kb
Host smart-4f33e37b-8fe6-4fab-900c-7797caf1c7bb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4048683156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.4048683156
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2582594802
Short name T657
Test name
Test status
Simulation time 261101945 ps
CPU time 0.92 seconds
Started Jul 06 05:26:34 PM PDT 24
Finished Jul 06 05:26:35 PM PDT 24
Peak memory 206152 kb
Host smart-e59792ac-cf03-460d-841f-c3c0b8118d2c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2582594802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2582594802
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2454830623
Short name T2053
Test name
Test status
Simulation time 210884585 ps
CPU time 0.95 seconds
Started Jul 06 05:26:22 PM PDT 24
Finished Jul 06 05:26:23 PM PDT 24
Peak memory 206184 kb
Host smart-ba9f62db-c67c-4b92-a2c7-d1d91c3253b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24548
30623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2454830623
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.187800694
Short name T473
Test name
Test status
Simulation time 3868012875 ps
CPU time 108.41 seconds
Started Jul 06 05:26:20 PM PDT 24
Finished Jul 06 05:28:09 PM PDT 24
Peak memory 206460 kb
Host smart-ed0fcfc8-73d0-413e-a7da-464845111e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18780
0694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.187800694
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1929235590
Short name T905
Test name
Test status
Simulation time 4953994762 ps
CPU time 36.08 seconds
Started Jul 06 05:26:24 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206436 kb
Host smart-371036af-dcb8-49a9-b8c3-7c4319066b4e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1929235590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1929235590
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.4041333747
Short name T1596
Test name
Test status
Simulation time 154153535 ps
CPU time 0.82 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:24 PM PDT 24
Peak memory 206200 kb
Host smart-d3367795-ce81-48af-8d03-6099117e21bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4041333747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.4041333747
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2777507710
Short name T873
Test name
Test status
Simulation time 148430855 ps
CPU time 0.79 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:25 PM PDT 24
Peak memory 206068 kb
Host smart-4a31ef5c-069b-49e5-aa5d-0f51f6f2d6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
07710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2777507710
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1968129703
Short name T140
Test name
Test status
Simulation time 234002992 ps
CPU time 0.94 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:24 PM PDT 24
Peak memory 206184 kb
Host smart-695901df-c8a0-4855-a37b-06245ed2740b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19681
29703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1968129703
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.934153240
Short name T1345
Test name
Test status
Simulation time 186248506 ps
CPU time 0.85 seconds
Started Jul 06 05:26:39 PM PDT 24
Finished Jul 06 05:26:40 PM PDT 24
Peak memory 206100 kb
Host smart-9b9b7d92-c45e-4717-993f-992d4d745818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93415
3240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.934153240
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1682952698
Short name T2189
Test name
Test status
Simulation time 173434154 ps
CPU time 0.82 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206176 kb
Host smart-cd7a4a6e-da19-49a9-89f0-bbf258fcfa53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829
52698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1682952698
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2170040281
Short name T370
Test name
Test status
Simulation time 174285565 ps
CPU time 0.78 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:25 PM PDT 24
Peak memory 206192 kb
Host smart-87bad2b4-e2ba-4a17-a29c-cdfd18915ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21700
40281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2170040281
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1218050508
Short name T2440
Test name
Test status
Simulation time 235350480 ps
CPU time 0.85 seconds
Started Jul 06 05:26:23 PM PDT 24
Finished Jul 06 05:26:25 PM PDT 24
Peak memory 206144 kb
Host smart-c93124ee-7619-4057-bea1-dbe22936e36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
50508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1218050508
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3422014333
Short name T717
Test name
Test status
Simulation time 260763323 ps
CPU time 1 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:26:45 PM PDT 24
Peak memory 206180 kb
Host smart-86a84cd0-5791-4c45-bce6-c4c96fed4834
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3422014333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3422014333
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3881426060
Short name T733
Test name
Test status
Simulation time 162554905 ps
CPU time 0.81 seconds
Started Jul 06 05:26:27 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206176 kb
Host smart-c6d3be19-8f4b-46f1-9b75-f0583f9549f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38814
26060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3881426060
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2699764943
Short name T1094
Test name
Test status
Simulation time 49902269 ps
CPU time 0.66 seconds
Started Jul 06 05:26:41 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 206148 kb
Host smart-8c92a5d3-4d38-4251-886b-116427aea64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26997
64943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2699764943
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3370784489
Short name T1541
Test name
Test status
Simulation time 18472086039 ps
CPU time 38.48 seconds
Started Jul 06 05:26:32 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 214632 kb
Host smart-d368dcec-671e-493c-9d30-59bfdcf7b696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33707
84489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3370784489
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2622536758
Short name T1606
Test name
Test status
Simulation time 137759322 ps
CPU time 0.81 seconds
Started Jul 06 05:26:32 PM PDT 24
Finished Jul 06 05:26:34 PM PDT 24
Peak memory 206200 kb
Host smart-8479441c-5e15-410e-90e3-a247f346fdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
36758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2622536758
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2786818753
Short name T759
Test name
Test status
Simulation time 172511779 ps
CPU time 0.81 seconds
Started Jul 06 05:26:29 PM PDT 24
Finished Jul 06 05:26:31 PM PDT 24
Peak memory 206188 kb
Host smart-fb36ed52-81a4-4f96-9303-7ff7caecfbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868
18753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2786818753
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2463815295
Short name T2106
Test name
Test status
Simulation time 212888480 ps
CPU time 0.87 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206132 kb
Host smart-c4284f58-8547-4a57-9007-f95f2d7b0140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24638
15295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2463815295
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1638526162
Short name T500
Test name
Test status
Simulation time 197180718 ps
CPU time 0.9 seconds
Started Jul 06 05:26:29 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206120 kb
Host smart-c9c723a4-b4ac-40ad-abab-ed3760412226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16385
26162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1638526162
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3188613504
Short name T2238
Test name
Test status
Simulation time 166692894 ps
CPU time 0.77 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:41 PM PDT 24
Peak memory 206196 kb
Host smart-37b42d0b-f25e-4421-9ff3-3282aab21edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
13504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3188613504
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2095894831
Short name T446
Test name
Test status
Simulation time 145274350 ps
CPU time 0.77 seconds
Started Jul 06 05:26:50 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206192 kb
Host smart-12dfe5a2-2863-4946-ab2d-bd35e33f3e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20958
94831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2095894831
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3016736232
Short name T1135
Test name
Test status
Simulation time 154141984 ps
CPU time 0.77 seconds
Started Jul 06 05:26:29 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206164 kb
Host smart-91363035-4d61-40ae-8cf6-f0c65135beb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167
36232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3016736232
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1104285852
Short name T1425
Test name
Test status
Simulation time 199479938 ps
CPU time 0.93 seconds
Started Jul 06 05:26:31 PM PDT 24
Finished Jul 06 05:26:32 PM PDT 24
Peak memory 206200 kb
Host smart-d2cf97e4-5dc1-4e88-8247-a20a06fc1daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
85852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1104285852
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2560939593
Short name T1310
Test name
Test status
Simulation time 5266302064 ps
CPU time 37.31 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:27:21 PM PDT 24
Peak memory 206528 kb
Host smart-a8d4fa27-927e-43a6-a70b-448288a67374
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2560939593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2560939593
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1309176557
Short name T1365
Test name
Test status
Simulation time 189051080 ps
CPU time 0.91 seconds
Started Jul 06 05:26:32 PM PDT 24
Finished Jul 06 05:26:34 PM PDT 24
Peak memory 206200 kb
Host smart-86aadeb3-5797-44af-a3e8-aceded26c6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13091
76557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1309176557
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1466741168
Short name T779
Test name
Test status
Simulation time 173202559 ps
CPU time 0.85 seconds
Started Jul 06 05:26:31 PM PDT 24
Finished Jul 06 05:26:32 PM PDT 24
Peak memory 206188 kb
Host smart-22e33f98-238f-4b07-883a-203ff55fc74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
41168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1466741168
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2764718852
Short name T609
Test name
Test status
Simulation time 1420993639 ps
CPU time 2.96 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206392 kb
Host smart-f84967d8-1856-4376-b6aa-d4ff00d0b9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647
18852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2764718852
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.335076936
Short name T2274
Test name
Test status
Simulation time 7570008421 ps
CPU time 75.56 seconds
Started Jul 06 05:26:34 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206344 kb
Host smart-01bc49d5-3e28-47a4-a07a-e747616073ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.335076936
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.928961617
Short name T2685
Test name
Test status
Simulation time 67127730 ps
CPU time 0.72 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206212 kb
Host smart-862217ff-2381-4c9a-b9b5-fa2561bfeff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=928961617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.928961617
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.458477515
Short name T10
Test name
Test status
Simulation time 3554454402 ps
CPU time 4.19 seconds
Started Jul 06 05:26:28 PM PDT 24
Finished Jul 06 05:26:33 PM PDT 24
Peak memory 206460 kb
Host smart-2ad5048d-352a-4686-b020-b155a1bf57fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=458477515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.458477515
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3296129267
Short name T1921
Test name
Test status
Simulation time 13439581723 ps
CPU time 12.17 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206148 kb
Host smart-de6555cf-25db-4467-a2c1-028bb9f53979
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3296129267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3296129267
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2679804582
Short name T1370
Test name
Test status
Simulation time 23398046730 ps
CPU time 23.39 seconds
Started Jul 06 05:26:41 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206220 kb
Host smart-1e732b1e-c335-49ef-a67b-57e3c495f6d1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2679804582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.2679804582
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3054818906
Short name T2573
Test name
Test status
Simulation time 181138494 ps
CPU time 0.84 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:44 PM PDT 24
Peak memory 206112 kb
Host smart-c9480ac0-715d-4698-870f-5e69cccf19b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30548
18906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3054818906
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3498271639
Short name T495
Test name
Test status
Simulation time 150806238 ps
CPU time 0.84 seconds
Started Jul 06 05:26:27 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206168 kb
Host smart-a6d5fab2-7cd2-4f7a-91af-6e683210d9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34982
71639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3498271639
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1813464790
Short name T189
Test name
Test status
Simulation time 361234754 ps
CPU time 1.25 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206224 kb
Host smart-d34b9964-7620-47be-bb59-839c2eae9f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18134
64790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1813464790
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.770894303
Short name T107
Test name
Test status
Simulation time 934355996 ps
CPU time 2.15 seconds
Started Jul 06 05:26:30 PM PDT 24
Finished Jul 06 05:26:33 PM PDT 24
Peak memory 206388 kb
Host smart-95c24720-f156-4a8a-9397-c2ad02d3ab9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77089
4303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.770894303
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.362351748
Short name T2468
Test name
Test status
Simulation time 15233721188 ps
CPU time 28.7 seconds
Started Jul 06 05:26:30 PM PDT 24
Finished Jul 06 05:26:59 PM PDT 24
Peak memory 206452 kb
Host smart-03a959c2-b926-4891-bb7c-6d6a0af88107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
1748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.362351748
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4038635263
Short name T933
Test name
Test status
Simulation time 460008479 ps
CPU time 1.43 seconds
Started Jul 06 05:26:30 PM PDT 24
Finished Jul 06 05:26:31 PM PDT 24
Peak memory 206180 kb
Host smart-824f762c-99e7-41e7-830a-5ce62b8a9b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40386
35263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4038635263
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1672741626
Short name T1369
Test name
Test status
Simulation time 140049177 ps
CPU time 0.76 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206128 kb
Host smart-a62c2d5c-8bd0-4ed1-b9ed-a1b60dac223b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16727
41626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1672741626
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2307012154
Short name T2062
Test name
Test status
Simulation time 36939945 ps
CPU time 0.66 seconds
Started Jul 06 05:26:30 PM PDT 24
Finished Jul 06 05:26:31 PM PDT 24
Peak memory 206176 kb
Host smart-4d9434da-874e-468d-9ad4-c1627b4d8f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23070
12154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2307012154
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2906404638
Short name T2181
Test name
Test status
Simulation time 1038134567 ps
CPU time 2.5 seconds
Started Jul 06 05:26:29 PM PDT 24
Finished Jul 06 05:26:32 PM PDT 24
Peak memory 206396 kb
Host smart-75f3a08c-3f71-4455-a37c-f25c43fb494a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29064
04638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2906404638
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2333425988
Short name T1465
Test name
Test status
Simulation time 163537639 ps
CPU time 1.19 seconds
Started Jul 06 05:26:34 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206336 kb
Host smart-ae441a9c-ebd6-423a-8d45-8cb6287f36a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23334
25988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2333425988
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1690462851
Short name T2609
Test name
Test status
Simulation time 195655585 ps
CPU time 0.83 seconds
Started Jul 06 05:26:30 PM PDT 24
Finished Jul 06 05:26:31 PM PDT 24
Peak memory 206172 kb
Host smart-3f39b5d2-2eb3-47d0-8a90-122853e54b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
62851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1690462851
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.254129064
Short name T19
Test name
Test status
Simulation time 166896614 ps
CPU time 0.8 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206156 kb
Host smart-ece38649-37cc-4d69-9afc-88ff4d91a39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25412
9064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.254129064
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2653380374
Short name T1888
Test name
Test status
Simulation time 235494562 ps
CPU time 0.94 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:50 PM PDT 24
Peak memory 206200 kb
Host smart-8fa08027-c4a5-4d5f-ac3e-936bb91a9d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
80374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2653380374
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.2960124360
Short name T875
Test name
Test status
Simulation time 6188643114 ps
CPU time 46.84 seconds
Started Jul 06 05:26:29 PM PDT 24
Finished Jul 06 05:27:16 PM PDT 24
Peak memory 206424 kb
Host smart-1cc4e08e-7eb0-46ec-86ee-73a01d298990
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2960124360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.2960124360
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.24488328
Short name T2219
Test name
Test status
Simulation time 188532432 ps
CPU time 0.86 seconds
Started Jul 06 05:26:28 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206180 kb
Host smart-e7577359-1c86-4dac-a6f3-43f3a2857cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.24488328
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2652322864
Short name T2320
Test name
Test status
Simulation time 23333401682 ps
CPU time 26.02 seconds
Started Jul 06 05:26:39 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206172 kb
Host smart-1ae9d71d-4350-48e3-8f90-c95c13d4bc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26523
22864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2652322864
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1414157100
Short name T1654
Test name
Test status
Simulation time 3298940981 ps
CPU time 3.87 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206260 kb
Host smart-cac9012a-3f37-4e10-86e5-ce7e0d84c2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
57100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1414157100
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3097447545
Short name T2406
Test name
Test status
Simulation time 11991266868 ps
CPU time 337.73 seconds
Started Jul 06 05:26:30 PM PDT 24
Finished Jul 06 05:32:08 PM PDT 24
Peak memory 206452 kb
Host smart-41ab7f9e-387a-490e-8860-1ff603139b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30974
47545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3097447545
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.712541497
Short name T2055
Test name
Test status
Simulation time 5856973845 ps
CPU time 160.99 seconds
Started Jul 06 05:26:27 PM PDT 24
Finished Jul 06 05:29:09 PM PDT 24
Peak memory 206456 kb
Host smart-8c6fe05c-d024-4997-b133-7c2cf313bf72
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=712541497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.712541497
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1991142522
Short name T1390
Test name
Test status
Simulation time 251900787 ps
CPU time 0.86 seconds
Started Jul 06 05:26:29 PM PDT 24
Finished Jul 06 05:26:30 PM PDT 24
Peak memory 206200 kb
Host smart-c92ab25b-071c-478b-b225-68b2ca980ea5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1991142522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1991142522
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.828095587
Short name T1628
Test name
Test status
Simulation time 192090749 ps
CPU time 0.87 seconds
Started Jul 06 05:26:42 PM PDT 24
Finished Jul 06 05:26:43 PM PDT 24
Peak memory 206432 kb
Host smart-60c2c4d0-4c8f-48ee-b424-78726c7b2ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82809
5587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.828095587
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.4121424272
Short name T2646
Test name
Test status
Simulation time 3877370701 ps
CPU time 103.96 seconds
Started Jul 06 05:26:31 PM PDT 24
Finished Jul 06 05:28:15 PM PDT 24
Peak memory 206444 kb
Host smart-d659ab86-fa48-4247-8e66-9c3319cc73b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41214
24272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.4121424272
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1834606632
Short name T2448
Test name
Test status
Simulation time 7238145771 ps
CPU time 194.67 seconds
Started Jul 06 05:26:50 PM PDT 24
Finished Jul 06 05:30:06 PM PDT 24
Peak memory 206376 kb
Host smart-2cfa3787-6ddf-49bc-9d74-82157058b11b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1834606632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1834606632
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2682613100
Short name T1569
Test name
Test status
Simulation time 246635589 ps
CPU time 0.92 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206200 kb
Host smart-489148da-12eb-416a-a487-574febfff1e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2682613100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2682613100
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3971267866
Short name T1295
Test name
Test status
Simulation time 146600598 ps
CPU time 0.83 seconds
Started Jul 06 05:26:37 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206184 kb
Host smart-1070520d-cbd0-4dd9-94a5-0502342b92b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
67866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3971267866
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.4258960149
Short name T141
Test name
Test status
Simulation time 218361906 ps
CPU time 0.92 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206188 kb
Host smart-15e94683-d290-4915-8a0d-f9cbc578b0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589
60149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.4258960149
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.162182286
Short name T1281
Test name
Test status
Simulation time 190874458 ps
CPU time 0.84 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206176 kb
Host smart-905ea2ca-2587-4989-8908-d953524d90c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16218
2286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.162182286
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3803097554
Short name T692
Test name
Test status
Simulation time 156528862 ps
CPU time 0.75 seconds
Started Jul 06 05:26:45 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206040 kb
Host smart-5a06ce35-eb6a-43d2-abf2-2589467a1fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38030
97554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3803097554
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2832062335
Short name T2144
Test name
Test status
Simulation time 158993329 ps
CPU time 0.77 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206124 kb
Host smart-9483c67a-5418-47ad-a79b-351576db6e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28320
62335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2832062335
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.4198566600
Short name T1729
Test name
Test status
Simulation time 157001186 ps
CPU time 0.76 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206188 kb
Host smart-0e2d70bb-98d4-43c1-a111-c8f36b58349d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41985
66600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.4198566600
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3629445869
Short name T422
Test name
Test status
Simulation time 224849863 ps
CPU time 0.99 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206176 kb
Host smart-f16e0883-8354-43a8-8300-9b2f2a8b7ea3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3629445869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3629445869
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2333614889
Short name T2289
Test name
Test status
Simulation time 151582873 ps
CPU time 0.79 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206164 kb
Host smart-0be8cdac-4a04-454c-bd16-b01a606f2819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23336
14889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2333614889
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.160029192
Short name T2363
Test name
Test status
Simulation time 60110590 ps
CPU time 0.68 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:26:45 PM PDT 24
Peak memory 206200 kb
Host smart-28782b64-ff45-4239-b182-c58b8c96c751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16002
9192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.160029192
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.875531578
Short name T1518
Test name
Test status
Simulation time 20787802901 ps
CPU time 47.37 seconds
Started Jul 06 05:26:39 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206556 kb
Host smart-eb81e1ae-1392-4580-8b73-65e2818e7a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87553
1578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.875531578
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1086011968
Short name T757
Test name
Test status
Simulation time 197447149 ps
CPU time 0.89 seconds
Started Jul 06 05:26:50 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206180 kb
Host smart-3d0d2bda-f162-4a7f-a632-0527eebf70b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10860
11968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1086011968
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3575921665
Short name T54
Test name
Test status
Simulation time 174412890 ps
CPU time 0.85 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206176 kb
Host smart-30a828e2-577e-4a41-8337-54112f1405bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
21665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3575921665
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2733916803
Short name T1702
Test name
Test status
Simulation time 252002327 ps
CPU time 0.93 seconds
Started Jul 06 05:26:38 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206180 kb
Host smart-ec164e96-8a2c-40f4-8c94-aed796d18d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27339
16803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2733916803
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3502327892
Short name T2232
Test name
Test status
Simulation time 171485638 ps
CPU time 0.83 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:37 PM PDT 24
Peak memory 206180 kb
Host smart-4f19d7a0-b050-464a-b157-3a965589aa4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
27892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3502327892
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1767028500
Short name T974
Test name
Test status
Simulation time 150504154 ps
CPU time 0.77 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:07 PM PDT 24
Peak memory 206156 kb
Host smart-65607c94-3e55-4c6e-af5e-8c033998301a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
28500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1767028500
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2547479618
Short name T783
Test name
Test status
Simulation time 158287002 ps
CPU time 0.85 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:26:35 PM PDT 24
Peak memory 206200 kb
Host smart-17095395-5bb5-44b8-955c-fa8a06fd65b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
79618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2547479618
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.812572983
Short name T952
Test name
Test status
Simulation time 157130191 ps
CPU time 0.84 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206180 kb
Host smart-9b444b10-ed25-478c-8445-748ae7f4553a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81257
2983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.812572983
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.767009030
Short name T2521
Test name
Test status
Simulation time 241032747 ps
CPU time 1.02 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206200 kb
Host smart-fa7bb8f9-a77a-4f1b-920f-a47dfed2b04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76700
9030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.767009030
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1253901074
Short name T1167
Test name
Test status
Simulation time 3594530430 ps
CPU time 99.54 seconds
Started Jul 06 05:26:49 PM PDT 24
Finished Jul 06 05:28:30 PM PDT 24
Peak memory 206480 kb
Host smart-ed881098-6ead-4233-b938-6b9a9aafb925
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1253901074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1253901074
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.545753425
Short name T1490
Test name
Test status
Simulation time 166252948 ps
CPU time 0.77 seconds
Started Jul 06 05:26:39 PM PDT 24
Finished Jul 06 05:26:40 PM PDT 24
Peak memory 206084 kb
Host smart-6e6ffafe-2cb1-4d6a-a15b-b407ea94daaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54575
3425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.545753425
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1172239425
Short name T1338
Test name
Test status
Simulation time 165374544 ps
CPU time 0.81 seconds
Started Jul 06 05:26:37 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206180 kb
Host smart-260a5856-2b3c-4e8e-9e6c-c244f0fb46af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
39425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1172239425
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2215615118
Short name T2589
Test name
Test status
Simulation time 1267582483 ps
CPU time 2.44 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 206344 kb
Host smart-be4e6da6-6bb5-49ea-a9fb-fbf0af09a491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156
15118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2215615118
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1728247403
Short name T975
Test name
Test status
Simulation time 4335806405 ps
CPU time 32.62 seconds
Started Jul 06 05:26:38 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206456 kb
Host smart-35733825-30c9-4bbb-a798-c62f2b92e070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17282
47403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1728247403
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3595228834
Short name T2602
Test name
Test status
Simulation time 66560650 ps
CPU time 0.73 seconds
Started Jul 06 05:26:49 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206236 kb
Host smart-03a7968f-5fb3-4bd1-8519-9c998be7adc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3595228834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3595228834
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3474184054
Short name T1510
Test name
Test status
Simulation time 4324572251 ps
CPU time 4.93 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 206480 kb
Host smart-c8ed2f8d-e3f7-41cc-88e3-ce0020665bf4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3474184054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.3474184054
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3712092977
Short name T829
Test name
Test status
Simulation time 13365723704 ps
CPU time 12.35 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206188 kb
Host smart-ef7824bd-312c-4121-bc73-8fa9d1f7bd00
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3712092977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3712092977
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.4116880425
Short name T2517
Test name
Test status
Simulation time 23413814969 ps
CPU time 30.71 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206232 kb
Host smart-07558508-f932-4b60-978e-34d4719ad0e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4116880425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.4116880425
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3418317021
Short name T519
Test name
Test status
Simulation time 169916460 ps
CPU time 0.78 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206176 kb
Host smart-91109c4e-7903-4f1e-a4bc-d7fb5e96a4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
17021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3418317021
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.286694308
Short name T2102
Test name
Test status
Simulation time 152078604 ps
CPU time 0.77 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206124 kb
Host smart-a994f6ce-768a-40ab-be04-af3c806a62e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
4308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.286694308
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3665851148
Short name T191
Test name
Test status
Simulation time 345716343 ps
CPU time 1.13 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206196 kb
Host smart-0541362d-19f7-499e-be70-638c22ec3caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
51148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3665851148
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.42043612
Short name T1740
Test name
Test status
Simulation time 1172207591 ps
CPU time 2.66 seconds
Started Jul 06 05:26:55 PM PDT 24
Finished Jul 06 05:26:58 PM PDT 24
Peak memory 206372 kb
Host smart-1cc25bbc-bc08-4782-a332-683b48a6be2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.42043612
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3791696597
Short name T1808
Test name
Test status
Simulation time 15985934709 ps
CPU time 30.39 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206528 kb
Host smart-96c813af-b918-45cc-9bf3-10b05f69498e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
96597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3791696597
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1497578008
Short name T1080
Test name
Test status
Simulation time 388056430 ps
CPU time 1.43 seconds
Started Jul 06 05:26:37 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206180 kb
Host smart-1f8c9df2-5961-4f5d-b3fa-6f44968264c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14975
78008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1497578008
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1051313101
Short name T675
Test name
Test status
Simulation time 140715934 ps
CPU time 0.86 seconds
Started Jul 06 05:26:37 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206200 kb
Host smart-0144f367-ce64-498d-8502-45dabd8a6eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10513
13101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1051313101
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.186572587
Short name T1582
Test name
Test status
Simulation time 39451390 ps
CPU time 0.7 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206184 kb
Host smart-1a3d6e45-076d-42bc-9f60-6aab882d100c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
2587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.186572587
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2855149406
Short name T745
Test name
Test status
Simulation time 801359594 ps
CPU time 1.95 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206416 kb
Host smart-c94065ef-2355-4cde-ac94-05f6802929c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28551
49406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2855149406
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3316219276
Short name T1459
Test name
Test status
Simulation time 161705148 ps
CPU time 1.55 seconds
Started Jul 06 05:26:39 PM PDT 24
Finished Jul 06 05:26:41 PM PDT 24
Peak memory 206388 kb
Host smart-246c43d4-dd2d-42cd-9e75-c75e6b7be2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
19276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3316219276
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2532870371
Short name T1517
Test name
Test status
Simulation time 233637035 ps
CPU time 0.96 seconds
Started Jul 06 05:26:36 PM PDT 24
Finished Jul 06 05:26:38 PM PDT 24
Peak memory 206156 kb
Host smart-73d82c6e-4d83-47db-b4a8-cddb5fc294b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25328
70371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2532870371
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.172554836
Short name T225
Test name
Test status
Simulation time 143632131 ps
CPU time 0.81 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206196 kb
Host smart-da19b1d4-235e-4032-ad08-e2f8344a1a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17255
4836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.172554836
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1540481218
Short name T1738
Test name
Test status
Simulation time 232695985 ps
CPU time 0.89 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206200 kb
Host smart-ca097e85-9e1b-4d0e-aae1-38f02356143d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
81218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1540481218
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.472868564
Short name T1676
Test name
Test status
Simulation time 6413288909 ps
CPU time 44.55 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 206424 kb
Host smart-d862a619-7e12-491f-9796-015d262b567c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=472868564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.472868564
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1081785876
Short name T2210
Test name
Test status
Simulation time 225081636 ps
CPU time 0.88 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206164 kb
Host smart-edb0bc0e-bb6a-401e-bd49-fffbe53f7c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10817
85876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1081785876
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3527683700
Short name T929
Test name
Test status
Simulation time 23293433254 ps
CPU time 24.49 seconds
Started Jul 06 05:26:45 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206248 kb
Host smart-995094db-e73f-4ef1-a1f5-353b269c5700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
83700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3527683700
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.4085061474
Short name T722
Test name
Test status
Simulation time 3331404875 ps
CPU time 3.91 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:26:56 PM PDT 24
Peak memory 206260 kb
Host smart-33c27813-5984-48cf-a268-9daec25572d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
61474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.4085061474
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1947129003
Short name T1044
Test name
Test status
Simulation time 9043197120 ps
CPU time 87.77 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206528 kb
Host smart-f4699509-8c42-4278-b980-324f41524795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19471
29003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1947129003
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.4288993062
Short name T436
Test name
Test status
Simulation time 4279960303 ps
CPU time 118.28 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:28:41 PM PDT 24
Peak memory 206428 kb
Host smart-06afdabe-cd5d-43d9-80c1-88d3d73802d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4288993062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.4288993062
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3854274842
Short name T2329
Test name
Test status
Simulation time 251622453 ps
CPU time 0.87 seconds
Started Jul 06 05:26:52 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 206204 kb
Host smart-30af4fdc-d483-433c-9957-9b0d4aa47dd1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3854274842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3854274842
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3319623290
Short name T1584
Test name
Test status
Simulation time 189792453 ps
CPU time 0.94 seconds
Started Jul 06 05:26:35 PM PDT 24
Finished Jul 06 05:26:36 PM PDT 24
Peak memory 206184 kb
Host smart-9b9c8efb-d8bf-4721-92da-4fa87a17bd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33196
23290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3319623290
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1111040102
Short name T2213
Test name
Test status
Simulation time 5155447801 ps
CPU time 48.1 seconds
Started Jul 06 05:26:33 PM PDT 24
Finished Jul 06 05:27:22 PM PDT 24
Peak memory 206512 kb
Host smart-22defce2-0568-43da-ad12-3d3153068837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
40102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1111040102
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2762912023
Short name T2342
Test name
Test status
Simulation time 6124132644 ps
CPU time 43.94 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:27:32 PM PDT 24
Peak memory 206452 kb
Host smart-7355be05-222c-4c0c-abed-049cd8f52b39
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2762912023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2762912023
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.790943760
Short name T319
Test name
Test status
Simulation time 159493488 ps
CPU time 0.86 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206180 kb
Host smart-d5ca2388-4f16-4a21-a3ce-5bb1dfacbdbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=790943760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.790943760
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.207234410
Short name T1332
Test name
Test status
Simulation time 162286015 ps
CPU time 0.83 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206192 kb
Host smart-5ba400ee-c8bc-4c1d-9f95-1789a3930f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20723
4410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.207234410
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.434121359
Short name T1217
Test name
Test status
Simulation time 192599602 ps
CPU time 0.85 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206176 kb
Host smart-4e951448-744f-4feb-9ca8-4b0cc06eea2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43412
1359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.434121359
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1644303421
Short name T1649
Test name
Test status
Simulation time 142668615 ps
CPU time 0.77 seconds
Started Jul 06 05:26:56 PM PDT 24
Finished Jul 06 05:26:57 PM PDT 24
Peak memory 206176 kb
Host smart-ab083bbb-e006-4841-9121-40f68296a47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16443
03421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1644303421
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.757000722
Short name T2514
Test name
Test status
Simulation time 154228227 ps
CPU time 0.82 seconds
Started Jul 06 05:26:37 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206204 kb
Host smart-7b19b05d-7904-4fdd-a96d-4174e7ce269f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75700
0722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.757000722
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1436749678
Short name T2275
Test name
Test status
Simulation time 164829812 ps
CPU time 0.81 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206160 kb
Host smart-8a4885c5-cc36-4abf-9abe-d6400101ef1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367
49678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1436749678
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2471877339
Short name T780
Test name
Test status
Simulation time 246931407 ps
CPU time 0.92 seconds
Started Jul 06 05:26:50 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206196 kb
Host smart-ea6aebfd-37e3-415a-b8ff-fafe691cd4af
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2471877339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2471877339
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.4137183310
Short name T1064
Test name
Test status
Simulation time 143471719 ps
CPU time 0.77 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:50 PM PDT 24
Peak memory 206088 kb
Host smart-a4009c74-b085-447d-9e58-490b0469cb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371
83310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.4137183310
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4007113287
Short name T40
Test name
Test status
Simulation time 37883455 ps
CPU time 0.65 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:50 PM PDT 24
Peak memory 206200 kb
Host smart-50152c26-4f0c-45ce-82e2-07506def7eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40071
13287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4007113287
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2649262043
Short name T1891
Test name
Test status
Simulation time 9671907227 ps
CPU time 21.73 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:27:15 PM PDT 24
Peak memory 206504 kb
Host smart-6d6bed59-c432-4b3c-b077-108637cb75ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26492
62043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2649262043
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.517011254
Short name T1436
Test name
Test status
Simulation time 156774303 ps
CPU time 0.88 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206204 kb
Host smart-98b06a0d-e991-441e-9015-a89ce5d1d45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51701
1254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.517011254
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.645536751
Short name T1341
Test name
Test status
Simulation time 219587563 ps
CPU time 0.95 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206120 kb
Host smart-5d44d4e7-019f-46de-b5d7-5383e5dffe27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64553
6751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.645536751
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2936224112
Short name T345
Test name
Test status
Simulation time 275338429 ps
CPU time 0.91 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 206088 kb
Host smart-9760b73e-e8ea-46ab-8560-fcfeca8a7914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29362
24112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2936224112
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.329610725
Short name T2382
Test name
Test status
Simulation time 204616147 ps
CPU time 0.86 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:41 PM PDT 24
Peak memory 206176 kb
Host smart-0941a5f2-81ed-4e7a-8f87-b212c23ce856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32961
0725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.329610725
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.588418590
Short name T1218
Test name
Test status
Simulation time 171617757 ps
CPU time 0.78 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206112 kb
Host smart-ef1a2035-0595-44ff-8fa3-69be4d3ac191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58841
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.588418590
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.216374764
Short name T925
Test name
Test status
Simulation time 147031934 ps
CPU time 0.74 seconds
Started Jul 06 05:26:41 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 206164 kb
Host smart-39c4c9cd-0abe-4158-916d-335b69516bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21637
4764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.216374764
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.601993679
Short name T1993
Test name
Test status
Simulation time 153976927 ps
CPU time 0.94 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:59 PM PDT 24
Peak memory 206200 kb
Host smart-1a00a81e-ffab-4322-ac59-d7fefa923248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60199
3679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.601993679
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1002132528
Short name T512
Test name
Test status
Simulation time 216098203 ps
CPU time 0.91 seconds
Started Jul 06 05:26:38 PM PDT 24
Finished Jul 06 05:26:39 PM PDT 24
Peak memory 206200 kb
Host smart-65cd2d1c-d0ae-4fd6-a402-9ac8c94af995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021
32528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1002132528
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2903816445
Short name T2671
Test name
Test status
Simulation time 5986339997 ps
CPU time 156.21 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:29:23 PM PDT 24
Peak memory 206424 kb
Host smart-620bcc67-5c95-4d99-9ed8-32e429e6d553
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2903816445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2903816445
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.554156086
Short name T1798
Test name
Test status
Simulation time 148757622 ps
CPU time 0.74 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206200 kb
Host smart-eb3ff1d4-d096-4a9a-bf95-82f5400ed94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55415
6086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.554156086
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.252183157
Short name T2251
Test name
Test status
Simulation time 161638788 ps
CPU time 0.82 seconds
Started Jul 06 05:26:58 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206168 kb
Host smart-d3cc499f-f10b-47b2-aa38-bd06a303ddb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25218
3157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.252183157
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2971900602
Short name T1771
Test name
Test status
Simulation time 875269911 ps
CPU time 1.8 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 206344 kb
Host smart-18e01532-5e51-4951-8f1b-9620e390c20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
00602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2971900602
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1847853311
Short name T2624
Test name
Test status
Simulation time 4609739274 ps
CPU time 44.57 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 206476 kb
Host smart-cdd4a408-8c59-4d80-aa22-ea218a1b4897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
53311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1847853311
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1170466766
Short name T1394
Test name
Test status
Simulation time 55681375 ps
CPU time 0.69 seconds
Started Jul 06 05:23:02 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206216 kb
Host smart-270daae9-b8e4-4a9e-ace7-52aa9291c557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1170466766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1170466766
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2799466211
Short name T16
Test name
Test status
Simulation time 4083726053 ps
CPU time 5.02 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:22:57 PM PDT 24
Peak memory 206460 kb
Host smart-4c367ac5-ab29-46ef-a646-d01bd0dcc65a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2799466211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2799466211
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3728162984
Short name T2688
Test name
Test status
Simulation time 13381433876 ps
CPU time 16.4 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:16 PM PDT 24
Peak memory 206252 kb
Host smart-7a629699-2806-406b-b130-36c79ad2eb20
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3728162984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3728162984
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.402870754
Short name T699
Test name
Test status
Simulation time 23462222301 ps
CPU time 25.7 seconds
Started Jul 06 05:22:55 PM PDT 24
Finished Jul 06 05:23:21 PM PDT 24
Peak memory 206424 kb
Host smart-eca6edad-6050-452b-aa4d-a0a4f49db557
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=402870754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.402870754
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2876573159
Short name T441
Test name
Test status
Simulation time 154002635 ps
CPU time 0.77 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:22:53 PM PDT 24
Peak memory 206112 kb
Host smart-5dc1eed5-3415-41da-91b7-fae7105fa677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765
73159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2876573159
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.51640142
Short name T68
Test name
Test status
Simulation time 199759357 ps
CPU time 0.81 seconds
Started Jul 06 05:22:55 PM PDT 24
Finished Jul 06 05:22:57 PM PDT 24
Peak memory 206204 kb
Host smart-ab901da2-9161-480e-b112-13a94f932259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51640
142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.51640142
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3451904210
Short name T1346
Test name
Test status
Simulation time 153791249 ps
CPU time 0.79 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:22:54 PM PDT 24
Peak memory 206200 kb
Host smart-2f423d8a-7767-419b-b1fa-18b170601b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34519
04210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3451904210
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.971853915
Short name T2641
Test name
Test status
Simulation time 267710445 ps
CPU time 1 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206096 kb
Host smart-3f0b18a3-102a-4a6e-8311-71923ce97ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97185
3915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.971853915
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1952149309
Short name T2137
Test name
Test status
Simulation time 1112273385 ps
CPU time 2.44 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:57 PM PDT 24
Peak memory 206308 kb
Host smart-0e9d619a-38f5-4a04-a809-13c743c0bb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
49309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1952149309
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2504718149
Short name T169
Test name
Test status
Simulation time 22298244684 ps
CPU time 39.41 seconds
Started Jul 06 05:23:09 PM PDT 24
Finished Jul 06 05:23:49 PM PDT 24
Peak memory 206524 kb
Host smart-f4c232df-3ff2-4120-90ee-904a7c601d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25047
18149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2504718149
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3335535503
Short name T2103
Test name
Test status
Simulation time 403052518 ps
CPU time 1.31 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:56 PM PDT 24
Peak memory 206200 kb
Host smart-49c8466f-4b7a-457b-9131-966628b60abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33355
35503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3335535503
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.938054024
Short name T1573
Test name
Test status
Simulation time 137093409 ps
CPU time 0.74 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:22:54 PM PDT 24
Peak memory 206148 kb
Host smart-13b03d33-9b55-4af9-a03b-af834b52e394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93805
4024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.938054024
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1819570274
Short name T1940
Test name
Test status
Simulation time 79824293 ps
CPU time 0.65 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:54 PM PDT 24
Peak memory 206196 kb
Host smart-6a5c73ca-9dc1-4d9e-88b6-4457c546fe58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
70274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1819570274
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3369501072
Short name T2493
Test name
Test status
Simulation time 901608797 ps
CPU time 2.33 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:57 PM PDT 24
Peak memory 206448 kb
Host smart-b1d427d8-b0a8-4e92-b564-1e2b7dea061f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695
01072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3369501072
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.543887156
Short name T196
Test name
Test status
Simulation time 151639056 ps
CPU time 1.19 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:22:55 PM PDT 24
Peak memory 206288 kb
Host smart-3bbe4d17-9c0e-45f8-90e8-2c89577dd42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54388
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.543887156
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.475274302
Short name T1020
Test name
Test status
Simulation time 87206628401 ps
CPU time 111.1 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:24:45 PM PDT 24
Peak memory 206452 kb
Host smart-46d68e77-f4b2-4e49-b2d3-4ffa23855dfb
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=475274302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.475274302
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.117022777
Short name T1368
Test name
Test status
Simulation time 99321178216 ps
CPU time 123.7 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:24:58 PM PDT 24
Peak memory 206432 kb
Host smart-231a5b02-9b0c-46eb-a9da-6a877d7df753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117022777 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.117022777
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1145522005
Short name T2346
Test name
Test status
Simulation time 96119500343 ps
CPU time 138.23 seconds
Started Jul 06 05:22:53 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 206456 kb
Host smart-d378b373-c183-45be-991c-25d36c657440
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1145522005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1145522005
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2878772360
Short name T1832
Test name
Test status
Simulation time 117895747461 ps
CPU time 192.74 seconds
Started Jul 06 05:22:55 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206464 kb
Host smart-f8aa1ba7-f74d-4fed-aa32-6edbe2e915e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878772360 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2878772360
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3842434084
Short name T566
Test name
Test status
Simulation time 102110073225 ps
CPU time 148.23 seconds
Started Jul 06 05:22:52 PM PDT 24
Finished Jul 06 05:25:21 PM PDT 24
Peak memory 206460 kb
Host smart-2751c9ba-72ae-491f-862d-c95708c658f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38424
34084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3842434084
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2475764154
Short name T963
Test name
Test status
Simulation time 203632701 ps
CPU time 0.87 seconds
Started Jul 06 05:22:54 PM PDT 24
Finished Jul 06 05:22:55 PM PDT 24
Peak memory 206184 kb
Host smart-26ce3dc7-d656-4195-9491-cc7bf45a02d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
64154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2475764154
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.31476594
Short name T1586
Test name
Test status
Simulation time 182361828 ps
CPU time 0.81 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206112 kb
Host smart-3be39f62-28bc-41fa-ab10-7e231957210a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31476
594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.31476594
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.4082704020
Short name T568
Test name
Test status
Simulation time 190033865 ps
CPU time 0.93 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206164 kb
Host smart-313bfb74-a480-449d-bbd3-8740fd993dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827
04020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.4082704020
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3903836947
Short name T2494
Test name
Test status
Simulation time 219855338 ps
CPU time 0.91 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206208 kb
Host smart-8cd00632-6c08-40d2-a87a-be2f1ee5f4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39038
36947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3903836947
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2858030925
Short name T1526
Test name
Test status
Simulation time 23255410513 ps
CPU time 22.44 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:23:21 PM PDT 24
Peak memory 206264 kb
Host smart-70685054-8dc0-48ab-96ad-e0e0a90b32f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580
30925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2858030925
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3406858066
Short name T1354
Test name
Test status
Simulation time 3308853759 ps
CPU time 3.88 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206264 kb
Host smart-a9d9167b-66a7-4b17-810c-3ea742915924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34068
58066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3406858066
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1422569466
Short name T2172
Test name
Test status
Simulation time 11222589950 ps
CPU time 296.9 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206508 kb
Host smart-ee05b26e-e23c-4a72-ba15-8a2951c31258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
69466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1422569466
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2954506759
Short name T2601
Test name
Test status
Simulation time 3791913639 ps
CPU time 25 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:23:25 PM PDT 24
Peak memory 206480 kb
Host smart-b33b0d14-34d3-439c-8674-b8f484049610
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2954506759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2954506759
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3193508134
Short name T771
Test name
Test status
Simulation time 253739235 ps
CPU time 0.89 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:23:00 PM PDT 24
Peak memory 206196 kb
Host smart-7ea8e0f9-4183-4948-a19b-d922ddf3d98f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3193508134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3193508134
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1035287171
Short name T902
Test name
Test status
Simulation time 196859338 ps
CPU time 0.83 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206196 kb
Host smart-3b96cd56-5d02-401f-8de9-31f1b1b4537d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352
87171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1035287171
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1263266165
Short name T336
Test name
Test status
Simulation time 5574216440 ps
CPU time 38.85 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206436 kb
Host smart-8d677ef8-ab15-470c-832e-84ee982e4622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12632
66165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1263266165
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.854142800
Short name T790
Test name
Test status
Simulation time 2911289878 ps
CPU time 75.78 seconds
Started Jul 06 05:22:56 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206456 kb
Host smart-b5948981-feb7-40b0-91e5-5608cb8878b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=854142800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.854142800
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2270350674
Short name T1015
Test name
Test status
Simulation time 179844044 ps
CPU time 0.85 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206116 kb
Host smart-d6aebefe-3064-4d04-8ffc-95c9e11c8fca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2270350674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2270350674
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.600998168
Short name T1464
Test name
Test status
Simulation time 143188949 ps
CPU time 0.79 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206188 kb
Host smart-d098d68c-364e-4d23-95b3-a3efc77456eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60099
8168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.600998168
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3834086032
Short name T144
Test name
Test status
Simulation time 193131634 ps
CPU time 0.86 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206176 kb
Host smart-8c7750aa-cb77-4561-8db8-d0c4fe2ec288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
86032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3834086032
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.4069674135
Short name T1683
Test name
Test status
Simulation time 189144285 ps
CPU time 0.88 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:23:00 PM PDT 24
Peak memory 206184 kb
Host smart-10dff6da-a2d1-49dd-b6c1-a0ab5d025c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40696
74135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.4069674135
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2003196424
Short name T1996
Test name
Test status
Simulation time 166985047 ps
CPU time 0.81 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206180 kb
Host smart-64eef59b-243d-4a79-a49d-0b82594cca1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
96424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2003196424
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3432073479
Short name T1718
Test name
Test status
Simulation time 167923675 ps
CPU time 0.8 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206192 kb
Host smart-2eddd23e-fb95-414e-a523-7e81e8e6e0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34320
73479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3432073479
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1651079936
Short name T1033
Test name
Test status
Simulation time 178822415 ps
CPU time 0.78 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206156 kb
Host smart-cd8abb07-c698-47ff-ba87-e1da1c0a0bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510
79936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1651079936
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.927703202
Short name T1373
Test name
Test status
Simulation time 227605282 ps
CPU time 0.88 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206124 kb
Host smart-4af1fec1-811b-44a0-b3e1-325f6f9935d8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=927703202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.927703202
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.231331444
Short name T2472
Test name
Test status
Simulation time 216022386 ps
CPU time 0.94 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206204 kb
Host smart-f645060a-6f90-41f5-9a77-cda8dd649809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133
1444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.231331444
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3122357097
Short name T1910
Test name
Test status
Simulation time 147036007 ps
CPU time 0.78 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:23:00 PM PDT 24
Peak memory 206220 kb
Host smart-8246e026-3ae3-4127-bfd0-58264327cd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31223
57097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3122357097
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.161556169
Short name T1505
Test name
Test status
Simulation time 56434050 ps
CPU time 0.69 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206112 kb
Host smart-44a9471a-7b70-450e-a7a9-c7ea994654ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16155
6169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.161556169
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2289781500
Short name T265
Test name
Test status
Simulation time 18119961472 ps
CPU time 43.61 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 214636 kb
Host smart-56403439-6ec1-4bc1-8bca-691c27184e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
81500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2289781500
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1643764278
Short name T2244
Test name
Test status
Simulation time 157563440 ps
CPU time 0.78 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:23:00 PM PDT 24
Peak memory 206196 kb
Host smart-7541bccf-a10f-447b-a96c-0291d7d8cb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16437
64278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1643764278
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3510207920
Short name T2553
Test name
Test status
Simulation time 219442358 ps
CPU time 0.86 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:59 PM PDT 24
Peak memory 206172 kb
Host smart-71be4122-5197-4d69-af28-40e21dadf528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35102
07920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3510207920
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3665496750
Short name T2548
Test name
Test status
Simulation time 10019310990 ps
CPU time 85.73 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206456 kb
Host smart-844db79e-8c1f-4f5f-ac6c-57bf4575365d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3665496750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3665496750
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1672308389
Short name T1955
Test name
Test status
Simulation time 13567379710 ps
CPU time 86.68 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:24:28 PM PDT 24
Peak memory 206500 kb
Host smart-a9e344a1-10bf-4387-91c6-2958970ea1ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1672308389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1672308389
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2525137390
Short name T1788
Test name
Test status
Simulation time 12275084812 ps
CPU time 233.86 seconds
Started Jul 06 05:22:58 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 206476 kb
Host smart-d4ad4e3d-bdb6-4a86-ae3e-9c057e3c1dd1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2525137390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2525137390
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.854241694
Short name T615
Test name
Test status
Simulation time 209955987 ps
CPU time 0.88 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206180 kb
Host smart-2c822ebb-a6ed-4115-a117-66d930eae75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85424
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.854241694
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1705041331
Short name T1789
Test name
Test status
Simulation time 198890808 ps
CPU time 0.85 seconds
Started Jul 06 05:22:57 PM PDT 24
Finished Jul 06 05:22:58 PM PDT 24
Peak memory 206112 kb
Host smart-23760979-1892-4155-85cd-80e6046a1a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
41331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1705041331
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1191024091
Short name T2122
Test name
Test status
Simulation time 167880211 ps
CPU time 0.85 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206188 kb
Host smart-1b7abd2b-fee7-4833-8699-95282e61d5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11910
24091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1191024091
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3838397906
Short name T2702
Test name
Test status
Simulation time 175222661 ps
CPU time 0.84 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206112 kb
Host smart-218d5ef2-2eaa-41fb-b84d-1dafee2551c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38383
97906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3838397906
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1752634026
Short name T224
Test name
Test status
Simulation time 519308305 ps
CPU time 1.44 seconds
Started Jul 06 05:23:05 PM PDT 24
Finished Jul 06 05:23:07 PM PDT 24
Peak memory 224092 kb
Host smart-c6ffd536-e6ca-444f-be65-34f27ed249d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1752634026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1752634026
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1069942990
Short name T1388
Test name
Test status
Simulation time 380716745 ps
CPU time 1.23 seconds
Started Jul 06 05:23:03 PM PDT 24
Finished Jul 06 05:23:04 PM PDT 24
Peak memory 206116 kb
Host smart-9668d626-ea7f-4a0f-8783-cdc5b762ad67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
42990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1069942990
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2144590549
Short name T2452
Test name
Test status
Simulation time 183468628 ps
CPU time 0.85 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206184 kb
Host smart-76fe4347-a506-4dca-ac1f-5c68ee97177b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21445
90549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2144590549
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2283688903
Short name T1566
Test name
Test status
Simulation time 174563518 ps
CPU time 0.95 seconds
Started Jul 06 05:23:02 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206180 kb
Host smart-fa3cf09d-30d3-4366-8a13-d8d9c224649e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836
88903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2283688903
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1448418117
Short name T2453
Test name
Test status
Simulation time 184101853 ps
CPU time 0.81 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206176 kb
Host smart-8858fa4d-1600-4915-9150-400a47f90060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484
18117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1448418117
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3166033693
Short name T226
Test name
Test status
Simulation time 262378231 ps
CPU time 1.11 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206176 kb
Host smart-d62f8fa8-8d82-44fc-a4d8-21e379b4cf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
33693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3166033693
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.640467989
Short name T1250
Test name
Test status
Simulation time 4868165229 ps
CPU time 128.5 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:25:09 PM PDT 24
Peak memory 206516 kb
Host smart-0b7ddddc-8002-4d2f-b2c3-5bc97f8c456b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=640467989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.640467989
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.46595579
Short name T2510
Test name
Test status
Simulation time 179758235 ps
CPU time 0.84 seconds
Started Jul 06 05:23:02 PM PDT 24
Finished Jul 06 05:23:03 PM PDT 24
Peak memory 206204 kb
Host smart-287454df-367a-411a-9476-796a13fc609c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46595
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.46595579
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.966773452
Short name T2615
Test name
Test status
Simulation time 248988943 ps
CPU time 0.94 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206204 kb
Host smart-04c057a2-87cf-4d39-9a3a-2a7cd7b0ae55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96677
3452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.966773452
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3149939950
Short name T2132
Test name
Test status
Simulation time 1022408806 ps
CPU time 2.15 seconds
Started Jul 06 05:23:01 PM PDT 24
Finished Jul 06 05:23:04 PM PDT 24
Peak memory 206336 kb
Host smart-632e14ac-806a-485a-be29-c65bb8097171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31499
39950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3149939950
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2763664296
Short name T2348
Test name
Test status
Simulation time 7442752307 ps
CPU time 51.45 seconds
Started Jul 06 05:23:02 PM PDT 24
Finished Jul 06 05:23:54 PM PDT 24
Peak memory 206464 kb
Host smart-50c10095-74fa-4b9e-9766-25b8ae127406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
64296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2763664296
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3625711294
Short name T477
Test name
Test status
Simulation time 54615052 ps
CPU time 0.7 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:59 PM PDT 24
Peak memory 206264 kb
Host smart-59c5cf3f-27b6-4412-ab29-ad98b6bdd9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3625711294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3625711294
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.560719223
Short name T825
Test name
Test status
Simulation time 3564674784 ps
CPU time 5.25 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206148 kb
Host smart-0f5ff042-a08a-465a-9063-ee34a4f27530
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=560719223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.560719223
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3428562172
Short name T872
Test name
Test status
Simulation time 13325020507 ps
CPU time 11.75 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:27:01 PM PDT 24
Peak memory 206420 kb
Host smart-5b79478b-0b02-4ae6-b485-5d4fd9bec1a0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3428562172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3428562172
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1384147438
Short name T50
Test name
Test status
Simulation time 23305353735 ps
CPU time 27.91 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:37 PM PDT 24
Peak memory 206436 kb
Host smart-2c4534b1-5511-4c8f-8c43-265f94a43549
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1384147438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1384147438
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.870702017
Short name T1037
Test name
Test status
Simulation time 197672341 ps
CPU time 0.77 seconds
Started Jul 06 05:26:40 PM PDT 24
Finished Jul 06 05:26:41 PM PDT 24
Peak memory 206164 kb
Host smart-990f1b08-8852-47f0-b6ac-db141f0eb835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87070
2017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.870702017
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1950812456
Short name T1012
Test name
Test status
Simulation time 162544302 ps
CPU time 0.79 seconds
Started Jul 06 05:26:45 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206116 kb
Host smart-0651c124-3e41-4038-9553-7b4941c3eac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508
12456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1950812456
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3652284370
Short name T110
Test name
Test status
Simulation time 428734901 ps
CPU time 1.55 seconds
Started Jul 06 05:26:49 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206208 kb
Host smart-1475cfdf-0013-4ee6-a799-71a27ffd6bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36522
84370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3652284370
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2689156147
Short name T2250
Test name
Test status
Simulation time 544932744 ps
CPU time 1.44 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206204 kb
Host smart-75f79aa3-1417-4d6c-a445-3784f1dbc2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26891
56147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2689156147
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2811874106
Short name T1187
Test name
Test status
Simulation time 20474513607 ps
CPU time 39.49 seconds
Started Jul 06 05:26:52 PM PDT 24
Finished Jul 06 05:27:32 PM PDT 24
Peak memory 206436 kb
Host smart-f366a38b-616a-4705-960c-7b5b01254f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
74106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2811874106
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1406262999
Short name T410
Test name
Test status
Simulation time 397951647 ps
CPU time 1.21 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206200 kb
Host smart-d9b44fc1-69dd-4822-980a-033100141c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14062
62999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1406262999
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3941218018
Short name T613
Test name
Test status
Simulation time 160330379 ps
CPU time 0.79 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206108 kb
Host smart-2af2dfa9-1deb-4e41-8a74-e021d7c0f1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
18018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3941218018
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3464200228
Short name T1974
Test name
Test status
Simulation time 46836895 ps
CPU time 0.67 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206108 kb
Host smart-ec13f3bb-2268-43e2-9f55-1b042416b5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34642
00228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3464200228
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3224156994
Short name T2311
Test name
Test status
Simulation time 817474784 ps
CPU time 1.93 seconds
Started Jul 06 05:27:04 PM PDT 24
Finished Jul 06 05:27:06 PM PDT 24
Peak memory 206344 kb
Host smart-9976bcd4-e218-4459-b89c-93eb3134caa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32241
56994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3224156994
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3721781337
Short name T2183
Test name
Test status
Simulation time 173266279 ps
CPU time 1.7 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206396 kb
Host smart-895e2b79-2022-4c6c-bc4f-73e30ae16265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37217
81337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3721781337
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3456058106
Short name T330
Test name
Test status
Simulation time 234503079 ps
CPU time 0.89 seconds
Started Jul 06 05:26:48 PM PDT 24
Finished Jul 06 05:26:50 PM PDT 24
Peak memory 206188 kb
Host smart-255c0ef2-40d0-413e-b714-2f901cc18d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
58106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3456058106
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3875138542
Short name T2403
Test name
Test status
Simulation time 148241770 ps
CPU time 0.75 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206204 kb
Host smart-f7d0babe-3b33-4c45-b884-9570813e3902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751
38542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3875138542
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3509632137
Short name T1827
Test name
Test status
Simulation time 219148831 ps
CPU time 0.94 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206108 kb
Host smart-2ef34919-f9e6-4759-8215-59429c3e8ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
32137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3509632137
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2246961038
Short name T2009
Test name
Test status
Simulation time 158415146 ps
CPU time 0.82 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:44 PM PDT 24
Peak memory 206120 kb
Host smart-fe36f63e-9a45-4070-a737-93cf5bf53a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
61038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2246961038
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3951696816
Short name T1777
Test name
Test status
Simulation time 23287309801 ps
CPU time 24.94 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206180 kb
Host smart-9c501d78-7e87-4657-8fbd-caf7abb0f00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
96816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3951696816
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3664635661
Short name T1337
Test name
Test status
Simulation time 3327172772 ps
CPU time 4.6 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206180 kb
Host smart-d071b4c9-8a5c-4c57-8e6e-f935bebb5253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36646
35661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3664635661
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.704788512
Short name T1842
Test name
Test status
Simulation time 10336097417 ps
CPU time 261.62 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:31:10 PM PDT 24
Peak memory 206408 kb
Host smart-1787af83-37cf-4117-9eec-d7776b29aa02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70478
8512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.704788512
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.973440198
Short name T45
Test name
Test status
Simulation time 5183006729 ps
CPU time 39.33 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:27:24 PM PDT 24
Peak memory 206420 kb
Host smart-9b73a66a-fbc3-4f09-ae72-f33080616aaf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=973440198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.973440198
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3261746491
Short name T2670
Test name
Test status
Simulation time 240898549 ps
CPU time 1.01 seconds
Started Jul 06 05:27:01 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206112 kb
Host smart-220b1624-790c-4c18-8cd4-e7a37325e060
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3261746491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3261746491
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3171873661
Short name T1959
Test name
Test status
Simulation time 195527159 ps
CPU time 0.94 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206160 kb
Host smart-bd7aaaae-7d89-48f1-bb7f-2591bacc3b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31718
73661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3171873661
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2644116054
Short name T88
Test name
Test status
Simulation time 3710631444 ps
CPU time 26.37 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206440 kb
Host smart-e403cb66-48ac-485b-ba4f-7514cdde1231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
16054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2644116054
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3227840415
Short name T1374
Test name
Test status
Simulation time 5962917916 ps
CPU time 56.18 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:27:49 PM PDT 24
Peak memory 206408 kb
Host smart-8dc1ca67-8a72-471a-9b32-77917cdb0b7d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3227840415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3227840415
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3079806042
Short name T1023
Test name
Test status
Simulation time 144353129 ps
CPU time 0.8 seconds
Started Jul 06 05:27:03 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206176 kb
Host smart-466b8f88-9332-46a9-bd7c-51e57233df16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3079806042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3079806042
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3298289752
Short name T1902
Test name
Test status
Simulation time 144921128 ps
CPU time 0.77 seconds
Started Jul 06 05:26:45 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206184 kb
Host smart-d92308c8-0b34-4fa8-a7b0-7fbdde9de712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
89752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3298289752
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2111473679
Short name T143
Test name
Test status
Simulation time 238322021 ps
CPU time 0.86 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:26:45 PM PDT 24
Peak memory 206100 kb
Host smart-35e6e9c8-da41-4354-af9f-5f5d7b9a5164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114
73679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2111473679
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.370553939
Short name T2088
Test name
Test status
Simulation time 223475206 ps
CPU time 0.88 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206184 kb
Host smart-5c0819d4-4c8f-4232-bc35-40131aec53b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
3939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.370553939
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1241692447
Short name T2441
Test name
Test status
Simulation time 151438579 ps
CPU time 0.85 seconds
Started Jul 06 05:27:05 PM PDT 24
Finished Jul 06 05:27:06 PM PDT 24
Peak memory 206196 kb
Host smart-15f7a899-7b38-44c4-a94a-7a483515cdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12416
92447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1241692447
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.622105640
Short name T1850
Test name
Test status
Simulation time 167136177 ps
CPU time 0.81 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206016 kb
Host smart-534541fc-5dd3-4392-8275-1eedbb02b590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62210
5640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.622105640
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3955494634
Short name T1481
Test name
Test status
Simulation time 217975696 ps
CPU time 0.85 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206180 kb
Host smart-9b5f8f64-8ba7-495f-9f7d-cffbc8a6a15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39554
94634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3955494634
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.814261417
Short name T1351
Test name
Test status
Simulation time 187709543 ps
CPU time 0.89 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:44 PM PDT 24
Peak memory 206196 kb
Host smart-e26038f7-ed92-4525-b4c0-5923484d99d2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=814261417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.814261417
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.897695024
Short name T2598
Test name
Test status
Simulation time 146708232 ps
CPU time 0.81 seconds
Started Jul 06 05:27:09 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206180 kb
Host smart-ba6da8b5-4cba-4749-9113-488409fe72ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89769
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.897695024
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.164257842
Short name T1917
Test name
Test status
Simulation time 62856302 ps
CPU time 0.73 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206192 kb
Host smart-3d8cc60f-e033-417c-b779-e2bc8be279fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16425
7842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.164257842
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1698457274
Short name T1724
Test name
Test status
Simulation time 13090948658 ps
CPU time 30.02 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:38 PM PDT 24
Peak memory 206520 kb
Host smart-2938cd00-950e-486b-9c0d-b8b57e7d7b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
57274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1698457274
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3292853913
Short name T1865
Test name
Test status
Simulation time 158940765 ps
CPU time 0.77 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206172 kb
Host smart-95bbc08e-5535-4dca-a147-ffb5f4269ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32928
53913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3292853913
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1960000224
Short name T1562
Test name
Test status
Simulation time 266840001 ps
CPU time 0.93 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:58 PM PDT 24
Peak memory 206156 kb
Host smart-d2b4981d-466a-473b-9c6e-cf8d956f5e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19600
00224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1960000224
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3317231117
Short name T2184
Test name
Test status
Simulation time 246059202 ps
CPU time 0.94 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 206176 kb
Host smart-3d290705-d305-4fe5-824c-d3bada44f1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33172
31117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3317231117
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.4119782024
Short name T2131
Test name
Test status
Simulation time 175284939 ps
CPU time 0.9 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206180 kb
Host smart-841337fe-c36a-49eb-83ab-69e848a1753f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41197
82024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.4119782024
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2179518813
Short name T1890
Test name
Test status
Simulation time 179442800 ps
CPU time 0.81 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206172 kb
Host smart-e141d409-9929-4ac4-a693-11a2d5007853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21795
18813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2179518813
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1532304212
Short name T90
Test name
Test status
Simulation time 158525586 ps
CPU time 0.82 seconds
Started Jul 06 05:27:03 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206168 kb
Host smart-e9b9b221-158a-45eb-b7ec-b8e62f31f3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
04212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1532304212
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1933627098
Short name T2625
Test name
Test status
Simulation time 150881707 ps
CPU time 0.79 seconds
Started Jul 06 05:26:58 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206204 kb
Host smart-8cbe57fd-b2a3-42e4-9461-f8ba39a6737d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
27098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1933627098
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2991756006
Short name T373
Test name
Test status
Simulation time 228037402 ps
CPU time 0.89 seconds
Started Jul 06 05:26:46 PM PDT 24
Finished Jul 06 05:26:48 PM PDT 24
Peak memory 206164 kb
Host smart-39ed6c3f-8d5e-4ad5-9fbf-ed8b56bcd692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29917
56006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2991756006
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1057460062
Short name T1992
Test name
Test status
Simulation time 4493961038 ps
CPU time 31.05 seconds
Started Jul 06 05:26:44 PM PDT 24
Finished Jul 06 05:27:16 PM PDT 24
Peak memory 206448 kb
Host smart-4dca7b2c-ea76-4a20-90d1-213346bad950
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1057460062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1057460062
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2064723974
Short name T776
Test name
Test status
Simulation time 174510389 ps
CPU time 0.81 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206164 kb
Host smart-c7e34ad1-7e30-4407-b76b-9bd7bee350c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
23974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2064723974
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.581316335
Short name T1617
Test name
Test status
Simulation time 207125852 ps
CPU time 0.87 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206204 kb
Host smart-e63406bf-c510-4376-98df-008cf231df76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58131
6335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.581316335
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2529564438
Short name T1509
Test name
Test status
Simulation time 385022594 ps
CPU time 1.22 seconds
Started Jul 06 05:26:47 PM PDT 24
Finished Jul 06 05:26:49 PM PDT 24
Peak memory 206184 kb
Host smart-762d596b-60a9-4712-8d2d-97c5a41330d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25295
64438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2529564438
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.646927215
Short name T1503
Test name
Test status
Simulation time 4130772773 ps
CPU time 29.26 seconds
Started Jul 06 05:26:45 PM PDT 24
Finished Jul 06 05:27:15 PM PDT 24
Peak memory 206516 kb
Host smart-3ccbb517-f1fd-412a-826e-990d36bf6ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64692
7215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.646927215
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3742967366
Short name T725
Test name
Test status
Simulation time 107601721 ps
CPU time 0.79 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206268 kb
Host smart-365b6217-89a1-4a72-92a8-ff8540cb507a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3742967366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3742967366
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3334252563
Short name T240
Test name
Test status
Simulation time 3841852527 ps
CPU time 4.14 seconds
Started Jul 06 05:26:43 PM PDT 24
Finished Jul 06 05:26:47 PM PDT 24
Peak memory 206516 kb
Host smart-1ed0854b-2759-4baa-9d77-bae71e0f0567
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3334252563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3334252563
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2334447897
Short name T2286
Test name
Test status
Simulation time 13482794102 ps
CPU time 16.63 seconds
Started Jul 06 05:27:01 PM PDT 24
Finished Jul 06 05:27:19 PM PDT 24
Peak memory 206500 kb
Host smart-01bb8bea-e1b3-48a4-8c2d-9ae8481adcba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2334447897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2334447897
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.119632403
Short name T7
Test name
Test status
Simulation time 23400638868 ps
CPU time 23.8 seconds
Started Jul 06 05:26:56 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206184 kb
Host smart-b8c96df2-34de-4743-83ab-978eb81ece5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=119632403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.119632403
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2613390207
Short name T2487
Test name
Test status
Simulation time 182619573 ps
CPU time 0.84 seconds
Started Jul 06 05:26:50 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206200 kb
Host smart-5b612faf-3781-4fb1-bdcf-428c56b90a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26133
90207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2613390207
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.4009620448
Short name T514
Test name
Test status
Simulation time 147231296 ps
CPU time 0.85 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206120 kb
Host smart-96aefbb5-2399-45d8-a8f9-cd19e2a73607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40096
20448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.4009620448
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3096272829
Short name T1862
Test name
Test status
Simulation time 561785930 ps
CPU time 1.68 seconds
Started Jul 06 05:27:07 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206296 kb
Host smart-7be98879-9afb-4b64-bbff-7b3aaa282f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
72829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3096272829
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1484310825
Short name T2507
Test name
Test status
Simulation time 439153899 ps
CPU time 1.16 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206160 kb
Host smart-2d6db09d-9991-4efa-8363-d3c85848176d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14843
10825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1484310825
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1097286775
Short name T563
Test name
Test status
Simulation time 6783302640 ps
CPU time 11.77 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206516 kb
Host smart-3ecd59a9-a336-4932-8eaa-f1883a65564c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10972
86775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1097286775
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.1493215534
Short name T587
Test name
Test status
Simulation time 326092606 ps
CPU time 1.33 seconds
Started Jul 06 05:26:50 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206164 kb
Host smart-c2cbf26b-52d4-4a55-aa65-c31af2d4e792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14932
15534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.1493215534
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.864612238
Short name T2640
Test name
Test status
Simulation time 146723600 ps
CPU time 0.8 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206172 kb
Host smart-67efc659-af67-4c64-84e8-ed6c2f3c944b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86461
2238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.864612238
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2036636995
Short name T391
Test name
Test status
Simulation time 35141512 ps
CPU time 0.67 seconds
Started Jul 06 05:26:49 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206180 kb
Host smart-01241dd2-a19b-40c6-88a7-51ce9f43e9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
36995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2036636995
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3867560852
Short name T2669
Test name
Test status
Simulation time 946404050 ps
CPU time 2.27 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206376 kb
Host smart-cb2c628d-5733-47a3-b85d-63b221065cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
60852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3867560852
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1626115249
Short name T1556
Test name
Test status
Simulation time 251460258 ps
CPU time 1.58 seconds
Started Jul 06 05:27:03 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206400 kb
Host smart-af6a171e-40d9-46c0-89fa-409397001f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16261
15249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1626115249
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2474514155
Short name T2388
Test name
Test status
Simulation time 173932889 ps
CPU time 0.8 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:58 PM PDT 24
Peak memory 206112 kb
Host smart-4f3db649-8762-4b98-aec2-b1ce803d8e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
14155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2474514155
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3196583056
Short name T339
Test name
Test status
Simulation time 193067959 ps
CPU time 0.82 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206112 kb
Host smart-17e8859d-2694-401e-88b9-16d390c52630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31965
83056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3196583056
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3818303513
Short name T1592
Test name
Test status
Simulation time 257595141 ps
CPU time 0.93 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:26:53 PM PDT 24
Peak memory 206164 kb
Host smart-5a8d7a14-01e7-466d-8127-273a2864c27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38183
03513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3818303513
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1262129360
Short name T678
Test name
Test status
Simulation time 201876660 ps
CPU time 0.87 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 206184 kb
Host smart-b4bf6943-b22d-444a-86df-11cdb4c78b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
29360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1262129360
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1725267995
Short name T1741
Test name
Test status
Simulation time 23331429535 ps
CPU time 23.49 seconds
Started Jul 06 05:26:52 PM PDT 24
Finished Jul 06 05:27:16 PM PDT 24
Peak memory 206268 kb
Host smart-2781c12b-f9e6-4f73-ad2b-4f9e19730bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17252
67995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1725267995
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1469131902
Short name T1491
Test name
Test status
Simulation time 3391077448 ps
CPU time 4.14 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206268 kb
Host smart-abee19fc-db82-4406-bbe4-00c94436c3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14691
31902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1469131902
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1176632809
Short name T2485
Test name
Test status
Simulation time 12384012539 ps
CPU time 119.54 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 206536 kb
Host smart-6a8c3411-9424-4e91-95d7-463bc5c9091b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11766
32809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1176632809
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2997326682
Short name T2080
Test name
Test status
Simulation time 3843276694 ps
CPU time 101.22 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206428 kb
Host smart-878d1c1f-20bb-4db3-93cf-205de784baf7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2997326682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2997326682
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2086600939
Short name T1817
Test name
Test status
Simulation time 301425166 ps
CPU time 0.95 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206124 kb
Host smart-f5545cd4-c991-4b7d-8bc7-eeea122919e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2086600939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2086600939
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3695122117
Short name T1392
Test name
Test status
Simulation time 197043690 ps
CPU time 0.92 seconds
Started Jul 06 05:27:01 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206152 kb
Host smart-fb9df680-3de7-4984-a4e6-966e510f0b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36951
22117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3695122117
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1060646825
Short name T559
Test name
Test status
Simulation time 4587054378 ps
CPU time 43.11 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206516 kb
Host smart-e1b1969d-bc10-48a0-8cfa-661728ca1f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606
46825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1060646825
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.736735841
Short name T1210
Test name
Test status
Simulation time 4811453044 ps
CPU time 45.97 seconds
Started Jul 06 05:27:13 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206452 kb
Host smart-25ebc207-b33c-4dca-9504-6bf00ec6851b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=736735841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.736735841
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2165995727
Short name T693
Test name
Test status
Simulation time 151647062 ps
CPU time 0.75 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206116 kb
Host smart-ab5b24a7-0369-4e99-8a4b-d593ddd251ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2165995727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2165995727
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.94676480
Short name T1778
Test name
Test status
Simulation time 138249991 ps
CPU time 0.76 seconds
Started Jul 06 05:26:52 PM PDT 24
Finished Jul 06 05:26:53 PM PDT 24
Peak memory 206136 kb
Host smart-7697d427-af62-4ecc-b0fd-cca33ca10882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94676
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.94676480
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.4184164024
Short name T521
Test name
Test status
Simulation time 189105261 ps
CPU time 0.85 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206200 kb
Host smart-0d73aedd-e5d6-4524-87d6-96af795cda13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41841
64024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.4184164024
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.569900494
Short name T1912
Test name
Test status
Simulation time 194769814 ps
CPU time 0.84 seconds
Started Jul 06 05:26:52 PM PDT 24
Finished Jul 06 05:26:53 PM PDT 24
Peak memory 206196 kb
Host smart-05aa88ef-e98e-4b07-bf8c-9f0c442d873e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56990
0494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.569900494
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.4201759557
Short name T344
Test name
Test status
Simulation time 172733659 ps
CPU time 0.83 seconds
Started Jul 06 05:26:51 PM PDT 24
Finished Jul 06 05:26:53 PM PDT 24
Peak memory 206144 kb
Host smart-0947bcfa-7218-4334-8d3c-049322f98b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42017
59557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.4201759557
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.4146746405
Short name T797
Test name
Test status
Simulation time 181662189 ps
CPU time 0.82 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206188 kb
Host smart-0098e8c4-82a2-48a4-ad61-38224cec9b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41467
46405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.4146746405
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1543802326
Short name T1125
Test name
Test status
Simulation time 245889167 ps
CPU time 0.94 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206204 kb
Host smart-c43ac588-f4eb-482b-b0b5-b7fdac837a52
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1543802326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1543802326
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2556095995
Short name T1965
Test name
Test status
Simulation time 172037377 ps
CPU time 0.82 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206020 kb
Host smart-acba1922-7d9a-4dd4-920e-1c7ed87ed2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25560
95995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2556095995
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1487553841
Short name T2547
Test name
Test status
Simulation time 42702430 ps
CPU time 0.63 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206196 kb
Host smart-cd34beda-ecd2-4345-b4bd-a9a74d11fcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14875
53841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1487553841
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2383817581
Short name T1228
Test name
Test status
Simulation time 13655686203 ps
CPU time 32.54 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:27:26 PM PDT 24
Peak memory 206556 kb
Host smart-f4d6446d-5017-4c3c-beae-e55836585db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23838
17581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2383817581
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.579728568
Short name T1204
Test name
Test status
Simulation time 183159176 ps
CPU time 0.88 seconds
Started Jul 06 05:26:55 PM PDT 24
Finished Jul 06 05:26:56 PM PDT 24
Peak memory 206116 kb
Host smart-803a681f-e16e-4963-893a-1cf5f03a7678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57972
8568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.579728568
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3165615077
Short name T1636
Test name
Test status
Simulation time 222204297 ps
CPU time 0.83 seconds
Started Jul 06 05:27:05 PM PDT 24
Finished Jul 06 05:27:07 PM PDT 24
Peak memory 206204 kb
Host smart-866d1601-30ad-4d4d-a89f-5873ebcc8b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31656
15077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3165615077
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1987754070
Short name T1493
Test name
Test status
Simulation time 151790446 ps
CPU time 0.82 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206180 kb
Host smart-587a60ec-555b-4af1-a98b-ea33cc8fc5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19877
54070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1987754070
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3958513508
Short name T1431
Test name
Test status
Simulation time 153112112 ps
CPU time 0.82 seconds
Started Jul 06 05:27:01 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206208 kb
Host smart-8ab028ed-9ab3-4a72-86dd-594224264344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
13508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3958513508
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1683801630
Short name T1971
Test name
Test status
Simulation time 147270466 ps
CPU time 0.77 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 206168 kb
Host smart-b68c71bc-5696-4a80-afdc-5d185974164e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16838
01630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1683801630
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4247153510
Short name T484
Test name
Test status
Simulation time 176560390 ps
CPU time 0.86 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206204 kb
Host smart-244aed30-f07d-4295-9c3d-1ba2dc89fc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
53510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4247153510
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.980009059
Short name T1296
Test name
Test status
Simulation time 161536583 ps
CPU time 0.82 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206124 kb
Host smart-535035c4-1dbf-43fe-a2d6-51bc44c909c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98000
9059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.980009059
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3945907289
Short name T2332
Test name
Test status
Simulation time 187988860 ps
CPU time 0.88 seconds
Started Jul 06 05:27:07 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206152 kb
Host smart-5b27abca-9259-426e-ac87-6a95a2cc5617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39459
07289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3945907289
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2446364974
Short name T775
Test name
Test status
Simulation time 3248491822 ps
CPU time 92.06 seconds
Started Jul 06 05:26:56 PM PDT 24
Finished Jul 06 05:28:28 PM PDT 24
Peak memory 206516 kb
Host smart-a4eb601b-d84a-40ee-a547-9f1a770c649d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2446364974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2446364974
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.764772646
Short name T1988
Test name
Test status
Simulation time 186771604 ps
CPU time 0.8 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206200 kb
Host smart-5b6ca366-cb28-4e70-a41e-52df89689d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76477
2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.764772646
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1861446702
Short name T2605
Test name
Test status
Simulation time 164934289 ps
CPU time 0.87 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206120 kb
Host smart-a79b70cb-883c-48f6-9b66-0814f8f1f767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18614
46702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1861446702
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2455515905
Short name T2224
Test name
Test status
Simulation time 1002507060 ps
CPU time 2.27 seconds
Started Jul 06 05:27:01 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206356 kb
Host smart-b4f2af2b-7c5d-408a-abab-b12069710484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
15905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2455515905
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3059704242
Short name T437
Test name
Test status
Simulation time 5481546181 ps
CPU time 38.63 seconds
Started Jul 06 05:26:55 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206380 kb
Host smart-af8973db-187b-4afa-9daf-f360d8f1ccb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30597
04242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3059704242
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1446315766
Short name T1379
Test name
Test status
Simulation time 71192995 ps
CPU time 0.74 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206248 kb
Host smart-dbd6987e-a844-4363-8c84-ed1410b24d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1446315766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1446315766
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.921617549
Short name T2450
Test name
Test status
Simulation time 4309765473 ps
CPU time 4.71 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:07 PM PDT 24
Peak memory 206520 kb
Host smart-f0bbf887-c518-4684-aaeb-f42e2461f10d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=921617549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.921617549
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.601681247
Short name T821
Test name
Test status
Simulation time 13367341491 ps
CPU time 12.6 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206268 kb
Host smart-592c11ee-9fa0-4e1f-ae44-de3b7fc11995
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=601681247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.601681247
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2567666439
Short name T727
Test name
Test status
Simulation time 23465830992 ps
CPU time 22.6 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206412 kb
Host smart-607d2b7c-10d5-477b-a38c-8337fe1308e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2567666439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2567666439
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3941297515
Short name T1795
Test name
Test status
Simulation time 171058411 ps
CPU time 0.78 seconds
Started Jul 06 05:27:05 PM PDT 24
Finished Jul 06 05:27:06 PM PDT 24
Peak memory 206156 kb
Host smart-1b1be035-cf47-4456-86e4-2065d14d33bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
97515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3941297515
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3311482122
Short name T1410
Test name
Test status
Simulation time 187081049 ps
CPU time 0.83 seconds
Started Jul 06 05:27:07 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206156 kb
Host smart-68f540c4-2b8e-43ad-b7b0-0f1bf966cb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33114
82122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3311482122
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3566256292
Short name T1352
Test name
Test status
Simulation time 147488792 ps
CPU time 0.78 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206204 kb
Host smart-6e6a5772-4ef7-4e5d-b9fd-1e60ff5e03a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35662
56292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3566256292
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2115338231
Short name T423
Test name
Test status
Simulation time 427332906 ps
CPU time 1.17 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206164 kb
Host smart-034a26df-1627-4c2f-b9b9-103d5cab1246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21153
38231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2115338231
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.617213780
Short name T1252
Test name
Test status
Simulation time 10593357096 ps
CPU time 19 seconds
Started Jul 06 05:27:07 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206464 kb
Host smart-9dfbad00-d461-43fe-8ffc-f692aadbfc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61721
3780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.617213780
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.1441531958
Short name T501
Test name
Test status
Simulation time 440272603 ps
CPU time 1.39 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206124 kb
Host smart-277f872b-a51c-4225-a15c-f181cc5734bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14415
31958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.1441531958
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2124483286
Short name T1642
Test name
Test status
Simulation time 139904484 ps
CPU time 0.74 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:58 PM PDT 24
Peak memory 206116 kb
Host smart-00be0e67-70c4-48f9-9ec6-89ffaffc29f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
83286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2124483286
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1060995589
Short name T739
Test name
Test status
Simulation time 61105167 ps
CPU time 0.65 seconds
Started Jul 06 05:26:55 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206144 kb
Host smart-a39dee18-5273-4bed-8c0f-831aa96ec657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10609
95589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1060995589
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3065096560
Short name T2075
Test name
Test status
Simulation time 996288274 ps
CPU time 2.42 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206412 kb
Host smart-78a50de7-bda5-42ea-9f53-5df27ba56640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30650
96560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3065096560
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2696916959
Short name T791
Test name
Test status
Simulation time 248703937 ps
CPU time 1.47 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206400 kb
Host smart-57035989-a776-4259-ab22-31acf7e2f171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
16959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2696916959
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2485172075
Short name T1638
Test name
Test status
Simulation time 198982763 ps
CPU time 0.86 seconds
Started Jul 06 05:26:56 PM PDT 24
Finished Jul 06 05:26:57 PM PDT 24
Peak memory 206084 kb
Host smart-ca1c2f32-acb2-4b20-b0f5-fd3b8bd059cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24851
72075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2485172075
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3302008974
Short name T1615
Test name
Test status
Simulation time 150796114 ps
CPU time 0.83 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206172 kb
Host smart-dd81ef05-a243-42a1-aa33-e3544f5e98b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33020
08974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3302008974
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.78673014
Short name T1163
Test name
Test status
Simulation time 176247290 ps
CPU time 0.88 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:59 PM PDT 24
Peak memory 206180 kb
Host smart-824c3f6e-c665-411f-b250-e671578120ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78673
014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.78673014
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2184721098
Short name T418
Test name
Test status
Simulation time 201920630 ps
CPU time 0.82 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206208 kb
Host smart-c2709eff-a644-4b9d-8fd0-697211354782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
21098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2184721098
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2466805487
Short name T2579
Test name
Test status
Simulation time 23313834511 ps
CPU time 29.3 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206268 kb
Host smart-285a1df6-b1cb-4200-b9f7-0e336f2e4a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24668
05487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2466805487
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3486257645
Short name T1103
Test name
Test status
Simulation time 3303678233 ps
CPU time 4.58 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206260 kb
Host smart-451f3bc8-b978-4c3a-8cb0-5f527049b592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34862
57645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3486257645
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2834668434
Short name T2380
Test name
Test status
Simulation time 11549467765 ps
CPU time 333.11 seconds
Started Jul 06 05:26:58 PM PDT 24
Finished Jul 06 05:32:33 PM PDT 24
Peak memory 206556 kb
Host smart-e57b764e-c8cd-417a-8bb8-dc2c30ccdafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28346
68434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2834668434
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3340278059
Short name T1429
Test name
Test status
Simulation time 5949937605 ps
CPU time 56.01 seconds
Started Jul 06 05:26:56 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206404 kb
Host smart-2e706f9f-c0f5-4f56-9547-cce63becf4dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3340278059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3340278059
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1359703556
Short name T612
Test name
Test status
Simulation time 248814685 ps
CPU time 0.91 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206200 kb
Host smart-24bee830-5baa-4201-a5a7-6eae00da7c9d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1359703556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1359703556
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1399459677
Short name T583
Test name
Test status
Simulation time 211278992 ps
CPU time 0.88 seconds
Started Jul 06 05:27:09 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206184 kb
Host smart-bf124062-f512-4461-a7ee-f1bcb95b3ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13994
59677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1399459677
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3244730008
Short name T1101
Test name
Test status
Simulation time 5459864471 ps
CPU time 41.46 seconds
Started Jul 06 05:26:53 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 206460 kb
Host smart-4f5526d7-932d-4644-9b34-cf9ea9777117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32447
30008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3244730008
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.621199476
Short name T2097
Test name
Test status
Simulation time 5206496804 ps
CPU time 36.27 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 206500 kb
Host smart-aa884613-7676-479e-946c-ae33f61a894e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=621199476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.621199476
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.761564977
Short name T2112
Test name
Test status
Simulation time 163629752 ps
CPU time 0.81 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:59 PM PDT 24
Peak memory 206188 kb
Host smart-f1ffc669-9999-45d9-96e8-3f198d88e684
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=761564977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.761564977
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1028245874
Short name T2375
Test name
Test status
Simulation time 175192537 ps
CPU time 0.79 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:00 PM PDT 24
Peak memory 206184 kb
Host smart-5b863c8d-7cb9-4676-8a4e-09000036fa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
45874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1028245874
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4040835904
Short name T135
Test name
Test status
Simulation time 263675475 ps
CPU time 0.93 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206200 kb
Host smart-9603fb21-3461-4711-a91c-98928554aa39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40408
35904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4040835904
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1596724370
Short name T2701
Test name
Test status
Simulation time 174728077 ps
CPU time 0.89 seconds
Started Jul 06 05:26:54 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 206192 kb
Host smart-882752c6-8af9-40a4-937a-a72da9db3cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
24370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1596724370
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.157042684
Short name T596
Test name
Test status
Simulation time 175873955 ps
CPU time 0.78 seconds
Started Jul 06 05:27:04 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206012 kb
Host smart-96ac5990-778e-4d06-85f3-2b251d3ed685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
2684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.157042684
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1203669720
Short name T2649
Test name
Test status
Simulation time 204068456 ps
CPU time 0.81 seconds
Started Jul 06 05:27:07 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206208 kb
Host smart-4e6277a8-5917-4d06-8703-61bf28fdf8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12036
69720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1203669720
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1645543366
Short name T2442
Test name
Test status
Simulation time 165009697 ps
CPU time 0.78 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206188 kb
Host smart-b258436c-0d0f-4643-9c40-2fb4947b60c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16455
43366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1645543366
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.4042767577
Short name T1590
Test name
Test status
Simulation time 214873644 ps
CPU time 0.91 seconds
Started Jul 06 05:26:57 PM PDT 24
Finished Jul 06 05:26:59 PM PDT 24
Peak memory 206200 kb
Host smart-740da5d0-128c-4fdc-b54e-4958d6fb9eb8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4042767577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.4042767577
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.176146198
Short name T694
Test name
Test status
Simulation time 170733392 ps
CPU time 0.79 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:12 PM PDT 24
Peak memory 206208 kb
Host smart-38e5fb55-284f-49dc-83dd-b2f07a195384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17614
6198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.176146198
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2298723490
Short name T2323
Test name
Test status
Simulation time 42443487 ps
CPU time 0.66 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206168 kb
Host smart-b75ce697-60b1-4069-9776-f47ff1a6b059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
23490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2298723490
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3527964090
Short name T267
Test name
Test status
Simulation time 8637094666 ps
CPU time 21.89 seconds
Started Jul 06 05:27:05 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206552 kb
Host smart-5118e70e-05b5-4380-8ae9-c390094c7b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35279
64090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3527964090
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3540468729
Short name T1486
Test name
Test status
Simulation time 213895280 ps
CPU time 0.88 seconds
Started Jul 06 05:27:04 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206188 kb
Host smart-49df476e-82e5-4f90-9c8e-99bae08f64e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35404
68729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3540468729
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.254314596
Short name T1960
Test name
Test status
Simulation time 186763997 ps
CPU time 0.85 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206156 kb
Host smart-5de45437-9ecd-4226-afbc-6840c235651a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25431
4596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.254314596
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1940354980
Short name T676
Test name
Test status
Simulation time 223434478 ps
CPU time 0.86 seconds
Started Jul 06 05:26:59 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206176 kb
Host smart-b65d7f07-2abc-4b78-9442-bbf02de12e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19403
54980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1940354980
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1100589636
Short name T2138
Test name
Test status
Simulation time 144215116 ps
CPU time 0.76 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206128 kb
Host smart-7d79e83a-a2c4-4bbe-9384-6617a20f46df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11005
89636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1100589636
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3744190773
Short name T77
Test name
Test status
Simulation time 186280240 ps
CPU time 0.86 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206200 kb
Host smart-5645d417-416a-484f-9f85-7664fa710f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37441
90773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3744190773
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2001648684
Short name T155
Test name
Test status
Simulation time 145209103 ps
CPU time 0.79 seconds
Started Jul 06 05:27:09 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206044 kb
Host smart-19606ec4-1c5f-404a-8953-b29acd5dd163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20016
48684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2001648684
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2035673008
Short name T953
Test name
Test status
Simulation time 158276306 ps
CPU time 0.74 seconds
Started Jul 06 05:27:00 PM PDT 24
Finished Jul 06 05:27:02 PM PDT 24
Peak memory 206200 kb
Host smart-39c8d05b-94e0-4d8e-acea-c6ed4936a6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20356
73008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2035673008
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1133546822
Short name T2025
Test name
Test status
Simulation time 201474523 ps
CPU time 0.91 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206156 kb
Host smart-7a19fc32-e58c-42d0-ae69-767dd8e28f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
46822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1133546822
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1216858018
Short name T1301
Test name
Test status
Simulation time 6670860524 ps
CPU time 184.19 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 206468 kb
Host smart-ef7b954b-2bd8-4026-897e-335cda0de9aa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1216858018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1216858018
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3581901956
Short name T1120
Test name
Test status
Simulation time 211891320 ps
CPU time 0.91 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206208 kb
Host smart-465bef75-f5ac-4781-9fb5-78c18ae134c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35819
01956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3581901956
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2818190535
Short name T2129
Test name
Test status
Simulation time 155159673 ps
CPU time 0.8 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206116 kb
Host smart-f66339c9-d968-4c0f-ab25-0bcc88e3797f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
90535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2818190535
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1882520943
Short name T1312
Test name
Test status
Simulation time 594475599 ps
CPU time 1.56 seconds
Started Jul 06 05:27:02 PM PDT 24
Finished Jul 06 05:27:04 PM PDT 24
Peak memory 206196 kb
Host smart-067f1590-0b5f-4022-925b-a54f8e727cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825
20943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1882520943
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3500478774
Short name T1796
Test name
Test status
Simulation time 2987769840 ps
CPU time 27.57 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:39 PM PDT 24
Peak memory 206432 kb
Host smart-3bbc8948-8767-4475-a6d9-96c0b92496a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004
78774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3500478774
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2466018149
Short name T2664
Test name
Test status
Simulation time 47967627 ps
CPU time 0.69 seconds
Started Jul 06 05:27:15 PM PDT 24
Finished Jul 06 05:27:16 PM PDT 24
Peak memory 206260 kb
Host smart-9f413c2d-ca29-4a66-9085-b0f2dfd2910e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2466018149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2466018149
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4231440339
Short name T232
Test name
Test status
Simulation time 3472437062 ps
CPU time 4.97 seconds
Started Jul 06 05:27:01 PM PDT 24
Finished Jul 06 05:27:07 PM PDT 24
Peak memory 206268 kb
Host smart-b8c0ba4d-6963-4fff-8197-5ec5807fbf1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4231440339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.4231440339
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1392831067
Short name T1814
Test name
Test status
Simulation time 13384551519 ps
CPU time 13.77 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:24 PM PDT 24
Peak memory 206236 kb
Host smart-8e5f595e-643f-44cf-98de-d05aec5a00d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1392831067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1392831067
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2909436695
Short name T1105
Test name
Test status
Simulation time 23394656507 ps
CPU time 22.71 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206176 kb
Host smart-fd805582-b837-4ff1-91b9-8e4d3f98ea3c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2909436695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2909436695
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3548730241
Short name T800
Test name
Test status
Simulation time 164249508 ps
CPU time 0.82 seconds
Started Jul 06 05:27:04 PM PDT 24
Finished Jul 06 05:27:05 PM PDT 24
Peak memory 206188 kb
Host smart-a2de3cf2-8d6c-42eb-b2d6-fd9601ecfd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35487
30241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3548730241
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.149903005
Short name T651
Test name
Test status
Simulation time 187746984 ps
CPU time 0.85 seconds
Started Jul 06 05:27:17 PM PDT 24
Finished Jul 06 05:27:18 PM PDT 24
Peak memory 206112 kb
Host smart-6865a14b-d7b1-4638-bdab-cd06d9890a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
3005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.149903005
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3396537192
Short name T1350
Test name
Test status
Simulation time 424737629 ps
CPU time 1.44 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206168 kb
Host smart-b91546e4-6291-411d-9ffb-fd5558aa39cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33965
37192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3396537192
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2478949521
Short name T2120
Test name
Test status
Simulation time 675736316 ps
CPU time 1.72 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:27:37 PM PDT 24
Peak memory 206476 kb
Host smart-0ef1e2bb-ca51-44ca-bff5-25ce0bdeada8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24789
49521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2478949521
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2575852386
Short name T99
Test name
Test status
Simulation time 7572694653 ps
CPU time 14.29 seconds
Started Jul 06 05:27:09 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206524 kb
Host smart-e1fa375a-01fe-4247-adfc-185ac1b5144f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25758
52386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2575852386
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3710046177
Short name T1680
Test name
Test status
Simulation time 343820981 ps
CPU time 1.1 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:12 PM PDT 24
Peak memory 206124 kb
Host smart-24a05e27-6f58-4712-b553-eec1734f9450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
46177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3710046177
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3331774088
Short name T2287
Test name
Test status
Simulation time 149867691 ps
CPU time 0.77 seconds
Started Jul 06 05:27:26 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206220 kb
Host smart-9d125300-f6c2-49fb-9782-7c18a0f95d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33317
74088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3331774088
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1515875375
Short name T399
Test name
Test status
Simulation time 63778937 ps
CPU time 0.73 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206180 kb
Host smart-d01b3027-86e2-4edb-85cb-e2657ebfd576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15158
75375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1515875375
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.570503141
Short name T2427
Test name
Test status
Simulation time 770940205 ps
CPU time 1.9 seconds
Started Jul 06 05:27:13 PM PDT 24
Finished Jul 06 05:27:15 PM PDT 24
Peak memory 206456 kb
Host smart-e868c742-a10a-4a1d-a6f0-1c06213a3524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57050
3141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.570503141
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3281221280
Short name T197
Test name
Test status
Simulation time 154167293 ps
CPU time 1.29 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206336 kb
Host smart-afcf585a-5789-40a4-90ea-65f684d40876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32812
21280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3281221280
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3721626206
Short name T1003
Test name
Test status
Simulation time 215890767 ps
CPU time 0.88 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206180 kb
Host smart-4b10515f-5d07-46db-8c48-ba9ca707b0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
26206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3721626206
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3603912995
Short name T504
Test name
Test status
Simulation time 157819242 ps
CPU time 0.8 seconds
Started Jul 06 05:27:05 PM PDT 24
Finished Jul 06 05:27:07 PM PDT 24
Peak memory 206196 kb
Host smart-f043c07e-4939-4d3e-9d35-af3ddadeb31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36039
12995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3603912995
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.638791698
Short name T2086
Test name
Test status
Simulation time 178194860 ps
CPU time 0.84 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:12 PM PDT 24
Peak memory 206120 kb
Host smart-74254f05-3259-42ed-b2d5-193a14b26884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63879
1698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.638791698
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3627905237
Short name T1554
Test name
Test status
Simulation time 7004214540 ps
CPU time 49.64 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206452 kb
Host smart-a1d8f76a-14e3-4009-9a6d-f8b8341b6b13
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3627905237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3627905237
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2541076776
Short name T2239
Test name
Test status
Simulation time 237141633 ps
CPU time 0.91 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206168 kb
Host smart-c6ca3008-f9e9-41f9-8245-89ac0942e255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
76776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2541076776
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.646636441
Short name T664
Test name
Test status
Simulation time 23317844381 ps
CPU time 21.66 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206248 kb
Host smart-e1c1cfcc-30f6-4baa-9db7-9fd6cde7e635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64663
6441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.646636441
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3789977561
Short name T1117
Test name
Test status
Simulation time 3322180446 ps
CPU time 4.04 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206236 kb
Host smart-059bd04d-69d8-48a6-99a0-ea02064753a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37899
77561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3789977561
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1104982763
Short name T1484
Test name
Test status
Simulation time 7569952260 ps
CPU time 207.07 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 206512 kb
Host smart-e831adf7-a157-4451-a756-c04e5156288e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11049
82763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1104982763
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2316908367
Short name T1876
Test name
Test status
Simulation time 2825020407 ps
CPU time 79.67 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:28:26 PM PDT 24
Peak memory 206448 kb
Host smart-64457b99-79de-4003-a41c-ad97651510c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2316908367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2316908367
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.100910236
Short name T1731
Test name
Test status
Simulation time 240639165 ps
CPU time 0.86 seconds
Started Jul 06 05:27:27 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206184 kb
Host smart-fa9f2e1a-f26f-4559-a85c-d5dba99114a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=100910236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.100910236
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2493839929
Short name T324
Test name
Test status
Simulation time 180100140 ps
CPU time 0.87 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:08 PM PDT 24
Peak memory 206160 kb
Host smart-41d99a21-535c-4007-b8b6-0fa96f16249f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
39929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2493839929
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1714254701
Short name T947
Test name
Test status
Simulation time 6340092635 ps
CPU time 59.33 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206516 kb
Host smart-ae9bc124-895b-4168-b9c7-b1bd72647ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
54701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1714254701
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1871280985
Short name T89
Test name
Test status
Simulation time 2693686799 ps
CPU time 26.37 seconds
Started Jul 06 05:27:06 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206436 kb
Host smart-78ebe0f6-99d4-49cb-952a-88cc23a57d9b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1871280985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1871280985
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1017717281
Short name T1837
Test name
Test status
Simulation time 148033638 ps
CPU time 0.85 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206200 kb
Host smart-b2f1243e-178c-497a-a7a4-cde37502ecec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1017717281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1017717281
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1129605488
Short name T956
Test name
Test status
Simulation time 144350479 ps
CPU time 0.79 seconds
Started Jul 06 05:27:09 PM PDT 24
Finished Jul 06 05:27:11 PM PDT 24
Peak memory 206188 kb
Host smart-e2516e18-84a3-411b-ab1e-5aa799f574b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
05488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1129605488
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2758586105
Short name T132
Test name
Test status
Simulation time 200616563 ps
CPU time 0.81 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206196 kb
Host smart-a3635fa0-96cd-4b14-ba95-59f1b9216f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27585
86105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2758586105
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.4078557322
Short name T2076
Test name
Test status
Simulation time 174892025 ps
CPU time 0.84 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206200 kb
Host smart-dbc47309-ff0b-4134-b8ca-56150697ce57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
57322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.4078557322
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2431090070
Short name T458
Test name
Test status
Simulation time 181384582 ps
CPU time 0.83 seconds
Started Jul 06 05:27:07 PM PDT 24
Finished Jul 06 05:27:09 PM PDT 24
Peak memory 206180 kb
Host smart-6e119494-45bb-4d3d-b273-c5902f041799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24310
90070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2431090070
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2353400749
Short name T2527
Test name
Test status
Simulation time 181860713 ps
CPU time 0.81 seconds
Started Jul 06 05:27:08 PM PDT 24
Finished Jul 06 05:27:10 PM PDT 24
Peak memory 206160 kb
Host smart-3a757748-71de-464e-8110-69c96f8191f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534
00749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2353400749
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1763829757
Short name T2530
Test name
Test status
Simulation time 156348295 ps
CPU time 0.81 seconds
Started Jul 06 05:27:17 PM PDT 24
Finished Jul 06 05:27:18 PM PDT 24
Peak memory 206164 kb
Host smart-58eb0e14-710a-4c89-8159-41a6f914d3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17638
29757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1763829757
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3310307887
Short name T2395
Test name
Test status
Simulation time 257351581 ps
CPU time 1.08 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206180 kb
Host smart-8626c5a3-4c3c-4c78-a332-f61e8df45048
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3310307887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3310307887
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1015957835
Short name T2588
Test name
Test status
Simulation time 142189165 ps
CPU time 0.8 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206164 kb
Host smart-db77687f-4a45-4a63-b122-fa1ed3176b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10159
57835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1015957835
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1479624151
Short name T2051
Test name
Test status
Simulation time 56720673 ps
CPU time 0.7 seconds
Started Jul 06 05:27:16 PM PDT 24
Finished Jul 06 05:27:17 PM PDT 24
Peak memory 206152 kb
Host smart-00a4d331-96a7-4afc-8c7e-2ff2a5777088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14796
24151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1479624151
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.337484695
Short name T94
Test name
Test status
Simulation time 12514539603 ps
CPU time 27.82 seconds
Started Jul 06 05:27:14 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206528 kb
Host smart-4b2e42db-8a53-4964-8262-01cb26959341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
4695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.337484695
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3723469771
Short name T388
Test name
Test status
Simulation time 206497087 ps
CPU time 0.93 seconds
Started Jul 06 05:27:17 PM PDT 24
Finished Jul 06 05:27:19 PM PDT 24
Peak memory 206120 kb
Host smart-96c98f01-510d-4475-a9cc-0da4275ae7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37234
69771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3723469771
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3901201147
Short name T570
Test name
Test status
Simulation time 175868297 ps
CPU time 0.81 seconds
Started Jul 06 05:27:13 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206124 kb
Host smart-e54fa88e-4538-43d8-a6d0-30f0589cad44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
01147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3901201147
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3560512714
Short name T1652
Test name
Test status
Simulation time 191358271 ps
CPU time 0.87 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206184 kb
Host smart-2f4be662-74dc-476b-ac49-edfc39b685c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35605
12714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3560512714
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3018243778
Short name T2508
Test name
Test status
Simulation time 154962062 ps
CPU time 0.88 seconds
Started Jul 06 05:27:13 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206192 kb
Host smart-cc9398aa-514e-4276-9e2b-209ee40ad5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30182
43778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3018243778
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1865437127
Short name T483
Test name
Test status
Simulation time 185707078 ps
CPU time 0.86 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:13 PM PDT 24
Peak memory 206204 kb
Host smart-85189e59-1f59-4128-a2fc-6eb2f06471b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18654
37127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1865437127
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3820462500
Short name T1579
Test name
Test status
Simulation time 154678343 ps
CPU time 0.77 seconds
Started Jul 06 05:27:13 PM PDT 24
Finished Jul 06 05:27:14 PM PDT 24
Peak memory 206172 kb
Host smart-8b3e4cee-5397-4341-8497-8702b61d7307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204
62500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3820462500
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3453265527
Short name T530
Test name
Test status
Simulation time 151775968 ps
CPU time 0.78 seconds
Started Jul 06 05:27:14 PM PDT 24
Finished Jul 06 05:27:16 PM PDT 24
Peak memory 206164 kb
Host smart-1bb1a2c1-946b-4da9-b78e-d93f80dec1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
65527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3453265527
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1229506317
Short name T2351
Test name
Test status
Simulation time 234841564 ps
CPU time 0.91 seconds
Started Jul 06 05:27:38 PM PDT 24
Finished Jul 06 05:27:39 PM PDT 24
Peak memory 206156 kb
Host smart-58307ccb-b7ec-4ab6-975f-d6e5b1d3d1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12295
06317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1229506317
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2178842598
Short name T2261
Test name
Test status
Simulation time 3703435712 ps
CPU time 105.03 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206484 kb
Host smart-d24fbe01-861b-403c-b34e-cf0652a54880
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2178842598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2178842598
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2888105882
Short name T635
Test name
Test status
Simulation time 156755914 ps
CPU time 0.77 seconds
Started Jul 06 05:27:14 PM PDT 24
Finished Jul 06 05:27:15 PM PDT 24
Peak memory 206192 kb
Host smart-1f22239f-951f-45c3-984b-ea647df3b939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
05882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2888105882
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1847339426
Short name T338
Test name
Test status
Simulation time 161045055 ps
CPU time 0.79 seconds
Started Jul 06 05:27:10 PM PDT 24
Finished Jul 06 05:27:12 PM PDT 24
Peak memory 206180 kb
Host smart-02e11dfc-417e-4877-9254-ffb44f193206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18473
39426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1847339426
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1260741224
Short name T1198
Test name
Test status
Simulation time 981537951 ps
CPU time 2.19 seconds
Started Jul 06 05:27:12 PM PDT 24
Finished Jul 06 05:27:15 PM PDT 24
Peak memory 206372 kb
Host smart-510c2222-de49-4877-9965-4e5f6f58b5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
41224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1260741224
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3637241850
Short name T1384
Test name
Test status
Simulation time 6192097593 ps
CPU time 59.53 seconds
Started Jul 06 05:27:15 PM PDT 24
Finished Jul 06 05:28:15 PM PDT 24
Peak memory 206456 kb
Host smart-4c8ee402-28f8-4650-a97e-e8dec2557b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372
41850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3637241850
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.385007126
Short name T561
Test name
Test status
Simulation time 41122093 ps
CPU time 0.7 seconds
Started Jul 06 05:27:20 PM PDT 24
Finished Jul 06 05:27:21 PM PDT 24
Peak memory 206164 kb
Host smart-4bbaa5af-f230-4e6a-b332-2d9b0a4d8c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=385007126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.385007126
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1566909279
Short name T610
Test name
Test status
Simulation time 4109323630 ps
CPU time 5.9 seconds
Started Jul 06 05:27:33 PM PDT 24
Finished Jul 06 05:27:40 PM PDT 24
Peak memory 206220 kb
Host smart-b91020c0-65a8-47be-815e-737a6ab11eda
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1566909279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1566909279
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1659407852
Short name T1353
Test name
Test status
Simulation time 13344304234 ps
CPU time 13.43 seconds
Started Jul 06 05:27:14 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206264 kb
Host smart-fc82d220-852b-4500-b9d0-43e5b19928cb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1659407852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1659407852
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3344769814
Short name T565
Test name
Test status
Simulation time 23330810144 ps
CPU time 28.85 seconds
Started Jul 06 05:27:15 PM PDT 24
Finished Jul 06 05:27:44 PM PDT 24
Peak memory 206256 kb
Host smart-b9ac8e06-ccd0-4bc2-a61e-a9daf82c2b56
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3344769814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3344769814
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1642614203
Short name T667
Test name
Test status
Simulation time 158345448 ps
CPU time 0.78 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206156 kb
Host smart-561306b1-0e9c-41d7-be68-f17d892bfcfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
14203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1642614203
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2266170695
Short name T1344
Test name
Test status
Simulation time 197069347 ps
CPU time 0.78 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206188 kb
Host smart-91f6b6e1-7a19-4357-a0f1-b7064afa6221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22661
70695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2266170695
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.4254372254
Short name T784
Test name
Test status
Simulation time 190179050 ps
CPU time 0.92 seconds
Started Jul 06 05:27:43 PM PDT 24
Finished Jul 06 05:27:44 PM PDT 24
Peak memory 206176 kb
Host smart-14dcca8b-8e14-4aff-87c6-b5996cc9c50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
72254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.4254372254
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_device_address.240702549
Short name T1326
Test name
Test status
Simulation time 11730447471 ps
CPU time 23.22 seconds
Started Jul 06 05:27:11 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206516 kb
Host smart-8b5ba872-5732-4fe5-a78e-6bee9f5384a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24070
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.240702549
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2605593416
Short name T1775
Test name
Test status
Simulation time 434700816 ps
CPU time 1.28 seconds
Started Jul 06 05:27:20 PM PDT 24
Finished Jul 06 05:27:22 PM PDT 24
Peak memory 206180 kb
Host smart-4f895d0f-8f36-4628-a81b-af1b3f24f577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26055
93416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2605593416
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2050730039
Short name T2034
Test name
Test status
Simulation time 130468072 ps
CPU time 0.76 seconds
Started Jul 06 05:27:18 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206204 kb
Host smart-adfb7db0-74f0-468e-98d4-78ac0ced86ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20507
30039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2050730039
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.591753279
Short name T2196
Test name
Test status
Simulation time 32463946 ps
CPU time 0.67 seconds
Started Jul 06 05:27:17 PM PDT 24
Finished Jul 06 05:27:18 PM PDT 24
Peak memory 206192 kb
Host smart-5737d17c-271f-49e8-b8a8-8f33f6704fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59175
3279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.591753279
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2782155254
Short name T1383
Test name
Test status
Simulation time 920052425 ps
CPU time 2.21 seconds
Started Jul 06 05:27:38 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206400 kb
Host smart-3c7a2665-e445-4ef9-bb71-a9ef58dd9dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27821
55254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2782155254
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3630314194
Short name T834
Test name
Test status
Simulation time 171629818 ps
CPU time 1.33 seconds
Started Jul 06 05:27:17 PM PDT 24
Finished Jul 06 05:27:19 PM PDT 24
Peak memory 206384 kb
Host smart-08658aa8-3067-4e1c-a512-adacc80c15d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
14194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3630314194
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3665332461
Short name T395
Test name
Test status
Simulation time 139423831 ps
CPU time 0.78 seconds
Started Jul 06 05:27:19 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206196 kb
Host smart-60b19a23-fa03-47fe-a1db-8f6ccc2f6a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36653
32461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3665332461
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1129244926
Short name T2067
Test name
Test status
Simulation time 166445284 ps
CPU time 0.84 seconds
Started Jul 06 05:27:41 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206012 kb
Host smart-9c6cc7dc-a422-42d6-b2ba-a3e5d5ad000a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292
44926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1129244926
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3757254951
Short name T1320
Test name
Test status
Simulation time 7661283057 ps
CPU time 208.67 seconds
Started Jul 06 05:27:24 PM PDT 24
Finished Jul 06 05:30:53 PM PDT 24
Peak memory 206512 kb
Host smart-17c73936-98de-4744-a434-c152c060fd09
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3757254951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3757254951
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1657213881
Short name T1220
Test name
Test status
Simulation time 265293857 ps
CPU time 0.98 seconds
Started Jul 06 05:27:36 PM PDT 24
Finished Jul 06 05:27:38 PM PDT 24
Peak memory 206204 kb
Host smart-40dafde2-3779-45e9-bc2a-39fae8e7d405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572
13881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1657213881
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1818984631
Short name T754
Test name
Test status
Simulation time 23331530295 ps
CPU time 21.5 seconds
Started Jul 06 05:27:18 PM PDT 24
Finished Jul 06 05:27:40 PM PDT 24
Peak memory 206240 kb
Host smart-9d600c04-5669-41c0-8d49-a2408a4ee83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
84631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1818984631
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.325621549
Short name T2610
Test name
Test status
Simulation time 3379135420 ps
CPU time 3.77 seconds
Started Jul 06 05:27:23 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206148 kb
Host smart-4bd06f53-7837-441f-a55d-ff2f5b5b553b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32562
1549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.325621549
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2012046567
Short name T1073
Test name
Test status
Simulation time 9786687313 ps
CPU time 278.19 seconds
Started Jul 06 05:27:18 PM PDT 24
Finished Jul 06 05:31:57 PM PDT 24
Peak memory 214704 kb
Host smart-b8f8f61e-7b25-40a3-bd63-6a0eb1d203d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
46567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2012046567
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3875236571
Short name T1031
Test name
Test status
Simulation time 7360154654 ps
CPU time 53.74 seconds
Started Jul 06 05:27:36 PM PDT 24
Finished Jul 06 05:28:30 PM PDT 24
Peak memory 206508 kb
Host smart-8dfa2b3a-e209-4600-89df-920d906bd002
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3875236571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3875236571
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.284960352
Short name T1305
Test name
Test status
Simulation time 232458372 ps
CPU time 0.86 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206144 kb
Host smart-f006f70d-56d6-4cda-9c23-1d2020573b3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=284960352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.284960352
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2048305264
Short name T885
Test name
Test status
Simulation time 195903212 ps
CPU time 0.89 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206108 kb
Host smart-c5c77008-ae36-4362-b0f7-61cedfb5237d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483
05264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2048305264
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2411687345
Short name T2614
Test name
Test status
Simulation time 6771890227 ps
CPU time 46.84 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206380 kb
Host smart-fe231046-efe4-4835-bcde-624cc874fee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24116
87345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2411687345
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3204550355
Short name T499
Test name
Test status
Simulation time 6277794444 ps
CPU time 181.26 seconds
Started Jul 06 05:27:19 PM PDT 24
Finished Jul 06 05:30:21 PM PDT 24
Peak memory 206464 kb
Host smart-757a87a4-b35f-44ba-aec0-e6ce6c2a0081
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3204550355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3204550355
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3515187365
Short name T815
Test name
Test status
Simulation time 169805645 ps
CPU time 0.79 seconds
Started Jul 06 05:27:30 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206156 kb
Host smart-afc88123-f9a7-4ffd-8c48-e3d8547ef0ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3515187365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3515187365
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1335544198
Short name T30
Test name
Test status
Simulation time 178796737 ps
CPU time 0.79 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 206144 kb
Host smart-4d191ecc-e8ea-44ad-8dd4-b12bfae27193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13355
44198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1335544198
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1279215270
Short name T2127
Test name
Test status
Simulation time 207344881 ps
CPU time 0.85 seconds
Started Jul 06 05:27:19 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206172 kb
Host smart-cbe49c28-e478-4168-b853-6a0b4a45efe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792
15270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1279215270
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1951052957
Short name T1859
Test name
Test status
Simulation time 188196345 ps
CPU time 0.83 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206160 kb
Host smart-b3eb5566-083a-464a-9b45-5cf0a8053450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19510
52957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1951052957
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.908970125
Short name T455
Test name
Test status
Simulation time 235821888 ps
CPU time 0.82 seconds
Started Jul 06 05:27:31 PM PDT 24
Finished Jul 06 05:27:32 PM PDT 24
Peak memory 206012 kb
Host smart-7d451519-bb41-4666-a481-c6f13aeda368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90897
0125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.908970125
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2606879032
Short name T937
Test name
Test status
Simulation time 268250935 ps
CPU time 0.96 seconds
Started Jul 06 05:27:20 PM PDT 24
Finished Jul 06 05:27:21 PM PDT 24
Peak memory 206188 kb
Host smart-9c6c374e-7e2d-4747-91f5-a2472eb47d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
79032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2606879032
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.785973959
Short name T1443
Test name
Test status
Simulation time 182476341 ps
CPU time 0.8 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206148 kb
Host smart-10c500dd-9337-45ab-92a7-4e92ad0de2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78597
3959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.785973959
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2238546624
Short name T2276
Test name
Test status
Simulation time 223720248 ps
CPU time 0.92 seconds
Started Jul 06 05:27:38 PM PDT 24
Finished Jul 06 05:27:39 PM PDT 24
Peak memory 206116 kb
Host smart-6f7fbc33-186f-4bbf-a3ad-de5b4d5fa256
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2238546624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2238546624
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1063461227
Short name T1400
Test name
Test status
Simulation time 163448095 ps
CPU time 0.79 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 206180 kb
Host smart-d874d6c2-1e36-4877-a1b5-490994f8f914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10634
61227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1063461227
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1421066938
Short name T1401
Test name
Test status
Simulation time 80861326 ps
CPU time 0.69 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206192 kb
Host smart-4a6f0303-35a5-462f-a89a-ed919d228099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14210
66938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1421066938
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1745603388
Short name T2230
Test name
Test status
Simulation time 13080630410 ps
CPU time 27.68 seconds
Started Jul 06 05:27:19 PM PDT 24
Finished Jul 06 05:27:47 PM PDT 24
Peak memory 206484 kb
Host smart-9d31cdef-c7f0-4069-ac49-fbccb1368e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17456
03388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1745603388
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.647588446
Short name T300
Test name
Test status
Simulation time 149034110 ps
CPU time 0.78 seconds
Started Jul 06 05:27:19 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206176 kb
Host smart-3a2a8383-7bd5-4062-903b-27b295eb0d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64758
8446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.647588446
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.997401645
Short name T1417
Test name
Test status
Simulation time 186241517 ps
CPU time 0.86 seconds
Started Jul 06 05:27:18 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206164 kb
Host smart-801fddf8-90fb-48fd-a536-ab9e46c4cbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99740
1645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.997401645
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2114951884
Short name T687
Test name
Test status
Simulation time 230478268 ps
CPU time 0.96 seconds
Started Jul 06 05:27:19 PM PDT 24
Finished Jul 06 05:27:20 PM PDT 24
Peak memory 206192 kb
Host smart-d0803d6f-fbc0-42ea-9bfd-f15bc44aa5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21149
51884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2114951884
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1113553205
Short name T2663
Test name
Test status
Simulation time 198947295 ps
CPU time 0.86 seconds
Started Jul 06 05:27:36 PM PDT 24
Finished Jul 06 05:27:38 PM PDT 24
Peak memory 206136 kb
Host smart-97f08baf-3158-448f-a543-2ae7dcb39a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
53205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1113553205
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3159586775
Short name T2148
Test name
Test status
Simulation time 192421945 ps
CPU time 0.88 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:27:48 PM PDT 24
Peak memory 206176 kb
Host smart-ae2c0c0f-7caf-44d0-a3f1-8637e3457a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
86775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3159586775
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.433335003
Short name T2085
Test name
Test status
Simulation time 170307739 ps
CPU time 0.8 seconds
Started Jul 06 05:27:23 PM PDT 24
Finished Jul 06 05:27:24 PM PDT 24
Peak memory 206084 kb
Host smart-eafd73f0-2cf4-474d-881e-bddd57ae86aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43333
5003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.433335003
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.4090065648
Short name T2486
Test name
Test status
Simulation time 145549648 ps
CPU time 0.82 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:47 PM PDT 24
Peak memory 206012 kb
Host smart-f0da262d-cf32-435e-b32e-aa721ee53747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40900
65648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.4090065648
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3087412781
Short name T884
Test name
Test status
Simulation time 249246400 ps
CPU time 0.98 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:24 PM PDT 24
Peak memory 206164 kb
Host smart-364e4008-4562-4756-95f5-792330fc6dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30874
12781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3087412781
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2539937470
Short name T2139
Test name
Test status
Simulation time 5141451447 ps
CPU time 37.62 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206496 kb
Host smart-dfe49c10-37e3-4d4a-af23-5a0fbcd024a8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2539937470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2539937470
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.946738856
Short name T753
Test name
Test status
Simulation time 183228055 ps
CPU time 0.82 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:27:36 PM PDT 24
Peak memory 206176 kb
Host smart-0eb300cc-f050-4856-8e9b-e9ecf4cc35e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94673
8856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.946738856
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.96573543
Short name T2680
Test name
Test status
Simulation time 177342598 ps
CPU time 0.79 seconds
Started Jul 06 05:27:31 PM PDT 24
Finished Jul 06 05:27:32 PM PDT 24
Peak memory 206012 kb
Host smart-65cf9130-a422-41f3-b8b0-1b24f51ed919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96573
543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.96573543
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2199960884
Short name T2160
Test name
Test status
Simulation time 996463030 ps
CPU time 2.12 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:48 PM PDT 24
Peak memory 206400 kb
Host smart-2be77b81-a25f-4eb8-8a04-aebf8a623819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
60884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2199960884
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3642875806
Short name T361
Test name
Test status
Simulation time 5559700902 ps
CPU time 144.38 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 206324 kb
Host smart-4a854d64-5a84-4f49-bdf3-73a36ebcfcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
75806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3642875806
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.529736783
Short name T932
Test name
Test status
Simulation time 105665994 ps
CPU time 0.77 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206136 kb
Host smart-28441dea-be03-431f-ae9a-7893613c7bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=529736783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.529736783
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2578896350
Short name T898
Test name
Test status
Simulation time 3512186591 ps
CPU time 4.48 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:55 PM PDT 24
Peak memory 206240 kb
Host smart-1b4aa727-1b36-4152-a3cf-fb73d0990ca0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2578896350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2578896350
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2622497586
Short name T640
Test name
Test status
Simulation time 13455537158 ps
CPU time 13.66 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206496 kb
Host smart-62b4be66-09de-4de1-9227-2b79e3a09f82
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2622497586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2622497586
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1546339109
Short name T1598
Test name
Test status
Simulation time 23303952120 ps
CPU time 24.4 seconds
Started Jul 06 05:27:25 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206232 kb
Host smart-d0dbec1a-7d31-4828-b831-69f832ac602f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1546339109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1546339109
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3394045910
Short name T2696
Test name
Test status
Simulation time 181260722 ps
CPU time 0.86 seconds
Started Jul 06 05:27:20 PM PDT 24
Finished Jul 06 05:27:21 PM PDT 24
Peak memory 206200 kb
Host smart-ce1b26d4-8562-4d5a-913a-fc1c3d6e600d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33940
45910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3394045910
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2429379280
Short name T863
Test name
Test status
Simulation time 161340097 ps
CPU time 0.78 seconds
Started Jul 06 05:27:37 PM PDT 24
Finished Jul 06 05:27:39 PM PDT 24
Peak memory 206168 kb
Host smart-6d55f90d-8417-46ab-9e4a-68f9ef63965d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24293
79280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2429379280
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.537354368
Short name T1650
Test name
Test status
Simulation time 440068892 ps
CPU time 1.4 seconds
Started Jul 06 05:27:51 PM PDT 24
Finished Jul 06 05:27:53 PM PDT 24
Peak memory 206160 kb
Host smart-5d8fb871-9434-490c-9a16-f960699ff30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53735
4368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.537354368
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3888847990
Short name T106
Test name
Test status
Simulation time 814788674 ps
CPU time 1.84 seconds
Started Jul 06 05:27:43 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206424 kb
Host smart-1bf91410-24dc-4231-82ea-015e868b891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38888
47990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3888847990
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.4178382148
Short name T1084
Test name
Test status
Simulation time 11163172898 ps
CPU time 21.48 seconds
Started Jul 06 05:27:38 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206480 kb
Host smart-7f20bfbc-7a5c-4592-9d62-2c65b9b7b73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783
82148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4178382148
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1527225501
Short name T1748
Test name
Test status
Simulation time 493877727 ps
CPU time 1.38 seconds
Started Jul 06 05:27:24 PM PDT 24
Finished Jul 06 05:27:25 PM PDT 24
Peak memory 206120 kb
Host smart-f8275bc9-80d1-45bf-9117-d40878fbe0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15272
25501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1527225501
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1440177048
Short name T1799
Test name
Test status
Simulation time 145988841 ps
CPU time 0.79 seconds
Started Jul 06 05:27:26 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206176 kb
Host smart-79076b0b-2c9f-46a4-8a06-40d408542d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401
77048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1440177048
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.4047323889
Short name T1032
Test name
Test status
Simulation time 49487642 ps
CPU time 0.73 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206180 kb
Host smart-6d04720c-75fb-4dfd-98af-3908aee3aaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40473
23889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.4047323889
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3753410040
Short name T1030
Test name
Test status
Simulation time 1000862444 ps
CPU time 2.43 seconds
Started Jul 06 05:27:39 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206464 kb
Host smart-214e0c08-9f39-4f6e-a95d-a90d05c7c73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37534
10040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3753410040
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2531707442
Short name T2201
Test name
Test status
Simulation time 234153851 ps
CPU time 1.36 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206392 kb
Host smart-7ecdd98a-23a7-4d2d-b345-9537563c10f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25317
07442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2531707442
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.533462387
Short name T1249
Test name
Test status
Simulation time 161102438 ps
CPU time 0.77 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206080 kb
Host smart-7d9b099a-52e2-475d-8e39-003f37a6eeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53346
2387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.533462387
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.778494044
Short name T2012
Test name
Test status
Simulation time 155973370 ps
CPU time 0.81 seconds
Started Jul 06 05:27:26 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206196 kb
Host smart-c69b35a5-116f-4aeb-a742-b193daed95a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77849
4044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.778494044
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1708995294
Short name T1372
Test name
Test status
Simulation time 273935488 ps
CPU time 0.99 seconds
Started Jul 06 05:27:28 PM PDT 24
Finished Jul 06 05:27:29 PM PDT 24
Peak memory 206084 kb
Host smart-49f64d04-f645-403f-b926-763a25f7d7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
95294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1708995294
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2775279709
Short name T2608
Test name
Test status
Simulation time 7328277904 ps
CPU time 70.22 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206468 kb
Host smart-c99b670e-611a-443d-9209-71d921700a79
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2775279709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2775279709
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1260192905
Short name T1114
Test name
Test status
Simulation time 192846321 ps
CPU time 0.83 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206204 kb
Host smart-5a1f5f08-a703-4f12-914d-223582b29b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12601
92905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1260192905
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1574585363
Short name T1984
Test name
Test status
Simulation time 23310198046 ps
CPU time 24.78 seconds
Started Jul 06 05:27:37 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206260 kb
Host smart-18d9df5d-3716-47ed-b6e6-9b81754a85d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
85363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1574585363
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2095093357
Short name T2126
Test name
Test status
Simulation time 3282253910 ps
CPU time 3.61 seconds
Started Jul 06 05:27:46 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206280 kb
Host smart-58aa6451-9cbf-42db-855e-c8d7360ad189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
93357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2095093357
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1925262497
Short name T1583
Test name
Test status
Simulation time 7488526705 ps
CPU time 201.2 seconds
Started Jul 06 05:27:42 PM PDT 24
Finished Jul 06 05:31:03 PM PDT 24
Peak memory 206532 kb
Host smart-1b896ef1-d513-4425-9bb5-04651003290a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19252
62497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1925262497
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3117605781
Short name T371
Test name
Test status
Simulation time 6855848136 ps
CPU time 185.53 seconds
Started Jul 06 05:27:24 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 206436 kb
Host smart-40eccbe8-63a9-46b0-a3d5-e5e095ff95d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3117605781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3117605781
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.699043487
Short name T1445
Test name
Test status
Simulation time 244341777 ps
CPU time 0.9 seconds
Started Jul 06 05:27:33 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206184 kb
Host smart-74f1704b-9829-480d-b68f-5597d3371a3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=699043487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.699043487
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.896289572
Short name T744
Test name
Test status
Simulation time 192428705 ps
CPU time 0.87 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 205988 kb
Host smart-806499ae-909e-4ead-a286-e6463fead1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89628
9572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.896289572
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.515841329
Short name T1803
Test name
Test status
Simulation time 4236647304 ps
CPU time 30.24 seconds
Started Jul 06 05:27:25 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206500 kb
Host smart-70d05296-4be7-46b8-b0ac-394187ee7c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51584
1329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.515841329
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1332260408
Short name T2551
Test name
Test status
Simulation time 3128723122 ps
CPU time 86.84 seconds
Started Jul 06 05:27:25 PM PDT 24
Finished Jul 06 05:28:52 PM PDT 24
Peak memory 206436 kb
Host smart-9adbc24b-021c-4286-ab17-1f5e25915bb2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1332260408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1332260408
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.590064635
Short name T934
Test name
Test status
Simulation time 173896531 ps
CPU time 0.81 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206140 kb
Host smart-359d0468-f3c7-4c73-8680-3faa7a7bb584
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=590064635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.590064635
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2202570508
Short name T607
Test name
Test status
Simulation time 147148114 ps
CPU time 0.81 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206140 kb
Host smart-3388f1e2-99d7-4572-b2e8-743dff8682a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
70508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2202570508
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2043680055
Short name T122
Test name
Test status
Simulation time 200228794 ps
CPU time 0.88 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206176 kb
Host smart-2a78235c-eacb-4bb3-bf7f-d578791e2b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20436
80055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2043680055
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2059120857
Short name T764
Test name
Test status
Simulation time 180957538 ps
CPU time 0.91 seconds
Started Jul 06 05:27:24 PM PDT 24
Finished Jul 06 05:27:25 PM PDT 24
Peak memory 206116 kb
Host smart-a6ff2e3f-0c3a-4827-a86b-73ae20451b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
20857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2059120857
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3202759303
Short name T1407
Test name
Test status
Simulation time 153433146 ps
CPU time 0.83 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:24 PM PDT 24
Peak memory 206192 kb
Host smart-c9b144e2-2e38-45f3-8372-e71ebfecbb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32027
59303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3202759303
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1533338992
Short name T354
Test name
Test status
Simulation time 155401087 ps
CPU time 0.76 seconds
Started Jul 06 05:27:26 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206204 kb
Host smart-5d895618-beca-4b97-b975-6b07e12016ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15333
38992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1533338992
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.498926676
Short name T782
Test name
Test status
Simulation time 146919858 ps
CPU time 0.76 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206192 kb
Host smart-705a8daa-859a-4e4b-9a29-7cabfc3e354c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49892
6676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.498926676
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.956955926
Short name T871
Test name
Test status
Simulation time 216981286 ps
CPU time 0.92 seconds
Started Jul 06 05:27:26 PM PDT 24
Finished Jul 06 05:27:27 PM PDT 24
Peak memory 206168 kb
Host smart-d6ae7618-2fdb-4baa-b464-f20e29589f0c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=956955926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.956955926
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.329291182
Short name T597
Test name
Test status
Simulation time 185701520 ps
CPU time 0.78 seconds
Started Jul 06 05:27:43 PM PDT 24
Finished Jul 06 05:27:44 PM PDT 24
Peak memory 206124 kb
Host smart-8e1e3810-a1ee-4596-99a4-b069894d324a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32929
1182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.329291182
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2519087294
Short name T1358
Test name
Test status
Simulation time 104313919 ps
CPU time 0.72 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206076 kb
Host smart-e6306105-b9ae-44ec-8353-366379bab05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
87294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2519087294
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3897672960
Short name T954
Test name
Test status
Simulation time 11451052652 ps
CPU time 24.82 seconds
Started Jul 06 05:27:24 PM PDT 24
Finished Jul 06 05:27:49 PM PDT 24
Peak memory 206536 kb
Host smart-0388fbf4-1d0c-417b-a30d-5f1231f64e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38976
72960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3897672960
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2049299274
Short name T2645
Test name
Test status
Simulation time 161587584 ps
CPU time 0.81 seconds
Started Jul 06 05:27:36 PM PDT 24
Finished Jul 06 05:27:37 PM PDT 24
Peak memory 206016 kb
Host smart-f8730f1d-a17f-4353-b91a-ce0972a1e4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20492
99274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2049299274
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2781078848
Short name T2391
Test name
Test status
Simulation time 177628107 ps
CPU time 0.89 seconds
Started Jul 06 05:27:22 PM PDT 24
Finished Jul 06 05:27:23 PM PDT 24
Peak memory 206144 kb
Host smart-38c30a9d-4627-4973-8432-671aa9b02338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27810
78848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2781078848
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.64120607
Short name T1474
Test name
Test status
Simulation time 216280105 ps
CPU time 0.87 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206212 kb
Host smart-dd80d77b-c544-4c0e-892a-113fb2aeb855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64120
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.64120607
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2772421057
Short name T2152
Test name
Test status
Simulation time 186848708 ps
CPU time 0.85 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:27:49 PM PDT 24
Peak memory 206160 kb
Host smart-a36502fa-6137-4302-a710-4190d013377d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27724
21057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2772421057
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3085442275
Short name T439
Test name
Test status
Simulation time 188914948 ps
CPU time 0.87 seconds
Started Jul 06 05:27:26 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206204 kb
Host smart-029299fb-83d5-4169-b57c-5571e43dffee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854
42275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3085442275
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3188364766
Short name T1632
Test name
Test status
Simulation time 200651064 ps
CPU time 0.79 seconds
Started Jul 06 05:27:25 PM PDT 24
Finished Jul 06 05:27:26 PM PDT 24
Peak memory 206164 kb
Host smart-b148ed67-9e6e-4da4-84da-d326bdaaa8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31883
64766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3188364766
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1755186430
Short name T1662
Test name
Test status
Simulation time 147180854 ps
CPU time 0.77 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206128 kb
Host smart-47d9826e-95df-493f-bf52-ac68ac56ef3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
86430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1755186430
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2087715144
Short name T601
Test name
Test status
Simulation time 242014724 ps
CPU time 1.01 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206108 kb
Host smart-681a0043-c034-4f37-a962-e880f312f727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
15144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2087715144
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2076074277
Short name T474
Test name
Test status
Simulation time 5843043031 ps
CPU time 56.37 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206496 kb
Host smart-1443fc01-9e8c-4814-838a-b0c00058a426
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2076074277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2076074277
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3460567853
Short name T2606
Test name
Test status
Simulation time 196427065 ps
CPU time 0.83 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 206160 kb
Host smart-2f21f9fe-f421-4536-b080-f12881b9519b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34605
67853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3460567853
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1483105216
Short name T1660
Test name
Test status
Simulation time 205140170 ps
CPU time 0.8 seconds
Started Jul 06 05:27:27 PM PDT 24
Finished Jul 06 05:27:28 PM PDT 24
Peak memory 206168 kb
Host smart-2bd7f647-bd6b-4717-8cf1-7ce9c171b5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
05216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1483105216
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2099854711
Short name T2173
Test name
Test status
Simulation time 1176937425 ps
CPU time 2.51 seconds
Started Jul 06 05:27:55 PM PDT 24
Finished Jul 06 05:27:58 PM PDT 24
Peak memory 206428 kb
Host smart-4783de1c-2881-4d91-8c4a-b6d4dae1cb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998
54711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2099854711
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.4235974987
Short name T1000
Test name
Test status
Simulation time 7703278088 ps
CPU time 52.64 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206304 kb
Host smart-874360d1-829d-482a-8138-2ae6fa2984f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42359
74987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.4235974987
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1668363597
Short name T1318
Test name
Test status
Simulation time 66067085 ps
CPU time 0.7 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:47 PM PDT 24
Peak memory 206268 kb
Host smart-dc15d759-50b4-40e1-a268-751195894f21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1668363597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1668363597
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2040465019
Short name T2594
Test name
Test status
Simulation time 3593813715 ps
CPU time 4.38 seconds
Started Jul 06 05:27:28 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206168 kb
Host smart-56f2feb3-d151-421b-a769-13dd10e52fbe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2040465019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2040465019
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1901410050
Short name T1619
Test name
Test status
Simulation time 13388217434 ps
CPU time 13.2 seconds
Started Jul 06 05:27:31 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206264 kb
Host smart-10789f3e-0e6d-4ee4-818b-89ac1551c684
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1901410050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1901410050
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.4153029756
Short name T1102
Test name
Test status
Simulation time 23301363259 ps
CPU time 23.45 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:54 PM PDT 24
Peak memory 206268 kb
Host smart-e4beb5fb-317c-4133-a285-1539b9f080ee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4153029756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.4153029756
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1280207273
Short name T1328
Test name
Test status
Simulation time 219125460 ps
CPU time 0.88 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206188 kb
Host smart-7aa286fb-c14d-4482-8491-43e3c2b96ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
07273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1280207273
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1619413335
Short name T1166
Test name
Test status
Simulation time 198371044 ps
CPU time 0.8 seconds
Started Jul 06 05:27:30 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206116 kb
Host smart-6b0519ab-89f7-4ef6-815f-c47916036585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16194
13335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1619413335
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.269464589
Short name T63
Test name
Test status
Simulation time 414273902 ps
CPU time 1.47 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206060 kb
Host smart-378701e5-18ff-44fa-b6cf-e1492bc27289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26946
4589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.269464589
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.4239947104
Short name T183
Test name
Test status
Simulation time 485314838 ps
CPU time 1.44 seconds
Started Jul 06 05:27:37 PM PDT 24
Finished Jul 06 05:27:39 PM PDT 24
Peak memory 206120 kb
Host smart-e5da9d23-1bcd-4315-8488-09186a3fa51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42399
47104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.4239947104
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2770028599
Short name T1356
Test name
Test status
Simulation time 21404178583 ps
CPU time 46.42 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:28:17 PM PDT 24
Peak memory 206444 kb
Host smart-ce651846-a571-40d4-b4d2-6ff257bee030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
28599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2770028599
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.959256127
Short name T86
Test name
Test status
Simulation time 488628403 ps
CPU time 1.39 seconds
Started Jul 06 05:27:28 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 206148 kb
Host smart-cefb9d43-969a-43e0-91a8-418ff96e8f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95925
6127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.959256127
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2971655793
Short name T47
Test name
Test status
Simulation time 182140536 ps
CPU time 0.81 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206184 kb
Host smart-4936c41c-1169-4ae3-9bde-1a9ce9d44375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29716
55793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2971655793
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3768285352
Short name T333
Test name
Test status
Simulation time 81093625 ps
CPU time 0.81 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206184 kb
Host smart-94193d4b-3877-4b81-8e9b-e14834f3ba10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37682
85352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3768285352
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2832896711
Short name T1500
Test name
Test status
Simulation time 879073904 ps
CPU time 2.11 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206440 kb
Host smart-7016e5ba-e853-47b1-ae17-051d8350f23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
96711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2832896711
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.414614202
Short name T2484
Test name
Test status
Simulation time 222873219 ps
CPU time 1.44 seconds
Started Jul 06 05:27:33 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 206392 kb
Host smart-d1c2f2a2-6552-42d6-8f05-40e5eb01927f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
4202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.414614202
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3289297901
Short name T1714
Test name
Test status
Simulation time 185948575 ps
CPU time 0.81 seconds
Started Jul 06 05:27:28 PM PDT 24
Finished Jul 06 05:27:29 PM PDT 24
Peak memory 206168 kb
Host smart-c211a0f0-89fd-46e5-9a1d-34591cf44c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
97901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3289297901
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.62371910
Short name T1489
Test name
Test status
Simulation time 196679277 ps
CPU time 0.78 seconds
Started Jul 06 05:27:27 PM PDT 24
Finished Jul 06 05:27:29 PM PDT 24
Peak memory 206200 kb
Host smart-92b811c3-1ab2-4bb1-9c5e-a521457ed6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62371
910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.62371910
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.4130216181
Short name T1197
Test name
Test status
Simulation time 220704231 ps
CPU time 0.93 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206196 kb
Host smart-3592d894-79f1-4078-8e9e-42cd32e5dadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41302
16181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.4130216181
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.717666207
Short name T2079
Test name
Test status
Simulation time 232874803 ps
CPU time 0.89 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206204 kb
Host smart-e817409f-d729-4767-85a5-402b4c3c3d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71766
6207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.717666207
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1310533945
Short name T2202
Test name
Test status
Simulation time 23311179374 ps
CPU time 23.36 seconds
Started Jul 06 05:27:31 PM PDT 24
Finished Jul 06 05:27:54 PM PDT 24
Peak memory 206236 kb
Host smart-ee731f63-6eed-4fe3-8878-e50fc66244e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13105
33945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1310533945
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.364846076
Short name T2046
Test name
Test status
Simulation time 3282063003 ps
CPU time 3.89 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206164 kb
Host smart-28524816-47f2-4cbf-b877-f8c26c6ea57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36484
6076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.364846076
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2227730450
Short name T5
Test name
Test status
Simulation time 5057336308 ps
CPU time 131.8 seconds
Started Jul 06 05:27:31 PM PDT 24
Finished Jul 06 05:29:43 PM PDT 24
Peak memory 206408 kb
Host smart-9f32c219-8c3b-4a40-b214-22ac54824780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22277
30450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2227730450
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.923446429
Short name T1717
Test name
Test status
Simulation time 7918891645 ps
CPU time 217.63 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:31:29 PM PDT 24
Peak memory 206272 kb
Host smart-3dd13b59-b10e-4e03-9abd-73cb6be58740
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=923446429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.923446429
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3911598720
Short name T818
Test name
Test status
Simulation time 245206866 ps
CPU time 0.88 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:47 PM PDT 24
Peak memory 206192 kb
Host smart-e63d1169-2ae8-41de-ac10-e82d2cbc5733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3911598720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3911598720
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1911168597
Short name T742
Test name
Test status
Simulation time 203066703 ps
CPU time 0.87 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:33 PM PDT 24
Peak memory 206092 kb
Host smart-2b03229b-8a22-4ec7-8eb4-51fba428e4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19111
68597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1911168597
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.61038474
Short name T1060
Test name
Test status
Simulation time 6430245205 ps
CPU time 58.94 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:28:53 PM PDT 24
Peak memory 206480 kb
Host smart-3236f1d9-278e-4969-8b1b-e70335a4b1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61038
474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.61038474
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1268404613
Short name T325
Test name
Test status
Simulation time 4469204700 ps
CPU time 31.41 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:28:21 PM PDT 24
Peak memory 206368 kb
Host smart-abc1e28f-d846-4b48-a092-480f7db8f700
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1268404613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1268404613
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2772051360
Short name T820
Test name
Test status
Simulation time 157205105 ps
CPU time 0.84 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206156 kb
Host smart-3372e484-ad9b-4cba-81a2-43cae9539b1b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2772051360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2772051360
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3553596254
Short name T430
Test name
Test status
Simulation time 152958632 ps
CPU time 0.76 seconds
Started Jul 06 05:27:30 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206160 kb
Host smart-19256b7a-6730-4b15-bd22-b8d1366680f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35535
96254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3553596254
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.74912400
Short name T120
Test name
Test status
Simulation time 186962475 ps
CPU time 0.93 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206128 kb
Host smart-24859cda-2eb4-4e79-9792-a59366e74e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74912
400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.74912400
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.2684586753
Short name T1269
Test name
Test status
Simulation time 173406138 ps
CPU time 0.85 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206184 kb
Host smart-49c2ec2b-aa12-4e29-909b-8e961f0840ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26845
86753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2684586753
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2621267315
Short name T29
Test name
Test status
Simulation time 205152761 ps
CPU time 0.9 seconds
Started Jul 06 05:27:51 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206112 kb
Host smart-85991761-1a22-4e23-b487-3e6de5417242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26212
67315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2621267315
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1846824063
Short name T908
Test name
Test status
Simulation time 180156540 ps
CPU time 0.85 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206212 kb
Host smart-788f7d5b-9b65-4cca-98de-48ea01100218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18468
24063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1846824063
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2118678448
Short name T182
Test name
Test status
Simulation time 147040884 ps
CPU time 0.8 seconds
Started Jul 06 05:27:30 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206156 kb
Host smart-ad93522d-c473-4692-8716-20763d3d657e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21186
78448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2118678448
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.534480444
Short name T1021
Test name
Test status
Simulation time 192446043 ps
CPU time 0.91 seconds
Started Jul 06 05:27:32 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206112 kb
Host smart-20f0aaae-5a1e-4921-91ed-0cca96114ce8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=534480444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.534480444
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1719906894
Short name T1542
Test name
Test status
Simulation time 147941220 ps
CPU time 0.86 seconds
Started Jul 06 05:27:29 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206180 kb
Host smart-9d9ab92a-aeed-47fa-b338-aabb97fdd8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17199
06894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1719906894
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.73836674
Short name T1671
Test name
Test status
Simulation time 34099504 ps
CPU time 0.66 seconds
Started Jul 06 05:27:30 PM PDT 24
Finished Jul 06 05:27:31 PM PDT 24
Peak memory 206196 kb
Host smart-75ecd6d4-69ec-4430-b075-1779a1319447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73836
674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.73836674
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1406485536
Short name T1830
Test name
Test status
Simulation time 18566198807 ps
CPU time 45.29 seconds
Started Jul 06 05:27:46 PM PDT 24
Finished Jul 06 05:28:32 PM PDT 24
Peak memory 206540 kb
Host smart-2e77a987-c685-4916-99c5-e00eaea68bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14064
85536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1406485536
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3591984801
Short name T387
Test name
Test status
Simulation time 194895009 ps
CPU time 0.88 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206196 kb
Host smart-dcec5549-c2da-4916-8701-b37491827405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35919
84801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3591984801
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.152199794
Short name T2004
Test name
Test status
Simulation time 240006177 ps
CPU time 0.89 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:27:48 PM PDT 24
Peak memory 206208 kb
Host smart-dbbcb3c7-da7c-4868-8fa2-5722a279f4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15219
9794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.152199794
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.492580727
Short name T1404
Test name
Test status
Simulation time 191977481 ps
CPU time 0.88 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:55 PM PDT 24
Peak memory 206124 kb
Host smart-2624c261-70b2-4e0a-8493-0ef4a3f3dd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49258
0727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.492580727
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4147861396
Short name T478
Test name
Test status
Simulation time 183336212 ps
CPU time 0.83 seconds
Started Jul 06 05:27:46 PM PDT 24
Finished Jul 06 05:27:47 PM PDT 24
Peak memory 206168 kb
Host smart-965dcbb3-4f0a-4b2c-9d8f-cfe0ed0d65d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478
61396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4147861396
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2660035444
Short name T1039
Test name
Test status
Simulation time 138249189 ps
CPU time 0.78 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206160 kb
Host smart-2380eba9-3e39-4c6d-ad51-d2e2e0d60995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26600
35444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2660035444
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.76834042
Short name T2302
Test name
Test status
Simulation time 159150696 ps
CPU time 0.77 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206176 kb
Host smart-859bbaab-faf7-4cfa-85fc-63525a39bbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76834
042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.76834042
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.985973393
Short name T1468
Test name
Test status
Simulation time 170641143 ps
CPU time 0.78 seconds
Started Jul 06 05:27:53 PM PDT 24
Finished Jul 06 05:27:54 PM PDT 24
Peak memory 206196 kb
Host smart-28db51e8-e652-4b80-bc28-03815339ac43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98597
3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.985973393
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1271555448
Short name T626
Test name
Test status
Simulation time 177170161 ps
CPU time 0.86 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:55 PM PDT 24
Peak memory 206172 kb
Host smart-f728c8b0-1188-4fab-9a55-7e5a1b064341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12715
55448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1271555448
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2938039470
Short name T1828
Test name
Test status
Simulation time 3395138988 ps
CPU time 25.69 seconds
Started Jul 06 05:27:34 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206424 kb
Host smart-246ed7bd-891e-422c-a522-c67884a40d6d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2938039470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2938039470
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2424382021
Short name T772
Test name
Test status
Simulation time 179828381 ps
CPU time 0.84 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206164 kb
Host smart-e603af66-4512-444c-b202-547623bd6d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
82021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2424382021
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.4248771636
Short name T1815
Test name
Test status
Simulation time 150999321 ps
CPU time 0.8 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:27:36 PM PDT 24
Peak memory 206164 kb
Host smart-7410b8eb-092c-4610-b396-296618fc511d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
71636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.4248771636
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2418558121
Short name T1709
Test name
Test status
Simulation time 260161674 ps
CPU time 0.95 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:27:36 PM PDT 24
Peak memory 206124 kb
Host smart-64211938-d585-4e73-845d-c6c70a171b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24185
58121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2418558121
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1667622830
Short name T1430
Test name
Test status
Simulation time 3694265343 ps
CPU time 34.59 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206416 kb
Host smart-1ae03bc0-d13a-43cf-a1a6-60345527a178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16676
22830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1667622830
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1008714691
Short name T1845
Test name
Test status
Simulation time 60423682 ps
CPU time 0.67 seconds
Started Jul 06 05:27:57 PM PDT 24
Finished Jul 06 05:27:58 PM PDT 24
Peak memory 206156 kb
Host smart-77ee168c-5800-4058-8be9-0b37172b67ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1008714691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1008714691
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2275933666
Short name T1421
Test name
Test status
Simulation time 3765711148 ps
CPU time 4.44 seconds
Started Jul 06 05:27:57 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206460 kb
Host smart-3455b89d-8035-4299-9893-1cf863cae2c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2275933666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2275933666
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1764933670
Short name T1317
Test name
Test status
Simulation time 13365603391 ps
CPU time 13.18 seconds
Started Jul 06 05:27:38 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206180 kb
Host smart-7b1dc877-4391-4d55-8528-8e56bf716297
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1764933670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1764933670
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3336877773
Short name T2398
Test name
Test status
Simulation time 23388745604 ps
CPU time 22.01 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206432 kb
Host smart-a9dae068-2ceb-4f2d-b040-3800017476f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3336877773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3336877773
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1658835108
Short name T2431
Test name
Test status
Simulation time 159448961 ps
CPU time 0.84 seconds
Started Jul 06 05:27:34 PM PDT 24
Finished Jul 06 05:27:36 PM PDT 24
Peak memory 206180 kb
Host smart-6c476fbd-1cd8-460a-818f-0251c9bbd7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16588
35108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1658835108
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.314954531
Short name T260
Test name
Test status
Simulation time 186762343 ps
CPU time 0.89 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:27:36 PM PDT 24
Peak memory 206120 kb
Host smart-0d48220b-54c0-4aa2-920a-51315d32745f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
4531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.314954531
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.4237679893
Short name T178
Test name
Test status
Simulation time 511734936 ps
CPU time 1.62 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:27:37 PM PDT 24
Peak memory 206384 kb
Host smart-517a3766-f11c-415e-af15-fab297cc975b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42376
79893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.4237679893
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2832002935
Short name T1494
Test name
Test status
Simulation time 1220461404 ps
CPU time 2.73 seconds
Started Jul 06 05:27:55 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206412 kb
Host smart-faeb6819-f99c-4011-a669-b7c26cafc65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28320
02935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2832002935
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.299184023
Short name T545
Test name
Test status
Simulation time 13599934485 ps
CPU time 28.1 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:28:23 PM PDT 24
Peak memory 206436 kb
Host smart-fcca3da3-2e8a-43e3-b211-7892776b6b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29918
4023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.299184023
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1555690776
Short name T1931
Test name
Test status
Simulation time 465040506 ps
CPU time 1.32 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206196 kb
Host smart-4999d992-8b67-467c-ada7-e6ddbbc375f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15556
90776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1555690776
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2878623351
Short name T652
Test name
Test status
Simulation time 139019339 ps
CPU time 0.76 seconds
Started Jul 06 05:27:51 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206208 kb
Host smart-29f4a799-bac2-48d1-ac88-34c72a5f48ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28786
23351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2878623351
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3952302238
Short name T935
Test name
Test status
Simulation time 50591032 ps
CPU time 0.68 seconds
Started Jul 06 05:27:33 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206164 kb
Host smart-c397d71f-74d3-4d85-9767-42a463f9367a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
02238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3952302238
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3989606231
Short name T1504
Test name
Test status
Simulation time 846174247 ps
CPU time 2 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206396 kb
Host smart-b49737a4-0a63-41b7-9e04-59a328262814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39896
06231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3989606231
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2867920593
Short name T1925
Test name
Test status
Simulation time 270452704 ps
CPU time 1.57 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206288 kb
Host smart-7411e4fe-f69e-4ce8-bd9e-a66808dc1d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28679
20593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2867920593
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3757601215
Short name T1635
Test name
Test status
Simulation time 265674010 ps
CPU time 0.94 seconds
Started Jul 06 05:27:38 PM PDT 24
Finished Jul 06 05:27:39 PM PDT 24
Peak memory 206096 kb
Host smart-fffa095a-6d80-4340-8fa1-774c6320b786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37576
01215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3757601215
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.401448247
Short name T1027
Test name
Test status
Simulation time 150353230 ps
CPU time 0.74 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206176 kb
Host smart-481cda3e-bb4e-4b59-82df-dcb9de50334f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40144
8247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.401448247
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.204083088
Short name T1908
Test name
Test status
Simulation time 219821268 ps
CPU time 0.9 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:27:52 PM PDT 24
Peak memory 206180 kb
Host smart-d8a55047-a344-4e9c-b2bc-7a8619f7cad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20408
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.204083088
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3900327341
Short name T1958
Test name
Test status
Simulation time 192305519 ps
CPU time 0.86 seconds
Started Jul 06 05:27:34 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 206204 kb
Host smart-d741f127-51a6-47ab-b16b-f203f234b2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003
27341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3900327341
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1429407294
Short name T1663
Test name
Test status
Simulation time 23335911380 ps
CPU time 24.11 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:28:15 PM PDT 24
Peak memory 206212 kb
Host smart-825c3ac5-226b-4e27-85ca-f743fb7a3d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14294
07294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1429407294
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.171157663
Short name T1810
Test name
Test status
Simulation time 3331195196 ps
CPU time 3.68 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206244 kb
Host smart-80a3bcc5-2a3d-4688-a911-cb2efe1bec87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17115
7663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.171157663
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1513185641
Short name T1047
Test name
Test status
Simulation time 10947854159 ps
CPU time 80.27 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:29:13 PM PDT 24
Peak memory 206488 kb
Host smart-d0d02cf2-ace0-4de7-a75f-11979d5d11b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
85641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1513185641
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.42016993
Short name T1327
Test name
Test status
Simulation time 6350734188 ps
CPU time 59.67 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206444 kb
Host smart-fa9a4464-1788-4656-ab19-e85759409fe9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=42016993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.42016993
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1129702113
Short name T2264
Test name
Test status
Simulation time 260692071 ps
CPU time 0.9 seconds
Started Jul 06 05:27:33 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206200 kb
Host smart-0519b203-4e59-4810-b53c-8a6ad5f8c1d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1129702113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1129702113
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2425799379
Short name T1843
Test name
Test status
Simulation time 216675738 ps
CPU time 0.89 seconds
Started Jul 06 05:27:33 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 206184 kb
Host smart-783cd122-8ff5-4c69-b548-a3129f6875b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
99379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2425799379
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3718382064
Short name T948
Test name
Test status
Simulation time 4276977734 ps
CPU time 123.31 seconds
Started Jul 06 05:27:35 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 206424 kb
Host smart-1387a80b-d316-4546-b5b2-fa796424af70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37183
82064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3718382064
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1879146154
Short name T1780
Test name
Test status
Simulation time 5596186114 ps
CPU time 39.97 seconds
Started Jul 06 05:27:39 PM PDT 24
Finished Jul 06 05:28:20 PM PDT 24
Peak memory 206352 kb
Host smart-2db71bba-7caa-4a61-ae20-9deac2e39a75
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1879146154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1879146154
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2660003620
Short name T704
Test name
Test status
Simulation time 179692415 ps
CPU time 0.84 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:27:58 PM PDT 24
Peak memory 206176 kb
Host smart-aee7b205-9ed8-4132-a95e-60728156f95d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2660003620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2660003620
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3461657087
Short name T1975
Test name
Test status
Simulation time 161766758 ps
CPU time 0.87 seconds
Started Jul 06 05:27:37 PM PDT 24
Finished Jul 06 05:27:38 PM PDT 24
Peak memory 206172 kb
Host smart-ee6115f2-74cd-4527-bbb0-1bc08a353380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34616
57087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3461657087
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3090036691
Short name T2597
Test name
Test status
Simulation time 189407670 ps
CPU time 0.87 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:55 PM PDT 24
Peak memory 206156 kb
Host smart-5e17bab0-3eea-4a66-ae40-e75a35d93e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
36691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3090036691
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.952211224
Short name T810
Test name
Test status
Simulation time 167573282 ps
CPU time 0.79 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:49 PM PDT 24
Peak memory 206200 kb
Host smart-f6d9ef5a-fc54-4170-9ef5-7f3536836034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95221
1224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.952211224
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2221021139
Short name T419
Test name
Test status
Simulation time 186683813 ps
CPU time 0.87 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206208 kb
Host smart-3e4b7e21-62c7-47fa-8770-db07e28af316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22210
21139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2221021139
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.321187257
Short name T2024
Test name
Test status
Simulation time 181378720 ps
CPU time 0.78 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206180 kb
Host smart-93b1c4bd-cfe0-47c5-996a-55f5dd1ec2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
7257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.321187257
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.4198805251
Short name T2460
Test name
Test status
Simulation time 247524333 ps
CPU time 0.94 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206188 kb
Host smart-fe49beb8-78d1-4868-a819-ae59f66c82de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4198805251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.4198805251
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2846978231
Short name T1043
Test name
Test status
Simulation time 213699365 ps
CPU time 0.82 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206184 kb
Host smart-fa3431d9-bb86-4eee-ab25-f1a817fddc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28469
78231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2846978231
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2862930572
Short name T737
Test name
Test status
Simulation time 35974066 ps
CPU time 0.65 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206148 kb
Host smart-33128e6e-3a70-4afe-84df-ec8c6c14fb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28629
30572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2862930572
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1304463605
Short name T1655
Test name
Test status
Simulation time 19596703445 ps
CPU time 45.06 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206496 kb
Host smart-c458a62a-50a6-426b-b04f-6c696d660dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13044
63605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1304463605
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2340887697
Short name T1545
Test name
Test status
Simulation time 204946735 ps
CPU time 0.89 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206192 kb
Host smart-3d12b9dd-3081-4da6-a9b4-e100f4093580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
87697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2340887697
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.788230642
Short name T1113
Test name
Test status
Simulation time 229692369 ps
CPU time 0.94 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206124 kb
Host smart-282917f4-242b-41d5-8630-fe9e18ae4c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78823
0642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.788230642
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.3710255202
Short name T2028
Test name
Test status
Simulation time 255783641 ps
CPU time 0.95 seconds
Started Jul 06 05:27:37 PM PDT 24
Finished Jul 06 05:27:38 PM PDT 24
Peak memory 206188 kb
Host smart-b66f8988-52d4-4c26-8293-04d6a59073c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
55202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.3710255202
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2327409831
Short name T805
Test name
Test status
Simulation time 164577665 ps
CPU time 0.82 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206116 kb
Host smart-fc6fc9a1-4020-408d-926e-04af8289eef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23274
09831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2327409831
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.606792239
Short name T412
Test name
Test status
Simulation time 192325124 ps
CPU time 0.85 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206224 kb
Host smart-0f7de717-9531-4e95-9c30-ecc975a62427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60679
2239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.606792239
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1996583079
Short name T2223
Test name
Test status
Simulation time 155732216 ps
CPU time 0.76 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206176 kb
Host smart-8659feb0-c296-4607-939f-ebd96122432d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19965
83079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1996583079
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4158750365
Short name T949
Test name
Test status
Simulation time 185851786 ps
CPU time 0.89 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206164 kb
Host smart-33c88da1-5533-4a66-89ed-c3c47d1f5249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41587
50365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4158750365
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3970138066
Short name T897
Test name
Test status
Simulation time 198718185 ps
CPU time 0.89 seconds
Started Jul 06 05:27:39 PM PDT 24
Finished Jul 06 05:27:41 PM PDT 24
Peak memory 206168 kb
Host smart-6d8b0dd3-5c40-4d22-89c1-78bcbb5f6dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39701
38066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3970138066
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.516734913
Short name T1319
Test name
Test status
Simulation time 4067258963 ps
CPU time 115.47 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:29:45 PM PDT 24
Peak memory 206516 kb
Host smart-4527979e-cc71-4dee-840d-09c8af58eb33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=516734913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.516734913
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3773371547
Short name T831
Test name
Test status
Simulation time 154668667 ps
CPU time 0.81 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 205916 kb
Host smart-7c64517a-1d18-48c3-8239-f793fc9cec65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
71547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3773371547
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.17916818
Short name T1165
Test name
Test status
Simulation time 174893499 ps
CPU time 0.8 seconds
Started Jul 06 05:27:55 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206192 kb
Host smart-998cb6d1-138f-43c0-a9af-91b17f927620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.17916818
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2161002903
Short name T2008
Test name
Test status
Simulation time 973126798 ps
CPU time 2.3 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206344 kb
Host smart-9c9cf613-7ea0-49ab-aa05-b6f4446f883e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21610
02903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2161002903
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3228578551
Short name T1266
Test name
Test status
Simulation time 3910643444 ps
CPU time 35.89 seconds
Started Jul 06 05:27:46 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206384 kb
Host smart-e2b3f617-2d3c-47db-87e4-f64f39a08343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285
78551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3228578551
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.4099571328
Short name T200
Test name
Test status
Simulation time 35934669 ps
CPU time 0.68 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:27:48 PM PDT 24
Peak memory 206244 kb
Host smart-b45fc586-7921-48d9-a1e3-026cc0aec03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4099571328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.4099571328
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1851037283
Short name T1885
Test name
Test status
Simulation time 3790310454 ps
CPU time 4.55 seconds
Started Jul 06 05:27:39 PM PDT 24
Finished Jul 06 05:27:43 PM PDT 24
Peak memory 206236 kb
Host smart-5c428b36-d4ee-4e77-90e5-f554d323864a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1851037283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1851037283
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.195129294
Short name T2142
Test name
Test status
Simulation time 13350120780 ps
CPU time 15.06 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206268 kb
Host smart-2bb9292a-e690-4e07-8405-223e91865168
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=195129294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.195129294
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.647710372
Short name T1146
Test name
Test status
Simulation time 23381271263 ps
CPU time 25.09 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206256 kb
Host smart-3013706b-152f-43d6-aa95-369a3d07545a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=647710372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.647710372
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1974068723
Short name T1947
Test name
Test status
Simulation time 179377872 ps
CPU time 0.83 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206112 kb
Host smart-f0814c7f-98a5-4b12-8064-6ca581080d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19740
68723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1974068723
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2472975643
Short name T648
Test name
Test status
Simulation time 157104153 ps
CPU time 0.78 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206208 kb
Host smart-77b3f914-2f78-4b3d-8afd-e493f673ee0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24729
75643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2472975643
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1708947179
Short name T543
Test name
Test status
Simulation time 322041505 ps
CPU time 1.19 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206204 kb
Host smart-adc0fd5e-271e-44f0-9175-1e20c2baa155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
47179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1708947179
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3891285253
Short name T179
Test name
Test status
Simulation time 836237595 ps
CPU time 1.98 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206400 kb
Host smart-0c232623-f12f-4b44-bc13-80261df3a6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38912
85253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3891285253
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3245709451
Short name T922
Test name
Test status
Simulation time 10138291822 ps
CPU time 20.69 seconds
Started Jul 06 05:27:41 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206452 kb
Host smart-dc3f6510-43da-4edb-9a7b-58b64b13bfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
09451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3245709451
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.368780226
Short name T1967
Test name
Test status
Simulation time 487917498 ps
CPU time 1.38 seconds
Started Jul 06 05:27:58 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206192 kb
Host smart-1231ca7d-0b50-4738-8ee5-59e5284ffdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36878
0226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.368780226
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1529575403
Short name T1213
Test name
Test status
Simulation time 158323110 ps
CPU time 0.75 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206204 kb
Host smart-895fc0fd-42dd-4209-a4ff-66aa18eb8ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15295
75403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1529575403
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1019580821
Short name T682
Test name
Test status
Simulation time 112848225 ps
CPU time 0.71 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:06 PM PDT 24
Peak memory 206112 kb
Host smart-80dd6b2d-5f61-40db-8ba3-f94c5a859d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
80821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1019580821
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1345889307
Short name T1786
Test name
Test status
Simulation time 984519980 ps
CPU time 2.47 seconds
Started Jul 06 05:27:39 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206400 kb
Host smart-bad88c2f-dd73-4222-9bc3-14ddf5a7f701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
89307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1345889307
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.148065737
Short name T874
Test name
Test status
Simulation time 187173495 ps
CPU time 1.75 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:27:53 PM PDT 24
Peak memory 206352 kb
Host smart-6b6fa54c-ea98-44b2-9da9-e44422265679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14806
5737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.148065737
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.605080650
Short name T1585
Test name
Test status
Simulation time 154708979 ps
CPU time 0.82 seconds
Started Jul 06 05:27:40 PM PDT 24
Finished Jul 06 05:27:42 PM PDT 24
Peak memory 206192 kb
Host smart-1de7aa61-2f9d-4b9a-83a6-a979d4c88e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60508
0650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.605080650
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.993515673
Short name T996
Test name
Test status
Simulation time 139539391 ps
CPU time 0.76 seconds
Started Jul 06 05:27:58 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206156 kb
Host smart-a48c4fe3-de34-447d-a4dd-8b9e11455510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99351
5673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.993515673
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2320073818
Short name T1834
Test name
Test status
Simulation time 237741476 ps
CPU time 1.03 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206172 kb
Host smart-e1cd129d-58d3-4a94-a66f-d5460791b633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23200
73818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2320073818
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.3131890011
Short name T79
Test name
Test status
Simulation time 8331272758 ps
CPU time 58.72 seconds
Started Jul 06 05:27:41 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206464 kb
Host smart-cdbc690e-5f77-4582-b6fb-cec92a9dcb3c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3131890011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3131890011
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1383440676
Short name T2483
Test name
Test status
Simulation time 171297218 ps
CPU time 0.9 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206160 kb
Host smart-86667746-4d0a-418a-a33f-7cf646592bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13834
40676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1383440676
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.699579608
Short name T611
Test name
Test status
Simulation time 23266040246 ps
CPU time 21.09 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206264 kb
Host smart-832778d8-2766-4a3c-b4a8-69f9a96765a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69957
9608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.699579608
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1602958444
Short name T2354
Test name
Test status
Simulation time 3281523664 ps
CPU time 3.75 seconds
Started Jul 06 05:28:06 PM PDT 24
Finished Jul 06 05:28:10 PM PDT 24
Peak memory 206244 kb
Host smart-d692314b-2f33-4a18-a69d-786df46cd487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16029
58444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1602958444
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.177746668
Short name T377
Test name
Test status
Simulation time 8880695345 ps
CPU time 63.38 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:29:07 PM PDT 24
Peak memory 206504 kb
Host smart-ade4ed21-35d1-476e-878b-6a5161246caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17774
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.177746668
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2051243644
Short name T2437
Test name
Test status
Simulation time 7843397424 ps
CPU time 217.75 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:31:25 PM PDT 24
Peak memory 206692 kb
Host smart-3ec14d30-8acd-43f3-a59d-67968bec6b73
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2051243644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2051243644
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1100161667
Short name T2513
Test name
Test status
Simulation time 241190265 ps
CPU time 0.93 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206168 kb
Host smart-db85d8ec-a62d-49a7-a108-b615de9dd7ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1100161667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1100161667
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.586074942
Short name T2002
Test name
Test status
Simulation time 193067197 ps
CPU time 0.85 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:27:48 PM PDT 24
Peak memory 206184 kb
Host smart-802c449c-054a-48ab-b9fc-d6ba444d7928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58607
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.586074942
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.4099435588
Short name T2387
Test name
Test status
Simulation time 6228133039 ps
CPU time 42.36 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206460 kb
Host smart-eb24214a-bcd7-4ace-9340-761989513e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
35588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.4099435588
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2726935462
Short name T785
Test name
Test status
Simulation time 6142699903 ps
CPU time 60.45 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206428 kb
Host smart-295a72f1-b751-4ff4-82ab-ab1aec4dfc03
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2726935462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2726935462
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3445297051
Short name T2500
Test name
Test status
Simulation time 167745021 ps
CPU time 0.81 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206172 kb
Host smart-51104b38-fa8f-4a23-a842-f9afbebf01f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3445297051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3445297051
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4249909266
Short name T1423
Test name
Test status
Simulation time 153474843 ps
CPU time 0.8 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206136 kb
Host smart-479ac957-9244-42db-9d8b-27439fd14ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
09266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4249909266
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1923817045
Short name T1634
Test name
Test status
Simulation time 192951690 ps
CPU time 0.85 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206196 kb
Host smart-2cefff6e-0ae9-4149-91de-b491405bafe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
17045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1923817045
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.550058135
Short name T1557
Test name
Test status
Simulation time 155533184 ps
CPU time 0.77 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206024 kb
Host smart-df086903-d98f-4116-ac2f-105ff5513b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55005
8135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.550058135
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3691116634
Short name T1568
Test name
Test status
Simulation time 222424971 ps
CPU time 0.88 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206176 kb
Host smart-4bd0b034-304d-4a03-bc8e-ee3a69be8c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911
16634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3691116634
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.363199591
Short name T1776
Test name
Test status
Simulation time 146983059 ps
CPU time 0.76 seconds
Started Jul 06 05:27:43 PM PDT 24
Finished Jul 06 05:27:44 PM PDT 24
Peak memory 206204 kb
Host smart-edfda557-554c-40e3-b0e9-a81afaf0a5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
9591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.363199591
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2192140565
Short name T2245
Test name
Test status
Simulation time 189620287 ps
CPU time 0.82 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 206168 kb
Host smart-4e0df3d5-e207-4331-b8a3-aad92250cae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21921
40565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2192140565
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2969168804
Short name T1966
Test name
Test status
Simulation time 198138216 ps
CPU time 0.95 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 206204 kb
Host smart-935a979a-318e-4b25-b0ce-c5a16423adfc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2969168804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2969168804
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1339347990
Short name T2479
Test name
Test status
Simulation time 137893875 ps
CPU time 0.76 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206428 kb
Host smart-ff650c86-488e-4fbb-a2cc-980b16d483cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13393
47990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1339347990
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2400922875
Short name T2651
Test name
Test status
Simulation time 43320669 ps
CPU time 0.71 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:45 PM PDT 24
Peak memory 206180 kb
Host smart-06d1ea49-2a81-496d-bcda-4e79114e153e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24009
22875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2400922875
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2919534624
Short name T1939
Test name
Test status
Simulation time 16788798706 ps
CPU time 35.98 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:29:20 PM PDT 24
Peak memory 205456 kb
Host smart-0c00d1f5-137f-4b04-8bdd-b38eb74d1919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
34624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2919534624
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.4238174186
Short name T1268
Test name
Test status
Simulation time 239820593 ps
CPU time 0.92 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206204 kb
Host smart-6b6ecb89-1b5c-4bc4-bee5-39f53bfbe445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42381
74186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.4238174186
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.286834744
Short name T335
Test name
Test status
Simulation time 189074323 ps
CPU time 0.83 seconds
Started Jul 06 05:27:55 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206180 kb
Host smart-3b63aa6a-f0bb-4aa0-b57a-bc666578ea23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28683
4744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.286834744
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2694360811
Short name T1752
Test name
Test status
Simulation time 183065880 ps
CPU time 0.81 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206432 kb
Host smart-33844f2b-9d26-4e1e-b445-e985aeba4f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943
60811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2694360811
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.81667149
Short name T2203
Test name
Test status
Simulation time 204233558 ps
CPU time 0.87 seconds
Started Jul 06 05:27:44 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 206196 kb
Host smart-869cd21e-b922-4b4a-9876-42473fc028b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81667
149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.81667149
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2538213868
Short name T366
Test name
Test status
Simulation time 171218107 ps
CPU time 0.77 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206436 kb
Host smart-966f0cc0-c60d-4478-a128-d7bfa16d7113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25382
13868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2538213868
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1775110779
Short name T1911
Test name
Test status
Simulation time 187411280 ps
CPU time 0.78 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206200 kb
Host smart-03577aff-50b0-44df-a67e-14bfc94dbd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17751
10779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1775110779
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2752780021
Short name T2393
Test name
Test status
Simulation time 154735243 ps
CPU time 0.8 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206208 kb
Host smart-817bb334-16d7-4f45-9be0-195cfa9d6acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27527
80021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2752780021
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1503679366
Short name T1131
Test name
Test status
Simulation time 242574037 ps
CPU time 0.97 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:27:53 PM PDT 24
Peak memory 206200 kb
Host smart-fec481bf-40c2-43d5-9d7e-35abbbf9877d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
79366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1503679366
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3739746976
Short name T1512
Test name
Test status
Simulation time 4349444449 ps
CPU time 28.9 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206752 kb
Host smart-a953bec4-0e43-4218-8045-fa3ed5016f7d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3739746976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3739746976
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2448697312
Short name T1881
Test name
Test status
Simulation time 221468795 ps
CPU time 0.81 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206208 kb
Host smart-7cd68f64-0e37-4b54-bf19-43e93c29a183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24486
97312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2448697312
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2629852595
Short name T1123
Test name
Test status
Simulation time 166132752 ps
CPU time 0.85 seconds
Started Jul 06 05:29:02 PM PDT 24
Finished Jul 06 05:29:03 PM PDT 24
Peak memory 205692 kb
Host smart-182a8baf-087f-4c80-b229-9061de40788b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298
52595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2629852595
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1493506415
Short name T1008
Test name
Test status
Simulation time 433048782 ps
CPU time 1.29 seconds
Started Jul 06 05:27:47 PM PDT 24
Finished Jul 06 05:27:49 PM PDT 24
Peak memory 206188 kb
Host smart-e3cdeac9-5875-4103-b579-03f81d3220c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14935
06415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1493506415
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1880885496
Short name T1070
Test name
Test status
Simulation time 6541293366 ps
CPU time 58.03 seconds
Started Jul 06 05:27:45 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206368 kb
Host smart-58b3ed89-0e19-4eaa-a698-31af2fcc7ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
85496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1880885496
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3046212923
Short name T2007
Test name
Test status
Simulation time 36336507 ps
CPU time 0.68 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206248 kb
Host smart-133ea643-8147-4755-9e50-53bfee3dd477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3046212923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3046212923
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.993450856
Short name T2018
Test name
Test status
Simulation time 3692024702 ps
CPU time 4.19 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:54 PM PDT 24
Peak memory 206460 kb
Host smart-7f4c69c7-93c4-4d10-9caf-16095f8c5636
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=993450856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.993450856
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2815554659
Short name T457
Test name
Test status
Simulation time 13396429825 ps
CPU time 12.61 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206268 kb
Host smart-c398ddf2-ad5d-4959-97fc-e1125b29b209
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2815554659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2815554659
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.4143039326
Short name T1906
Test name
Test status
Simulation time 23369624700 ps
CPU time 21.01 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206472 kb
Host smart-c414eb7a-96bc-4e95-9677-4d9d456b19ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4143039326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.4143039326
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.773404480
Short name T1244
Test name
Test status
Simulation time 152990440 ps
CPU time 0.81 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 205792 kb
Host smart-58871e4b-13d1-4e71-987a-0d3f23485f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77340
4480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.773404480
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4180910000
Short name T1108
Test name
Test status
Simulation time 143979246 ps
CPU time 0.8 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206200 kb
Host smart-45f65ae2-3b9e-492c-add0-bee88f101794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
10000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4180910000
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1795883025
Short name T1196
Test name
Test status
Simulation time 513553141 ps
CPU time 1.55 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206388 kb
Host smart-007f3fc5-70df-4110-89a2-54d0bbf39edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
83025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1795883025
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3981543745
Short name T64
Test name
Test status
Simulation time 299750168 ps
CPU time 1.08 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206064 kb
Host smart-54761bca-3f5b-4312-ac70-4aa2d512ca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39815
43745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3981543745
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2656344560
Short name T185
Test name
Test status
Simulation time 18207375129 ps
CPU time 31.75 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206072 kb
Host smart-d7214b1b-694b-4d48-bdc9-c153655e30b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26563
44560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2656344560
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1560429023
Short name T1053
Test name
Test status
Simulation time 381104810 ps
CPU time 1.33 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:27:54 PM PDT 24
Peak memory 206172 kb
Host smart-c01a5085-ccaa-4300-8e3f-862eb33f2420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15604
29023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1560429023
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.424339373
Short name T788
Test name
Test status
Simulation time 169167929 ps
CPU time 0.81 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206176 kb
Host smart-5e7def11-da9c-4ce7-b1b7-a3232ccf9ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42433
9373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.424339373
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.272370031
Short name T334
Test name
Test status
Simulation time 55311382 ps
CPU time 0.68 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206132 kb
Host smart-f12dca12-4501-457e-b117-a383633ae1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27237
0031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.272370031
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2330512149
Short name T2462
Test name
Test status
Simulation time 980487263 ps
CPU time 2.32 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206452 kb
Host smart-3238a0f8-daa5-451e-8113-59991b3c28a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23305
12149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2330512149
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.868096775
Short name T2303
Test name
Test status
Simulation time 172717929 ps
CPU time 1.88 seconds
Started Jul 06 05:27:50 PM PDT 24
Finished Jul 06 05:27:53 PM PDT 24
Peak memory 206424 kb
Host smart-bee6dddf-38a9-41c3-aa88-149bb4f007d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86809
6775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.868096775
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1941316576
Short name T1106
Test name
Test status
Simulation time 271459218 ps
CPU time 1.03 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206096 kb
Host smart-db650ec9-9175-4fa4-a203-a723be731100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19413
16576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1941316576
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3395389014
Short name T2117
Test name
Test status
Simulation time 209939200 ps
CPU time 0.8 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206196 kb
Host smart-3ffd4630-0a85-44bc-ae47-5d28c9420ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33953
89014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3395389014
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3992808124
Short name T1056
Test name
Test status
Simulation time 227834172 ps
CPU time 0.88 seconds
Started Jul 06 05:28:06 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206116 kb
Host smart-1173bf18-e228-451c-8323-c3f3bd8fa0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39928
08124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3992808124
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.644213411
Short name T101
Test name
Test status
Simulation time 5947646330 ps
CPU time 54.3 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206472 kb
Host smart-b1668c1c-a2d9-4b7d-bbb4-1b8f1c759844
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=644213411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.644213411
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1970561884
Short name T598
Test name
Test status
Simulation time 160216397 ps
CPU time 0.82 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206176 kb
Host smart-d142044a-d666-4b98-85a8-9ff1deb5660a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19705
61884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1970561884
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1955705127
Short name T2162
Test name
Test status
Simulation time 23355577387 ps
CPU time 23.58 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:23 PM PDT 24
Peak memory 206268 kb
Host smart-6ece3a4f-8aa0-461d-ac95-72a9aeee89c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19557
05127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1955705127
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3276071887
Short name T2660
Test name
Test status
Simulation time 3329936452 ps
CPU time 3.68 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:53 PM PDT 24
Peak memory 206264 kb
Host smart-d5a81f26-03f9-4e53-a6f5-3b9ffa05190f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
71887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3276071887
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.329095955
Short name T732
Test name
Test status
Simulation time 9216010902 ps
CPU time 86.68 seconds
Started Jul 06 05:28:06 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 206512 kb
Host smart-b58634ce-be1d-4c8f-8afa-564d32d4cb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32909
5955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.329095955
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.543704123
Short name T1728
Test name
Test status
Simulation time 4581644663 ps
CPU time 123 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 206416 kb
Host smart-9c8bac56-0696-4652-9a79-bef7e73ca65e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=543704123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.543704123
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2144477966
Short name T2211
Test name
Test status
Simulation time 265596561 ps
CPU time 0.94 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206168 kb
Host smart-3535fb9a-8bab-4710-a81e-cbebde1bc0cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2144477966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2144477966
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1580635989
Short name T398
Test name
Test status
Simulation time 199859218 ps
CPU time 0.83 seconds
Started Jul 06 05:27:49 PM PDT 24
Finished Jul 06 05:27:51 PM PDT 24
Peak memory 206184 kb
Host smart-81a0a3b1-3371-48ab-b6b0-67563eb495a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
35989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1580635989
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1492076455
Short name T427
Test name
Test status
Simulation time 6591247369 ps
CPU time 182.93 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 206456 kb
Host smart-8a2fbea3-7cc7-493e-9c50-eb59a5125b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14920
76455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1492076455
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3175633056
Short name T1749
Test name
Test status
Simulation time 7030579607 ps
CPU time 193.19 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:31:14 PM PDT 24
Peak memory 206452 kb
Host smart-b95f0e19-8017-4f2b-a7c6-926c3e1ce072
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3175633056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3175633056
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3447032746
Short name T1641
Test name
Test status
Simulation time 160326190 ps
CPU time 0.81 seconds
Started Jul 06 05:27:58 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206156 kb
Host smart-daf69c1b-36fb-461b-83bf-8fbb617dde58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3447032746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3447032746
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1440466498
Short name T1454
Test name
Test status
Simulation time 166115964 ps
CPU time 0.78 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206156 kb
Host smart-9e57aff8-b458-4948-a61b-42716d341291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14404
66498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1440466498
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1006301654
Short name T2358
Test name
Test status
Simulation time 195733681 ps
CPU time 0.83 seconds
Started Jul 06 05:28:09 PM PDT 24
Finished Jul 06 05:28:10 PM PDT 24
Peak memory 206040 kb
Host smart-fc3a1be7-6666-48f5-970b-93bc857e4a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10063
01654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1006301654
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.471970873
Short name T991
Test name
Test status
Simulation time 160541851 ps
CPU time 0.79 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206200 kb
Host smart-4fc7a289-d8c6-4c20-afbc-189b5f7a22e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47197
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.471970873
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1533951805
Short name T1693
Test name
Test status
Simulation time 198288976 ps
CPU time 0.85 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:10 PM PDT 24
Peak memory 206116 kb
Host smart-a89e85a0-8e76-4c37-8538-a03b1430baca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15339
51805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1533951805
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1018172351
Short name T927
Test name
Test status
Simulation time 180760045 ps
CPU time 0.88 seconds
Started Jul 06 05:27:53 PM PDT 24
Finished Jul 06 05:27:54 PM PDT 24
Peak memory 206204 kb
Host smart-fd3f4b22-5162-4c5a-9d3b-72f7a2a61dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10181
72351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1018172351
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.98352691
Short name T1496
Test name
Test status
Simulation time 159694981 ps
CPU time 0.78 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206024 kb
Host smart-c8a7c466-4ff7-4579-8842-e3a93c544609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98352
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.98352691
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3657641316
Short name T1647
Test name
Test status
Simulation time 256593228 ps
CPU time 1.01 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206204 kb
Host smart-0be9be25-7ac7-465e-9aa4-4a3c6273222a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3657641316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3657641316
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1327248344
Short name T2163
Test name
Test status
Simulation time 161340402 ps
CPU time 0.88 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206188 kb
Host smart-ed825f59-9f20-4d94-847d-d8baa823f218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
48344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1327248344
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.44410547
Short name T492
Test name
Test status
Simulation time 76842764 ps
CPU time 0.67 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206160 kb
Host smart-47f3c26c-5f4c-41fe-b954-eb2e44277944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44410
547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.44410547
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3347425143
Short name T2539
Test name
Test status
Simulation time 10243467729 ps
CPU time 27.04 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206508 kb
Host smart-26764529-d65e-4977-bf82-2068f337f22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33474
25143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3347425143
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2000818720
Short name T1520
Test name
Test status
Simulation time 159638406 ps
CPU time 0.85 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:27:53 PM PDT 24
Peak memory 206200 kb
Host smart-edd95c51-320f-49cc-83f3-460fb69b5c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20008
18720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2000818720
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.435571605
Short name T856
Test name
Test status
Simulation time 222749534 ps
CPU time 0.89 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206200 kb
Host smart-a259521e-c6d6-4cf1-89a0-e1ce96ad32fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43557
1605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.435571605
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3793570958
Short name T486
Test name
Test status
Simulation time 188151784 ps
CPU time 0.88 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206180 kb
Host smart-690e4fd7-9fc1-415c-8615-d3d324ff9ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37935
70958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3793570958
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1194725646
Short name T1551
Test name
Test status
Simulation time 155776829 ps
CPU time 0.8 seconds
Started Jul 06 05:27:48 PM PDT 24
Finished Jul 06 05:27:50 PM PDT 24
Peak memory 206164 kb
Host smart-efc74df5-8943-4de1-8a10-f66bd0b5fa52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
25646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1194725646
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3731551751
Short name T1532
Test name
Test status
Simulation time 140204874 ps
CPU time 0.76 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206200 kb
Host smart-af2eeab4-1513-41d6-b124-c61dae2e7ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37315
51751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3731551751
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3395665990
Short name T1242
Test name
Test status
Simulation time 173360885 ps
CPU time 0.87 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206152 kb
Host smart-02046088-38dd-4769-8554-e6fa4e407161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956
65990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3395665990
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2170008011
Short name T2186
Test name
Test status
Simulation time 151053859 ps
CPU time 0.82 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206172 kb
Host smart-e1e8ecd7-3229-42cc-b9fa-86ce2cd6992b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21700
08011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2170008011
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2031047101
Short name T394
Test name
Test status
Simulation time 222207876 ps
CPU time 0.92 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206200 kb
Host smart-ba68bbb9-3e3d-46e8-8b9a-41a4f8ef7b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
47101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2031047101
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2666065785
Short name T833
Test name
Test status
Simulation time 5112351653 ps
CPU time 141.92 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:30:28 PM PDT 24
Peak memory 206512 kb
Host smart-e925d3ce-bab3-45ce-ae9f-72912a5a64f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2666065785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2666065785
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2964620097
Short name T866
Test name
Test status
Simulation time 151194406 ps
CPU time 0.81 seconds
Started Jul 06 05:27:58 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206204 kb
Host smart-a3d0b88a-d9f2-4846-84d9-51350f9a7d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29646
20097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2964620097
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3180544343
Short name T2360
Test name
Test status
Simulation time 182042943 ps
CPU time 0.85 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206120 kb
Host smart-8750fa80-9cae-40ac-b505-a2d839d95ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805
44343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3180544343
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.4002981568
Short name T2475
Test name
Test status
Simulation time 1087850485 ps
CPU time 2.43 seconds
Started Jul 06 05:27:53 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206420 kb
Host smart-49a3c301-18e2-462a-b0d2-7f5ee58eab23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
81568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.4002981568
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1719839472
Short name T861
Test name
Test status
Simulation time 4058736223 ps
CPU time 29.46 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:36 PM PDT 24
Peak memory 206472 kb
Host smart-559e0d71-89c3-42f1-9120-273035642148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17198
39472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1719839472
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1283110918
Short name T376
Test name
Test status
Simulation time 41400761 ps
CPU time 0.66 seconds
Started Jul 06 05:23:18 PM PDT 24
Finished Jul 06 05:23:19 PM PDT 24
Peak memory 206244 kb
Host smart-ea65001d-c5d5-471f-8fb1-01728d8044c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1283110918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1283110918
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1509136848
Short name T2446
Test name
Test status
Simulation time 3757446018 ps
CPU time 4.76 seconds
Started Jul 06 05:23:03 PM PDT 24
Finished Jul 06 05:23:09 PM PDT 24
Peak memory 206444 kb
Host smart-2b1fa93b-12ce-4f3e-a199-7bee300124ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1509136848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1509136848
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1784480517
Short name T2252
Test name
Test status
Simulation time 13424209290 ps
CPU time 15.64 seconds
Started Jul 06 05:23:07 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206512 kb
Host smart-a2ef66e6-7478-4eac-b591-4ba6934efb0d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1784480517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1784480517
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3564815540
Short name T2465
Test name
Test status
Simulation time 23403678809 ps
CPU time 25.66 seconds
Started Jul 06 05:23:02 PM PDT 24
Finished Jul 06 05:23:28 PM PDT 24
Peak memory 206444 kb
Host smart-8b8d92fd-54d1-4d1e-a9f6-412db0c3d506
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3564815540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3564815540
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1227133508
Short name T706
Test name
Test status
Simulation time 207419672 ps
CPU time 0.9 seconds
Started Jul 06 05:23:00 PM PDT 24
Finished Jul 06 05:23:02 PM PDT 24
Peak memory 206160 kb
Host smart-2c1892db-58a9-46c4-9c15-770dadfa28b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12271
33508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1227133508
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3704348339
Short name T55
Test name
Test status
Simulation time 167125249 ps
CPU time 0.83 seconds
Started Jul 06 05:23:02 PM PDT 24
Finished Jul 06 05:23:04 PM PDT 24
Peak memory 206120 kb
Host smart-61ea403e-3bce-4338-9d7e-221d6416d858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37043
48339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3704348339
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1266374331
Short name T69
Test name
Test status
Simulation time 138358836 ps
CPU time 0.86 seconds
Started Jul 06 05:22:59 PM PDT 24
Finished Jul 06 05:23:01 PM PDT 24
Peak memory 206176 kb
Host smart-7003033b-0a61-4b90-8161-8483ee608322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12663
74331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1266374331
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2349763180
Short name T793
Test name
Test status
Simulation time 141474249 ps
CPU time 0.86 seconds
Started Jul 06 05:23:08 PM PDT 24
Finished Jul 06 05:23:09 PM PDT 24
Peak memory 206160 kb
Host smart-3743f1f0-71b6-4f7a-84a9-5947ffac379f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23497
63180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2349763180
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3569780438
Short name T2586
Test name
Test status
Simulation time 182647310 ps
CPU time 0.87 seconds
Started Jul 06 05:23:11 PM PDT 24
Finished Jul 06 05:23:12 PM PDT 24
Peak memory 206112 kb
Host smart-9245fc95-7bf2-4e3a-be8c-c9b42f45daf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35697
80438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3569780438
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3958547864
Short name T1200
Test name
Test status
Simulation time 744371876 ps
CPU time 1.87 seconds
Started Jul 06 05:23:08 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 206452 kb
Host smart-22bc666a-bee0-4a15-9890-16a0cb670379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
47864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3958547864
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.722778363
Short name T958
Test name
Test status
Simulation time 295692419 ps
CPU time 1.04 seconds
Started Jul 06 05:23:07 PM PDT 24
Finished Jul 06 05:23:09 PM PDT 24
Peak memory 206200 kb
Host smart-2f5aa70e-3088-44c8-9422-a2f1a7df6430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72277
8363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.722778363
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.4250003674
Short name T2415
Test name
Test status
Simulation time 143826434 ps
CPU time 0.79 seconds
Started Jul 06 05:23:05 PM PDT 24
Finished Jul 06 05:23:07 PM PDT 24
Peak memory 206152 kb
Host smart-38ad147c-dfe2-46ff-a92e-f7e0738753d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42500
03674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.4250003674
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1266302540
Short name T1189
Test name
Test status
Simulation time 60005807 ps
CPU time 0.72 seconds
Started Jul 06 05:23:09 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 205316 kb
Host smart-8234eee0-f07e-4503-857b-ccb47e8ddcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12663
02540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1266302540
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2564854695
Short name T383
Test name
Test status
Simulation time 920084124 ps
CPU time 2.18 seconds
Started Jul 06 05:23:08 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 206396 kb
Host smart-237ce1d1-d4b3-433d-a406-13bdb7e9c89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25648
54695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2564854695
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.707741664
Short name T513
Test name
Test status
Simulation time 336823773 ps
CPU time 2.12 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:23:15 PM PDT 24
Peak memory 206400 kb
Host smart-75232cb8-43d1-43d1-908f-56b99e1f799a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70774
1664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.707741664
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2918481201
Short name T442
Test name
Test status
Simulation time 85219965703 ps
CPU time 105.64 seconds
Started Jul 06 05:23:07 PM PDT 24
Finished Jul 06 05:24:53 PM PDT 24
Peak memory 206440 kb
Host smart-7a0e13f1-9cb9-488c-b77e-c507f6950e55
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2918481201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2918481201
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1725743612
Short name T899
Test name
Test status
Simulation time 92125296806 ps
CPU time 115.44 seconds
Started Jul 06 05:23:10 PM PDT 24
Finished Jul 06 05:25:06 PM PDT 24
Peak memory 206440 kb
Host smart-bb7a35c5-9cf6-40d7-9986-a4f5956defef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725743612 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1725743612
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.553632353
Short name T799
Test name
Test status
Simulation time 98130257839 ps
CPU time 142.3 seconds
Started Jul 06 05:23:08 PM PDT 24
Finished Jul 06 05:25:31 PM PDT 24
Peak memory 206460 kb
Host smart-c4d854ff-f5cc-4f9b-be33-d8614d7e51b4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=553632353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.553632353
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1906762688
Short name T405
Test name
Test status
Simulation time 120953596920 ps
CPU time 164.97 seconds
Started Jul 06 05:23:06 PM PDT 24
Finished Jul 06 05:25:51 PM PDT 24
Peak memory 206448 kb
Host smart-657b9234-608c-4184-a99b-89456c2f5f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906762688 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1906762688
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3701929718
Short name T1360
Test name
Test status
Simulation time 112166853577 ps
CPU time 139.55 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:25:32 PM PDT 24
Peak memory 206468 kb
Host smart-fd68b924-5c0f-4c21-9747-35df05494e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
29718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3701929718
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.728564998
Short name T2697
Test name
Test status
Simulation time 187681889 ps
CPU time 0.84 seconds
Started Jul 06 05:23:08 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 206172 kb
Host smart-171a7edb-a832-4b9c-81ec-c6d04c0e7479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72856
4998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.728564998
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3466601577
Short name T2459
Test name
Test status
Simulation time 146181080 ps
CPU time 0.78 seconds
Started Jul 06 05:23:06 PM PDT 24
Finished Jul 06 05:23:07 PM PDT 24
Peak memory 206196 kb
Host smart-8809dd9d-2dea-4ad2-aba1-27ab6323e675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34666
01577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3466601577
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1085863196
Short name T1819
Test name
Test status
Simulation time 203019697 ps
CPU time 0.91 seconds
Started Jul 06 05:23:09 PM PDT 24
Finished Jul 06 05:23:10 PM PDT 24
Peak memory 206220 kb
Host smart-f4c9884e-2820-4cae-8930-e76ade68798e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10858
63196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1085863196
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2966901821
Short name T888
Test name
Test status
Simulation time 188834478 ps
CPU time 0.83 seconds
Started Jul 06 05:23:07 PM PDT 24
Finished Jul 06 05:23:08 PM PDT 24
Peak memory 206188 kb
Host smart-42a9fcfd-d55a-489c-ad55-de77931d8eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29669
01821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2966901821
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3098426592
Short name T1640
Test name
Test status
Simulation time 23303953866 ps
CPU time 26.33 seconds
Started Jul 06 05:23:09 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 205372 kb
Host smart-e0a64b2d-f21e-4421-9e4f-ae92408a1899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
26592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3098426592
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2404451949
Short name T2194
Test name
Test status
Simulation time 3294118646 ps
CPU time 3.54 seconds
Started Jul 06 05:23:09 PM PDT 24
Finished Jul 06 05:23:13 PM PDT 24
Peak memory 206228 kb
Host smart-4ac2adce-f569-45c7-846c-f9628cf4bcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24044
51949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2404451949
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3409347563
Short name T2560
Test name
Test status
Simulation time 10793169160 ps
CPU time 103.02 seconds
Started Jul 06 05:23:11 PM PDT 24
Finished Jul 06 05:24:55 PM PDT 24
Peak memory 206508 kb
Host smart-b1ce7d3e-5b54-480a-bad1-f5d47de15723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34093
47563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3409347563
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1232164919
Short name T1248
Test name
Test status
Simulation time 5591512987 ps
CPU time 40.06 seconds
Started Jul 06 05:23:10 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206452 kb
Host smart-c5a7c1f4-1646-42d5-8b9c-60f590f1b269
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1232164919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1232164919
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.4193651056
Short name T1016
Test name
Test status
Simulation time 248266013 ps
CPU time 0.93 seconds
Started Jul 06 05:23:16 PM PDT 24
Finished Jul 06 05:23:17 PM PDT 24
Peak memory 206192 kb
Host smart-c6250d59-50fe-408c-8f19-70ce386f81a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4193651056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.4193651056
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1688429368
Short name T480
Test name
Test status
Simulation time 195919012 ps
CPU time 0.85 seconds
Started Jul 06 05:23:14 PM PDT 24
Finished Jul 06 05:23:15 PM PDT 24
Peak memory 206176 kb
Host smart-75639590-1c68-40ca-9a00-bc44764af00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
29368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1688429368
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.473868456
Short name T151
Test name
Test status
Simulation time 6302245210 ps
CPU time 60.21 seconds
Started Jul 06 05:23:13 PM PDT 24
Finished Jul 06 05:24:13 PM PDT 24
Peak memory 206512 kb
Host smart-ba8e3ffe-0aca-4d08-ba17-294a4eeec727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47386
8456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.473868456
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3992382560
Short name T2492
Test name
Test status
Simulation time 4004716932 ps
CPU time 110.32 seconds
Started Jul 06 05:23:10 PM PDT 24
Finished Jul 06 05:25:00 PM PDT 24
Peak memory 206292 kb
Host smart-8c30125f-9e54-43df-830b-c5ea170f2cbb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3992382560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3992382560
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.3931556222
Short name T1173
Test name
Test status
Simulation time 161363600 ps
CPU time 0.8 seconds
Started Jul 06 05:23:15 PM PDT 24
Finished Jul 06 05:23:16 PM PDT 24
Peak memory 206204 kb
Host smart-1e77a398-cca3-4e20-98bd-d41aa9a51b71
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3931556222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.3931556222
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1918371315
Short name T1905
Test name
Test status
Simulation time 141453733 ps
CPU time 0.8 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:23:13 PM PDT 24
Peak memory 206112 kb
Host smart-1a958bd1-353d-4d25-a8eb-fc0ceae66124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19183
71315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1918371315
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3028122849
Short name T1495
Test name
Test status
Simulation time 206262963 ps
CPU time 0.91 seconds
Started Jul 06 05:23:10 PM PDT 24
Finished Jul 06 05:23:12 PM PDT 24
Peak memory 206164 kb
Host smart-b7b7b217-ccd8-4689-a289-01ca86a9ecd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30281
22849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3028122849
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.4250122899
Short name T1355
Test name
Test status
Simulation time 158285524 ps
CPU time 0.85 seconds
Started Jul 06 05:23:18 PM PDT 24
Finished Jul 06 05:23:19 PM PDT 24
Peak memory 206200 kb
Host smart-13628e9b-6eb8-4fbf-907e-53305e889730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
22899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.4250122899
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1554439720
Short name T2092
Test name
Test status
Simulation time 151211905 ps
CPU time 0.86 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:23:13 PM PDT 24
Peak memory 206200 kb
Host smart-7aaa94b1-2157-47a2-af1c-81ecf9ab72a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544
39720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1554439720
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.114499879
Short name T1138
Test name
Test status
Simulation time 182359774 ps
CPU time 0.83 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:23:13 PM PDT 24
Peak memory 206164 kb
Host smart-5507f26f-7e79-4a3a-96d8-d4affc6da918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11449
9879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.114499879
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3274479930
Short name T2000
Test name
Test status
Simulation time 155971683 ps
CPU time 0.9 seconds
Started Jul 06 05:23:11 PM PDT 24
Finished Jul 06 05:23:12 PM PDT 24
Peak memory 206200 kb
Host smart-6fe676f9-708d-4b80-b573-407daa2ab1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32744
79930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3274479930
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.882353700
Short name T586
Test name
Test status
Simulation time 220881626 ps
CPU time 0.92 seconds
Started Jul 06 05:23:10 PM PDT 24
Finished Jul 06 05:23:11 PM PDT 24
Peak memory 206156 kb
Host smart-9fe842e9-0ddb-4cda-99ef-79f64792b135
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=882353700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.882353700
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1903365224
Short name T217
Test name
Test status
Simulation time 177241245 ps
CPU time 0.91 seconds
Started Jul 06 05:23:16 PM PDT 24
Finished Jul 06 05:23:17 PM PDT 24
Peak memory 206204 kb
Host smart-eb381e80-dcfd-48b3-b0da-5ceb862052b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
65224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1903365224
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2103548185
Short name T2635
Test name
Test status
Simulation time 148094845 ps
CPU time 0.8 seconds
Started Jul 06 05:23:13 PM PDT 24
Finished Jul 06 05:23:14 PM PDT 24
Peak memory 206096 kb
Host smart-8d662788-ca9f-43ec-8df2-74d3549f5774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21035
48185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2103548185
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2538909175
Short name T41
Test name
Test status
Simulation time 81253463 ps
CPU time 0.71 seconds
Started Jul 06 05:23:11 PM PDT 24
Finished Jul 06 05:23:12 PM PDT 24
Peak memory 206092 kb
Host smart-044789aa-3412-44bd-94ae-9f1542d8d541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
09175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2538909175
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3769513150
Short name T1898
Test name
Test status
Simulation time 15147752158 ps
CPU time 33.75 seconds
Started Jul 06 05:23:11 PM PDT 24
Finished Jul 06 05:23:45 PM PDT 24
Peak memory 206504 kb
Host smart-72bc87c8-935a-456f-8d25-c82526b81016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37695
13150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3769513150
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1115186065
Short name T853
Test name
Test status
Simulation time 195520675 ps
CPU time 0.9 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:23:13 PM PDT 24
Peak memory 206172 kb
Host smart-5dee7949-427d-419c-bcaf-f950c3ead075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11151
86065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1115186065
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3092792141
Short name T919
Test name
Test status
Simulation time 186181117 ps
CPU time 0.93 seconds
Started Jul 06 05:23:13 PM PDT 24
Finished Jul 06 05:23:14 PM PDT 24
Peak memory 206176 kb
Host smart-de9f7429-9994-4580-b511-77b9240796ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
92141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3092792141
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1892693495
Short name T1763
Test name
Test status
Simulation time 11444949403 ps
CPU time 101.23 seconds
Started Jul 06 05:23:14 PM PDT 24
Finished Jul 06 05:24:56 PM PDT 24
Peak memory 206544 kb
Host smart-cdc324e7-f8b4-4333-9f1d-3e53dac2e9b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1892693495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1892693495
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.310891675
Short name T1924
Test name
Test status
Simulation time 3928996624 ps
CPU time 20.84 seconds
Started Jul 06 05:23:13 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206436 kb
Host smart-42573aca-ac8c-45a1-a270-855735f02d77
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=310891675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.310891675
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2809676487
Short name T1004
Test name
Test status
Simulation time 12284160090 ps
CPU time 230.87 seconds
Started Jul 06 05:23:15 PM PDT 24
Finished Jul 06 05:27:06 PM PDT 24
Peak memory 206496 kb
Host smart-910bc14b-25aa-4813-bf0e-2cc04516408b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2809676487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2809676487
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2544974973
Short name T2191
Test name
Test status
Simulation time 206526045 ps
CPU time 0.86 seconds
Started Jul 06 05:23:15 PM PDT 24
Finished Jul 06 05:23:16 PM PDT 24
Peak memory 206116 kb
Host smart-7999bfc8-dc9f-4b41-a6eb-c768ad128475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25449
74973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2544974973
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3534526445
Short name T1972
Test name
Test status
Simulation time 173195026 ps
CPU time 0.86 seconds
Started Jul 06 05:23:15 PM PDT 24
Finished Jul 06 05:23:16 PM PDT 24
Peak memory 206116 kb
Host smart-f247daba-a332-42b5-9b0d-552347cf0ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35345
26445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3534526445
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4287737172
Short name T2604
Test name
Test status
Simulation time 148574447 ps
CPU time 0.8 seconds
Started Jul 06 05:23:12 PM PDT 24
Finished Jul 06 05:23:13 PM PDT 24
Peak memory 206204 kb
Host smart-ba0ba5db-6fe6-4abb-ba12-8411263974c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42877
37172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4287737172
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1430809004
Short name T2150
Test name
Test status
Simulation time 174978862 ps
CPU time 0.85 seconds
Started Jul 06 05:23:14 PM PDT 24
Finished Jul 06 05:23:15 PM PDT 24
Peak memory 206204 kb
Host smart-b1375eff-76c1-409c-bfd6-9330e345bcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
09004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1430809004
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2108759985
Short name T58
Test name
Test status
Simulation time 330814181 ps
CPU time 1.17 seconds
Started Jul 06 05:23:11 PM PDT 24
Finished Jul 06 05:23:12 PM PDT 24
Peak memory 206100 kb
Host smart-3d10086d-11e9-4a3d-a329-082053d9f3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21087
59985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2108759985
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2308828579
Short name T435
Test name
Test status
Simulation time 332540886 ps
CPU time 1.07 seconds
Started Jul 06 05:23:16 PM PDT 24
Finished Jul 06 05:23:17 PM PDT 24
Peak memory 206208 kb
Host smart-381cb76b-2ec6-4bb7-823f-696dedf3a8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23088
28579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2308828579
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3375055744
Short name T718
Test name
Test status
Simulation time 143908316 ps
CPU time 0.79 seconds
Started Jul 06 05:23:16 PM PDT 24
Finished Jul 06 05:23:17 PM PDT 24
Peak memory 206116 kb
Host smart-72054f3f-c271-4692-b26b-8df30b929f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33750
55744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3375055744
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2722749742
Short name T438
Test name
Test status
Simulation time 168783302 ps
CPU time 0.78 seconds
Started Jul 06 05:23:25 PM PDT 24
Finished Jul 06 05:23:26 PM PDT 24
Peak memory 206192 kb
Host smart-03803b64-8c47-4762-9474-c51b028f88f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
49742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2722749742
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2539914131
Short name T2367
Test name
Test status
Simulation time 240278794 ps
CPU time 1.05 seconds
Started Jul 06 05:23:25 PM PDT 24
Finished Jul 06 05:23:26 PM PDT 24
Peak memory 206200 kb
Host smart-b41e716b-681b-4476-810d-59790745670f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25399
14131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2539914131
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1962225049
Short name T1531
Test name
Test status
Simulation time 5275229966 ps
CPU time 36.53 seconds
Started Jul 06 05:23:17 PM PDT 24
Finished Jul 06 05:23:54 PM PDT 24
Peak memory 206436 kb
Host smart-7c69549f-a5d4-469f-99dc-0d9e97c19221
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1962225049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1962225049
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4042687175
Short name T102
Test name
Test status
Simulation time 190339639 ps
CPU time 0.85 seconds
Started Jul 06 05:23:26 PM PDT 24
Finished Jul 06 05:23:27 PM PDT 24
Peak memory 206168 kb
Host smart-cfb021a7-1225-4b07-bb4b-c7d94045e5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40426
87175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4042687175
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2563646587
Short name T1377
Test name
Test status
Simulation time 172394966 ps
CPU time 0.77 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:23:28 PM PDT 24
Peak memory 206180 kb
Host smart-fab1503f-2a84-4a6f-8b70-c314724bcd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25636
46587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2563646587
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.79995919
Short name T1944
Test name
Test status
Simulation time 783292587 ps
CPU time 1.76 seconds
Started Jul 06 05:23:17 PM PDT 24
Finished Jul 06 05:23:19 PM PDT 24
Peak memory 206344 kb
Host smart-586615fe-1a62-4f40-92b5-7df47dd4e4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79995
919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.79995919
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1906693015
Short name T1447
Test name
Test status
Simulation time 4759033192 ps
CPU time 131.89 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206456 kb
Host smart-d3a7c943-474a-49ef-bb35-adc67bfff4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066
93015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1906693015
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.4137811775
Short name T180
Test name
Test status
Simulation time 15462507573 ps
CPU time 133.04 seconds
Started Jul 06 05:23:17 PM PDT 24
Finished Jul 06 05:25:30 PM PDT 24
Peak memory 206444 kb
Host smart-37c75b43-4093-4508-854e-4f4d7eb8966a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4137811775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.4137811775
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3682082055
Short name T201
Test name
Test status
Simulation time 41648334 ps
CPU time 0.7 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206280 kb
Host smart-4aa22b6c-1303-4e9d-b8ca-2c17815adf90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3682082055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3682082055
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.4208315788
Short name T1659
Test name
Test status
Simulation time 4214271020 ps
CPU time 5.96 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206520 kb
Host smart-5b203c1c-347d-46c3-9c87-fd83f7e1c7bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4208315788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.4208315788
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1234125255
Short name T1260
Test name
Test status
Simulation time 13373874392 ps
CPU time 13.59 seconds
Started Jul 06 05:27:55 PM PDT 24
Finished Jul 06 05:28:09 PM PDT 24
Peak memory 206256 kb
Host smart-47296066-505b-4232-bec3-f3125bb05fa1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1234125255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1234125255
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.225655377
Short name T1559
Test name
Test status
Simulation time 23420088724 ps
CPU time 21.36 seconds
Started Jul 06 05:27:52 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206460 kb
Host smart-95d0fb08-917c-4980-ab60-e0f82f8c2053
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=225655377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.225655377
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1500893331
Short name T2365
Test name
Test status
Simulation time 146589986 ps
CPU time 0.83 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:27:57 PM PDT 24
Peak memory 206188 kb
Host smart-036c99e7-4129-4afc-8291-688760abed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
93331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1500893331
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2372834190
Short name T1745
Test name
Test status
Simulation time 143115717 ps
CPU time 0.74 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206120 kb
Host smart-0436b71c-52b3-4f26-bdff-b64f006b9fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23728
34190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2372834190
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1315630317
Short name T970
Test name
Test status
Simulation time 570464464 ps
CPU time 1.85 seconds
Started Jul 06 05:27:57 PM PDT 24
Finished Jul 06 05:28:00 PM PDT 24
Peak memory 206456 kb
Host smart-ea20bac2-c98b-4a7e-b0ab-a89e346d08c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13156
30317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1315630317
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3075580382
Short name T192
Test name
Test status
Simulation time 889102489 ps
CPU time 2.15 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:27:58 PM PDT 24
Peak memory 206296 kb
Host smart-aebcce13-1eef-4695-886e-662a4b2251ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
80382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3075580382
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.208552341
Short name T177
Test name
Test status
Simulation time 20251480908 ps
CPU time 41.52 seconds
Started Jul 06 05:27:56 PM PDT 24
Finished Jul 06 05:28:38 PM PDT 24
Peak memory 206380 kb
Host smart-c3606701-a540-4bfc-80f4-8afd59dcefa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20855
2341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.208552341
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1013195675
Short name T2647
Test name
Test status
Simulation time 329990858 ps
CPU time 1.16 seconds
Started Jul 06 05:27:57 PM PDT 24
Finished Jul 06 05:27:59 PM PDT 24
Peak memory 206180 kb
Host smart-9a884738-96d6-487d-950d-ab8a8f96ba39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10131
95675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1013195675
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1627084861
Short name T2356
Test name
Test status
Simulation time 150148210 ps
CPU time 0.87 seconds
Started Jul 06 05:28:09 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206156 kb
Host smart-fbbb7199-9fc8-49a0-81b4-48d605707a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270
84861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1627084861
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1593901250
Short name T1675
Test name
Test status
Simulation time 35232202 ps
CPU time 0.67 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:06 PM PDT 24
Peak memory 206180 kb
Host smart-4d3c249d-f3ac-48be-8be9-b5615a43456e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15939
01250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1593901250
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.266708271
Short name T2456
Test name
Test status
Simulation time 846003156 ps
CPU time 2.1 seconds
Started Jul 06 05:27:53 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206344 kb
Host smart-b2467298-8fcd-44fd-b99b-6439965ebf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
8271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.266708271
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2768829757
Short name T2188
Test name
Test status
Simulation time 208035760 ps
CPU time 1.36 seconds
Started Jul 06 05:27:54 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206372 kb
Host smart-27f43b2b-14fa-44bd-8cfb-480f12b58b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27688
29757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2768829757
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.16128196
Short name T579
Test name
Test status
Simulation time 264343958 ps
CPU time 0.99 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206176 kb
Host smart-2ba7b59d-34bf-4b64-94fd-c300a8519175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128
196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.16128196
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4018617648
Short name T2039
Test name
Test status
Simulation time 179373507 ps
CPU time 0.79 seconds
Started Jul 06 05:27:55 PM PDT 24
Finished Jul 06 05:27:56 PM PDT 24
Peak memory 206080 kb
Host smart-7ace93cc-1e31-45b6-9802-4c13331f4ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40186
17648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4018617648
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2070529998
Short name T879
Test name
Test status
Simulation time 244135292 ps
CPU time 0.91 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206116 kb
Host smart-6a91ce55-f6e3-47fe-82c7-11b9994fa5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20705
29998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2070529998
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2828590188
Short name T1544
Test name
Test status
Simulation time 274658139 ps
CPU time 0.9 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:06 PM PDT 24
Peak memory 206044 kb
Host smart-b7aa408d-9f62-4c8d-9c84-d2fbc8ef7825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
90188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2828590188
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.25809900
Short name T838
Test name
Test status
Simulation time 23362109051 ps
CPU time 23.86 seconds
Started Jul 06 05:27:53 PM PDT 24
Finished Jul 06 05:28:17 PM PDT 24
Peak memory 206184 kb
Host smart-80b4a20f-ce76-478f-aad1-008a4efb1fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809
900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.25809900
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2238320761
Short name T1620
Test name
Test status
Simulation time 3347258376 ps
CPU time 3.97 seconds
Started Jul 06 05:28:17 PM PDT 24
Finished Jul 06 05:28:21 PM PDT 24
Peak memory 206220 kb
Host smart-b3184e93-a9f5-4e33-9d05-c965b4a92b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22383
20761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2238320761
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2814119742
Short name T2268
Test name
Test status
Simulation time 10133613648 ps
CPU time 100.46 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:29:44 PM PDT 24
Peak memory 206532 kb
Host smart-a1f27404-b4ca-4b62-a17d-2b90cc709840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
19742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2814119742
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3619805551
Short name T1816
Test name
Test status
Simulation time 3038735401 ps
CPU time 29.2 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206524 kb
Host smart-6d0b8b6e-5d37-43ee-b829-dfe31f7c027a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3619805551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3619805551
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.403057171
Short name T1594
Test name
Test status
Simulation time 246456332 ps
CPU time 0.9 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206188 kb
Host smart-7c22500d-249e-4ca7-a4f1-a65dff7d01be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=403057171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.403057171
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3393674768
Short name T33
Test name
Test status
Simulation time 218686163 ps
CPU time 0.87 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206108 kb
Host smart-60c052ec-d218-49f7-9cf5-986a01159385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936
74768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3393674768
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2695840222
Short name T2626
Test name
Test status
Simulation time 4430841978 ps
CPU time 122.77 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:30:07 PM PDT 24
Peak memory 206424 kb
Host smart-5ced7828-9dda-4aa3-97df-d3ccac5b85db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26958
40222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2695840222
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.309730383
Short name T404
Test name
Test status
Simulation time 3260581187 ps
CPU time 86.83 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 206452 kb
Host smart-96839396-84f5-49db-af7f-95e1ad235f07
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=309730383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.309730383
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3690562373
Short name T340
Test name
Test status
Simulation time 165768803 ps
CPU time 0.89 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206184 kb
Host smart-ca3519a4-57f3-4cfc-8ae8-6d5377572e5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3690562373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3690562373
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1996317955
Short name T2167
Test name
Test status
Simulation time 145543880 ps
CPU time 0.78 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206188 kb
Host smart-882c304b-c408-4966-8523-422ee5fb48ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
17955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1996317955
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1611903601
Short name T119
Test name
Test status
Simulation time 189121442 ps
CPU time 0.84 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:02 PM PDT 24
Peak memory 206200 kb
Host smart-a5bc1bf0-5bbe-477c-b581-29f4ef72d5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
03601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1611903601
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2886409474
Short name T2491
Test name
Test status
Simulation time 172240908 ps
CPU time 0.81 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206112 kb
Host smart-0cba8845-7c44-4a6c-8ad9-8e5fa54fe66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
09474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2886409474
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2030700992
Short name T2229
Test name
Test status
Simulation time 147867219 ps
CPU time 0.79 seconds
Started Jul 06 05:28:02 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206200 kb
Host smart-23dc0744-136c-48d9-ba14-5750e483412b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20307
00992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2030700992
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.990528578
Short name T867
Test name
Test status
Simulation time 168150349 ps
CPU time 0.85 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206180 kb
Host smart-c55ced31-caf0-4d12-a523-ef6c5e5c5a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99052
8578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.990528578
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2790201856
Short name T159
Test name
Test status
Simulation time 152827783 ps
CPU time 0.82 seconds
Started Jul 06 05:28:12 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206160 kb
Host smart-a66f7d1d-00d7-47cb-ba08-7ac1b8727b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27902
01856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2790201856
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3805172258
Short name T2218
Test name
Test status
Simulation time 212851869 ps
CPU time 0.9 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:04 PM PDT 24
Peak memory 206204 kb
Host smart-23b95cc0-8d1c-4f0d-a652-9c469ae6b15a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3805172258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3805172258
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.768864477
Short name T44
Test name
Test status
Simulation time 148037232 ps
CPU time 0.77 seconds
Started Jul 06 05:27:59 PM PDT 24
Finished Jul 06 05:28:01 PM PDT 24
Peak memory 206180 kb
Host smart-752c9678-5e75-4306-a586-fa1106350b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76886
4477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.768864477
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1726182844
Short name T447
Test name
Test status
Simulation time 52434855 ps
CPU time 0.68 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206172 kb
Host smart-f55fdf51-3e67-4ea2-b475-7493d47ef46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17261
82844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1726182844
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.405988687
Short name T2580
Test name
Test status
Simulation time 19369938293 ps
CPU time 40.86 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206508 kb
Host smart-d543939a-cdb5-4d76-929a-0452af38e004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40598
8687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.405988687
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2176478253
Short name T666
Test name
Test status
Simulation time 180940181 ps
CPU time 0.86 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206204 kb
Host smart-fd836d2b-7207-41b0-a633-6437deff3ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21764
78253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2176478253
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2507396744
Short name T1666
Test name
Test status
Simulation time 286081541 ps
CPU time 0.92 seconds
Started Jul 06 05:28:00 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206176 kb
Host smart-fa2bbbfd-5e99-4759-ad9b-5f73ea95811c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25073
96744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2507396744
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1802986554
Short name T968
Test name
Test status
Simulation time 266564103 ps
CPU time 0.94 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206204 kb
Host smart-59e6cd69-94c0-4f49-802e-9fcbbfe99682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029
86554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1802986554
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3015032180
Short name T683
Test name
Test status
Simulation time 174576264 ps
CPU time 0.83 seconds
Started Jul 06 05:28:06 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206164 kb
Host smart-00aa806a-025c-4929-b526-8b4a4b015687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
32180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3015032180
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.276557374
Short name T2178
Test name
Test status
Simulation time 179730403 ps
CPU time 0.82 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206164 kb
Host smart-d32f5c83-7cc2-45f0-94fd-05905e39ca95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27655
7374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.276557374
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1513036148
Short name T149
Test name
Test status
Simulation time 194615987 ps
CPU time 0.84 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206204 kb
Host smart-d217176c-f42d-4cc5-94c9-b9ad7ae2a2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15130
36148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1513036148
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3459931054
Short name T2428
Test name
Test status
Simulation time 164241126 ps
CPU time 0.84 seconds
Started Jul 06 05:28:01 PM PDT 24
Finished Jul 06 05:28:03 PM PDT 24
Peak memory 206084 kb
Host smart-9bceabf0-28e5-4acf-a927-6d219c1881c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34599
31054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3459931054
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3013886629
Short name T1918
Test name
Test status
Simulation time 229352786 ps
CPU time 0.95 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206204 kb
Host smart-cab6414d-1ccf-4f8b-aa62-5bdfab6a6dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
86629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3013886629
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1827331375
Short name T1029
Test name
Test status
Simulation time 5902509252 ps
CPU time 56.62 seconds
Started Jul 06 05:28:03 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 206424 kb
Host smart-98b2d39c-9588-4ff1-9d43-d2d8e6da3c7f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1827331375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1827331375
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.620825508
Short name T2273
Test name
Test status
Simulation time 202404525 ps
CPU time 0.83 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206116 kb
Host smart-916d6a5f-c456-4733-924d-1b37a6c81a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62082
5508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.620825508
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1575292237
Short name T1804
Test name
Test status
Simulation time 183120323 ps
CPU time 0.85 seconds
Started Jul 06 05:28:16 PM PDT 24
Finished Jul 06 05:28:17 PM PDT 24
Peak memory 206188 kb
Host smart-39bb76f4-5dcc-49ea-85b8-e6fc1f952809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
92237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1575292237
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.748580070
Short name T1398
Test name
Test status
Simulation time 560003093 ps
CPU time 1.44 seconds
Started Jul 06 05:28:06 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206112 kb
Host smart-8e68be09-2d16-43d1-8b50-a8f3fbab6b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74858
0070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.748580070
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2977732435
Short name T456
Test name
Test status
Simulation time 4647540180 ps
CPU time 35.56 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:42 PM PDT 24
Peak memory 206380 kb
Host smart-8e6d6a3f-5bef-4839-9800-d765ccd78a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29777
32435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2977732435
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3067052210
Short name T199
Test name
Test status
Simulation time 43890376 ps
CPU time 0.75 seconds
Started Jul 06 05:28:15 PM PDT 24
Finished Jul 06 05:28:16 PM PDT 24
Peak memory 206256 kb
Host smart-623f2c7a-13ac-4f8d-a451-88708ce6b6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3067052210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3067052210
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2279072955
Short name T2636
Test name
Test status
Simulation time 4055033295 ps
CPU time 5.36 seconds
Started Jul 06 05:28:26 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206420 kb
Host smart-5abf34bd-4db9-435f-9c8e-9755530dd3f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2279072955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2279072955
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.4189182877
Short name T2347
Test name
Test status
Simulation time 13391571782 ps
CPU time 13.03 seconds
Started Jul 06 05:28:09 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206264 kb
Host smart-f84a7f5e-8116-46a6-afa5-1df364d5600f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4189182877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.4189182877
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3679940974
Short name T2667
Test name
Test status
Simulation time 172381199 ps
CPU time 0.81 seconds
Started Jul 06 05:28:15 PM PDT 24
Finished Jul 06 05:28:16 PM PDT 24
Peak memory 206168 kb
Host smart-b4c8ff60-bc66-4719-91d6-233cf4f5c177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36799
40974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3679940974
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2404287453
Short name T553
Test name
Test status
Simulation time 143558347 ps
CPU time 0.77 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:06 PM PDT 24
Peak memory 206164 kb
Host smart-ecab6630-ee72-40e4-afed-495c3ae184b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24042
87453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2404287453
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1503823993
Short name T2404
Test name
Test status
Simulation time 602224415 ps
CPU time 1.6 seconds
Started Jul 06 05:28:23 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206408 kb
Host smart-4756c15e-4b88-4c4c-964c-d7a439090006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15038
23993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1503823993
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3630484853
Short name T1234
Test name
Test status
Simulation time 305558458 ps
CPU time 1.04 seconds
Started Jul 06 05:28:05 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206192 kb
Host smart-bd4b2949-c5aa-4760-9a15-83d330d4a768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
84853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3630484853
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1076245021
Short name T98
Test name
Test status
Simulation time 8260256003 ps
CPU time 16.21 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:23 PM PDT 24
Peak memory 206380 kb
Host smart-7d90beac-b97d-4596-8dbd-42053fb8c6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
45021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1076245021
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.334527585
Short name T2284
Test name
Test status
Simulation time 548768830 ps
CPU time 1.45 seconds
Started Jul 06 05:28:27 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206164 kb
Host smart-f9d602af-6d34-4110-8581-d4705de57852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33452
7585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.334527585
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1064922272
Short name T715
Test name
Test status
Simulation time 141195995 ps
CPU time 0.8 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:28:12 PM PDT 24
Peak memory 206200 kb
Host smart-259b3869-193a-495b-91c6-fcaa118a6d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10649
22272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1064922272
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1396483204
Short name T2019
Test name
Test status
Simulation time 55572818 ps
CPU time 0.68 seconds
Started Jul 06 05:28:04 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 206164 kb
Host smart-fdfc24f1-4417-46e2-8292-e01e8c490838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964
83204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1396483204
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1426012788
Short name T844
Test name
Test status
Simulation time 759619422 ps
CPU time 1.92 seconds
Started Jul 06 05:28:20 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206400 kb
Host smart-1718d3f2-beb4-4296-8e84-a3076e9d9d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14260
12788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1426012788
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2895055302
Short name T1389
Test name
Test status
Simulation time 371906101 ps
CPU time 2.25 seconds
Started Jul 06 05:28:06 PM PDT 24
Finished Jul 06 05:28:09 PM PDT 24
Peak memory 206424 kb
Host smart-66333d90-324f-4387-bba6-685ee7709725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
55302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2895055302
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2347086278
Short name T1882
Test name
Test status
Simulation time 190607906 ps
CPU time 0.94 seconds
Started Jul 06 05:28:14 PM PDT 24
Finished Jul 06 05:28:15 PM PDT 24
Peak memory 206064 kb
Host smart-a7e4b978-255c-4764-88ee-7ad481f7b597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
86278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2347086278
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2287026463
Short name T1222
Test name
Test status
Simulation time 158294555 ps
CPU time 0.76 seconds
Started Jul 06 05:28:28 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206196 kb
Host smart-ac93288b-d318-46d5-80e5-2f152e184ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22870
26463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2287026463
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3074427194
Short name T808
Test name
Test status
Simulation time 162248901 ps
CPU time 0.89 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206176 kb
Host smart-54385311-db12-45dd-a663-c0c5c3b08faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30744
27194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3074427194
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2314079430
Short name T2505
Test name
Test status
Simulation time 245762675 ps
CPU time 0.93 seconds
Started Jul 06 05:28:13 PM PDT 24
Finished Jul 06 05:28:14 PM PDT 24
Peak memory 206204 kb
Host smart-694a26b3-f0d1-44b2-a9bd-e59fb2e1be5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140
79430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2314079430
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2246334755
Short name T1704
Test name
Test status
Simulation time 23386448329 ps
CPU time 23.34 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206200 kb
Host smart-17f418c1-9de8-45b0-b1d7-1bdd34c7903a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22463
34755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2246334755
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3745678422
Short name T671
Test name
Test status
Simulation time 3325463108 ps
CPU time 4.68 seconds
Started Jul 06 05:28:16 PM PDT 24
Finished Jul 06 05:28:21 PM PDT 24
Peak memory 206268 kb
Host smart-7179a183-c8a7-405e-a60c-1d3dac4ee880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37456
78422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3745678422
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.4193231929
Short name T2572
Test name
Test status
Simulation time 7420563370 ps
CPU time 193.89 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:31:50 PM PDT 24
Peak memory 206476 kb
Host smart-db187813-ef12-482e-aac1-b1a41eb066a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
31929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.4193231929
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1929174683
Short name T1646
Test name
Test status
Simulation time 5857866467 ps
CPU time 59.59 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:29:10 PM PDT 24
Peak memory 206460 kb
Host smart-626f775d-f35e-449f-b1ac-4958085374f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1929174683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1929174683
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1886868690
Short name T1405
Test name
Test status
Simulation time 258917071 ps
CPU time 0.92 seconds
Started Jul 06 05:28:18 PM PDT 24
Finished Jul 06 05:28:19 PM PDT 24
Peak memory 206156 kb
Host smart-f524e4ca-58b3-4585-80ea-480620798c49
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1886868690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1886868690
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1712407936
Short name T2536
Test name
Test status
Simulation time 231720920 ps
CPU time 0.89 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206184 kb
Host smart-9639fea2-c044-4c93-9579-86739a09ab85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
07936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1712407936
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3540609245
Short name T2296
Test name
Test status
Simulation time 4236152718 ps
CPU time 41.59 seconds
Started Jul 06 05:28:20 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206480 kb
Host smart-de67636a-2df9-4716-8b6a-dfd09ed3b286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35406
09245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3540609245
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1543972448
Short name T2546
Test name
Test status
Simulation time 5203492789 ps
CPU time 38.94 seconds
Started Jul 06 05:28:08 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206472 kb
Host smart-a4ae6a00-cd44-4268-8f05-457a969eb856
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1543972448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1543972448
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3016648054
Short name T318
Test name
Test status
Simulation time 157710679 ps
CPU time 0.84 seconds
Started Jul 06 05:28:27 PM PDT 24
Finished Jul 06 05:28:28 PM PDT 24
Peak memory 206200 kb
Host smart-7a25b8ce-3a5b-4043-bc4b-bb98066f6cda
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3016648054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3016648054
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2053403821
Short name T1324
Test name
Test status
Simulation time 143628026 ps
CPU time 0.77 seconds
Started Jul 06 05:28:12 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206164 kb
Host smart-1f2b5383-c433-428d-9f65-498dea6f5ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20534
03821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2053403821
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2227877521
Short name T118
Test name
Test status
Simulation time 202703277 ps
CPU time 0.9 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206180 kb
Host smart-749fb25f-cce2-402d-a07d-ccdd06c563fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22278
77521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2227877521
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1651126501
Short name T1682
Test name
Test status
Simulation time 164854386 ps
CPU time 0.81 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:08 PM PDT 24
Peak memory 206192 kb
Host smart-1a46c8e4-c051-4ad8-bad0-c203cf4d99f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
26501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1651126501
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2058743497
Short name T1779
Test name
Test status
Simulation time 241115153 ps
CPU time 0.91 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206200 kb
Host smart-88a59c54-482f-4e89-acd5-427805e0d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20587
43497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2058743497
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3767138824
Short name T2288
Test name
Test status
Simulation time 191123191 ps
CPU time 0.83 seconds
Started Jul 06 05:28:07 PM PDT 24
Finished Jul 06 05:28:09 PM PDT 24
Peak memory 206128 kb
Host smart-593a58c9-291a-47bc-a902-b99633d6e55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37671
38824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3767138824
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4208981988
Short name T2457
Test name
Test status
Simulation time 175519492 ps
CPU time 0.79 seconds
Started Jul 06 05:28:14 PM PDT 24
Finished Jul 06 05:28:15 PM PDT 24
Peak memory 206152 kb
Host smart-5b4c27c3-284d-438f-9447-9822c6f54720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089
81988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4208981988
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.976019268
Short name T2362
Test name
Test status
Simulation time 265815717 ps
CPU time 1.02 seconds
Started Jul 06 05:28:09 PM PDT 24
Finished Jul 06 05:28:10 PM PDT 24
Peak memory 206208 kb
Host smart-f971f539-1c4f-4b85-adcd-508a0bf2bd94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=976019268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.976019268
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4127463620
Short name T233
Test name
Test status
Simulation time 138400925 ps
CPU time 0.74 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206180 kb
Host smart-7a285a38-47f6-49d7-a8a5-a9ed39ce5373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41274
63620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4127463620
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.579646094
Short name T26
Test name
Test status
Simulation time 47048907 ps
CPU time 0.65 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206200 kb
Host smart-026e1a46-6649-4f04-afd9-3b7f83f9bef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57964
6094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.579646094
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2831735750
Short name T1469
Test name
Test status
Simulation time 16809240180 ps
CPU time 43.16 seconds
Started Jul 06 05:28:12 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206548 kb
Host smart-1ae3faeb-e9bf-4da3-8138-baca8175783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
35750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2831735750
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.459613591
Short name T2057
Test name
Test status
Simulation time 175455003 ps
CPU time 0.85 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206200 kb
Host smart-0fbc126d-45b8-4f90-a35d-540d5d87c517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45961
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.459613591
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3883583872
Short name T522
Test name
Test status
Simulation time 199018350 ps
CPU time 0.91 seconds
Started Jul 06 05:28:15 PM PDT 24
Finished Jul 06 05:28:16 PM PDT 24
Peak memory 206172 kb
Host smart-4aa5eaca-b6bb-4d2c-8e00-507ae3d7be90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835
83872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3883583872
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3611179798
Short name T977
Test name
Test status
Simulation time 318375326 ps
CPU time 0.92 seconds
Started Jul 06 05:28:25 PM PDT 24
Finished Jul 06 05:28:26 PM PDT 24
Peak memory 206224 kb
Host smart-de01f990-6359-455c-8d83-ca69e0e9b4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36111
79798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3611179798
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.864776984
Short name T2195
Test name
Test status
Simulation time 190575837 ps
CPU time 0.83 seconds
Started Jul 06 05:28:12 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206100 kb
Host smart-d47da5a3-082a-4e0e-a564-3c164431dc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86477
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.864776984
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1563322119
Short name T2331
Test name
Test status
Simulation time 145773458 ps
CPU time 0.78 seconds
Started Jul 06 05:28:27 PM PDT 24
Finished Jul 06 05:28:28 PM PDT 24
Peak memory 206168 kb
Host smart-b2bb09b3-03dd-47f4-bfd3-4884b643ec3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633
22119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1563322119
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.578156647
Short name T585
Test name
Test status
Simulation time 161251263 ps
CPU time 0.84 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:28:12 PM PDT 24
Peak memory 206188 kb
Host smart-340e02c9-1018-4eda-8d8c-c98c0b043c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57815
6647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.578156647
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3675847551
Short name T2212
Test name
Test status
Simulation time 212308461 ps
CPU time 0.88 seconds
Started Jul 06 05:28:12 PM PDT 24
Finished Jul 06 05:28:13 PM PDT 24
Peak memory 206200 kb
Host smart-1eafe207-05c4-4256-a857-6f2688301d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36758
47551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3675847551
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.4174234024
Short name T1042
Test name
Test status
Simulation time 210408456 ps
CPU time 0.91 seconds
Started Jul 06 05:28:28 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206012 kb
Host smart-40790fde-e201-4a26-b899-ea4513745e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41742
34024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.4174234024
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2853280009
Short name T550
Test name
Test status
Simulation time 7231544422 ps
CPU time 52.04 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:29:04 PM PDT 24
Peak memory 206520 kb
Host smart-88debeac-e51c-43ab-9b2d-a81fc82fc044
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2853280009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2853280009
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.819746554
Short name T2070
Test name
Test status
Simulation time 155711814 ps
CPU time 0.82 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206184 kb
Host smart-f96baa11-a522-4a2f-9733-ba9265214e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81974
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.819746554
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.65187826
Short name T1957
Test name
Test status
Simulation time 195562250 ps
CPU time 0.88 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206204 kb
Host smart-b39fead6-d90a-48bc-980a-4bf712ee5fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65187
826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.65187826
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.3272277318
Short name T624
Test name
Test status
Simulation time 492164239 ps
CPU time 1.35 seconds
Started Jul 06 05:28:18 PM PDT 24
Finished Jul 06 05:28:19 PM PDT 24
Peak memory 206012 kb
Host smart-a0d2df90-483c-43c1-b607-92368e2df200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32722
77318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3272277318
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.866824096
Short name T830
Test name
Test status
Simulation time 5085168681 ps
CPU time 35.57 seconds
Started Jul 06 05:28:26 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206468 kb
Host smart-a05ce5e4-dc6a-489d-8683-aefa7067fbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86682
4096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.866824096
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.489662740
Short name T603
Test name
Test status
Simulation time 47846257 ps
CPU time 0.67 seconds
Started Jul 06 05:28:31 PM PDT 24
Finished Jul 06 05:28:32 PM PDT 24
Peak memory 206268 kb
Host smart-e9ebb17a-b1dc-48e5-8a2f-6b16617ee28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=489662740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.489662740
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3593055504
Short name T2503
Test name
Test status
Simulation time 4250247856 ps
CPU time 5.28 seconds
Started Jul 06 05:28:13 PM PDT 24
Finished Jul 06 05:28:19 PM PDT 24
Peak memory 206516 kb
Host smart-167a6504-c319-4244-b624-0aa8309426d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3593055504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3593055504
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1468169405
Short name T1710
Test name
Test status
Simulation time 13384399632 ps
CPU time 13.39 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:28:24 PM PDT 24
Peak memory 206196 kb
Host smart-a8954536-a520-4201-9395-5fd03097ebef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1468169405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1468169405
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1931531616
Short name T1734
Test name
Test status
Simulation time 23334749243 ps
CPU time 24.72 seconds
Started Jul 06 05:28:12 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206244 kb
Host smart-20d6048a-fb36-48d3-bae3-7867dbbfd3f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1931531616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1931531616
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1211873786
Short name T906
Test name
Test status
Simulation time 194798217 ps
CPU time 0.82 seconds
Started Jul 06 05:28:39 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206200 kb
Host smart-8e305940-8403-46dc-9d4e-a2f204c85d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12118
73786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1211873786
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1947222011
Short name T989
Test name
Test status
Simulation time 156970871 ps
CPU time 0.83 seconds
Started Jul 06 05:28:22 PM PDT 24
Finished Jul 06 05:28:23 PM PDT 24
Peak memory 206204 kb
Host smart-992c0586-fb79-4eb7-a5d5-acdb615da57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472
22011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1947222011
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.4268549981
Short name T2409
Test name
Test status
Simulation time 338243750 ps
CPU time 1.21 seconds
Started Jul 06 05:28:30 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206188 kb
Host smart-68f60efc-1648-4883-a920-42036db653fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42685
49981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.4268549981
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.137154749
Short name T2534
Test name
Test status
Simulation time 1377544272 ps
CPU time 3.63 seconds
Started Jul 06 05:28:17 PM PDT 24
Finished Jul 06 05:28:21 PM PDT 24
Peak memory 206280 kb
Host smart-0ccefcf3-2985-4979-b75c-7cab33aca0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13715
4749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.137154749
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.424039337
Short name T505
Test name
Test status
Simulation time 8313909114 ps
CPU time 18.18 seconds
Started Jul 06 05:28:31 PM PDT 24
Finished Jul 06 05:28:50 PM PDT 24
Peak memory 206464 kb
Host smart-31d1d066-b7b3-4e7b-a373-6334d6770770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
9337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.424039337
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.901132358
Short name T1614
Test name
Test status
Simulation time 507327690 ps
CPU time 1.53 seconds
Started Jul 06 05:28:16 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 206064 kb
Host smart-dda11439-7830-4101-ad77-416520e6d51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90113
2358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.901132358
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2273234560
Short name T1035
Test name
Test status
Simulation time 154907217 ps
CPU time 0.77 seconds
Started Jul 06 05:28:10 PM PDT 24
Finished Jul 06 05:28:12 PM PDT 24
Peak memory 206164 kb
Host smart-9c2fb460-05d2-4f4e-b3d2-c2ee7005f50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22732
34560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2273234560
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1333564923
Short name T703
Test name
Test status
Simulation time 42613089 ps
CPU time 0.67 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:28:12 PM PDT 24
Peak memory 206156 kb
Host smart-1f4074f7-f9f9-4b07-8ffb-0272fc733492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13335
64923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1333564923
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.139067932
Short name T2155
Test name
Test status
Simulation time 870881918 ps
CPU time 1.97 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206356 kb
Host smart-1d771bdb-fb94-42d8-b634-576e3bf6922d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
7932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.139067932
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1659549873
Short name T2385
Test name
Test status
Simulation time 172538950 ps
CPU time 1.27 seconds
Started Jul 06 05:28:23 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206444 kb
Host smart-1101257a-51d3-4832-a951-8aa4fbc7cc41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16595
49873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1659549873
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3463718760
Short name T1343
Test name
Test status
Simulation time 177528516 ps
CPU time 0.86 seconds
Started Jul 06 05:28:09 PM PDT 24
Finished Jul 06 05:28:11 PM PDT 24
Peak memory 206172 kb
Host smart-4093655b-c373-4895-98b7-1ec33da2cf91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
18760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3463718760
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2161628416
Short name T1701
Test name
Test status
Simulation time 187954760 ps
CPU time 0.81 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:28:12 PM PDT 24
Peak memory 206164 kb
Host smart-c3549598-5e93-4bf8-85e0-5930a25cf3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21616
28416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2161628416
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1383020195
Short name T1275
Test name
Test status
Simulation time 165178714 ps
CPU time 0.83 seconds
Started Jul 06 05:28:35 PM PDT 24
Finished Jul 06 05:28:42 PM PDT 24
Peak memory 206204 kb
Host smart-7204851d-ce77-46ca-bbea-5a64a272e712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13830
20195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1383020195
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1889373680
Short name T1938
Test name
Test status
Simulation time 6369428587 ps
CPU time 168.37 seconds
Started Jul 06 05:28:11 PM PDT 24
Finished Jul 06 05:31:00 PM PDT 24
Peak memory 206516 kb
Host smart-dabf809d-9199-4df5-9435-818128462478
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1889373680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1889373680
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3789037145
Short name T379
Test name
Test status
Simulation time 233201387 ps
CPU time 0.88 seconds
Started Jul 06 05:28:13 PM PDT 24
Finished Jul 06 05:28:14 PM PDT 24
Peak memory 206204 kb
Host smart-d72cdbb8-cc7f-4325-880f-0357ca73bbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37890
37145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3789037145
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1775176430
Short name T2414
Test name
Test status
Simulation time 23305156057 ps
CPU time 23.14 seconds
Started Jul 06 05:28:31 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206080 kb
Host smart-bbbc5316-2baa-4d97-b3e2-9d9b955d1bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17751
76430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1775176430
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.463828574
Short name T2693
Test name
Test status
Simulation time 3302478799 ps
CPU time 4.03 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206208 kb
Host smart-7525be8a-a5c1-4052-9800-402518eef6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46382
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.463828574
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2451451863
Short name T2529
Test name
Test status
Simulation time 13827806585 ps
CPU time 125.28 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 206544 kb
Host smart-b378306c-a522-4206-b9da-346aababd01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24514
51863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2451451863
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.4078932727
Short name T1722
Test name
Test status
Simulation time 4497227811 ps
CPU time 41.75 seconds
Started Jul 06 05:28:20 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206316 kb
Host smart-ee36d417-d04a-4c25-9aa8-564bf415ac13
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4078932727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.4078932727
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.281588181
Short name T2700
Test name
Test status
Simulation time 287891801 ps
CPU time 0.97 seconds
Started Jul 06 05:28:13 PM PDT 24
Finished Jul 06 05:28:14 PM PDT 24
Peak memory 206204 kb
Host smart-b59c4f69-0456-4be7-b28f-5235984b1cc7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=281588181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.281588181
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1868559782
Short name T1017
Test name
Test status
Simulation time 195524503 ps
CPU time 0.95 seconds
Started Jul 06 05:28:16 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 206068 kb
Host smart-d82f4292-a0d2-4701-b5e0-9439a62747e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
59782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1868559782
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1475770412
Short name T2032
Test name
Test status
Simulation time 3626757162 ps
CPU time 33.95 seconds
Started Jul 06 05:28:16 PM PDT 24
Finished Jul 06 05:28:50 PM PDT 24
Peak memory 206460 kb
Host smart-67b91ab1-2646-444a-9f3d-216162472afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
70412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1475770412
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1723050543
Short name T2629
Test name
Test status
Simulation time 6609882211 ps
CPU time 46.7 seconds
Started Jul 06 05:28:22 PM PDT 24
Finished Jul 06 05:29:09 PM PDT 24
Peak memory 206404 kb
Host smart-d0c53099-6c53-4679-9eec-0968fc29307b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1723050543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1723050543
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3407439629
Short name T1963
Test name
Test status
Simulation time 158705996 ps
CPU time 0.8 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206196 kb
Host smart-100c94f6-eded-4f09-a47d-fae2d40c2d8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3407439629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3407439629
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3387191309
Short name T1599
Test name
Test status
Simulation time 140913779 ps
CPU time 0.74 seconds
Started Jul 06 05:28:17 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 206180 kb
Host smart-43ab506f-a3b3-4e86-9ff4-f35f3bda10c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33871
91309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3387191309
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1442624136
Short name T72
Test name
Test status
Simulation time 206064894 ps
CPU time 0.86 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206116 kb
Host smart-1598e2c3-53d2-4ad1-b74c-79b3ebc75d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14426
24136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1442624136
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4135434188
Short name T605
Test name
Test status
Simulation time 179308891 ps
CPU time 0.81 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206168 kb
Host smart-017ada93-5871-4071-a41a-683c896c7f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41354
34188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4135434188
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3301633765
Short name T1303
Test name
Test status
Simulation time 173177809 ps
CPU time 0.81 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206184 kb
Host smart-08c358e5-b06f-4090-b722-dc6558810c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33016
33765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3301633765
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3777795583
Short name T719
Test name
Test status
Simulation time 176859480 ps
CPU time 0.84 seconds
Started Jul 06 05:28:23 PM PDT 24
Finished Jul 06 05:28:24 PM PDT 24
Peak memory 206204 kb
Host smart-620b6732-0fd3-49b7-ba2f-ba0ece1beefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
95583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3777795583
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3951454853
Short name T670
Test name
Test status
Simulation time 151800579 ps
CPU time 0.85 seconds
Started Jul 06 05:28:17 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 206180 kb
Host smart-8ec34922-b89c-45ad-bc6f-d24926b0dc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39514
54853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3951454853
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2445677891
Short name T2304
Test name
Test status
Simulation time 220734193 ps
CPU time 1 seconds
Started Jul 06 05:28:19 PM PDT 24
Finished Jul 06 05:28:20 PM PDT 24
Peak memory 206124 kb
Host smart-002e683b-1dc5-42ec-9ada-d3b8703076b5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2445677891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2445677891
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.4011069521
Short name T1412
Test name
Test status
Simulation time 153561197 ps
CPU time 0.78 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206164 kb
Host smart-09d51567-93ef-4130-bdb5-a5cfff88cadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40110
69521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.4011069521
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3604080216
Short name T2407
Test name
Test status
Simulation time 76502204 ps
CPU time 0.67 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206172 kb
Host smart-5dfd9063-abb8-4f2b-9982-14a3841abd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36040
80216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3604080216
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1691052225
Short name T1225
Test name
Test status
Simulation time 14184650206 ps
CPU time 30.81 seconds
Started Jul 06 05:28:18 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206400 kb
Host smart-ee88731f-ecac-4244-9fba-acc888b4602f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
52225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1691052225
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3499875707
Short name T1104
Test name
Test status
Simulation time 181477949 ps
CPU time 0.86 seconds
Started Jul 06 05:28:18 PM PDT 24
Finished Jul 06 05:28:19 PM PDT 24
Peak memory 206200 kb
Host smart-f29601ca-126d-4d05-abf4-bcafc8bf31f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998
75707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3499875707
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.918299333
Short name T393
Test name
Test status
Simulation time 199609316 ps
CPU time 0.83 seconds
Started Jul 06 05:28:20 PM PDT 24
Finished Jul 06 05:28:21 PM PDT 24
Peak memory 206120 kb
Host smart-2947847f-6cdb-4f60-9ad2-495854e37301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91829
9333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.918299333
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.3633837275
Short name T1298
Test name
Test status
Simulation time 236493715 ps
CPU time 0.96 seconds
Started Jul 06 05:28:17 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 206104 kb
Host smart-f93cf07c-55bf-4f34-8bae-75542dc9cd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338
37275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.3633837275
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1429274221
Short name T1005
Test name
Test status
Simulation time 174497139 ps
CPU time 0.8 seconds
Started Jul 06 05:28:30 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206204 kb
Host smart-ca5147bc-4eaf-4d5c-92bb-0ed840e0aab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14292
74221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1429274221
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1509880477
Short name T957
Test name
Test status
Simulation time 161554349 ps
CPU time 0.86 seconds
Started Jul 06 05:28:29 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206120 kb
Host smart-d87d7d50-6aa3-48a2-8a74-bd9ea679a990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15098
80477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1509880477
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2237331409
Short name T1920
Test name
Test status
Simulation time 151190709 ps
CPU time 0.77 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206176 kb
Host smart-c713ff19-db24-43d0-87e4-b46bf394c958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22373
31409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2237331409
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1334483514
Short name T1997
Test name
Test status
Simulation time 158105713 ps
CPU time 0.86 seconds
Started Jul 06 05:28:17 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 206120 kb
Host smart-ec9cdefb-10dd-4b53-8db0-615f2315353f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13344
83514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1334483514
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3176715028
Short name T402
Test name
Test status
Simulation time 226276608 ps
CPU time 0.99 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:28:41 PM PDT 24
Peak memory 205780 kb
Host smart-fcb8d409-c43b-4fe3-920e-76f16c638c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31767
15028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3176715028
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2587697158
Short name T1535
Test name
Test status
Simulation time 6845892301 ps
CPU time 182.67 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:31:39 PM PDT 24
Peak memory 206508 kb
Host smart-2e222c94-a379-4296-83f8-6b314a33c163
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2587697158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2587697158
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1354107045
Short name T1285
Test name
Test status
Simulation time 169229415 ps
CPU time 0.86 seconds
Started Jul 06 05:28:42 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206128 kb
Host smart-cb2d83a2-10c4-47ba-9016-763f43f9f73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13541
07045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1354107045
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1362822545
Short name T1609
Test name
Test status
Simulation time 218678905 ps
CPU time 0.97 seconds
Started Jul 06 05:28:18 PM PDT 24
Finished Jul 06 05:28:19 PM PDT 24
Peak memory 206184 kb
Host smart-0eeb826e-5bda-43ce-a4bc-f78208aeec57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13628
22545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1362822545
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2409996557
Short name T2417
Test name
Test status
Simulation time 192217552 ps
CPU time 0.9 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:52 PM PDT 24
Peak memory 206200 kb
Host smart-3a361e61-ab7d-4b97-9855-a4f1421b93bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24099
96557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2409996557
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2076395577
Short name T2396
Test name
Test status
Simulation time 5316030600 ps
CPU time 143.76 seconds
Started Jul 06 05:28:29 PM PDT 24
Finished Jul 06 05:31:03 PM PDT 24
Peak memory 206488 kb
Host smart-76e862d0-b718-4066-969f-3e14c4cb847d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20763
95577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2076395577
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.4029870553
Short name T2420
Test name
Test status
Simulation time 100059500 ps
CPU time 0.72 seconds
Started Jul 06 05:28:39 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206240 kb
Host smart-2ad9dffc-5e3e-4e87-80ea-00adf45afafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4029870553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4029870553
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1724258990
Short name T1387
Test name
Test status
Simulation time 3741554519 ps
CPU time 4.35 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:36 PM PDT 24
Peak memory 206376 kb
Host smart-c3aef164-da81-4871-9571-95e0e6e7cbdf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1724258990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1724258990
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3849768736
Short name T1291
Test name
Test status
Simulation time 13413882680 ps
CPU time 12.58 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206532 kb
Host smart-64dd9ed4-8972-470d-a874-4059992e45b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3849768736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3849768736
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3994152125
Short name T1604
Test name
Test status
Simulation time 23439249376 ps
CPU time 23.26 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206444 kb
Host smart-f2d6910e-3040-42e0-8a90-55806459760d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3994152125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3994152125
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3826842029
Short name T1140
Test name
Test status
Simulation time 199496453 ps
CPU time 0.87 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206116 kb
Host smart-9e605915-d505-48af-af64-16990c8d187d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38268
42029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3826842029
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2157511898
Short name T806
Test name
Test status
Simulation time 190740419 ps
CPU time 0.82 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206196 kb
Host smart-35aa7052-754e-4e8d-931a-8b8d9b2544d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21575
11898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2157511898
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.706464821
Short name T2341
Test name
Test status
Simulation time 443608702 ps
CPU time 1.46 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:52 PM PDT 24
Peak memory 206160 kb
Host smart-20a10477-8dd9-40c5-8b67-5c6c4f7487fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70646
4821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.706464821
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1987354396
Short name T160
Test name
Test status
Simulation time 1018491342 ps
CPU time 2.32 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:24 PM PDT 24
Peak memory 206376 kb
Host smart-62aaeb00-49ad-4eb1-b82d-16864fa4ba37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
54396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1987354396
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.572853700
Short name T1978
Test name
Test status
Simulation time 18926646226 ps
CPU time 37.35 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:29:32 PM PDT 24
Peak memory 206456 kb
Host smart-5ca295aa-937c-4d9e-83fe-9f5fea746a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57285
3700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.572853700
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.2865970468
Short name T2430
Test name
Test status
Simulation time 465608023 ps
CPU time 1.4 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:28:53 PM PDT 24
Peak memory 205996 kb
Host smart-dd5ea86d-d9d1-45df-91ae-3fcf62c348ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28659
70468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.2865970468
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1937857043
Short name T2683
Test name
Test status
Simulation time 163041765 ps
CPU time 0.76 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206120 kb
Host smart-e21e79eb-d158-4d7c-9f8c-0b51b2998ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378
57043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1937857043
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1603088055
Short name T450
Test name
Test status
Simulation time 46424569 ps
CPU time 0.67 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206144 kb
Host smart-d58b6f1b-c189-453d-adfc-94b6a33866c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16030
88055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1603088055
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2813822526
Short name T886
Test name
Test status
Simulation time 668985425 ps
CPU time 1.82 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:24 PM PDT 24
Peak memory 206448 kb
Host smart-be04e06b-d01e-49e5-b69c-36c2a7620b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28138
22526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2813822526
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.928258515
Short name T1878
Test name
Test status
Simulation time 178062754 ps
CPU time 1.86 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206448 kb
Host smart-45800679-796a-4ae3-80da-7f7304ad2b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92825
8515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.928258515
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4041758213
Short name T1623
Test name
Test status
Simulation time 159084280 ps
CPU time 0.78 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206092 kb
Host smart-43e2d74d-c6f0-4fb4-bd30-8ab207a3d315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40417
58213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4041758213
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2733295373
Short name T1757
Test name
Test status
Simulation time 152721939 ps
CPU time 0.77 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206168 kb
Host smart-02ad8b59-d64c-46b7-94ea-dee3dec26d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27332
95373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2733295373
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1315374722
Short name T589
Test name
Test status
Simulation time 246575036 ps
CPU time 0.97 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206176 kb
Host smart-44ef7487-e0a8-4c95-8194-e6ea27ee86ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13153
74722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1315374722
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3375946398
Short name T1470
Test name
Test status
Simulation time 7051644016 ps
CPU time 69.96 seconds
Started Jul 06 05:28:23 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 206456 kb
Host smart-a82361c2-5883-4f90-9085-93b09c3ab391
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3375946398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3375946398
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1612063282
Short name T930
Test name
Test status
Simulation time 180408384 ps
CPU time 0.82 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206160 kb
Host smart-5c35f22c-7c8a-4e86-9790-78901c2087ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
63282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1612063282
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3019209284
Short name T921
Test name
Test status
Simulation time 23349169700 ps
CPU time 23.71 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:29:05 PM PDT 24
Peak memory 206248 kb
Host smart-a62837eb-2038-4801-8c6e-70389fa40f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30192
09284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3019209284
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.539545749
Short name T1884
Test name
Test status
Simulation time 3287635344 ps
CPU time 4.32 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206256 kb
Host smart-67873655-a961-4286-87b7-a88d916288d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53954
5749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.539545749
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2462091563
Short name T701
Test name
Test status
Simulation time 12517783469 ps
CPU time 344.33 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:34:06 PM PDT 24
Peak memory 206444 kb
Host smart-42640e1a-1bc7-4704-99a9-1c2482333f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
91563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2462091563
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3753193531
Short name T2619
Test name
Test status
Simulation time 3652405407 ps
CPU time 95.74 seconds
Started Jul 06 05:28:22 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 206444 kb
Host smart-f407d010-85d1-44da-b07c-3fcaebdbe230
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3753193531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3753193531
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3051270601
Short name T1116
Test name
Test status
Simulation time 244603134 ps
CPU time 0.88 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206200 kb
Host smart-692d8a84-edce-4e07-893d-a7c7a9ac8869
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3051270601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3051270601
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.166422367
Short name T2176
Test name
Test status
Simulation time 208415963 ps
CPU time 0.9 seconds
Started Jul 06 05:28:23 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206160 kb
Host smart-09bd6e01-bf28-40cd-9598-a401a28e1a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16642
2367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.166422367
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1337602962
Short name T576
Test name
Test status
Simulation time 5881866022 ps
CPU time 158.02 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:31:14 PM PDT 24
Peak memory 206444 kb
Host smart-e206b9f1-c9b0-4288-9c30-0f0fc8d5fd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
02962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1337602962
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1277553986
Short name T1297
Test name
Test status
Simulation time 5825061715 ps
CPU time 40.02 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:29:21 PM PDT 24
Peak memory 206040 kb
Host smart-d7a2c0b5-902c-4116-9cce-1d80a5e5cec2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1277553986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1277553986
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3890634457
Short name T1897
Test name
Test status
Simulation time 154468928 ps
CPU time 0.8 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206144 kb
Host smart-4b20a182-8faa-4ad5-bac0-f71deca6769b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3890634457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3890634457
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1037032671
Short name T738
Test name
Test status
Simulation time 144669735 ps
CPU time 0.8 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206128 kb
Host smart-239999f4-5eaa-49a8-9f8a-e6e0a7bbe03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
32671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1037032671
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2899292039
Short name T131
Test name
Test status
Simulation time 271085456 ps
CPU time 0.97 seconds
Started Jul 06 05:28:39 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206012 kb
Host smart-2c65db3c-a27d-47cd-b134-d8e452dd0fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28992
92039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2899292039
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2073252387
Short name T2582
Test name
Test status
Simulation time 162883605 ps
CPU time 0.81 seconds
Started Jul 06 05:28:39 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206156 kb
Host smart-31073ea9-c6c6-4e64-939b-3105c1d15855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
52387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2073252387
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.216402377
Short name T1889
Test name
Test status
Simulation time 169024278 ps
CPU time 0.84 seconds
Started Jul 06 05:28:23 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206200 kb
Host smart-d8589650-1260-4960-b4dc-a7a425662db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
2377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.216402377
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2325376042
Short name T621
Test name
Test status
Simulation time 146712467 ps
CPU time 0.78 seconds
Started Jul 06 05:28:24 PM PDT 24
Finished Jul 06 05:28:25 PM PDT 24
Peak memory 206204 kb
Host smart-a573191a-af94-49ef-adb5-4cb0a2634baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
76042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2325376042
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.829388127
Short name T2622
Test name
Test status
Simulation time 157814028 ps
CPU time 0.77 seconds
Started Jul 06 05:32:25 PM PDT 24
Finished Jul 06 05:32:26 PM PDT 24
Peak memory 206012 kb
Host smart-b4e0785d-b66a-421a-8ffd-5ce31c6b9d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82938
8127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.829388127
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.6060169
Short name T1521
Test name
Test status
Simulation time 250464202 ps
CPU time 0.9 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206016 kb
Host smart-26fdad83-f9a9-4b0e-b3d8-a13d7677808b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=6060169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.6060169
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1812857821
Short name T1558
Test name
Test status
Simulation time 141467228 ps
CPU time 0.77 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206180 kb
Host smart-26a0ac06-ecd6-4e22-93ed-afbd6c353274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
57821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1812857821
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.4229269751
Short name T910
Test name
Test status
Simulation time 62283440 ps
CPU time 0.74 seconds
Started Jul 06 05:28:21 PM PDT 24
Finished Jul 06 05:28:22 PM PDT 24
Peak memory 206184 kb
Host smart-59c9edb2-9b88-4268-9c2f-facc39dd8805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
69751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.4229269751
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2223253635
Short name T266
Test name
Test status
Simulation time 14104721417 ps
CPU time 30.9 seconds
Started Jul 06 05:28:31 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206544 kb
Host smart-ab70f306-86e6-4faa-9cc6-d391bb964cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22232
53635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2223253635
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2912868966
Short name T2022
Test name
Test status
Simulation time 159453175 ps
CPU time 0.78 seconds
Started Jul 06 05:28:27 PM PDT 24
Finished Jul 06 05:28:28 PM PDT 24
Peak memory 206164 kb
Host smart-d1b4a49c-8a37-460f-b9e4-19219581680e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29128
68966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2912868966
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2901124110
Short name T1982
Test name
Test status
Simulation time 225368452 ps
CPU time 0.92 seconds
Started Jul 06 05:28:30 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206172 kb
Host smart-04cff8c1-8188-473a-babe-193a3dd7e34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29011
24110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2901124110
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1186477656
Short name T981
Test name
Test status
Simulation time 219112603 ps
CPU time 0.87 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206088 kb
Host smart-b80075fb-351c-4803-99e0-ea628a664474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11864
77656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1186477656
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1255511818
Short name T1411
Test name
Test status
Simulation time 193318758 ps
CPU time 0.86 seconds
Started Jul 06 05:28:31 PM PDT 24
Finished Jul 06 05:28:32 PM PDT 24
Peak memory 206180 kb
Host smart-3c048749-a070-4086-9e7b-9ee2934651b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12555
11818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1255511818
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.983832969
Short name T2233
Test name
Test status
Simulation time 189127525 ps
CPU time 0.83 seconds
Started Jul 06 05:28:28 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206200 kb
Host smart-80f58c17-ae75-41f0-905a-c22519aa9e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98383
2969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.983832969
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1265486022
Short name T1235
Test name
Test status
Simulation time 158468964 ps
CPU time 0.83 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206148 kb
Host smart-8c6e355e-d9e9-4afa-af86-d1dd1d7c9a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
86022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1265486022
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3945356368
Short name T928
Test name
Test status
Simulation time 151084069 ps
CPU time 0.78 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206212 kb
Host smart-24533d3d-8f32-405a-9a96-d0d02a0233ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
56368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3945356368
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3695928437
Short name T1367
Test name
Test status
Simulation time 229419959 ps
CPU time 0.94 seconds
Started Jul 06 05:28:31 PM PDT 24
Finished Jul 06 05:28:32 PM PDT 24
Peak memory 206084 kb
Host smart-e208c971-1849-4cde-a08b-e3b466306bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
28437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3695928437
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.28125062
Short name T628
Test name
Test status
Simulation time 6316063984 ps
CPU time 179.65 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:31:33 PM PDT 24
Peak memory 206516 kb
Host smart-d1d65d22-6873-4d16-8b5a-4a4556c423b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=28125062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.28125062
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.4164167102
Short name T920
Test name
Test status
Simulation time 160366435 ps
CPU time 0.8 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206148 kb
Host smart-91354e5a-15ed-484c-9e59-3bf7540b9fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41641
67102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.4164167102
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.915419845
Short name T1245
Test name
Test status
Simulation time 169473543 ps
CPU time 0.78 seconds
Started Jul 06 05:28:30 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206112 kb
Host smart-2bb10d9c-a17b-4ce3-a9ef-9ee2183397fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91541
9845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.915419845
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.319840028
Short name T858
Test name
Test status
Simulation time 329440594 ps
CPU time 1.11 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206176 kb
Host smart-5251ef7c-7ae1-4d70-bcb2-d16cb4854d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31984
0028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.319840028
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.4077751519
Short name T1178
Test name
Test status
Simulation time 4452975879 ps
CPU time 40.72 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206272 kb
Host smart-c2cbec94-b3fd-4444-b981-eb17d0c5de61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40777
51519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.4077751519
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3705423506
Short name T1861
Test name
Test status
Simulation time 34872532 ps
CPU time 0.63 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206140 kb
Host smart-ca26cc0d-fec3-40ea-9880-3657ef598c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3705423506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3705423506
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2169312632
Short name T1743
Test name
Test status
Simulation time 3973074203 ps
CPU time 4.56 seconds
Started Jul 06 05:28:27 PM PDT 24
Finished Jul 06 05:28:32 PM PDT 24
Peak memory 206516 kb
Host smart-c667c1dd-06c9-49ca-b372-288c24945ff3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2169312632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2169312632
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.910739665
Short name T1156
Test name
Test status
Simulation time 13337013574 ps
CPU time 12.53 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:29:09 PM PDT 24
Peak memory 206420 kb
Host smart-a8c6f141-5cb2-4a02-ab74-e88e84438bac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=910739665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.910739665
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3157695724
Short name T2350
Test name
Test status
Simulation time 23376359718 ps
CPU time 23.73 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:29:14 PM PDT 24
Peak memory 206284 kb
Host smart-414a7c09-cd03-4c5f-ab15-487653358eb2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3157695724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3157695724
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1202446879
Short name T482
Test name
Test status
Simulation time 176569434 ps
CPU time 0.87 seconds
Started Jul 06 05:28:30 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206200 kb
Host smart-8bc05104-ceca-441a-b9b5-77a5b16f0c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024
46879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1202446879
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2537811734
Short name T2661
Test name
Test status
Simulation time 160028034 ps
CPU time 0.88 seconds
Started Jul 06 05:28:29 PM PDT 24
Finished Jul 06 05:28:30 PM PDT 24
Peak memory 206188 kb
Host smart-c7a186d9-46e2-45cc-9463-4bd5868f47ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
11734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2537811734
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3107015105
Short name T1705
Test name
Test status
Simulation time 414158080 ps
CPU time 1.32 seconds
Started Jul 06 05:28:28 PM PDT 24
Finished Jul 06 05:28:29 PM PDT 24
Peak memory 206204 kb
Host smart-9c7ba855-d99c-49c3-bfab-d2275fff9ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31070
15105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3107015105
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1799558659
Short name T374
Test name
Test status
Simulation time 12007420009 ps
CPU time 23.34 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206452 kb
Host smart-aca95b9c-1353-41f3-9334-6b73eed8601f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
58659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1799558659
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1616287227
Short name T1127
Test name
Test status
Simulation time 385242139 ps
CPU time 1.28 seconds
Started Jul 06 05:28:42 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206116 kb
Host smart-18713aae-3d4d-4fe8-9d54-e364195e96fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16162
87227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1616287227
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_enable.3687770177
Short name T848
Test name
Test status
Simulation time 37041013 ps
CPU time 0.63 seconds
Started Jul 06 05:28:45 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206120 kb
Host smart-a462684f-5c20-4178-a982-011997e02254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36877
70177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3687770177
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3802552272
Short name T2278
Test name
Test status
Simulation time 810714668 ps
CPU time 2.05 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206412 kb
Host smart-c7271919-abe6-417d-8e73-0763209434ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38025
52272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3802552272
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1467305539
Short name T2246
Test name
Test status
Simulation time 158491680 ps
CPU time 1.24 seconds
Started Jul 06 05:29:35 PM PDT 24
Finished Jul 06 05:29:37 PM PDT 24
Peak memory 206188 kb
Host smart-7f77c485-409b-4332-869e-033b4a3ac9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14673
05539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1467305539
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3087020710
Short name T1782
Test name
Test status
Simulation time 198411062 ps
CPU time 0.87 seconds
Started Jul 06 05:28:29 PM PDT 24
Finished Jul 06 05:28:31 PM PDT 24
Peak memory 206092 kb
Host smart-8b914ed3-4215-4d35-9189-e24014a33357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870
20710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3087020710
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2741000119
Short name T2511
Test name
Test status
Simulation time 148207640 ps
CPU time 0.78 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206168 kb
Host smart-43ed6ed7-f7e1-43fb-9c7b-c68c458ccbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27410
00119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2741000119
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.141961073
Short name T1577
Test name
Test status
Simulation time 175092685 ps
CPU time 0.83 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206200 kb
Host smart-acfc8d88-58e2-45c3-bc26-8c41a50969fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14196
1073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.141961073
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.4250038745
Short name T903
Test name
Test status
Simulation time 281176536 ps
CPU time 0.92 seconds
Started Jul 06 05:28:38 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206200 kb
Host smart-81bf3dfb-84eb-4fc3-89fb-855c32b3cbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42500
38745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.4250038745
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1646156742
Short name T673
Test name
Test status
Simulation time 23360096731 ps
CPU time 21.47 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:29:17 PM PDT 24
Peak memory 206256 kb
Host smart-a90e2604-92e1-4a9b-9ec0-99c8f2cc9271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461
56742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1646156742
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.870262389
Short name T471
Test name
Test status
Simulation time 3317788590 ps
CPU time 3.53 seconds
Started Jul 06 05:28:29 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206172 kb
Host smart-41781a24-35fe-4c5f-97ea-9301839f8d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87026
2389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.870262389
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.297700585
Short name T2369
Test name
Test status
Simulation time 8803940472 ps
CPU time 235.2 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:32:28 PM PDT 24
Peak memory 206504 kb
Host smart-2b73d572-93f6-4312-b031-1d04230f648d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29770
0585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.297700585
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3545100656
Short name T2045
Test name
Test status
Simulation time 5056453563 ps
CPU time 50.5 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:29:23 PM PDT 24
Peak memory 206452 kb
Host smart-c1779a88-3173-480b-b39b-8d12fad1c52c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3545100656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3545100656
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1834644167
Short name T967
Test name
Test status
Simulation time 246174613 ps
CPU time 0.91 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206124 kb
Host smart-a0242b70-062e-47f5-ad76-0515419552b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1834644167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1834644167
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2526784256
Short name T1176
Test name
Test status
Simulation time 265433555 ps
CPU time 0.89 seconds
Started Jul 06 05:29:40 PM PDT 24
Finished Jul 06 05:29:41 PM PDT 24
Peak memory 205944 kb
Host smart-dbb8e1f2-6c49-40ec-bf04-faed447caead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25267
84256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2526784256
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1671805913
Short name T2585
Test name
Test status
Simulation time 5005818048 ps
CPU time 31.74 seconds
Started Jul 06 05:29:26 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 206204 kb
Host smart-5bb5b84f-e8a8-493b-9e03-2ebd8ff4938a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718
05913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1671805913
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.219243958
Short name T1565
Test name
Test status
Simulation time 4590169532 ps
CPU time 33.23 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:29:07 PM PDT 24
Peak memory 206408 kb
Host smart-b6835d86-4f5f-461e-80ba-b920d8ba70f8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=219243958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.219243958
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.554556168
Short name T2262
Test name
Test status
Simulation time 164697460 ps
CPU time 0.8 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206176 kb
Host smart-4474b56d-ecd7-4fdf-baaf-5a77f5862e10
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=554556168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.554556168
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2218079563
Short name T1735
Test name
Test status
Simulation time 156541366 ps
CPU time 0.78 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206192 kb
Host smart-1f2f6206-38ca-47bf-b756-de90eb1660d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22180
79563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2218079563
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.16427703
Short name T114
Test name
Test status
Simulation time 245353992 ps
CPU time 0.91 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206168 kb
Host smart-39be6202-05a9-4f01-b5a2-8312f2f8722d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16427
703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.16427703
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2214636487
Short name T1246
Test name
Test status
Simulation time 199743256 ps
CPU time 0.85 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:36 PM PDT 24
Peak memory 206212 kb
Host smart-be99e265-a12b-4e7f-944a-a1e32981248c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
36487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2214636487
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.807394831
Short name T2001
Test name
Test status
Simulation time 197864080 ps
CPU time 0.81 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:33 PM PDT 24
Peak memory 206084 kb
Host smart-c45fc9e8-e241-4e4e-a57d-d7c4ada1b7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80739
4831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.807394831
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.4118318010
Short name T1608
Test name
Test status
Simulation time 177926751 ps
CPU time 0.79 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206196 kb
Host smart-7a201a81-1c6c-4ec6-ba60-bedda1fa28cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41183
18010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.4118318010
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4132912307
Short name T460
Test name
Test status
Simulation time 152271292 ps
CPU time 0.79 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206176 kb
Host smart-d2f22560-0f71-4381-bf59-141f3d57c6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41329
12307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4132912307
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.4289984667
Short name T2359
Test name
Test status
Simulation time 220188256 ps
CPU time 1 seconds
Started Jul 06 05:28:35 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206208 kb
Host smart-720e9dc9-3a1a-4c2a-ad34-13730cae7883
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4289984667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.4289984667
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2349087823
Short name T926
Test name
Test status
Simulation time 146095798 ps
CPU time 0.78 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206160 kb
Host smart-2fabb7c0-a001-4d88-ad5b-b3ec14e46e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23490
87823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2349087823
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3430241014
Short name T1742
Test name
Test status
Simulation time 36135455 ps
CPU time 0.66 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206192 kb
Host smart-5445f9b8-d98d-44cf-8325-aa9000d1f538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34302
41014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3430241014
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1526671877
Short name T2480
Test name
Test status
Simulation time 20034766027 ps
CPU time 45.13 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:29:30 PM PDT 24
Peak memory 206388 kb
Host smart-2aac9c6f-010b-427b-8b00-cc8dd271a85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15266
71877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1526671877
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.976848869
Short name T2426
Test name
Test status
Simulation time 182564438 ps
CPU time 0.88 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:28:52 PM PDT 24
Peak memory 206220 kb
Host smart-ef6459f9-4450-49da-8498-446156411e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97684
8869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.976848869
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2189935631
Short name T2370
Test name
Test status
Simulation time 175070400 ps
CPU time 0.86 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206204 kb
Host smart-82c33af2-543b-49a6-b948-506ddf218ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21899
35631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2189935631
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2806325703
Short name T1077
Test name
Test status
Simulation time 230422731 ps
CPU time 0.92 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206224 kb
Host smart-aac02c5c-9e3c-4fde-9fc9-75500292a8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28063
25703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2806325703
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1316482035
Short name T751
Test name
Test status
Simulation time 179209120 ps
CPU time 0.88 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206180 kb
Host smart-b1fdf07c-42bb-4af7-b0fc-699f4eb40d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
82035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1316482035
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3081525696
Short name T2013
Test name
Test status
Simulation time 142581125 ps
CPU time 0.78 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206156 kb
Host smart-80b7e4ef-3698-4e04-a0f1-421d90525131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
25696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3081525696
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3099833519
Short name T1134
Test name
Test status
Simulation time 152035605 ps
CPU time 0.81 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206196 kb
Host smart-4a1c789e-0f15-4d5c-9bcf-20b62fa1b1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
33519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3099833519
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1448304805
Short name T1708
Test name
Test status
Simulation time 156834295 ps
CPU time 0.76 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206184 kb
Host smart-2a2eaa45-9bd9-4204-b5c0-d5722b554351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14483
04805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1448304805
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1118360138
Short name T1818
Test name
Test status
Simulation time 222511144 ps
CPU time 0.91 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206160 kb
Host smart-fea6adeb-bb02-4d04-afb5-dc3cc427b806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11183
60138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1118360138
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2354588237
Short name T1082
Test name
Test status
Simulation time 5696574676 ps
CPU time 167.14 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:31:20 PM PDT 24
Peak memory 206496 kb
Host smart-912703b3-2254-49b9-ad01-0b349fd8bf3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2354588237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2354588237
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2997505271
Short name T656
Test name
Test status
Simulation time 193301615 ps
CPU time 0.81 seconds
Started Jul 06 05:28:37 PM PDT 24
Finished Jul 06 05:28:38 PM PDT 24
Peak memory 206188 kb
Host smart-4a39a4ae-5b86-414a-b526-192448e04914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
05271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2997505271
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2550708384
Short name T1238
Test name
Test status
Simulation time 182367276 ps
CPU time 0.81 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206196 kb
Host smart-7eaac895-53fd-44de-93b6-a147f4de2819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25507
08384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2550708384
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2415046699
Short name T2590
Test name
Test status
Simulation time 859534915 ps
CPU time 2 seconds
Started Jul 06 05:28:37 PM PDT 24
Finished Jul 06 05:28:39 PM PDT 24
Peak memory 206364 kb
Host smart-ff2f8cc3-be24-400b-9ab9-d0c95ae1e762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24150
46699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2415046699
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2864831002
Short name T1397
Test name
Test status
Simulation time 4679460927 ps
CPU time 45.27 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:29:21 PM PDT 24
Peak memory 206496 kb
Host smart-30e0e49e-3bef-42f0-aead-b81f39ef326b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28648
31002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2864831002
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2161788777
Short name T2267
Test name
Test status
Simulation time 34394683 ps
CPU time 0.68 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206208 kb
Host smart-fe08b659-37db-48c4-a2ab-d1d137c25b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2161788777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2161788777
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1103043015
Short name T12
Test name
Test status
Simulation time 4006360947 ps
CPU time 4.45 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:54 PM PDT 24
Peak memory 206416 kb
Host smart-01da7ade-141b-450c-b3d5-2c6e980c169f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1103043015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1103043015
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2654238957
Short name T1534
Test name
Test status
Simulation time 13412351228 ps
CPU time 13.07 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206444 kb
Host smart-c78cfce7-9582-43fe-a50c-23d7daf2b05f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2654238957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2654238957
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2989081258
Short name T1499
Test name
Test status
Simulation time 23482301408 ps
CPU time 27.73 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:29:12 PM PDT 24
Peak memory 206512 kb
Host smart-9e2a15bc-5d32-4b6e-a482-3c4b6f13a198
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2989081258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.2989081258
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.821622438
Short name T1691
Test name
Test status
Simulation time 164047123 ps
CPU time 0.84 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206192 kb
Host smart-51edc05c-ab8c-449b-a2dc-fa60fef4bfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82162
2438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.821622438
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3855184048
Short name T1160
Test name
Test status
Simulation time 153121435 ps
CPU time 0.81 seconds
Started Jul 06 05:28:33 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206100 kb
Host smart-62cd4eb6-0298-43e5-9012-d354ef45bfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
84048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3855184048
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1931413005
Short name T1790
Test name
Test status
Simulation time 437132818 ps
CPU time 1.37 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206216 kb
Host smart-9edf5e38-f520-439b-9fc8-8777880cc3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19314
13005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1931413005
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3926243342
Short name T2258
Test name
Test status
Simulation time 431796841 ps
CPU time 1.18 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206208 kb
Host smart-580a14a0-7f44-4619-82eb-02faa8bf152b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39262
43342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3926243342
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2974561799
Short name T1065
Test name
Test status
Simulation time 11851546471 ps
CPU time 25.37 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 206544 kb
Host smart-a47208e1-38e9-4ddb-a228-dccbc9482c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
61799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2974561799
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4181569387
Short name T2054
Test name
Test status
Simulation time 318384353 ps
CPU time 1.17 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206160 kb
Host smart-e3b92903-c315-4ab7-aa11-3bf476ea5094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41815
69387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4181569387
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.4005165396
Short name T1363
Test name
Test status
Simulation time 143297871 ps
CPU time 0.85 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206200 kb
Host smart-e1116f7e-603c-4c7c-8b09-a66243794b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40051
65396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.4005165396
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3673192199
Short name T1998
Test name
Test status
Simulation time 39710438 ps
CPU time 0.69 seconds
Started Jul 06 05:28:34 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 206180 kb
Host smart-4db41666-3d16-4b06-a742-cda043aa4b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731
92199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3673192199
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.200654870
Short name T1078
Test name
Test status
Simulation time 942309125 ps
CPU time 2.15 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206432 kb
Host smart-e1e1802c-e4c8-4d74-bbd8-dbb3ac8f8747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20065
4870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.200654870
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2228637046
Short name T777
Test name
Test status
Simulation time 265719057 ps
CPU time 1.55 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206372 kb
Host smart-e0663654-4b47-4a33-9c1c-2f0d64c7cc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22286
37046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2228637046
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3838823107
Short name T28
Test name
Test status
Simulation time 279230366 ps
CPU time 0.97 seconds
Started Jul 06 05:28:32 PM PDT 24
Finished Jul 06 05:28:34 PM PDT 24
Peak memory 206156 kb
Host smart-8f67b42b-5234-476c-9b8a-78a31c49a8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
23107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3838823107
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1138256286
Short name T2298
Test name
Test status
Simulation time 163091048 ps
CPU time 0.8 seconds
Started Jul 06 05:28:36 PM PDT 24
Finished Jul 06 05:28:37 PM PDT 24
Peak memory 206196 kb
Host smart-a1f64359-f132-43f6-874d-10097b65f7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11382
56286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1138256286
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1133225949
Short name T1926
Test name
Test status
Simulation time 230083448 ps
CPU time 0.87 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206204 kb
Host smart-a0ae268f-3259-49e5-a391-2a53456fa609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
25949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1133225949
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3378496861
Short name T2477
Test name
Test status
Simulation time 191618036 ps
CPU time 0.9 seconds
Started Jul 06 05:28:35 PM PDT 24
Finished Jul 06 05:28:36 PM PDT 24
Peak memory 206204 kb
Host smart-87b9170a-beb1-4a53-9135-662bccaa4b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33784
96861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3378496861
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.644493351
Short name T1519
Test name
Test status
Simulation time 23314826784 ps
CPU time 27.39 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 206268 kb
Host smart-7eea6440-4732-4cf6-a815-136dd99eebd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64449
3351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.644493351
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2042337987
Short name T726
Test name
Test status
Simulation time 3283465167 ps
CPU time 3.53 seconds
Started Jul 06 05:28:42 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206240 kb
Host smart-8646ee6a-be5d-47a8-bcb4-d85039942e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
37987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2042337987
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.46812909
Short name T2603
Test name
Test status
Simulation time 11475957248 ps
CPU time 109.13 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 206500 kb
Host smart-d4a9a1dc-f429-4a7a-ab83-ba7588a4e970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46812
909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.46812909
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2358301787
Short name T416
Test name
Test status
Simulation time 5128982836 ps
CPU time 34.89 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 206472 kb
Host smart-765cfb69-cc8b-4b04-91ea-ec6aaad1f048
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2358301787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2358301787
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3332969166
Short name T1051
Test name
Test status
Simulation time 236912911 ps
CPU time 1.02 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206200 kb
Host smart-2f8ed932-bf05-45c2-aa31-5e87008f9bb8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3332969166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3332969166
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3819814329
Short name T2291
Test name
Test status
Simulation time 194500895 ps
CPU time 0.9 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206168 kb
Host smart-d9468786-1ed6-459c-a8be-9b4d5516262b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38198
14329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3819814329
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3929169588
Short name T547
Test name
Test status
Simulation time 6333936115 ps
CPU time 176.5 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:31:38 PM PDT 24
Peak memory 206344 kb
Host smart-e7b57490-2159-4145-8450-64184866e6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
69588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3929169588
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3514299904
Short name T645
Test name
Test status
Simulation time 4921639187 ps
CPU time 35.06 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:29:21 PM PDT 24
Peak memory 206508 kb
Host smart-4a541718-a837-452b-acc9-56556333b575
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3514299904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3514299904
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1310595978
Short name T363
Test name
Test status
Simulation time 191635642 ps
CPU time 0.88 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206136 kb
Host smart-4ec38b57-5bbd-43bb-9b02-e92ed5058cb3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1310595978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1310595978
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1816524549
Short name T2140
Test name
Test status
Simulation time 142854750 ps
CPU time 0.77 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206184 kb
Host smart-e4556935-b16e-4209-83cb-d92cb2a93fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18165
24549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1816524549
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2254487133
Short name T1847
Test name
Test status
Simulation time 243015715 ps
CPU time 0.9 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206192 kb
Host smart-e3272f39-4aa8-4b78-a260-cffb7d24594a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22544
87133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2254487133
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2597496387
Short name T2464
Test name
Test status
Simulation time 150289901 ps
CPU time 0.81 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206164 kb
Host smart-af9ac6fc-3df3-482e-bed1-34e3de840f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
96387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2597496387
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1813694322
Short name T496
Test name
Test status
Simulation time 164299998 ps
CPU time 0.77 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:50 PM PDT 24
Peak memory 206040 kb
Host smart-b1b7427b-03d7-4bd5-8612-31bdeb4858eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18136
94322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1813694322
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3047405655
Short name T592
Test name
Test status
Simulation time 174676459 ps
CPU time 0.79 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:28:42 PM PDT 24
Peak memory 206184 kb
Host smart-cad6eb71-8582-4cf4-8d30-573299e7cad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30474
05655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3047405655
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2542234113
Short name T1340
Test name
Test status
Simulation time 146214090 ps
CPU time 0.75 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206180 kb
Host smart-57453f1b-b7a1-41c7-8af7-1b83468908a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25422
34113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2542234113
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2339954824
Short name T1523
Test name
Test status
Simulation time 292922916 ps
CPU time 1.06 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:28:41 PM PDT 24
Peak memory 206180 kb
Host smart-d0499805-eb85-4d05-a821-3143b339adbf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2339954824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2339954824
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1471359294
Short name T2330
Test name
Test status
Simulation time 154218181 ps
CPU time 0.8 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:28:42 PM PDT 24
Peak memory 206116 kb
Host smart-288f9ab4-3460-45f5-a941-5bffcdfe0002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
59294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1471359294
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.4145984754
Short name T2031
Test name
Test status
Simulation time 50769755 ps
CPU time 0.66 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206148 kb
Host smart-576104f0-f086-470a-b687-a99ff5674826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41459
84754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.4145984754
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.432802762
Short name T680
Test name
Test status
Simulation time 11412009468 ps
CPU time 23.15 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:29:12 PM PDT 24
Peak memory 206552 kb
Host smart-fc96b484-1ccf-404e-b80f-b5241baae1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43280
2762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.432802762
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1953283346
Short name T1744
Test name
Test status
Simulation time 169701842 ps
CPU time 0.84 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206216 kb
Host smart-eb4f7814-3a8b-4124-b25d-97d59d244ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19532
83346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1953283346
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1638993583
Short name T1045
Test name
Test status
Simulation time 216539694 ps
CPU time 0.88 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:28:42 PM PDT 24
Peak memory 206184 kb
Host smart-35871b67-0dc0-41e3-b8e4-083127d7f9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
93583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1638993583
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2932351655
Short name T2049
Test name
Test status
Simulation time 181076523 ps
CPU time 0.87 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206156 kb
Host smart-2049a0b5-e127-4eaf-91ef-3141fd4b3b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29323
51655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2932351655
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.832819512
Short name T979
Test name
Test status
Simulation time 178399850 ps
CPU time 0.89 seconds
Started Jul 06 05:28:42 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206096 kb
Host smart-419d0575-c46e-40ab-94be-1b086ec71695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83281
9512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.832819512
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4274488589
Short name T828
Test name
Test status
Simulation time 185776859 ps
CPU time 0.83 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206112 kb
Host smart-6b4039aa-961d-4ef8-8daa-fbb39f3d2e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42744
88589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4274488589
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.133097237
Short name T2668
Test name
Test status
Simulation time 154760370 ps
CPU time 0.82 seconds
Started Jul 06 05:29:02 PM PDT 24
Finished Jul 06 05:29:03 PM PDT 24
Peak memory 206180 kb
Host smart-95c4912b-8e5d-4ff1-9d85-608f25e873ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13309
7237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.133097237
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.472193136
Short name T2512
Test name
Test status
Simulation time 144487696 ps
CPU time 0.81 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206208 kb
Host smart-ae46fe9c-f8e8-4aed-badd-c72c39e57fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47219
3136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.472193136
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2750394706
Short name T2133
Test name
Test status
Simulation time 246129896 ps
CPU time 0.93 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:45 PM PDT 24
Peak memory 206164 kb
Host smart-251714cd-7b12-4234-ba7e-4d75aa5d21de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27503
94706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2750394706
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3062651634
Short name T1473
Test name
Test status
Simulation time 4645414579 ps
CPU time 125.08 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:31:00 PM PDT 24
Peak memory 206532 kb
Host smart-467b9711-7277-4a38-aeca-1abf30066bda
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3062651634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3062651634
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1553110860
Short name T1393
Test name
Test status
Simulation time 176788522 ps
CPU time 0.79 seconds
Started Jul 06 05:28:41 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206188 kb
Host smart-fec141d5-9194-48cd-a6cd-262ea7b7e047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
10860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1553110860
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2271993674
Short name T2143
Test name
Test status
Simulation time 194181973 ps
CPU time 0.8 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206436 kb
Host smart-ba73099d-df63-45b5-bacf-22ef3ced78a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22719
93674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2271993674
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.319749832
Short name T2352
Test name
Test status
Simulation time 1367376180 ps
CPU time 3.01 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206448 kb
Host smart-999fbc7b-124c-4258-80ad-40d181660762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
9832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.319749832
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.310590572
Short name T766
Test name
Test status
Simulation time 7836755418 ps
CPU time 72.63 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 206460 kb
Host smart-87a4b736-5454-4229-9198-3ee77a50963e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31059
0572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.310590572
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1670922099
Short name T950
Test name
Test status
Simulation time 78641647 ps
CPU time 0.74 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206268 kb
Host smart-097d41bc-fa95-4373-bcac-8512f323f2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1670922099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1670922099
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1883420742
Short name T1621
Test name
Test status
Simulation time 3460665634 ps
CPU time 4.47 seconds
Started Jul 06 05:28:42 PM PDT 24
Finished Jul 06 05:28:47 PM PDT 24
Peak memory 206500 kb
Host smart-8d6da1d8-7b58-4f68-a692-3f34428ab476
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1883420742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1883420742
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3982849750
Short name T1739
Test name
Test status
Simulation time 13339271846 ps
CPU time 15.32 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:29:10 PM PDT 24
Peak memory 206492 kb
Host smart-dc559746-091a-4a22-acf1-7784df9d2eed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3982849750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3982849750
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2104331562
Short name T1229
Test name
Test status
Simulation time 23370423248 ps
CPU time 23.74 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206276 kb
Host smart-3a8a58bb-37c5-4a5c-9837-2cd7263331e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2104331562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2104331562
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2967004747
Short name T1224
Test name
Test status
Simulation time 205107873 ps
CPU time 0.93 seconds
Started Jul 06 05:28:40 PM PDT 24
Finished Jul 06 05:28:41 PM PDT 24
Peak memory 206100 kb
Host smart-be90a381-47fc-4909-b63f-dda7ff77486f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
04747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2967004747
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.535691507
Short name T1170
Test name
Test status
Simulation time 172631436 ps
CPU time 0.81 seconds
Started Jul 06 05:28:43 PM PDT 24
Finished Jul 06 05:28:44 PM PDT 24
Peak memory 206200 kb
Host smart-24e784f7-56e1-405c-8aec-8b7962fb2460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53569
1507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.535691507
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1371000217
Short name T1093
Test name
Test status
Simulation time 170550678 ps
CPU time 0.76 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 205940 kb
Host smart-0f86dadc-0412-4369-bc96-3cc45c85ffca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13710
00217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1371000217
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.940976795
Short name T2518
Test name
Test status
Simulation time 608407254 ps
CPU time 1.61 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206384 kb
Host smart-4b261bec-cc5a-400b-9a7b-3b1b6be4c310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94097
6795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.940976795
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.865679756
Short name T1159
Test name
Test status
Simulation time 15752354247 ps
CPU time 37.04 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 206180 kb
Host smart-8e6e94c9-bb31-477d-8e44-b232b04ab52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86567
9756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.865679756
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1639947057
Short name T552
Test name
Test status
Simulation time 379335108 ps
CPU time 1.29 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:28:53 PM PDT 24
Peak memory 206204 kb
Host smart-563a7f1a-e776-47d1-aefb-0e12682a5e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16399
47057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1639947057
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1750375474
Short name T1359
Test name
Test status
Simulation time 136305880 ps
CPU time 0.74 seconds
Started Jul 06 05:28:42 PM PDT 24
Finished Jul 06 05:28:43 PM PDT 24
Peak memory 206176 kb
Host smart-5fc8ddbb-76df-40a0-8d42-58581c9af4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17503
75474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1750375474
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2101304498
Short name T331
Test name
Test status
Simulation time 87098224 ps
CPU time 0.73 seconds
Started Jul 06 05:28:45 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206164 kb
Host smart-fd7c1c3c-8c9d-4c65-9a57-a14f544bd8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
04498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2101304498
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3977059687
Short name T1707
Test name
Test status
Simulation time 1042811733 ps
CPU time 2.44 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206468 kb
Host smart-0ecefdf1-8a62-496d-83bb-093be2be7cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39770
59687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3977059687
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2663127612
Short name T462
Test name
Test status
Simulation time 178635208 ps
CPU time 1.95 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206444 kb
Host smart-c58e7e9a-a518-479d-b40e-4e0dad8daaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26631
27612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2663127612
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3263673803
Short name T1670
Test name
Test status
Simulation time 186011429 ps
CPU time 0.84 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206184 kb
Host smart-cbb4d6e7-ecac-46e8-bed6-ed06ce56fe74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636
73803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3263673803
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1542251418
Short name T1770
Test name
Test status
Simulation time 143231514 ps
CPU time 0.73 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206172 kb
Host smart-3fb6e81e-90a5-4d19-8463-dc36232eac56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15422
51418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1542251418
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3651396495
Short name T1062
Test name
Test status
Simulation time 246778350 ps
CPU time 0.9 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206192 kb
Host smart-16f0abba-4832-444d-abec-0195840f6cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36513
96495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3651396495
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3680911146
Short name T1812
Test name
Test status
Simulation time 197975585 ps
CPU time 0.85 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206212 kb
Host smart-a46da601-4050-4eeb-8f28-8280d74d7193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36809
11146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3680911146
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3031195536
Short name T2324
Test name
Test status
Simulation time 23294905024 ps
CPU time 22.98 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:29:20 PM PDT 24
Peak memory 206224 kb
Host smart-64718482-6ec7-451d-927e-58f4ea71e864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
95536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3031195536
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.192172644
Short name T997
Test name
Test status
Simulation time 3299587218 ps
CPU time 4.17 seconds
Started Jul 06 05:29:00 PM PDT 24
Finished Jul 06 05:29:05 PM PDT 24
Peak memory 206240 kb
Host smart-693e2721-ec84-45bf-801c-bc09a60018d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
2644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.192172644
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1607553536
Short name T2576
Test name
Test status
Simulation time 11833167993 ps
CPU time 115.92 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 206532 kb
Host smart-346b6839-ad35-4915-b306-440442cb3762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075
53536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1607553536
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2783792736
Short name T2094
Test name
Test status
Simulation time 5595947348 ps
CPU time 53.28 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:29:42 PM PDT 24
Peak memory 206452 kb
Host smart-af1e98c7-98f1-45b8-b365-d6a1a668f07a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2783792736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2783792736
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3679584784
Short name T798
Test name
Test status
Simulation time 245708091 ps
CPU time 0.91 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206196 kb
Host smart-4bc2c404-2ff3-45d9-9dcc-702d781fc0e1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3679584784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3679584784
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.255524462
Short name T677
Test name
Test status
Simulation time 190419387 ps
CPU time 0.87 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206184 kb
Host smart-e42f28c4-0948-4950-b1fe-6468eb72d728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.255524462
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.57353308
Short name T1572
Test name
Test status
Simulation time 4304748593 ps
CPU time 29.8 seconds
Started Jul 06 05:28:45 PM PDT 24
Finished Jul 06 05:29:15 PM PDT 24
Peak memory 206468 kb
Host smart-2195511e-a5f6-4ad1-ab68-626f1ea96805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57353
308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.57353308
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1472440536
Short name T697
Test name
Test status
Simulation time 7036132664 ps
CPU time 66.04 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:30:03 PM PDT 24
Peak memory 206408 kb
Host smart-e0bdf809-0c03-4a3c-a5ef-c6ebde46899d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1472440536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1472440536
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.508077461
Short name T1871
Test name
Test status
Simulation time 179201610 ps
CPU time 0.81 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206204 kb
Host smart-903ce163-4ca3-42d1-b40c-24fef3ec9a7d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=508077461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.508077461
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3252293604
Short name T1271
Test name
Test status
Simulation time 178547282 ps
CPU time 0.83 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206108 kb
Host smart-b48d6f99-b193-4fe7-bebb-bb33aa8b8411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32522
93604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3252293604
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.606002960
Short name T127
Test name
Test status
Simulation time 203517130 ps
CPU time 0.87 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206144 kb
Host smart-c971f660-e64f-4d47-9707-7495a437a79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60600
2960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.606002960
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2155629011
Short name T20
Test name
Test status
Simulation time 176471144 ps
CPU time 0.89 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206176 kb
Host smart-e7c6a39e-5a79-4242-bd1e-6fc12892f2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
29011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2155629011
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2641477254
Short name T789
Test name
Test status
Simulation time 182177437 ps
CPU time 0.81 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206200 kb
Host smart-8834245a-2c5f-48b1-95c0-9c927e149ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
77254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2641477254
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1516421814
Short name T2497
Test name
Test status
Simulation time 154940080 ps
CPU time 0.85 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206208 kb
Host smart-e42a5c18-88e1-4b1f-96ec-5b886b52766a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15164
21814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1516421814
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1749204589
Short name T734
Test name
Test status
Simulation time 186975747 ps
CPU time 0.81 seconds
Started Jul 06 05:29:01 PM PDT 24
Finished Jul 06 05:29:03 PM PDT 24
Peak memory 206184 kb
Host smart-3abd7066-8906-4d9c-a3a5-d1f478b69e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17492
04589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1749204589
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.39309977
Short name T2153
Test name
Test status
Simulation time 231734506 ps
CPU time 0.96 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 205968 kb
Host smart-af17df91-5526-42a8-9f30-940b74a93e67
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=39309977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.39309977
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.771783384
Short name T1927
Test name
Test status
Simulation time 145198553 ps
CPU time 0.79 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206172 kb
Host smart-ad24a605-b0a2-496e-9da8-4e734eb2bb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77178
3384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.771783384
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1262809193
Short name T931
Test name
Test status
Simulation time 89924574 ps
CPU time 0.71 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206204 kb
Host smart-014fa065-0313-4956-b8be-955b95a38d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12628
09193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1262809193
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2569590379
Short name T95
Test name
Test status
Simulation time 19179930925 ps
CPU time 44.3 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:29:40 PM PDT 24
Peak memory 206500 kb
Host smart-ea574e89-c01d-4d94-9af6-c3d062485fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
90379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2569590379
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.964697667
Short name T1347
Test name
Test status
Simulation time 204318050 ps
CPU time 0.85 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 205780 kb
Host smart-6b425608-91d8-4ab3-84f5-9ea39aace0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96469
7667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.964697667
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4005508777
Short name T1083
Test name
Test status
Simulation time 150835047 ps
CPU time 0.79 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206156 kb
Host smart-bdac349c-f4d6-4700-a49b-83902368f716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40055
08777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4005508777
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.706753655
Short name T1049
Test name
Test status
Simulation time 233453695 ps
CPU time 0.88 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206184 kb
Host smart-196164e1-82f2-4c04-9b9b-b4d11c2c3570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70675
3655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.706753655
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1425415306
Short name T857
Test name
Test status
Simulation time 188891477 ps
CPU time 0.88 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206184 kb
Host smart-b0be7be2-f921-41f9-a617-d51120f28d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
15306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1425415306
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3290121311
Short name T2620
Test name
Test status
Simulation time 153751244 ps
CPU time 0.77 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206124 kb
Host smart-b4f28d1c-4902-441f-bc75-201546d5bd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
21311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3290121311
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3946609149
Short name T2035
Test name
Test status
Simulation time 187569881 ps
CPU time 0.84 seconds
Started Jul 06 05:29:01 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206104 kb
Host smart-1115673c-10ea-4e5e-a865-54f77c8c44f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
09149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3946609149
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1572528856
Short name T1455
Test name
Test status
Simulation time 149630256 ps
CPU time 0.77 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:44 PM PDT 24
Peak memory 205944 kb
Host smart-7ffadc09-9a29-4275-a164-61e9b78c79f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15725
28856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1572528856
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4014151034
Short name T476
Test name
Test status
Simulation time 207875792 ps
CPU time 0.9 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206152 kb
Host smart-9a6f30f2-be1d-4704-a83d-6c9d739a0ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40141
51034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4014151034
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.285686916
Short name T581
Test name
Test status
Simulation time 4932122182 ps
CPU time 49.04 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 206532 kb
Host smart-f9573710-d2ea-4fe5-bf3f-5b13e2863334
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=285686916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.285686916
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.149733318
Short name T2023
Test name
Test status
Simulation time 163148262 ps
CPU time 0.86 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206152 kb
Host smart-8eda60d5-d482-45f7-9575-e45163b4b726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14973
3318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.149733318
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1528360856
Short name T1461
Test name
Test status
Simulation time 183233484 ps
CPU time 0.83 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206208 kb
Host smart-e73a66a7-b4bf-4dca-95d8-6ab2ba9c2e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15283
60856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1528360856
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2507761379
Short name T618
Test name
Test status
Simulation time 371888156 ps
CPU time 1.17 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206200 kb
Host smart-1e32acc9-f49d-4a3a-a150-a86780c82150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
61379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2507761379
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1087452796
Short name T1063
Test name
Test status
Simulation time 7033187200 ps
CPU time 199.3 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:32:09 PM PDT 24
Peak memory 206540 kb
Host smart-74e68404-1545-40e1-b9b5-ec7b23316d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
52796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1087452796
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.792205913
Short name T774
Test name
Test status
Simulation time 44676725 ps
CPU time 0.68 seconds
Started Jul 06 05:28:50 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206236 kb
Host smart-58abf43f-df37-4e7c-8f00-c40a6daaa3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=792205913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.792205913
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2888588856
Short name T1313
Test name
Test status
Simulation time 4128080102 ps
CPU time 5.25 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:05 PM PDT 24
Peak memory 206488 kb
Host smart-8f886240-a752-4062-a139-368f289c9ae8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2888588856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2888588856
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.992918649
Short name T533
Test name
Test status
Simulation time 13317467121 ps
CPU time 12.31 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206436 kb
Host smart-56e866a9-9889-4832-8083-e1f0528ade24
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=992918649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.992918649
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.813643995
Short name T653
Test name
Test status
Simulation time 23371260791 ps
CPU time 27.73 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206536 kb
Host smart-8de94b84-8659-4e52-8634-cc8bdcd79c04
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=813643995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.813643995
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2240093771
Short name T1048
Test name
Test status
Simulation time 154107997 ps
CPU time 0.85 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206188 kb
Host smart-3c348330-08e3-4229-a288-4ec506964dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22400
93771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2240093771
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.81804728
Short name T2692
Test name
Test status
Simulation time 149805679 ps
CPU time 0.77 seconds
Started Jul 06 05:28:47 PM PDT 24
Finished Jul 06 05:28:49 PM PDT 24
Peak memory 206184 kb
Host smart-cb98901a-abda-4572-a0fd-354b1779d89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81804
728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.81804728
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.83193452
Short name T2478
Test name
Test status
Simulation time 226235758 ps
CPU time 0.98 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:28:48 PM PDT 24
Peak memory 206100 kb
Host smart-98b05eda-5cf1-44f3-9daf-a989d8cbe3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83193
452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.83193452
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.4184028009
Short name T2451
Test name
Test status
Simulation time 733231891 ps
CPU time 1.89 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206428 kb
Host smart-c364306f-2ea5-456d-b86b-40e34b94ff1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41840
28009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.4184028009
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.4016013814
Short name T2455
Test name
Test status
Simulation time 21479616161 ps
CPU time 35.97 seconds
Started Jul 06 05:28:46 PM PDT 24
Finished Jul 06 05:29:23 PM PDT 24
Peak memory 206508 kb
Host smart-7cb30157-2452-4433-9d9d-a2ee6c15e858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40160
13814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.4016013814
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1177200083
Short name T1145
Test name
Test status
Simulation time 433635121 ps
CPU time 1.32 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:28:51 PM PDT 24
Peak memory 206164 kb
Host smart-49796e94-ad2d-4c72-8494-7e5c135b6dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11772
00083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1177200083
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2010725821
Short name T1674
Test name
Test status
Simulation time 159517483 ps
CPU time 0.77 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206208 kb
Host smart-a934d81a-19a0-497a-a33d-f229df149630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
25821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2010725821
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2726265582
Short name T2559
Test name
Test status
Simulation time 46006036 ps
CPU time 0.68 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:28:52 PM PDT 24
Peak memory 206176 kb
Host smart-370ce7b6-c423-4e92-baad-c92f4ab78c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27262
65582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2726265582
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1166512547
Short name T1223
Test name
Test status
Simulation time 1152328796 ps
CPU time 2.5 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206452 kb
Host smart-f47d22da-107f-46e5-8d6d-c4f7607b439c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
12547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1166512547
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1500519690
Short name T2266
Test name
Test status
Simulation time 207042822 ps
CPU time 2.25 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 206408 kb
Host smart-42ccb249-2edd-4bc6-892d-c36ccab10b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15005
19690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1500519690
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3108056410
Short name T1231
Test name
Test status
Simulation time 271245724 ps
CPU time 1 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206068 kb
Host smart-403fa499-ddf2-48be-ac55-77a899db3582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
56410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3108056410
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1224049904
Short name T1699
Test name
Test status
Simulation time 142282819 ps
CPU time 0.75 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 205936 kb
Host smart-f79525f8-ec9c-478a-bb39-bfaacc5929eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240
49904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1224049904
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2015460829
Short name T1193
Test name
Test status
Simulation time 160277958 ps
CPU time 0.78 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:32 PM PDT 24
Peak memory 205940 kb
Host smart-81a4c9f3-952f-4caa-a2a3-eb149490f24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20154
60829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2015460829
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3679520150
Short name T365
Test name
Test status
Simulation time 236179041 ps
CPU time 0.97 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206204 kb
Host smart-2799b1fb-0e8c-4599-8015-b16e33488134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795
20150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3679520150
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1977742913
Short name T1970
Test name
Test status
Simulation time 23310555104 ps
CPU time 22.66 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:29:15 PM PDT 24
Peak memory 206500 kb
Host smart-50d23359-44a2-4418-8136-883c1b9ec9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19777
42913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1977742913
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3275780409
Short name T862
Test name
Test status
Simulation time 3341007647 ps
CPU time 3.92 seconds
Started Jul 06 05:28:49 PM PDT 24
Finished Jul 06 05:28:54 PM PDT 24
Peak memory 206240 kb
Host smart-c588b9d2-6431-4652-a21e-1acd1374fbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32757
80409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3275780409
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3846398363
Short name T1450
Test name
Test status
Simulation time 10146203267 ps
CPU time 90.35 seconds
Started Jul 06 05:28:48 PM PDT 24
Finished Jul 06 05:30:19 PM PDT 24
Peak memory 206512 kb
Host smart-8c212aaa-47de-40db-a357-b43bc4748784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38463
98363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3846398363
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.593370272
Short name T608
Test name
Test status
Simulation time 5641665004 ps
CPU time 40.42 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 206452 kb
Host smart-d1668235-96ef-4e0e-ac19-88fb3709f612
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=593370272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.593370272
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.2621237240
Short name T1282
Test name
Test status
Simulation time 267800496 ps
CPU time 0.94 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206200 kb
Host smart-9bb12298-77f3-4484-88b2-8d3501900d8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2621237240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.2621237240
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2324050309
Short name T2474
Test name
Test status
Simulation time 204939888 ps
CPU time 0.85 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206184 kb
Host smart-a65d47c9-2ef8-4890-ba17-c9b37e5acd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
50309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2324050309
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.1181807638
Short name T795
Test name
Test status
Simulation time 6430925055 ps
CPU time 61.23 seconds
Started Jul 06 05:28:50 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 206440 kb
Host smart-a7cacba6-5fc4-4e8b-aebf-46c3ed540692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11818
07638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.1181807638
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2754910596
Short name T1202
Test name
Test status
Simulation time 5616452540 ps
CPU time 146.6 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:31:21 PM PDT 24
Peak memory 206452 kb
Host smart-7b74fb3f-5ebe-4553-b359-3077b2a81f92
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2754910596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2754910596
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.299249343
Short name T660
Test name
Test status
Simulation time 161344222 ps
CPU time 0.82 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206172 kb
Host smart-e26c26ff-9e6a-44e0-8d1b-a7a80b0f4dad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=299249343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.299249343
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.478105798
Short name T567
Test name
Test status
Simulation time 158037146 ps
CPU time 0.89 seconds
Started Jul 06 05:28:44 PM PDT 24
Finished Jul 06 05:28:46 PM PDT 24
Peak memory 206184 kb
Host smart-b172ab42-4d58-47fc-bfd6-b7c7d08e3d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47810
5798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.478105798
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1070380229
Short name T116
Test name
Test status
Simulation time 203074932 ps
CPU time 0.87 seconds
Started Jul 06 05:29:02 PM PDT 24
Finished Jul 06 05:29:03 PM PDT 24
Peak memory 206156 kb
Host smart-adb97fc0-c749-4e26-8f72-e70f57cc6d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10703
80229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1070380229
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3412059840
Short name T1403
Test name
Test status
Simulation time 169722717 ps
CPU time 0.81 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206176 kb
Host smart-082c1358-e2fd-41f8-bb03-b2d53fe12e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120
59840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3412059840
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2385911814
Short name T980
Test name
Test status
Simulation time 153821556 ps
CPU time 0.8 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206200 kb
Host smart-1cef659e-591f-42c5-ac1a-b80f61fa195d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23859
11814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2385911814
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.312946067
Short name T1954
Test name
Test status
Simulation time 160733252 ps
CPU time 0.84 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206172 kb
Host smart-19b832f1-ef17-4140-80dc-a571d8fe3de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31294
6067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.312946067
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3298261953
Short name T1968
Test name
Test status
Simulation time 160658621 ps
CPU time 0.81 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:54 PM PDT 24
Peak memory 206156 kb
Host smart-24d8e664-c521-4aba-bc4a-8a07f25bb1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
61953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3298261953
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.4030078661
Short name T1727
Test name
Test status
Simulation time 232455080 ps
CPU time 0.99 seconds
Started Jul 06 05:28:51 PM PDT 24
Finished Jul 06 05:28:52 PM PDT 24
Peak memory 206208 kb
Host smart-11dbac52-c051-4348-88cf-2e22c44f6716
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4030078661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.4030078661
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.15941783
Short name T2554
Test name
Test status
Simulation time 139087738 ps
CPU time 0.77 seconds
Started Jul 06 05:29:10 PM PDT 24
Finished Jul 06 05:29:11 PM PDT 24
Peak memory 206160 kb
Host smart-f4a6f361-485b-475e-a85d-ea2b50408863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.15941783
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2212467348
Short name T472
Test name
Test status
Simulation time 33138363 ps
CPU time 0.66 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206196 kb
Host smart-ec83bd98-7110-42bb-8bee-42d0810a10d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22124
67348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2212467348
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1694474072
Short name T263
Test name
Test status
Simulation time 8890712330 ps
CPU time 19.82 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206452 kb
Host smart-7ea76cbb-fa2b-426f-a951-dcb67c4f0856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16944
74072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1694474072
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.109332339
Short name T2687
Test name
Test status
Simulation time 166203123 ps
CPU time 0.87 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:55 PM PDT 24
Peak memory 206184 kb
Host smart-63051dcf-a92b-4d07-8d5f-0c3e44621d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10933
2339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.109332339
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3607844709
Short name T451
Test name
Test status
Simulation time 237247545 ps
CPU time 0.88 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:14 PM PDT 24
Peak memory 206120 kb
Host smart-f34d22bd-d385-44cb-b6f6-ebd4b45b8268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36078
44709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3607844709
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.638705040
Short name T1838
Test name
Test status
Simulation time 238469593 ps
CPU time 0.96 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206040 kb
Host smart-92d67e44-40e6-4122-853b-8426b2dbb060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63870
5040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.638705040
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1427258032
Short name T911
Test name
Test status
Simulation time 162771382 ps
CPU time 0.76 seconds
Started Jul 06 05:29:08 PM PDT 24
Finished Jul 06 05:29:08 PM PDT 24
Peak memory 206160 kb
Host smart-f1a2cf38-795a-4b5c-90c2-f28fa7185dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
58032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1427258032
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1395525507
Short name T2248
Test name
Test status
Simulation time 187102508 ps
CPU time 0.8 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206180 kb
Host smart-9fb76b41-9a29-4d26-b822-fe1916ac2893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13955
25507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1395525507
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1051249746
Short name T523
Test name
Test status
Simulation time 204748991 ps
CPU time 0.84 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206176 kb
Host smart-be0590f7-79bd-4aa6-9d0b-1338c59cbb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10512
49746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1051249746
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.4038947773
Short name T1622
Test name
Test status
Simulation time 158135996 ps
CPU time 0.77 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206176 kb
Host smart-10476dee-ebf8-483c-b616-9d66fd1c8ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
47773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.4038947773
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1347619292
Short name T907
Test name
Test status
Simulation time 186547834 ps
CPU time 0.87 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:59 PM PDT 24
Peak memory 206176 kb
Host smart-87edfb99-d916-4c98-95ce-60d034add9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13476
19292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1347619292
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.4003847798
Short name T1869
Test name
Test status
Simulation time 6165800520 ps
CPU time 164.28 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:31:42 PM PDT 24
Peak memory 206532 kb
Host smart-8cf1ab68-52c6-4c60-b7a4-ee2c28ede92a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4003847798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.4003847798
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3882006363
Short name T1976
Test name
Test status
Simulation time 186782941 ps
CPU time 0.8 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:28:57 PM PDT 24
Peak memory 206204 kb
Host smart-aedf4b83-050d-49ec-b44d-0ecf36111f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
06363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3882006363
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2997995751
Short name T1508
Test name
Test status
Simulation time 212043688 ps
CPU time 0.81 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:54 PM PDT 24
Peak memory 206196 kb
Host smart-481033c8-05b5-453c-abaa-a9103a4006e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29979
95751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2997995751
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3141944782
Short name T2444
Test name
Test status
Simulation time 1271354666 ps
CPU time 2.46 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206380 kb
Host smart-3ba3d90a-7a2e-4c40-a8ee-b51a397368d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31419
44782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3141944782
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3882302013
Short name T681
Test name
Test status
Simulation time 4297360143 ps
CPU time 112.38 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:30:50 PM PDT 24
Peak memory 206324 kb
Host smart-e33809ba-a741-4e40-81bf-fcc7f7896a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
02013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3882302013
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2254993838
Short name T1482
Test name
Test status
Simulation time 45300289 ps
CPU time 0.68 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 206228 kb
Host smart-58de6635-6e56-4937-8c56-1afd2a3cab26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2254993838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2254993838
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.99880327
Short name T2156
Test name
Test status
Simulation time 3598042800 ps
CPU time 4.92 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206264 kb
Host smart-8b28628f-f7c9-4259-aa6b-252d4a4c8cf4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=99880327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.99880327
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3553009548
Short name T11
Test name
Test status
Simulation time 13339565080 ps
CPU time 12.19 seconds
Started Jul 06 05:28:54 PM PDT 24
Finished Jul 06 05:29:08 PM PDT 24
Peak memory 206264 kb
Host smart-00c8048b-db10-4c44-9db9-83e3031d5949
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3553009548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3553009548
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3510231347
Short name T2569
Test name
Test status
Simulation time 23361502282 ps
CPU time 23.79 seconds
Started Jul 06 05:28:52 PM PDT 24
Finished Jul 06 05:29:17 PM PDT 24
Peak memory 206268 kb
Host smart-d64e1c85-aace-45ab-b9c6-ec0b54dbe694
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3510231347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3510231347
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2968426431
Short name T909
Test name
Test status
Simulation time 146820421 ps
CPU time 0.79 seconds
Started Jul 06 05:28:55 PM PDT 24
Finished Jul 06 05:28:58 PM PDT 24
Peak memory 206176 kb
Host smart-568e469d-ac73-4720-bd82-65bc4e84ed8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29684
26431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2968426431
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3655318397
Short name T1335
Test name
Test status
Simulation time 166493749 ps
CPU time 0.77 seconds
Started Jul 06 05:28:53 PM PDT 24
Finished Jul 06 05:28:56 PM PDT 24
Peak memory 206148 kb
Host smart-d09c5058-c417-4a7a-9639-f9a39de50a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36553
18397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3655318397
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1884918219
Short name T756
Test name
Test status
Simulation time 362927464 ps
CPU time 1.25 seconds
Started Jul 06 05:28:59 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 206168 kb
Host smart-3e3e61c7-0281-488a-975e-7c26dd1948e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18849
18219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1884918219
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1869006959
Short name T1148
Test name
Test status
Simulation time 432574860 ps
CPU time 1.42 seconds
Started Jul 06 05:29:00 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206100 kb
Host smart-e0401f6b-2126-45ce-893d-c08e48524ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18690
06959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1869006959
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3142599008
Short name T2674
Test name
Test status
Simulation time 19978772536 ps
CPU time 38.32 seconds
Started Jul 06 05:28:56 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 206460 kb
Host smart-1f4b3694-fe68-4251-b41b-6fbee9d91a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31425
99008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3142599008
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3103276806
Short name T804
Test name
Test status
Simulation time 326573351 ps
CPU time 1.14 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 206180 kb
Host smart-0f093753-b6ad-49f9-910e-562e502d5a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31032
76806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3103276806
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.535019829
Short name T2504
Test name
Test status
Simulation time 155703810 ps
CPU time 0.8 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 206200 kb
Host smart-485a39d4-1512-4e00-969b-a9c124fe6fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53501
9829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.535019829
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1817275882
Short name T695
Test name
Test status
Simulation time 55392706 ps
CPU time 0.7 seconds
Started Jul 06 05:29:21 PM PDT 24
Finished Jul 06 05:29:22 PM PDT 24
Peak memory 206136 kb
Host smart-0b262117-2e31-47ec-8c33-52ad86823005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18172
75882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1817275882
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1669211723
Short name T1137
Test name
Test status
Simulation time 903137025 ps
CPU time 2.04 seconds
Started Jul 06 05:29:08 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 206452 kb
Host smart-27245059-1119-4450-b418-40f95705483f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16692
11723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1669211723
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3484855751
Short name T1853
Test name
Test status
Simulation time 176405928 ps
CPU time 1.91 seconds
Started Jul 06 05:28:59 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206376 kb
Host smart-fe89849f-0461-427b-aa6a-36e989f92ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848
55751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3484855751
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2628685438
Short name T649
Test name
Test status
Simulation time 219484865 ps
CPU time 0.94 seconds
Started Jul 06 05:29:00 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206184 kb
Host smart-d1aff6b9-e3ab-415c-9a6f-b7aac0432773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26286
85438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2628685438
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4284326987
Short name T489
Test name
Test status
Simulation time 151584031 ps
CPU time 0.8 seconds
Started Jul 06 05:29:00 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206180 kb
Host smart-c8aca8a6-5d07-4d5a-a0da-fc461aa8df7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42843
26987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4284326987
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4000241234
Short name T1052
Test name
Test status
Simulation time 161293320 ps
CPU time 0.81 seconds
Started Jul 06 05:29:20 PM PDT 24
Finished Jul 06 05:29:21 PM PDT 24
Peak memory 206200 kb
Host smart-49a44d4d-1cd2-42ae-9b50-20dcbd6143a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
41234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4000241234
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.3810099797
Short name T998
Test name
Test status
Simulation time 6889546288 ps
CPU time 191.68 seconds
Started Jul 06 05:28:59 PM PDT 24
Finished Jul 06 05:32:12 PM PDT 24
Peak memory 206484 kb
Host smart-9df65408-5db0-4ab9-825b-0756bef45aa9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3810099797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.3810099797
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.526253692
Short name T1564
Test name
Test status
Simulation time 175435937 ps
CPU time 0.86 seconds
Started Jul 06 05:29:18 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206204 kb
Host smart-9500e06f-9ae9-4ff4-b68e-3a481618f885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52625
3692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.526253692
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.4045978722
Short name T2563
Test name
Test status
Simulation time 23295385278 ps
CPU time 25 seconds
Started Jul 06 05:28:59 PM PDT 24
Finished Jul 06 05:29:25 PM PDT 24
Peak memory 206236 kb
Host smart-6fe4d29a-6fed-42fa-8b65-94bbf39c5e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40459
78722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.4045978722
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1578976621
Short name T540
Test name
Test status
Simulation time 3309681434 ps
CPU time 3.5 seconds
Started Jul 06 05:29:03 PM PDT 24
Finished Jul 06 05:29:07 PM PDT 24
Peak memory 206268 kb
Host smart-f9986543-2287-4825-960c-fc012eb0742f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15789
76621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1578976621
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1173172692
Short name T2003
Test name
Test status
Simulation time 6145787375 ps
CPU time 43.04 seconds
Started Jul 06 05:29:12 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 206496 kb
Host smart-4df4267e-68e3-45af-9323-92fc28c1cc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
72692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1173172692
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1963708152
Short name T1334
Test name
Test status
Simulation time 3390006838 ps
CPU time 32.19 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 206504 kb
Host smart-e5746827-51e2-4863-9d0c-fbbbe216bc24
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1963708152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1963708152
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2254740441
Short name T1111
Test name
Test status
Simulation time 247027606 ps
CPU time 0.98 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206124 kb
Host smart-a323cd16-c5da-463d-a7e7-26d58235a296
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2254740441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2254740441
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2257094467
Short name T2225
Test name
Test status
Simulation time 190203361 ps
CPU time 0.89 seconds
Started Jul 06 05:28:59 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 206172 kb
Host smart-bafec83b-181a-4616-95fa-bda65728fcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
94467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2257094467
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2225043265
Short name T1946
Test name
Test status
Simulation time 4881351866 ps
CPU time 35.23 seconds
Started Jul 06 05:29:21 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 206380 kb
Host smart-39dabfe6-eb66-460e-9a92-2dca7957bc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22250
43265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2225043265
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2842760607
Short name T1948
Test name
Test status
Simulation time 7147662208 ps
CPU time 205.23 seconds
Started Jul 06 05:29:00 PM PDT 24
Finished Jul 06 05:32:26 PM PDT 24
Peak memory 206384 kb
Host smart-7ed21b0b-d340-42f5-b855-d8134916430c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2842760607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2842760607
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2084092783
Short name T1603
Test name
Test status
Simulation time 153968117 ps
CPU time 0.79 seconds
Started Jul 06 05:29:08 PM PDT 24
Finished Jul 06 05:29:09 PM PDT 24
Peak memory 206184 kb
Host smart-45036655-2ea2-48e5-b15c-126baf41fa31
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2084092783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2084092783
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2096699718
Short name T2628
Test name
Test status
Simulation time 170706761 ps
CPU time 0.87 seconds
Started Jul 06 05:29:00 PM PDT 24
Finished Jul 06 05:29:02 PM PDT 24
Peak memory 206172 kb
Host smart-63f98adc-265a-463a-a32a-cbc88c2f487a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20966
99718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2096699718
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2612527721
Short name T117
Test name
Test status
Simulation time 191654632 ps
CPU time 0.81 seconds
Started Jul 06 05:29:21 PM PDT 24
Finished Jul 06 05:29:22 PM PDT 24
Peak memory 206156 kb
Host smart-ea110011-88f9-4273-994c-c5af5acdd9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26125
27721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2612527721
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.856221933
Short name T1124
Test name
Test status
Simulation time 152305177 ps
CPU time 0.78 seconds
Started Jul 06 05:29:17 PM PDT 24
Finished Jul 06 05:29:18 PM PDT 24
Peak memory 206184 kb
Host smart-0d52a267-a689-4444-a982-8c026e25ca25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85622
1933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.856221933
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3085886695
Short name T1233
Test name
Test status
Simulation time 148325666 ps
CPU time 0.79 seconds
Started Jul 06 05:28:58 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206200 kb
Host smart-539da9c8-3468-4ccf-9ab9-63b49a931c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30858
86695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3085886695
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2200508609
Short name T2461
Test name
Test status
Simulation time 163273540 ps
CPU time 0.85 seconds
Started Jul 06 05:28:57 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 206148 kb
Host smart-5bd827f6-f1a9-40f7-b591-9456b440c303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22005
08609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2200508609
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4013257815
Short name T961
Test name
Test status
Simulation time 175882477 ps
CPU time 0.82 seconds
Started Jul 06 05:29:03 PM PDT 24
Finished Jul 06 05:29:04 PM PDT 24
Peak memory 206164 kb
Host smart-5fd456c2-b9ad-4614-a141-41e869221073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40132
57815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4013257815
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1128399446
Short name T1820
Test name
Test status
Simulation time 241497428 ps
CPU time 0.99 seconds
Started Jul 06 05:29:05 PM PDT 24
Finished Jul 06 05:29:11 PM PDT 24
Peak memory 206212 kb
Host smart-57c7e94c-fb32-4f3a-8270-8f1a0fd69452
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1128399446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1128399446
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1777389465
Short name T535
Test name
Test status
Simulation time 145586888 ps
CPU time 0.8 seconds
Started Jul 06 05:29:09 PM PDT 24
Finished Jul 06 05:29:10 PM PDT 24
Peak memory 206056 kb
Host smart-478a68bb-e126-413c-9398-533e97e084c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17773
89465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1777389465
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2855009832
Short name T2438
Test name
Test status
Simulation time 97355407 ps
CPU time 0.71 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 206192 kb
Host smart-e16bbe15-176e-4091-b2e0-bb6bcb33cd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
09832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2855009832
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1078554774
Short name T2149
Test name
Test status
Simulation time 16309732228 ps
CPU time 34.32 seconds
Started Jul 06 05:29:03 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 206552 kb
Host smart-f7163c89-6333-4b25-964e-b2adb3522e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10785
54774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1078554774
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3991504391
Short name T1934
Test name
Test status
Simulation time 164621302 ps
CPU time 0.81 seconds
Started Jul 06 05:29:05 PM PDT 24
Finished Jul 06 05:29:06 PM PDT 24
Peak memory 206176 kb
Host smart-6c5120a4-89a6-4c21-b703-96962ae061c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
04391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3991504391
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2611621360
Short name T781
Test name
Test status
Simulation time 237764817 ps
CPU time 0.88 seconds
Started Jul 06 05:29:21 PM PDT 24
Finished Jul 06 05:29:22 PM PDT 24
Peak memory 206172 kb
Host smart-b6e39103-5864-409d-8371-a9f03e767d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
21360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2611621360
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1548825835
Short name T2596
Test name
Test status
Simulation time 164747160 ps
CPU time 0.78 seconds
Started Jul 06 05:29:04 PM PDT 24
Finished Jul 06 05:29:05 PM PDT 24
Peak memory 206204 kb
Host smart-23310369-9329-487d-a88d-df165d122c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15488
25835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1548825835
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2941430361
Short name T1855
Test name
Test status
Simulation time 182458755 ps
CPU time 0.83 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:29:20 PM PDT 24
Peak memory 206132 kb
Host smart-0283fce3-5105-49b0-b57e-02eca6f95635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29414
30361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2941430361
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3359075462
Short name T2411
Test name
Test status
Simulation time 181173969 ps
CPU time 0.84 seconds
Started Jul 06 05:29:05 PM PDT 24
Finished Jul 06 05:29:06 PM PDT 24
Peak memory 206104 kb
Host smart-3ff18f0d-c15d-4608-b065-fdca22d4e85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590
75462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3359075462
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.4098860925
Short name T2321
Test name
Test status
Simulation time 153904538 ps
CPU time 0.81 seconds
Started Jul 06 05:29:18 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206140 kb
Host smart-3b07e500-c798-42a7-9b30-2275e0e2e1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40988
60925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.4098860925
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.519666925
Short name T2216
Test name
Test status
Simulation time 172782273 ps
CPU time 0.86 seconds
Started Jul 06 05:29:05 PM PDT 24
Finished Jul 06 05:29:07 PM PDT 24
Peak memory 206180 kb
Host smart-4503455c-d7ff-4b32-90d1-32974c2f7570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51966
6925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.519666925
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.528985564
Short name T811
Test name
Test status
Simulation time 229569523 ps
CPU time 0.91 seconds
Started Jul 06 05:29:03 PM PDT 24
Finished Jul 06 05:29:04 PM PDT 24
Peak memory 206200 kb
Host smart-261437db-2144-4553-ac3d-5d65f282d8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52898
5564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.528985564
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1778969908
Short name T1325
Test name
Test status
Simulation time 6557526460 ps
CPU time 61.11 seconds
Started Jul 06 05:29:09 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 206384 kb
Host smart-1a5df2d5-c551-42a9-97e2-9b845c0738f1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1778969908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1778969908
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2132790764
Short name T147
Test name
Test status
Simulation time 206444876 ps
CPU time 0.86 seconds
Started Jul 06 05:29:18 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206200 kb
Host smart-e3e94a10-759c-4ad0-b145-fb6d43f3fec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
90764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2132790764
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.4024093901
Short name T1956
Test name
Test status
Simulation time 198619659 ps
CPU time 0.89 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:25 PM PDT 24
Peak memory 206184 kb
Host smart-9ccde397-3936-4b5a-8bbe-4ed20bf8ece2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40240
93901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4024093901
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.250899791
Short name T2272
Test name
Test status
Simulation time 1201983751 ps
CPU time 2.56 seconds
Started Jul 06 05:29:04 PM PDT 24
Finished Jul 06 05:29:07 PM PDT 24
Peak memory 206380 kb
Host smart-899f1c2e-dd67-45ab-a55b-d2b0ffb4ddaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25089
9791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.250899791
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1641150449
Short name T637
Test name
Test status
Simulation time 4409628060 ps
CPU time 125.66 seconds
Started Jul 06 05:29:02 PM PDT 24
Finished Jul 06 05:31:08 PM PDT 24
Peak memory 206508 kb
Host smart-18893bf9-85d4-4f4d-9bfa-8d11f33cbac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411
50449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1641150449
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1231053062
Short name T2005
Test name
Test status
Simulation time 43212589 ps
CPU time 0.67 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:25 PM PDT 24
Peak memory 206172 kb
Host smart-66b26c68-efc9-4173-b75d-d0ee35564879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1231053062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1231053062
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.4137572761
Short name T49
Test name
Test status
Simulation time 4330985880 ps
CPU time 5.75 seconds
Started Jul 06 05:29:09 PM PDT 24
Finished Jul 06 05:29:15 PM PDT 24
Peak memory 206380 kb
Host smart-63d2de8c-f728-49f3-a458-a641986bf6e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4137572761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.4137572761
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3886018318
Short name T241
Test name
Test status
Simulation time 13473359158 ps
CPU time 12.23 seconds
Started Jul 06 05:29:03 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 206512 kb
Host smart-5e319d4e-9ced-4526-be0e-c450b8c711fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3886018318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3886018318
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3573434067
Short name T993
Test name
Test status
Simulation time 23337700172 ps
CPU time 23.37 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 206240 kb
Host smart-ad1eee62-e832-455c-b9d6-ce02f6c1cc59
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3573434067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3573434067
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3384240871
Short name T1721
Test name
Test status
Simulation time 160403806 ps
CPU time 0.89 seconds
Started Jul 06 05:29:02 PM PDT 24
Finished Jul 06 05:29:03 PM PDT 24
Peak memory 206124 kb
Host smart-4e282155-5b7b-42f2-b8ec-4760cb6a560b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33842
40871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3384240871
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2649088656
Short name T65
Test name
Test status
Simulation time 223192442 ps
CPU time 0.93 seconds
Started Jul 06 05:29:02 PM PDT 24
Finished Jul 06 05:29:04 PM PDT 24
Peak memory 206172 kb
Host smart-63d2ad83-fd7e-47b7-b69b-20878ba50c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
88656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2649088656
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.967717674
Short name T2633
Test name
Test status
Simulation time 230142386 ps
CPU time 0.99 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:30 PM PDT 24
Peak memory 206160 kb
Host smart-1b6c098b-02bd-4643-b900-2433fb24c0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96771
7674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.967717674
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3242291339
Short name T891
Test name
Test status
Simulation time 695620995 ps
CPU time 1.8 seconds
Started Jul 06 05:29:04 PM PDT 24
Finished Jul 06 05:29:06 PM PDT 24
Peak memory 206428 kb
Host smart-5e2ef541-5425-44ce-a708-b28dcbf19f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
91339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3242291339
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.724822698
Short name T97
Test name
Test status
Simulation time 15808725215 ps
CPU time 30.37 seconds
Started Jul 06 05:29:07 PM PDT 24
Finished Jul 06 05:29:37 PM PDT 24
Peak memory 206512 kb
Host smart-0646977d-fe19-49bb-9194-42c4e64318ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72482
2698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.724822698
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.879685737
Short name T812
Test name
Test status
Simulation time 355382577 ps
CPU time 1.17 seconds
Started Jul 06 05:29:12 PM PDT 24
Finished Jul 06 05:29:18 PM PDT 24
Peak memory 206184 kb
Host smart-b712df0b-af3d-4ab9-bfa7-1b0cd5da052b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87968
5737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.879685737
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2602340459
Short name T1144
Test name
Test status
Simulation time 144926670 ps
CPU time 0.79 seconds
Started Jul 06 05:29:04 PM PDT 24
Finished Jul 06 05:29:05 PM PDT 24
Peak memory 206180 kb
Host smart-f96d0bc2-e00d-4f51-993f-f436cbd4b284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26023
40459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2602340459
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.437633154
Short name T503
Test name
Test status
Simulation time 69061313 ps
CPU time 0.72 seconds
Started Jul 06 05:29:09 PM PDT 24
Finished Jul 06 05:29:10 PM PDT 24
Peak memory 206160 kb
Host smart-8c3b826a-07ca-4901-b49c-80955fe62615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43763
3154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.437633154
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2318440263
Short name T939
Test name
Test status
Simulation time 876214210 ps
CPU time 2.1 seconds
Started Jul 06 05:29:17 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206280 kb
Host smart-31f5952d-3c02-448e-a684-ce1829d88ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23184
40263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2318440263
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1085142161
Short name T2107
Test name
Test status
Simulation time 276851506 ps
CPU time 1.61 seconds
Started Jul 06 05:29:26 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 206444 kb
Host smart-c57378fc-4501-4dc5-b6d6-01328c91164b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10851
42161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1085142161
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3168484434
Short name T1157
Test name
Test status
Simulation time 237023221 ps
CPU time 0.94 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:29:13 PM PDT 24
Peak memory 206184 kb
Host smart-7194a949-6563-4853-a3dc-8d04b3516ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
84434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3168484434
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2941267371
Short name T627
Test name
Test status
Simulation time 144550469 ps
CPU time 0.87 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:29:13 PM PDT 24
Peak memory 206180 kb
Host smart-37c93fc5-6966-4a8b-9cf8-c5ef6f2e74eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29412
67371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2941267371
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1916517966
Short name T593
Test name
Test status
Simulation time 259842534 ps
CPU time 0.96 seconds
Started Jul 06 05:29:22 PM PDT 24
Finished Jul 06 05:29:23 PM PDT 24
Peak memory 206156 kb
Host smart-e9e1a096-a069-42f3-a2ce-445f4e2665d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
17966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1916517966
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2283077245
Short name T917
Test name
Test status
Simulation time 195327198 ps
CPU time 0.85 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:29:12 PM PDT 24
Peak memory 206172 kb
Host smart-0b9fa6d7-c431-46d2-8508-d50581611237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
77245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2283077245
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1235481688
Short name T1688
Test name
Test status
Simulation time 23323207736 ps
CPU time 24.71 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 206224 kb
Host smart-a2080f01-4d62-4900-b75a-dc7434590ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354
81688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1235481688
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.660899523
Short name T663
Test name
Test status
Simulation time 3332102170 ps
CPU time 3.84 seconds
Started Jul 06 05:29:27 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 206264 kb
Host smart-b9605946-d0dc-4ff3-b1f7-438a629479b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66089
9523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.660899523
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3201542807
Short name T2655
Test name
Test status
Simulation time 8588913766 ps
CPU time 235.71 seconds
Started Jul 06 05:29:08 PM PDT 24
Finished Jul 06 05:33:04 PM PDT 24
Peak memory 206524 kb
Host smart-323ce3ab-1c7f-407b-998a-e00a1899e187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
42807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3201542807
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3147775609
Short name T965
Test name
Test status
Simulation time 6055357102 ps
CPU time 165.52 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:32:20 PM PDT 24
Peak memory 206456 kb
Host smart-f68bb950-3b91-43f7-8c9f-1444752ad156
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3147775609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3147775609
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.39401899
Short name T1761
Test name
Test status
Simulation time 272101488 ps
CPU time 0.94 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:29:17 PM PDT 24
Peak memory 206088 kb
Host smart-46d6abb2-5f62-4d11-8f5c-bed22791a4de
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=39401899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.39401899
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2614764681
Short name T459
Test name
Test status
Simulation time 186958011 ps
CPU time 0.84 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 206152 kb
Host smart-4d44bb78-e3f1-4226-8ac6-ef1564b42de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26147
64681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2614764681
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1441118645
Short name T823
Test name
Test status
Simulation time 3422215168 ps
CPU time 97.2 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:30:49 PM PDT 24
Peak memory 206492 kb
Host smart-2e5568ab-2057-4274-99ab-9fe9eaff5191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
18645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1441118645
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3247059610
Short name T1760
Test name
Test status
Simulation time 7389476476 ps
CPU time 52.18 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:30:08 PM PDT 24
Peak memory 206336 kb
Host smart-65f0031d-d654-4652-baca-61ae1e328f90
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3247059610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3247059610
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1948604998
Short name T1665
Test name
Test status
Simulation time 150772835 ps
CPU time 0.78 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 206196 kb
Host smart-26872b49-9dfa-40a4-9041-5947c5dcd241
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1948604998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1948604998
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2314982192
Short name T449
Test name
Test status
Simulation time 154245397 ps
CPU time 0.8 seconds
Started Jul 06 05:29:08 PM PDT 24
Finished Jul 06 05:29:10 PM PDT 24
Peak memory 206176 kb
Host smart-13961f30-d792-4349-8f34-52052a2ea365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23149
82192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2314982192
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2507004174
Short name T137
Test name
Test status
Simulation time 187267967 ps
CPU time 0.83 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 206160 kb
Host smart-df8c5877-7df0-4520-994f-6ca1ec30dff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25070
04174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2507004174
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1303361343
Short name T2408
Test name
Test status
Simulation time 187084688 ps
CPU time 0.83 seconds
Started Jul 06 05:29:21 PM PDT 24
Finished Jul 06 05:29:22 PM PDT 24
Peak memory 206200 kb
Host smart-f167d267-65b7-4ee3-9167-aa442456387f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13033
61343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1303361343
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1803091612
Short name T773
Test name
Test status
Simulation time 221647624 ps
CPU time 0.86 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 206156 kb
Host smart-0485a897-7f46-4bca-a529-e860591c36e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
91612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1803091612
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4169668006
Short name T580
Test name
Test status
Simulation time 201883272 ps
CPU time 0.91 seconds
Started Jul 06 05:29:10 PM PDT 24
Finished Jul 06 05:29:11 PM PDT 24
Peak memory 206112 kb
Host smart-b5d61fec-3d5d-46f8-be55-f68a199578dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
68006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4169668006
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3658179587
Short name T1130
Test name
Test status
Simulation time 181938811 ps
CPU time 0.81 seconds
Started Jul 06 05:29:16 PM PDT 24
Finished Jul 06 05:29:18 PM PDT 24
Peak memory 206064 kb
Host smart-52591f01-e4ed-4d30-8ba1-fd11734aef6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36581
79587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3658179587
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3957756462
Short name T2657
Test name
Test status
Simulation time 211379595 ps
CPU time 0.93 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:30 PM PDT 24
Peak memory 206156 kb
Host smart-7bdf4e66-055d-4121-b2a9-72cbe1256dce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3957756462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3957756462
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.196664698
Short name T205
Test name
Test status
Simulation time 178791835 ps
CPU time 0.78 seconds
Started Jul 06 05:29:10 PM PDT 24
Finished Jul 06 05:29:11 PM PDT 24
Peak memory 206088 kb
Host smart-7f31bc22-c1b3-4769-8aea-e93af212a556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19666
4698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.196664698
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3269867988
Short name T1801
Test name
Test status
Simulation time 36681136 ps
CPU time 0.68 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:29:13 PM PDT 24
Peak memory 206192 kb
Host smart-aa83b846-5051-4fcc-a51b-99f1922379f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32698
67988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3269867988
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3364448488
Short name T2390
Test name
Test status
Simulation time 8282008417 ps
CPU time 17.19 seconds
Started Jul 06 05:29:10 PM PDT 24
Finished Jul 06 05:29:28 PM PDT 24
Peak memory 206368 kb
Host smart-fbd6048e-6aaa-406e-b26d-e3de86c9c6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33644
48488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3364448488
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1541308366
Short name T1022
Test name
Test status
Simulation time 165470864 ps
CPU time 0.85 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:14 PM PDT 24
Peak memory 206188 kb
Host smart-d985cc18-e1a2-4794-91ed-6d69c6dc93cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15413
08366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1541308366
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1294398089
Short name T1580
Test name
Test status
Simulation time 211422692 ps
CPU time 0.87 seconds
Started Jul 06 05:29:18 PM PDT 24
Finished Jul 06 05:29:19 PM PDT 24
Peak memory 206156 kb
Host smart-8dfb6486-b4f5-4bfe-8e28-8132c5553b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12943
98089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1294398089
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1023520821
Short name T855
Test name
Test status
Simulation time 228853960 ps
CPU time 0.88 seconds
Started Jul 06 05:29:10 PM PDT 24
Finished Jul 06 05:29:11 PM PDT 24
Peak memory 206112 kb
Host smart-9749e948-d1c6-4ea2-8a77-e5130d01588c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235
20821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1023520821
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.4189211378
Short name T34
Test name
Test status
Simulation time 186638684 ps
CPU time 0.98 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 206180 kb
Host smart-51acead2-1740-4c67-9ff0-1d37939de2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
11378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.4189211378
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3183110900
Short name T1440
Test name
Test status
Simulation time 165199813 ps
CPU time 0.84 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 206176 kb
Host smart-183e0643-e604-4fa3-a385-a85fb068f47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
10900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3183110900
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1365676288
Short name T604
Test name
Test status
Simulation time 189659444 ps
CPU time 0.84 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:29:13 PM PDT 24
Peak memory 206200 kb
Host smart-f8c69ffe-4d0c-487d-8cac-f02bab9044d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13656
76288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1365676288
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1116437133
Short name T1415
Test name
Test status
Simulation time 150281853 ps
CPU time 0.79 seconds
Started Jul 06 05:29:26 PM PDT 24
Finished Jul 06 05:29:27 PM PDT 24
Peak memory 206152 kb
Host smart-61ba71b2-8236-45d2-bf91-2882f04ddabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11164
37133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1116437133
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.682330111
Short name T2215
Test name
Test status
Simulation time 243080470 ps
CPU time 0.9 seconds
Started Jul 06 05:29:16 PM PDT 24
Finished Jul 06 05:29:18 PM PDT 24
Peak memory 206156 kb
Host smart-3efab628-1628-49bd-9755-8712c7ebda64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68233
0111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.682330111
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.4279142966
Short name T572
Test name
Test status
Simulation time 3362578428 ps
CPU time 90.71 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:31:02 PM PDT 24
Peak memory 206540 kb
Host smart-da4fe274-3a8a-4d3c-ad83-091dc547ec95
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4279142966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.4279142966
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2865611667
Short name T959
Test name
Test status
Simulation time 177150470 ps
CPU time 0.85 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 206164 kb
Host smart-729033cf-0c13-4927-9e85-b80928f636d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28656
11667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2865611667
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1111143053
Short name T1595
Test name
Test status
Simulation time 192459421 ps
CPU time 0.81 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 206184 kb
Host smart-8d295830-4e2a-4c24-80ca-8e055e7bd195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111
43053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1111143053
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2362531667
Short name T881
Test name
Test status
Simulation time 1082792953 ps
CPU time 2.35 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 206372 kb
Host smart-d66506ed-5ec1-4231-96b5-e112617a3020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
31667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2362531667
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.4069617197
Short name T2208
Test name
Test status
Simulation time 7778046588 ps
CPU time 72.47 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 206300 kb
Host smart-56bbd67e-d13f-413f-a738-c29a68642614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40696
17197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.4069617197
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1888550519
Short name T2524
Test name
Test status
Simulation time 116710145 ps
CPU time 0.8 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206208 kb
Host smart-b04b869d-6ff0-4ec1-89ac-65205e7e95d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1888550519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1888550519
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1074738437
Short name T1681
Test name
Test status
Simulation time 3634176855 ps
CPU time 5.12 seconds
Started Jul 06 05:23:18 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206460 kb
Host smart-ef91a17d-2f74-431e-9c0b-1c9136db454d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1074738437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1074738437
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.4284495890
Short name T1961
Test name
Test status
Simulation time 13316734623 ps
CPU time 12.59 seconds
Started Jul 06 05:23:24 PM PDT 24
Finished Jul 06 05:23:37 PM PDT 24
Peak memory 206468 kb
Host smart-1ecab872-daf2-4b9c-8935-e0a1c77808c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4284495890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.4284495890
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2282784443
Short name T2064
Test name
Test status
Simulation time 23340602799 ps
CPU time 22.08 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206464 kb
Host smart-b270c434-0737-4421-aaef-f849172176c8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2282784443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2282784443
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3811945794
Short name T2333
Test name
Test status
Simulation time 191551528 ps
CPU time 0.82 seconds
Started Jul 06 05:23:17 PM PDT 24
Finished Jul 06 05:23:18 PM PDT 24
Peak memory 206200 kb
Host smart-3888f54b-e520-486c-92b7-63971da6d72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38119
45794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3811945794
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2310619101
Short name T529
Test name
Test status
Simulation time 183779427 ps
CPU time 0.82 seconds
Started Jul 06 05:23:18 PM PDT 24
Finished Jul 06 05:23:19 PM PDT 24
Peak memory 206120 kb
Host smart-17a33fee-968c-431f-a4e6-a4d9b4c0ac83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23106
19101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2310619101
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2903518288
Short name T2295
Test name
Test status
Simulation time 265202917 ps
CPU time 0.99 seconds
Started Jul 06 05:23:17 PM PDT 24
Finished Jul 06 05:23:18 PM PDT 24
Peak memory 206160 kb
Host smart-0345e4e8-3087-4842-baf0-fba4121e0c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035
18288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2903518288
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1475440687
Short name T2538
Test name
Test status
Simulation time 1355206746 ps
CPU time 3.06 seconds
Started Jul 06 05:23:24 PM PDT 24
Finished Jul 06 05:23:28 PM PDT 24
Peak memory 206336 kb
Host smart-9a619e31-fdc1-4947-bc18-8cca38c6a657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14754
40687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1475440687
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.426586559
Short name T1396
Test name
Test status
Simulation time 11016707654 ps
CPU time 20.96 seconds
Started Jul 06 05:23:18 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206512 kb
Host smart-bfdad4aa-8f31-410b-bc05-be50d4ce2ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658
6559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.426586559
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3032049729
Short name T390
Test name
Test status
Simulation time 395630154 ps
CPU time 1.19 seconds
Started Jul 06 05:23:26 PM PDT 24
Finished Jul 06 05:23:27 PM PDT 24
Peak memory 206144 kb
Host smart-7b64a687-e8de-465b-9ed9-e24a1dedc1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30320
49729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3032049729
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2886382803
Short name T475
Test name
Test status
Simulation time 135207174 ps
CPU time 0.78 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:31 PM PDT 24
Peak memory 206204 kb
Host smart-78361435-0ed4-4944-a74c-8b29f6793f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28863
82803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2886382803
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3954847081
Short name T2135
Test name
Test status
Simulation time 39077648 ps
CPU time 0.64 seconds
Started Jul 06 05:23:26 PM PDT 24
Finished Jul 06 05:23:27 PM PDT 24
Peak memory 206196 kb
Host smart-0e341a7d-b0df-4472-b858-db552ab949e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548
47081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3954847081
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1436695994
Short name T368
Test name
Test status
Simulation time 811353467 ps
CPU time 2.18 seconds
Started Jul 06 05:23:26 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206428 kb
Host smart-e4b248c7-f08a-421f-955d-687536ab5dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14366
95994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1436695994
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1235110894
Short name T851
Test name
Test status
Simulation time 165927180 ps
CPU time 1.64 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206364 kb
Host smart-89625fc4-484d-4db2-8016-8514c35d7727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12351
10894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1235110894
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2041403020
Short name T1090
Test name
Test status
Simulation time 239320817 ps
CPU time 0.98 seconds
Started Jul 06 05:23:22 PM PDT 24
Finished Jul 06 05:23:24 PM PDT 24
Peak memory 206108 kb
Host smart-86cc321b-1fae-4492-acf8-51e957a90531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20414
03020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2041403020
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1513456421
Short name T2205
Test name
Test status
Simulation time 140217372 ps
CPU time 0.81 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206200 kb
Host smart-37e41579-5f40-48a7-bba7-9ade5c0bc3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
56421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1513456421
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2971783231
Short name T2318
Test name
Test status
Simulation time 224098962 ps
CPU time 0.83 seconds
Started Jul 06 05:23:22 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206164 kb
Host smart-99b42d1e-ee3b-46d6-bf42-a46ec5c5cf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29717
83231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2971783231
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.177549823
Short name T2290
Test name
Test status
Simulation time 5661001989 ps
CPU time 53.29 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:24:22 PM PDT 24
Peak memory 206428 kb
Host smart-84afca0a-9ddb-4978-a0cf-bcaceabc466c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=177549823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.177549823
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1614763815
Short name T984
Test name
Test status
Simulation time 198160270 ps
CPU time 0.86 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206180 kb
Host smart-f0c19be2-bbb6-406e-bdb2-861c236aa999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16147
63815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1614763815
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.4142008390
Short name T429
Test name
Test status
Simulation time 23271671655 ps
CPU time 23.27 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206264 kb
Host smart-f13688b1-4fe6-4d0d-8ebf-cf5f039a1cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41420
08390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.4142008390
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2999447098
Short name T337
Test name
Test status
Simulation time 3281109378 ps
CPU time 3.9 seconds
Started Jul 06 05:23:30 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206260 kb
Host smart-6195d41a-a9c8-4009-8394-ca90b96b3f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
47098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2999447098
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1810758852
Short name T2220
Test name
Test status
Simulation time 7817357761 ps
CPU time 212.24 seconds
Started Jul 06 05:23:23 PM PDT 24
Finished Jul 06 05:26:56 PM PDT 24
Peak memory 206452 kb
Host smart-696a6ce3-7966-4b82-aa62-dd36c270c24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
58852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1810758852
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3054847309
Short name T946
Test name
Test status
Simulation time 3991701285 ps
CPU time 27.85 seconds
Started Jul 06 05:23:23 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206368 kb
Host smart-8093895c-79dc-48c7-850b-00828458842f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3054847309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3054847309
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1491967703
Short name T707
Test name
Test status
Simulation time 261223369 ps
CPU time 0.93 seconds
Started Jul 06 05:23:21 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206176 kb
Host smart-8aec359e-77bc-4547-9268-a6d75a0fde6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1491967703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1491967703
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.90008852
Short name T85
Test name
Test status
Simulation time 215172719 ps
CPU time 0.89 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:32 PM PDT 24
Peak memory 206204 kb
Host smart-9a0c2e00-d1e2-4ea9-b4e7-a9aced0cc7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90008
852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.90008852
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2908611820
Short name T1261
Test name
Test status
Simulation time 4675266213 ps
CPU time 42.69 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:24:11 PM PDT 24
Peak memory 206500 kb
Host smart-b8294460-4128-4ab8-bb65-532e26df5557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
11820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2908611820
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2498191311
Short name T2658
Test name
Test status
Simulation time 2982292316 ps
CPU time 82.64 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:24:52 PM PDT 24
Peak memory 206408 kb
Host smart-aa6192a5-0435-42f2-87fd-3ffbe137fe33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2498191311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2498191311
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.727864658
Short name T2090
Test name
Test status
Simulation time 153773202 ps
CPU time 0.81 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:30 PM PDT 24
Peak memory 206204 kb
Host smart-bcf462ee-d0c5-4a41-af6d-b39f7eb69f8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=727864658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.727864658
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3325370814
Short name T2593
Test name
Test status
Simulation time 174941625 ps
CPU time 0.81 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:30 PM PDT 24
Peak memory 206128 kb
Host smart-9ab51769-1b46-49a3-ab86-1ceccc1b2d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
70814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3325370814
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1650615966
Short name T126
Test name
Test status
Simulation time 198895350 ps
CPU time 0.85 seconds
Started Jul 06 05:23:21 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206164 kb
Host smart-76caac84-19c8-433c-a98b-4a414edb99d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16506
15966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1650615966
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.334099980
Short name T1408
Test name
Test status
Simulation time 160349311 ps
CPU time 0.86 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206144 kb
Host smart-6225a026-da87-4a2a-91c0-390ec32f09f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33409
9980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.334099980
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1830431183
Short name T1601
Test name
Test status
Simulation time 205810067 ps
CPU time 0.79 seconds
Started Jul 06 05:23:30 PM PDT 24
Finished Jul 06 05:23:31 PM PDT 24
Peak memory 206140 kb
Host smart-9ac5989c-565c-4367-88ef-e05a906ccf35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18304
31183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1830431183
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3932798749
Short name T2595
Test name
Test status
Simulation time 170822525 ps
CPU time 0.83 seconds
Started Jul 06 05:23:30 PM PDT 24
Finished Jul 06 05:23:31 PM PDT 24
Peak memory 206148 kb
Host smart-59460d9b-5e92-4995-86e9-7d31c79e94e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39327
98749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3932798749
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4095283853
Short name T2423
Test name
Test status
Simulation time 191084268 ps
CPU time 0.83 seconds
Started Jul 06 05:23:23 PM PDT 24
Finished Jul 06 05:23:24 PM PDT 24
Peak memory 206156 kb
Host smart-46cdfd81-06a4-4587-b894-510cf53d1f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
83853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4095283853
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2169156802
Short name T943
Test name
Test status
Simulation time 169845765 ps
CPU time 0.93 seconds
Started Jul 06 05:23:22 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206164 kb
Host smart-a7f28fa1-c144-4887-a915-e5ba8c61b621
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2169156802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2169156802
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1931606440
Short name T1466
Test name
Test status
Simulation time 143755305 ps
CPU time 0.76 seconds
Started Jul 06 05:23:24 PM PDT 24
Finished Jul 06 05:23:25 PM PDT 24
Peak memory 206184 kb
Host smart-11d2caca-3adf-4348-a9f1-5718864c6a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316
06440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1931606440
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1820883767
Short name T25
Test name
Test status
Simulation time 78062066 ps
CPU time 0.72 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:30 PM PDT 24
Peak memory 206136 kb
Host smart-31336eb5-1a64-474c-879a-e91d21f774fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
83767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1820883767
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2593309208
Short name T1449
Test name
Test status
Simulation time 7895331792 ps
CPU time 18.14 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:47 PM PDT 24
Peak memory 206404 kb
Host smart-27569616-2282-4e66-b350-0b7f0f550a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25933
09208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2593309208
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3542029268
Short name T1860
Test name
Test status
Simulation time 177085237 ps
CPU time 0.83 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206180 kb
Host smart-1f8bd101-c615-4181-b05f-a4be6d6ce697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35420
29268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3542029268
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.345393919
Short name T558
Test name
Test status
Simulation time 222978836 ps
CPU time 0.87 seconds
Started Jul 06 05:23:23 PM PDT 24
Finished Jul 06 05:23:24 PM PDT 24
Peak memory 206184 kb
Host smart-567b4d86-30db-4197-861b-176811b03308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34539
3919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.345393919
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3519842822
Short name T2371
Test name
Test status
Simulation time 12908512816 ps
CPU time 85.5 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:24:53 PM PDT 24
Peak memory 206472 kb
Host smart-d91991fc-e666-413b-970d-29260b21ebb0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3519842822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3519842822
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.781353288
Short name T2159
Test name
Test status
Simulation time 8528051096 ps
CPU time 213.6 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:27:03 PM PDT 24
Peak memory 206556 kb
Host smart-a4b025b7-79ec-4373-89fa-bf876c26fa5c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=781353288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.781353288
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3268894349
Short name T1207
Test name
Test status
Simulation time 21975675386 ps
CPU time 473.81 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:31:27 PM PDT 24
Peak memory 206524 kb
Host smart-32b197ec-5153-4233-9476-6188bf155ce8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3268894349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3268894349
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1493890286
Short name T1868
Test name
Test status
Simulation time 198215610 ps
CPU time 0.86 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206124 kb
Host smart-0d0b31b8-eebb-49ee-9c08-881759b22626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14938
90286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1493890286
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3224239636
Short name T497
Test name
Test status
Simulation time 159209301 ps
CPU time 0.81 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:30 PM PDT 24
Peak memory 206156 kb
Host smart-117ee1ab-e667-4b7b-ba53-c2cfdcb32aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32242
39636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3224239636
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2899106798
Short name T469
Test name
Test status
Simulation time 136556785 ps
CPU time 0.76 seconds
Started Jul 06 05:23:21 PM PDT 24
Finished Jul 06 05:23:23 PM PDT 24
Peak memory 206196 kb
Host smart-fec741ba-479d-49d1-bf5e-6cbce9b3c91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28991
06798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2899106798
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.720492968
Short name T328
Test name
Test status
Simulation time 164036631 ps
CPU time 0.82 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206204 kb
Host smart-330504cd-0c0d-4a8a-8a0e-16bd5e135ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72049
2968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.720492968
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3906907694
Short name T1892
Test name
Test status
Simulation time 211589110 ps
CPU time 0.82 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:29 PM PDT 24
Peak memory 206176 kb
Host smart-ff72c24c-aca3-414b-b5bd-a36c78484c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39069
07694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3906907694
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1233382958
Short name T557
Test name
Test status
Simulation time 223531986 ps
CPU time 0.96 seconds
Started Jul 06 05:23:22 PM PDT 24
Finished Jul 06 05:23:24 PM PDT 24
Peak memory 206200 kb
Host smart-464a8f0e-7455-4fd3-9cd8-97cf0efd2f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
82958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1233382958
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3992812948
Short name T1416
Test name
Test status
Simulation time 5880199395 ps
CPU time 41.54 seconds
Started Jul 06 05:23:30 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206524 kb
Host smart-b8c40231-30cd-4fdc-aa2b-d9d18b83318e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3992812948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3992812948
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3252289135
Short name T620
Test name
Test status
Simulation time 180226309 ps
CPU time 0.78 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206176 kb
Host smart-073157e7-5724-4313-a3fa-e28c1936b44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32522
89135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3252289135
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.261895293
Short name T1903
Test name
Test status
Simulation time 150255147 ps
CPU time 0.78 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:30 PM PDT 24
Peak memory 206180 kb
Host smart-15069ff2-4ea3-448f-bfa8-8e8cfd124da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26189
5293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.261895293
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2535488468
Short name T1054
Test name
Test status
Simulation time 564390591 ps
CPU time 1.49 seconds
Started Jul 06 05:23:34 PM PDT 24
Finished Jul 06 05:23:36 PM PDT 24
Peak memory 206184 kb
Host smart-3b0dd4bf-0125-4faf-bd3b-6fde8eefb12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25354
88468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2535488468
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2169646152
Short name T796
Test name
Test status
Simulation time 3005836050 ps
CPU time 28.11 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206488 kb
Host smart-ad183876-eaa7-4879-89a4-50fecc890b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21696
46152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2169646152
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.333268986
Short name T2254
Test name
Test status
Simulation time 75997520 ps
CPU time 0.73 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206244 kb
Host smart-3d191ec0-1a3a-4eb3-bcaf-873e1a4dfad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=333268986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.333268986
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3459666737
Short name T2447
Test name
Test status
Simulation time 4301313126 ps
CPU time 5.48 seconds
Started Jul 06 05:23:29 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206436 kb
Host smart-dbe41eef-6bab-4f98-b85d-0e85c7ceb942
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3459666737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3459666737
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3641764238
Short name T1511
Test name
Test status
Simulation time 13369294854 ps
CPU time 13.42 seconds
Started Jul 06 05:23:26 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206264 kb
Host smart-550c6e8b-5fc1-401f-bc90-86dbd8535860
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3641764238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3641764238
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3950017278
Short name T528
Test name
Test status
Simulation time 23382405147 ps
CPU time 24.39 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:55 PM PDT 24
Peak memory 206264 kb
Host smart-3ec0c3ee-3407-4480-9c55-0e39735e5666
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3950017278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3950017278
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2516689171
Short name T2317
Test name
Test status
Simulation time 183316723 ps
CPU time 0.85 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206156 kb
Host smart-b740a509-769b-4e61-9015-051892a90e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
89171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2516689171
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2544495751
Short name T978
Test name
Test status
Simulation time 161748292 ps
CPU time 0.77 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206184 kb
Host smart-e6ee45ca-ffbd-494c-94d4-45b397502714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25444
95751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2544495751
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1659286317
Short name T511
Test name
Test status
Simulation time 168173806 ps
CPU time 0.82 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206144 kb
Host smart-71c4b8a8-60ae-446d-a2de-1cf3655c4775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
86317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1659286317
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3503325559
Short name T2280
Test name
Test status
Simulation time 954231475 ps
CPU time 2.2 seconds
Started Jul 06 05:23:30 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206316 kb
Host smart-aa56ea8f-afd0-4e14-9f8f-fe7382f1b9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
25559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3503325559
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3616518452
Short name T1267
Test name
Test status
Simulation time 9580902084 ps
CPU time 20.75 seconds
Started Jul 06 05:23:28 PM PDT 24
Finished Jul 06 05:23:49 PM PDT 24
Peak memory 206360 kb
Host smart-4120cf0d-dd74-4f4b-9ba6-b4544adf67ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36165
18452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3616518452
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3659170572
Short name T1294
Test name
Test status
Simulation time 406922598 ps
CPU time 1.31 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206136 kb
Host smart-d0530801-e6e8-46a6-a57a-635dd2c5ce76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36591
70572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3659170572
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1075526599
Short name T1631
Test name
Test status
Simulation time 166563811 ps
CPU time 0.8 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206156 kb
Host smart-6830a7ca-71f3-452d-8eba-3c8eecddfb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
26599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1075526599
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.437034544
Short name T2666
Test name
Test status
Simulation time 35942077 ps
CPU time 0.65 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206148 kb
Host smart-1cb987e2-651f-4868-af81-9f2815bd37ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43703
4544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.437034544
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.481522027
Short name T2665
Test name
Test status
Simulation time 879453331 ps
CPU time 2.06 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:36 PM PDT 24
Peak memory 206356 kb
Host smart-e9056651-64bb-41d5-b363-37420e5e12aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48152
2027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.481522027
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.848333460
Short name T2482
Test name
Test status
Simulation time 318426607 ps
CPU time 1.92 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:43 PM PDT 24
Peak memory 206380 kb
Host smart-b05f7019-341c-45be-a1f3-bf45e33b1f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84833
3460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.848333460
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3011078114
Short name T2618
Test name
Test status
Simulation time 159676057 ps
CPU time 0.8 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206180 kb
Host smart-f60b742e-b389-43dd-bb5a-280f2936830a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
78114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3011078114
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.10162929
Short name T1501
Test name
Test status
Simulation time 165820655 ps
CPU time 0.78 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:23:28 PM PDT 24
Peak memory 206180 kb
Host smart-415e204f-0053-4401-92fe-06be11e2fb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.10162929
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3583649001
Short name T375
Test name
Test status
Simulation time 183087220 ps
CPU time 0.79 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:32 PM PDT 24
Peak memory 206184 kb
Host smart-bfb2c3b8-fbcc-4a78-a216-7ee4e23f3e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35836
49001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3583649001
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.1921705943
Short name T78
Test name
Test status
Simulation time 6282451668 ps
CPU time 179.83 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:26:28 PM PDT 24
Peak memory 206484 kb
Host smart-3533461c-64e7-4ec7-ac04-73da703d3025
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1921705943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1921705943
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1831463812
Short name T1919
Test name
Test status
Simulation time 239031149 ps
CPU time 0.92 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206160 kb
Host smart-78b2c846-a3ed-4e1a-9278-fcce12924093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18314
63812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1831463812
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1742679861
Short name T1725
Test name
Test status
Simulation time 23314124558 ps
CPU time 23.52 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206232 kb
Host smart-e89988c6-0207-4d99-9bed-b4546aaca399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17426
79861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1742679861
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.358889701
Short name T1983
Test name
Test status
Simulation time 3355274451 ps
CPU time 3.97 seconds
Started Jul 06 05:23:30 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206264 kb
Host smart-a182e223-1974-45a9-a3dd-285594671294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35888
9701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.358889701
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2508223143
Short name T1085
Test name
Test status
Simulation time 14141526659 ps
CPU time 100.26 seconds
Started Jul 06 05:23:27 PM PDT 24
Finished Jul 06 05:25:07 PM PDT 24
Peak memory 206408 kb
Host smart-d29f9977-5771-42f6-901e-0b8f80b5be47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25082
23143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2508223143
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2309192920
Short name T2555
Test name
Test status
Simulation time 5009561875 ps
CPU time 35.54 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:24:09 PM PDT 24
Peak memory 206412 kb
Host smart-2425d510-fe1b-489d-bcae-4121cb3cef8c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2309192920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2309192920
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.862875613
Short name T541
Test name
Test status
Simulation time 232931105 ps
CPU time 0.94 seconds
Started Jul 06 05:23:34 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206172 kb
Host smart-f1ee7e4e-3dc8-491e-90ce-ff3a82ce1ed6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=862875613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.862875613
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.525314403
Short name T537
Test name
Test status
Simulation time 197185896 ps
CPU time 0.85 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206144 kb
Host smart-1d70c717-6534-40e7-bdec-15a64a99ff5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52531
4403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.525314403
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2296463421
Short name T2689
Test name
Test status
Simulation time 5963449326 ps
CPU time 43.97 seconds
Started Jul 06 05:23:35 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206424 kb
Host smart-b41f881b-f581-4146-9683-ae87d63117dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22964
63421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2296463421
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1493897448
Short name T710
Test name
Test status
Simulation time 5304697460 ps
CPU time 39.2 seconds
Started Jul 06 05:23:34 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206404 kb
Host smart-9ab2566e-0e5c-4ed2-8c29-f46143aa5372
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1493897448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1493897448
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1983641776
Short name T923
Test name
Test status
Simulation time 147803423 ps
CPU time 0.86 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206152 kb
Host smart-082ba5da-a43a-4313-b339-4b6490cf0ea4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1983641776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1983641776
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4033291367
Short name T1142
Test name
Test status
Simulation time 193043659 ps
CPU time 0.89 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206200 kb
Host smart-7d987cc2-9f24-4401-a1a6-d9c37a3ec53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40332
91367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4033291367
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2712020128
Short name T123
Test name
Test status
Simulation time 196325408 ps
CPU time 0.88 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206200 kb
Host smart-0868ee63-fcc7-4b14-946c-72c363385fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27120
20128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2712020128
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3896156506
Short name T2421
Test name
Test status
Simulation time 216828554 ps
CPU time 0.89 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:32 PM PDT 24
Peak memory 206164 kb
Host smart-a67dab8a-d70a-4f52-a2c0-2c34ca99c62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38961
56506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3896156506
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3203314725
Short name T1214
Test name
Test status
Simulation time 177934644 ps
CPU time 0.78 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:32 PM PDT 24
Peak memory 206200 kb
Host smart-3504bbad-59bd-4c1b-b35a-cf524cab07e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32033
14725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3203314725
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3666757713
Short name T1371
Test name
Test status
Simulation time 183322168 ps
CPU time 0.83 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206164 kb
Host smart-2195939a-1934-4e2c-add7-87691d3756aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36667
57713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3666757713
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3174344415
Short name T1066
Test name
Test status
Simulation time 148388078 ps
CPU time 0.79 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206180 kb
Host smart-6dded7a5-2370-4424-b450-900c672a3904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
44415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3174344415
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.656786002
Short name T841
Test name
Test status
Simulation time 214262593 ps
CPU time 0.89 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206164 kb
Host smart-ddb4ff1f-3515-4a81-8d7f-98e9fe25675f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=656786002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.656786002
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1633261352
Short name T2616
Test name
Test status
Simulation time 139461626 ps
CPU time 0.78 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206200 kb
Host smart-ed005545-1337-4112-be40-3bbfd669b1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16332
61352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1633261352
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.257693046
Short name T2445
Test name
Test status
Simulation time 39717502 ps
CPU time 0.68 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206160 kb
Host smart-bafa19f2-b5d0-4c79-9d61-e2f3d45c5d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769
3046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.257693046
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.108803370
Short name T1315
Test name
Test status
Simulation time 6529076675 ps
CPU time 15.37 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:49 PM PDT 24
Peak memory 206564 kb
Host smart-a8f8a22b-08b5-4823-b4a5-eac30428f165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10880
3370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.108803370
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3346870299
Short name T1533
Test name
Test status
Simulation time 191332937 ps
CPU time 0.86 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206120 kb
Host smart-b025762c-16d9-412b-87cf-e5827c7e4d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33468
70299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3346870299
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2541762071
Short name T2048
Test name
Test status
Simulation time 173970733 ps
CPU time 0.8 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206200 kb
Host smart-48387af7-f2ec-44c9-92ff-41a68f12e419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25417
62071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2541762071
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3699829120
Short name T168
Test name
Test status
Simulation time 5697515725 ps
CPU time 138.59 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:25:53 PM PDT 24
Peak memory 206552 kb
Host smart-7f5eed92-3a47-49f2-8c68-659c4a25bbc1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3699829120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3699829120
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3358366572
Short name T2104
Test name
Test status
Simulation time 10932058164 ps
CPU time 308.17 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:28:40 PM PDT 24
Peak memory 206548 kb
Host smart-30a89030-dd50-46fd-9dc0-91847d5f4bf3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3358366572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3358366572
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3310965770
Short name T202
Test name
Test status
Simulation time 13574614790 ps
CPU time 90.3 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:25:02 PM PDT 24
Peak memory 206524 kb
Host smart-5e1ef13c-7d07-45df-8c1c-9c5d92c4d581
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3310965770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3310965770
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.277688939
Short name T854
Test name
Test status
Simulation time 228481953 ps
CPU time 0.89 seconds
Started Jul 06 05:23:33 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206200 kb
Host smart-801b9944-b09e-417c-b259-7b554b03613a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
8939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.277688939
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.419979437
Short name T2402
Test name
Test status
Simulation time 162095945 ps
CPU time 0.81 seconds
Started Jul 06 05:23:31 PM PDT 24
Finished Jul 06 05:23:33 PM PDT 24
Peak memory 206200 kb
Host smart-1e82a93d-6aec-4cd2-8146-4f5281dfc725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
9437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.419979437
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3731407778
Short name T2026
Test name
Test status
Simulation time 177521549 ps
CPU time 0.89 seconds
Started Jul 06 05:23:34 PM PDT 24
Finished Jul 06 05:23:36 PM PDT 24
Peak memory 206204 kb
Host smart-85411646-f135-4198-847e-02ead7028140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37314
07778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3731407778
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3216723040
Short name T1935
Test name
Test status
Simulation time 161071925 ps
CPU time 0.79 seconds
Started Jul 06 05:23:34 PM PDT 24
Finished Jul 06 05:23:35 PM PDT 24
Peak memory 206220 kb
Host smart-7759515d-93ff-45e1-95ce-5505bbd764cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
23040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3216723040
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.959786174
Short name T2065
Test name
Test status
Simulation time 147022935 ps
CPU time 0.81 seconds
Started Jul 06 05:23:32 PM PDT 24
Finished Jul 06 05:23:34 PM PDT 24
Peak memory 206124 kb
Host smart-33efbfa0-1ce8-45f7-b847-3bb9f635f544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95978
6174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.959786174
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2517174177
Short name T2058
Test name
Test status
Simulation time 229630016 ps
CPU time 1.12 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206200 kb
Host smart-eeabf258-b8fe-423c-befc-6587baba6b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171
74177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2517174177
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1637217379
Short name T2190
Test name
Test status
Simulation time 4373389643 ps
CPU time 30.11 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:24:08 PM PDT 24
Peak memory 206440 kb
Host smart-086b43df-52c1-475e-a20e-05c0a55351e1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1637217379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1637217379
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.367104829
Short name T2648
Test name
Test status
Simulation time 185858939 ps
CPU time 0.87 seconds
Started Jul 06 05:23:36 PM PDT 24
Finished Jul 06 05:23:37 PM PDT 24
Peak memory 206204 kb
Host smart-c956a3eb-1b66-4556-963e-75e6170dd17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
4829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.367104829
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.4184569713
Short name T1733
Test name
Test status
Simulation time 164278908 ps
CPU time 0.77 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206200 kb
Host smart-6790ae21-88db-4174-bbc9-4c0f8ffd9368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
69713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.4184569713
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.840249546
Short name T2082
Test name
Test status
Simulation time 460731674 ps
CPU time 1.32 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206108 kb
Host smart-f2824226-9b24-47c9-8323-d115722cd109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84024
9546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.840249546
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.427231747
Short name T1989
Test name
Test status
Simulation time 4021167060 ps
CPU time 37.26 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:24:15 PM PDT 24
Peak memory 206460 kb
Host smart-9c9b4d63-038b-4289-a2fc-74fe80d0aecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
1747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.427231747
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.4076511875
Short name T2006
Test name
Test status
Simulation time 40405016 ps
CPU time 0.67 seconds
Started Jul 06 05:23:43 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206244 kb
Host smart-1147a59e-77e5-436d-ad28-8fae736ed406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4076511875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.4076511875
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.4120555464
Short name T2515
Test name
Test status
Simulation time 4322547657 ps
CPU time 5.09 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:48 PM PDT 24
Peak memory 206460 kb
Host smart-cedf939d-fc9c-49a6-bbfa-e764d9ac2d1e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4120555464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.4120555464
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3052743965
Short name T1121
Test name
Test status
Simulation time 13480534344 ps
CPU time 13.4 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:52 PM PDT 24
Peak memory 206496 kb
Host smart-d1c37de3-c490-4697-b8a6-5b8a67bbcc53
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3052743965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3052743965
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3256432825
Short name T204
Test name
Test status
Simulation time 23376066131 ps
CPU time 21.65 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:24:02 PM PDT 24
Peak memory 206536 kb
Host smart-e65831ee-e028-4616-a56b-78107dcf810e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3256432825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3256432825
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.542819046
Short name T1765
Test name
Test status
Simulation time 195197483 ps
CPU time 0.84 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206160 kb
Host smart-66e71584-8d67-48a2-9180-08e1d717ddf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54281
9046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.542819046
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3424421162
Short name T359
Test name
Test status
Simulation time 138822756 ps
CPU time 0.83 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206220 kb
Host smart-173c36a4-f78c-47fa-93e0-207b5562a066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34244
21162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3424421162
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3786115639
Short name T2675
Test name
Test status
Simulation time 445049633 ps
CPU time 1.31 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206192 kb
Host smart-40466f12-71d9-4575-9f6f-b13231249301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
15639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3786115639
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2145518891
Short name T1797
Test name
Test status
Simulation time 1079075049 ps
CPU time 2.51 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206396 kb
Host smart-491f883f-e923-4b01-85a7-f782a60e8be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21455
18891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2145518891
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.3306360339
Short name T1610
Test name
Test status
Simulation time 9936428544 ps
CPU time 22.18 seconds
Started Jul 06 05:23:36 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206444 kb
Host smart-692abca7-cfba-4e23-a590-fa131e0951c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33063
60339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3306360339
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.361002893
Short name T2542
Test name
Test status
Simulation time 344200512 ps
CPU time 1.17 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206180 kb
Host smart-2598caba-4fee-46f6-890a-b89b193904d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
2893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.361002893
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2991501985
Short name T231
Test name
Test status
Simulation time 138737137 ps
CPU time 0.79 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206184 kb
Host smart-d621c5c2-5cae-4c75-ba94-c717a48c9f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
01985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2991501985
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3990979823
Short name T890
Test name
Test status
Simulation time 83713724 ps
CPU time 0.69 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:23:38 PM PDT 24
Peak memory 206196 kb
Host smart-cab753f3-9c7e-4f16-a34c-172e28f68d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
79823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3990979823
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2281789638
Short name T2587
Test name
Test status
Simulation time 932655805 ps
CPU time 2.54 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:43 PM PDT 24
Peak memory 206348 kb
Host smart-2e7d892e-a09f-4995-a7df-a8e64f04a4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22817
89638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2281789638
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1074650792
Short name T1700
Test name
Test status
Simulation time 225180567 ps
CPU time 1.35 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206372 kb
Host smart-69690bad-ded0-4943-8ba0-8d5c5f1df84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10746
50792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1074650792
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2500342696
Short name T1600
Test name
Test status
Simulation time 239433070 ps
CPU time 0.91 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206196 kb
Host smart-98bf55e7-f595-4dc7-ae95-216637202105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
42696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2500342696
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3214362288
Short name T599
Test name
Test status
Simulation time 198209176 ps
CPU time 0.81 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206120 kb
Host smart-474e7aa5-c557-4f3e-aa33-79897bf3b08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
62288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3214362288
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2514208373
Short name T2110
Test name
Test status
Simulation time 188198543 ps
CPU time 0.83 seconds
Started Jul 06 05:23:35 PM PDT 24
Finished Jul 06 05:23:36 PM PDT 24
Peak memory 206156 kb
Host smart-9699e83f-7817-48a8-b166-481b7cd21847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142
08373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2514208373
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1291102222
Short name T1644
Test name
Test status
Simulation time 6740623346 ps
CPU time 184.88 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:26:46 PM PDT 24
Peak memory 206432 kb
Host smart-8fd80a09-39e1-49b8-9abc-139dfdc4ebdd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1291102222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1291102222
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2837113955
Short name T1292
Test name
Test status
Simulation time 218727375 ps
CPU time 0.92 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206104 kb
Host smart-678306aa-9706-4bc9-a6e6-deafaefc5ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28371
13955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2837113955
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.94386843
Short name T1177
Test name
Test status
Simulation time 23309370830 ps
CPU time 25.84 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:24:06 PM PDT 24
Peak memory 206236 kb
Host smart-211953cf-5d86-474c-b6b0-bb033b8251fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94386
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.94386843
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1140477203
Short name T403
Test name
Test status
Simulation time 3259949899 ps
CPU time 3.76 seconds
Started Jul 06 05:23:35 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206264 kb
Host smart-1d58f836-59bd-48a7-a231-c62de504cad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
77203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1140477203
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3332687463
Short name T2209
Test name
Test status
Simulation time 7102687047 ps
CPU time 191.87 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:26:51 PM PDT 24
Peak memory 206496 kb
Host smart-c46275fb-e09c-4fde-be8c-b9a2dac198b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33326
87463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3332687463
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.319382299
Short name T6
Test name
Test status
Simulation time 4509641931 ps
CPU time 122.34 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:25:39 PM PDT 24
Peak memory 206408 kb
Host smart-6e7abe22-001e-4075-bd8a-c59985b9ad62
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=319382299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.319382299
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.557840977
Short name T1769
Test name
Test status
Simulation time 250291688 ps
CPU time 0.91 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206208 kb
Host smart-9c4a32df-6d77-418e-9796-02700b2bc9b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=557840977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.557840977
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.713977930
Short name T1014
Test name
Test status
Simulation time 198656968 ps
CPU time 0.89 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206176 kb
Host smart-2b5df193-1d7e-4a98-a8d6-9f4f09d4e206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71397
7930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.713977930
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.521342363
Short name T2386
Test name
Test status
Simulation time 3911226219 ps
CPU time 38.21 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206428 kb
Host smart-e1fc26ba-7e6e-40b9-8296-a88a2ece040a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52134
2363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.521342363
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1071079553
Short name T824
Test name
Test status
Simulation time 6600719761 ps
CPU time 61.26 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 206452 kb
Host smart-f64ad578-7332-4404-ba78-877619248fe0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1071079553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1071079553
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2817319492
Short name T1624
Test name
Test status
Simulation time 161437102 ps
CPU time 0.86 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206204 kb
Host smart-7d16a050-2b14-40e3-a5d8-1ae9fa550b79
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2817319492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2817319492
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4122335303
Short name T2498
Test name
Test status
Simulation time 196075067 ps
CPU time 0.83 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206212 kb
Host smart-816c2625-2ee5-4d95-8459-e42edd5b0091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
35303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4122335303
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.604572103
Short name T2179
Test name
Test status
Simulation time 213277407 ps
CPU time 0.89 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206196 kb
Host smart-fc58f82d-3aa1-44b0-a82c-473762fc0d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60457
2103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.604572103
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1434681354
Short name T1692
Test name
Test status
Simulation time 160544494 ps
CPU time 0.82 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:40 PM PDT 24
Peak memory 206200 kb
Host smart-790bc706-793b-4bf5-921f-6a5d43fcb4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14346
81354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1434681354
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.708564807
Short name T538
Test name
Test status
Simulation time 191785923 ps
CPU time 0.86 seconds
Started Jul 06 05:23:37 PM PDT 24
Finished Jul 06 05:23:38 PM PDT 24
Peak memory 206116 kb
Host smart-95d14817-019f-4981-876a-d03be452a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70856
4807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.708564807
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.295125503
Short name T2495
Test name
Test status
Simulation time 226647151 ps
CPU time 0.94 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206104 kb
Host smart-37a2dc00-31bc-43c8-8820-498cb96b406b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29512
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.295125503
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2000200891
Short name T698
Test name
Test status
Simulation time 151154061 ps
CPU time 0.81 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206180 kb
Host smart-f5139e46-a021-4ce3-b3e5-360a27afbcd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002
00891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2000200891
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1237673144
Short name T1658
Test name
Test status
Simulation time 202726607 ps
CPU time 0.92 seconds
Started Jul 06 05:23:36 PM PDT 24
Finished Jul 06 05:23:37 PM PDT 24
Peak memory 206164 kb
Host smart-ff177250-6e34-4a0a-b76b-0d715ed49de3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1237673144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1237673144
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.804250595
Short name T1591
Test name
Test status
Simulation time 148313204 ps
CPU time 0.79 seconds
Started Jul 06 05:23:39 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206204 kb
Host smart-86bd4762-aa42-4776-b43a-1c61ea80b42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80425
0595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.804250595
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3852394518
Short name T1829
Test name
Test status
Simulation time 94658005 ps
CPU time 0.69 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 206196 kb
Host smart-9c27ecd7-18fb-4760-931d-c57e55666c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
94518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3852394518
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3638374272
Short name T2357
Test name
Test status
Simulation time 19948047305 ps
CPU time 41.35 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:24:23 PM PDT 24
Peak memory 206416 kb
Host smart-829ae1d1-3ad4-49c5-8af2-20c359137252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
74272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3638374272
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.862899453
Short name T381
Test name
Test status
Simulation time 191389939 ps
CPU time 0.84 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206180 kb
Host smart-229e8ada-ff42-47d8-9bdc-4323557e487b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86289
9453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.862899453
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.712324832
Short name T1057
Test name
Test status
Simulation time 219050863 ps
CPU time 0.91 seconds
Started Jul 06 05:23:36 PM PDT 24
Finished Jul 06 05:23:37 PM PDT 24
Peak memory 206180 kb
Host smart-51d62c80-da59-4a1e-b23d-a218a6b8c588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71232
4832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.712324832
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3126465950
Short name T2496
Test name
Test status
Simulation time 7858408044 ps
CPU time 113.17 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:25:36 PM PDT 24
Peak memory 206516 kb
Host smart-ed069dfb-d675-4e0f-abd6-7cf3b6afa776
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3126465950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3126465950
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2301698590
Short name T1794
Test name
Test status
Simulation time 8345426482 ps
CPU time 41.92 seconds
Started Jul 06 05:23:43 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206464 kb
Host smart-6135ef03-2b7b-4623-ab73-7525c9764a0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2301698590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2301698590
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2647921154
Short name T2401
Test name
Test status
Simulation time 16869537051 ps
CPU time 378.96 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:30:02 PM PDT 24
Peak memory 206500 kb
Host smart-8007dbcc-4ba3-4d7e-bc6a-cc54481fba0c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2647921154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2647921154
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3195101137
Short name T1514
Test name
Test status
Simulation time 239930051 ps
CPU time 0.88 seconds
Started Jul 06 05:23:38 PM PDT 24
Finished Jul 06 05:23:39 PM PDT 24
Peak memory 206148 kb
Host smart-adf045f4-9e77-4db3-8b64-3347be82b552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
01137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3195101137
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1531884626
Short name T1061
Test name
Test status
Simulation time 144217327 ps
CPU time 0.79 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206124 kb
Host smart-89235889-2de9-44c8-a181-9738834dcc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15318
84626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1531884626
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1824679597
Short name T1203
Test name
Test status
Simulation time 180584954 ps
CPU time 0.84 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:43 PM PDT 24
Peak memory 206200 kb
Host smart-2fde8ec8-504e-4b4e-8a07-95c77a9c3aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18246
79597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1824679597
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.200481235
Short name T154
Test name
Test status
Simulation time 144296337 ps
CPU time 0.83 seconds
Started Jul 06 05:23:40 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206184 kb
Host smart-aab0af2d-6960-4485-b9f3-fd2eb6467d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20048
1235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.200481235
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3070502819
Short name T1179
Test name
Test status
Simulation time 173114202 ps
CPU time 0.76 seconds
Started Jul 06 05:23:45 PM PDT 24
Finished Jul 06 05:23:46 PM PDT 24
Peak memory 206200 kb
Host smart-dea7f781-7acf-484d-b272-e519ddd68fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30705
02819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3070502819
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.368609135
Short name T1639
Test name
Test status
Simulation time 263544082 ps
CPU time 1 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206152 kb
Host smart-355ce8db-5101-41b5-b85b-1f37c55c38d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
9135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.368609135
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.448253045
Short name T1549
Test name
Test status
Simulation time 5088818122 ps
CPU time 37.12 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206504 kb
Host smart-17285f97-841d-4b86-b01e-ca7e907b0c87
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=448253045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.448253045
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2645958683
Short name T768
Test name
Test status
Simulation time 151176921 ps
CPU time 0.81 seconds
Started Jul 06 05:23:44 PM PDT 24
Finished Jul 06 05:23:45 PM PDT 24
Peak memory 206112 kb
Host smart-4ceebff4-888a-494d-8362-633ad29c144d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
58683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2645958683
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.332451304
Short name T546
Test name
Test status
Simulation time 162773181 ps
CPU time 0.8 seconds
Started Jul 06 05:23:45 PM PDT 24
Finished Jul 06 05:23:46 PM PDT 24
Peak memory 206120 kb
Host smart-38045840-0b66-466e-99f0-f0482ec0bc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33245
1304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.332451304
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.1638308447
Short name T2124
Test name
Test status
Simulation time 273224280 ps
CPU time 1.03 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:23:43 PM PDT 24
Peak memory 206180 kb
Host smart-43aa5530-c657-4669-97d0-668370fe3241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
08447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1638308447
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2245400548
Short name T1183
Test name
Test status
Simulation time 4545208310 ps
CPU time 121.29 seconds
Started Jul 06 05:23:45 PM PDT 24
Finished Jul 06 05:25:46 PM PDT 24
Peak memory 206544 kb
Host smart-20f2b1b6-a5ff-49b7-9214-99f77da1b441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22454
00548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2245400548
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.480853855
Short name T1206
Test name
Test status
Simulation time 43371149 ps
CPU time 0.72 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:23:55 PM PDT 24
Peak memory 206248 kb
Host smart-296141a1-f578-4bee-8af2-b90cb24c029a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=480853855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.480853855
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3912699982
Short name T1848
Test name
Test status
Simulation time 3516332098 ps
CPU time 5 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:23:47 PM PDT 24
Peak memory 206264 kb
Host smart-b1e655bc-22eb-46f9-b7c3-4596f46790dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3912699982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3912699982
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1034203536
Short name T1679
Test name
Test status
Simulation time 13314513019 ps
CPU time 16.04 seconds
Started Jul 06 05:23:43 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206272 kb
Host smart-384dcea2-575b-4f9a-972b-bdcf99841dd6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1034203536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1034203536
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2194938168
Short name T1485
Test name
Test status
Simulation time 23343116156 ps
CPU time 22.94 seconds
Started Jul 06 05:23:44 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 206436 kb
Host smart-8c9222bf-d202-47aa-a8fe-482fb7d31e5d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2194938168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2194938168
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2880305194
Short name T2119
Test name
Test status
Simulation time 161181050 ps
CPU time 0.82 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:23:42 PM PDT 24
Peak memory 206116 kb
Host smart-23b63470-7e72-483e-9822-df4ced84c029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803
05194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2880305194
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3004958338
Short name T622
Test name
Test status
Simulation time 148592520 ps
CPU time 0.79 seconds
Started Jul 06 05:23:45 PM PDT 24
Finished Jul 06 05:23:46 PM PDT 24
Peak memory 206116 kb
Host smart-c78b3acd-bc11-4b7f-b2d6-cb653ac52f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30049
58338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3004958338
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.295777507
Short name T1706
Test name
Test status
Simulation time 275095897 ps
CPU time 1.03 seconds
Started Jul 06 05:23:43 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206184 kb
Host smart-abb27446-4f58-4b2f-936b-a082af5fb068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
7507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.295777507
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2016635967
Short name T2379
Test name
Test status
Simulation time 807609924 ps
CPU time 1.94 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206440 kb
Host smart-46b529f3-76b9-46ac-b0a9-c8ebc1639b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20166
35967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2016635967
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3541322621
Short name T1747
Test name
Test status
Simulation time 20705676076 ps
CPU time 38.32 seconds
Started Jul 06 05:23:41 PM PDT 24
Finished Jul 06 05:24:20 PM PDT 24
Peak memory 206384 kb
Host smart-eac6060a-3185-47d8-a3e1-6196c7594a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35413
22621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3541322621
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.175834279
Short name T1792
Test name
Test status
Simulation time 378092689 ps
CPU time 1.21 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:44 PM PDT 24
Peak memory 206108 kb
Host smart-948893de-434f-46fb-a947-287640f18d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17583
4279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.175834279
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2650262593
Short name T2525
Test name
Test status
Simulation time 158939833 ps
CPU time 0.77 seconds
Started Jul 06 05:23:44 PM PDT 24
Finished Jul 06 05:23:45 PM PDT 24
Peak memory 206184 kb
Host smart-f2d3d0b9-de53-42c1-9c3e-a2531b92e07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
62593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2650262593
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3630975379
Short name T255
Test name
Test status
Simulation time 30393224 ps
CPU time 0.65 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:43 PM PDT 24
Peak memory 206140 kb
Host smart-1b22461e-358c-45e6-9272-c522b2c7c275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36309
75379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3630975379
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.825635420
Short name T1199
Test name
Test status
Simulation time 1041164725 ps
CPU time 2.24 seconds
Started Jul 06 05:23:42 PM PDT 24
Finished Jul 06 05:23:45 PM PDT 24
Peak memory 206384 kb
Host smart-3ef788ac-179a-4f30-8a35-f7969755194c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82563
5420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.825635420
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1238800894
Short name T2366
Test name
Test status
Simulation time 183869944 ps
CPU time 2.02 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206412 kb
Host smart-df97a1da-d4cd-4397-95d7-a38b9a8be40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12388
00894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1238800894
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.19200226
Short name T1453
Test name
Test status
Simulation time 240218357 ps
CPU time 0.97 seconds
Started Jul 06 05:23:48 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206176 kb
Host smart-bd460ff7-063f-4091-8627-888f830dcda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19200
226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.19200226
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3848689507
Short name T1836
Test name
Test status
Simulation time 159301081 ps
CPU time 0.8 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206164 kb
Host smart-3f248d2f-a1da-4aee-b848-16d75b43ce72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
89507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3848689507
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1009728978
Short name T1018
Test name
Test status
Simulation time 257639829 ps
CPU time 0.96 seconds
Started Jul 06 05:23:48 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206120 kb
Host smart-dfa56f59-857e-4ac3-ba2a-6e5a436fa406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10097
28978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1009728978
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1036739499
Short name T1422
Test name
Test status
Simulation time 180014623 ps
CPU time 0.81 seconds
Started Jul 06 05:23:48 PM PDT 24
Finished Jul 06 05:23:49 PM PDT 24
Peak memory 206204 kb
Host smart-b2fd88ea-5cc9-4140-bead-4ba2cd5992d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10367
39499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1036739499
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.967534540
Short name T1753
Test name
Test status
Simulation time 23306494701 ps
CPU time 23.59 seconds
Started Jul 06 05:23:48 PM PDT 24
Finished Jul 06 05:24:12 PM PDT 24
Peak memory 206224 kb
Host smart-dee665e1-4ce3-49fe-8a31-63a4ca8de6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96753
4540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.967534540
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3051688764
Short name T2578
Test name
Test status
Simulation time 3322708829 ps
CPU time 3.87 seconds
Started Jul 06 05:23:48 PM PDT 24
Finished Jul 06 05:23:52 PM PDT 24
Peak memory 206264 kb
Host smart-9eb70562-54b0-49e5-b9b6-c723ab828bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30516
88764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3051688764
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.4040844794
Short name T1424
Test name
Test status
Simulation time 6699681810 ps
CPU time 185.05 seconds
Started Jul 06 05:23:47 PM PDT 24
Finished Jul 06 05:26:52 PM PDT 24
Peak memory 206512 kb
Host smart-b1cc6718-0465-4dea-a2a2-d5e6a2e15d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40408
44794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.4040844794
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.3615896208
Short name T654
Test name
Test status
Simulation time 5582038516 ps
CPU time 51.58 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:24:41 PM PDT 24
Peak memory 206424 kb
Host smart-f1c3c2a3-0842-4348-a909-145ddbb4a5e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3615896208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.3615896208
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2389193237
Short name T688
Test name
Test status
Simulation time 233205571 ps
CPU time 1 seconds
Started Jul 06 05:23:51 PM PDT 24
Finished Jul 06 05:23:52 PM PDT 24
Peak memory 206204 kb
Host smart-fd887048-182e-41be-8b13-f5b5de9fa4df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2389193237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2389193237
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3954923425
Short name T2526
Test name
Test status
Simulation time 188710133 ps
CPU time 0.86 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206160 kb
Host smart-264feb99-e8b0-490b-a2eb-d5960c7ae845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39549
23425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3954923425
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2450281939
Short name T743
Test name
Test status
Simulation time 5352387109 ps
CPU time 149.08 seconds
Started Jul 06 05:23:48 PM PDT 24
Finished Jul 06 05:26:18 PM PDT 24
Peak memory 206492 kb
Host smart-d93c4b29-6c9b-480a-92e5-1ba9ba0d3e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24502
81939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2450281939
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2338418577
Short name T617
Test name
Test status
Simulation time 5859504171 ps
CPU time 43.31 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 206428 kb
Host smart-2209e48f-91d1-4851-be02-ad664bf4c812
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2338418577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2338418577
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2735717514
Short name T2418
Test name
Test status
Simulation time 162098267 ps
CPU time 0.86 seconds
Started Jul 06 05:23:47 PM PDT 24
Finished Jul 06 05:23:48 PM PDT 24
Peak memory 206208 kb
Host smart-3a09f78e-94f0-4ebd-bb7f-3c3b8c486b19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2735717514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2735717514
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.953329507
Short name T1209
Test name
Test status
Simulation time 149120551 ps
CPU time 0.8 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206172 kb
Host smart-b37a1885-7196-4317-9716-14275430299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95332
9507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.953329507
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3960522722
Short name T133
Test name
Test status
Simulation time 206015548 ps
CPU time 0.82 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206168 kb
Host smart-78a99502-cfa2-4825-9e3f-13da6fbf0eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
22722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3960522722
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4084561918
Short name T748
Test name
Test status
Simulation time 184494232 ps
CPU time 0.85 seconds
Started Jul 06 05:23:46 PM PDT 24
Finished Jul 06 05:23:48 PM PDT 24
Peak memory 206172 kb
Host smart-606a697e-079d-4a5f-b47b-b1641c2e2523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40845
61918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4084561918
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3385734352
Short name T329
Test name
Test status
Simulation time 176292884 ps
CPU time 0.78 seconds
Started Jul 06 05:23:47 PM PDT 24
Finished Jul 06 05:23:49 PM PDT 24
Peak memory 206200 kb
Host smart-0da5f278-2184-4f16-b131-441b4384ca6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
34352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3385734352
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1500577643
Short name T2052
Test name
Test status
Simulation time 149984051 ps
CPU time 0.89 seconds
Started Jul 06 05:23:50 PM PDT 24
Finished Jul 06 05:23:51 PM PDT 24
Peak memory 206200 kb
Host smart-8098c0f0-4286-436f-b042-d0c866ffb780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15005
77643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1500577643
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.936788876
Short name T767
Test name
Test status
Simulation time 164805823 ps
CPU time 0.79 seconds
Started Jul 06 05:23:47 PM PDT 24
Finished Jul 06 05:23:48 PM PDT 24
Peak memory 206164 kb
Host smart-7041924a-c2a0-42d5-9ea9-6f7bf26386aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93678
8876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.936788876
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2724325596
Short name T1025
Test name
Test status
Simulation time 233228384 ps
CPU time 0.99 seconds
Started Jul 06 05:23:49 PM PDT 24
Finished Jul 06 05:23:50 PM PDT 24
Peak memory 206196 kb
Host smart-3680021b-a515-4d9d-8fe3-e6f42e8964eb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2724325596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2724325596
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.888985628
Short name T2182
Test name
Test status
Simulation time 142039723 ps
CPU time 0.74 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:23:54 PM PDT 24
Peak memory 206108 kb
Host smart-bed25aea-8874-4360-9064-63645b79c21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88898
5628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.888985628
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3391758714
Short name T1696
Test name
Test status
Simulation time 38421572 ps
CPU time 0.64 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:23:54 PM PDT 24
Peak memory 206200 kb
Host smart-4926c5c8-f8b3-4563-a347-5bdcc5e1dddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33917
58714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3391758714
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.480110701
Short name T1823
Test name
Test status
Simulation time 16430620667 ps
CPU time 36.72 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:24:31 PM PDT 24
Peak memory 206552 kb
Host smart-599cf7f7-e300-4f79-857f-8a0d82f07e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48011
0701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.480110701
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1090489006
Short name T46
Test name
Test status
Simulation time 167185075 ps
CPU time 0.9 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:23:55 PM PDT 24
Peak memory 206200 kb
Host smart-6996d70d-a56d-41db-8635-095455c5da1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
89006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1090489006
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.796086310
Short name T1192
Test name
Test status
Simulation time 201591829 ps
CPU time 0.85 seconds
Started Jul 06 05:23:56 PM PDT 24
Finished Jul 06 05:23:58 PM PDT 24
Peak memory 206100 kb
Host smart-a31b059a-313e-4d32-bb3b-408516ef25c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79608
6310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.796086310
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1280488504
Short name T2361
Test name
Test status
Simulation time 6055984293 ps
CPU time 36.8 seconds
Started Jul 06 05:24:00 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206500 kb
Host smart-1944661e-937d-4649-9923-50c5d83c8c00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1280488504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1280488504
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.4102548520
Short name T995
Test name
Test status
Simulation time 13613215673 ps
CPU time 97.26 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:25:30 PM PDT 24
Peak memory 206380 kb
Host smart-d4635166-5c57-4dce-a406-353056d72681
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4102548520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.4102548520
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3077455657
Short name T2343
Test name
Test status
Simulation time 12991659530 ps
CPU time 253.45 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:28:07 PM PDT 24
Peak memory 206516 kb
Host smart-919df20c-e615-4a7f-a6c6-b2c484725fe0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3077455657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3077455657
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2551457527
Short name T2591
Test name
Test status
Simulation time 237143490 ps
CPU time 0.96 seconds
Started Jul 06 05:23:55 PM PDT 24
Finished Jul 06 05:23:56 PM PDT 24
Peak memory 206156 kb
Host smart-81e73ccf-96e3-4d9b-aa98-953e4a9bd85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514
57527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2551457527
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1330217141
Short name T2292
Test name
Test status
Simulation time 159032625 ps
CPU time 0.79 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206188 kb
Host smart-b5caad7c-9c1c-421e-bfe5-0e8c7e30f4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13302
17141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1330217141
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1378157304
Short name T389
Test name
Test status
Simulation time 172305638 ps
CPU time 0.85 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:23:55 PM PDT 24
Peak memory 206172 kb
Host smart-44065608-643a-441d-b4e6-8df85fbb9549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13781
57304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1378157304
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3938001967
Short name T1560
Test name
Test status
Simulation time 165533938 ps
CPU time 0.78 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:23:55 PM PDT 24
Peak memory 206192 kb
Host smart-65b8b98d-b7a0-4b91-bf95-69b3031ff818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
01967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3938001967
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2655114437
Short name T1366
Test name
Test status
Simulation time 151595518 ps
CPU time 0.76 seconds
Started Jul 06 05:23:55 PM PDT 24
Finished Jul 06 05:23:56 PM PDT 24
Peak memory 206164 kb
Host smart-43ea6329-2b19-43da-b6d0-b6e3582a0614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551
14437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2655114437
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2038261751
Short name T1311
Test name
Test status
Simulation time 234598716 ps
CPU time 0.91 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206188 kb
Host smart-ec18b922-5f74-4745-988c-3957ddcb215f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20382
61751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2038261751
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3432029157
Short name T2281
Test name
Test status
Simulation time 5980773401 ps
CPU time 55.56 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:24:50 PM PDT 24
Peak memory 206520 kb
Host smart-2e62b44c-6e45-4d86-9391-4de783f2c571
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3432029157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3432029157
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2168277798
Short name T1172
Test name
Test status
Simulation time 269094549 ps
CPU time 0.94 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:23:54 PM PDT 24
Peak memory 206168 kb
Host smart-2267f5f9-dce7-4680-bfd3-ffb9e1afe474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21682
77798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2168277798
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2145616678
Short name T2533
Test name
Test status
Simulation time 158227945 ps
CPU time 0.84 seconds
Started Jul 06 05:23:55 PM PDT 24
Finished Jul 06 05:23:56 PM PDT 24
Peak memory 206104 kb
Host smart-420dfa25-2d14-41a9-9e8b-5c92efcd9d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21456
16678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2145616678
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3872113021
Short name T1758
Test name
Test status
Simulation time 575394604 ps
CPU time 1.68 seconds
Started Jul 06 05:23:52 PM PDT 24
Finished Jul 06 05:23:54 PM PDT 24
Peak memory 206152 kb
Host smart-20054259-a02b-44a4-9045-7d1d479755c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38721
13021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3872113021
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.816632500
Short name T1205
Test name
Test status
Simulation time 3183609830 ps
CPU time 23.15 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:24:18 PM PDT 24
Peak memory 206464 kb
Host smart-bb0ce678-9e20-406b-851c-01708a6eb02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81663
2500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.816632500
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1236978502
Short name T1079
Test name
Test status
Simulation time 56514390 ps
CPU time 0.71 seconds
Started Jul 06 05:24:03 PM PDT 24
Finished Jul 06 05:24:05 PM PDT 24
Peak memory 206252 kb
Host smart-449e6e55-3680-4aea-ba91-f1c0b9b659bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1236978502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1236978502
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2368478313
Short name T1483
Test name
Test status
Simulation time 3510254173 ps
CPU time 4.48 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206204 kb
Host smart-10cc513a-1936-4166-b9d3-86464d8306a8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2368478313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2368478313
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1292599329
Short name T1098
Test name
Test status
Simulation time 13499935049 ps
CPU time 13.18 seconds
Started Jul 06 05:23:54 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 206432 kb
Host smart-de209076-a0de-4d01-b13f-25799734e6cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1292599329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1292599329
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.4062792878
Short name T969
Test name
Test status
Simulation time 23303485281 ps
CPU time 22.07 seconds
Started Jul 06 05:23:53 PM PDT 24
Finished Jul 06 05:24:15 PM PDT 24
Peak memory 206460 kb
Host smart-dcb0f47e-f508-4190-a63e-3db744f91e45
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4062792878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.4062792878
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2072058544
Short name T1539
Test name
Test status
Simulation time 186694714 ps
CPU time 0.83 seconds
Started Jul 06 05:23:52 PM PDT 24
Finished Jul 06 05:23:53 PM PDT 24
Peak memory 206144 kb
Host smart-369a365b-2ac4-4ec2-b476-c582dbbff3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
58544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2072058544
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1778518334
Short name T1164
Test name
Test status
Simulation time 142490369 ps
CPU time 0.8 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206200 kb
Host smart-703c8ba2-941e-4454-bea1-191e2fb94e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
18334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1778518334
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.322569936
Short name T1302
Test name
Test status
Simulation time 904673108 ps
CPU time 2.24 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206320 kb
Host smart-99c644f4-8cad-4c75-8421-bfadc33ef29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32256
9936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.322569936
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.456541279
Short name T802
Test name
Test status
Simulation time 10087829389 ps
CPU time 20.48 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:22 PM PDT 24
Peak memory 206424 kb
Host smart-df909ca3-4a82-4825-b38e-8a11986fff17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45654
1279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.456541279
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3963157352
Short name T38
Test name
Test status
Simulation time 344587984 ps
CPU time 1.22 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206176 kb
Host smart-f0a92b3d-7656-42b6-8268-c46f2d42f57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39631
57352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3963157352
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3480013809
Short name T2306
Test name
Test status
Simulation time 144652244 ps
CPU time 0.79 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206164 kb
Host smart-7e92e0fd-bf5d-4c18-bf07-51e4b0ef3395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34800
13809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3480013809
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1019068322
Short name T691
Test name
Test status
Simulation time 41905565 ps
CPU time 0.65 seconds
Started Jul 06 05:23:58 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206164 kb
Host smart-ccbe5597-38dd-481c-9389-cece0e095415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10190
68322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1019068322
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.590208481
Short name T2042
Test name
Test status
Simulation time 973514391 ps
CPU time 2.16 seconds
Started Jul 06 05:23:58 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206292 kb
Host smart-6eebdc35-5b5a-4c21-afdd-4f3ec1278485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59020
8481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.590208481
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4288813453
Short name T658
Test name
Test status
Simulation time 234937371 ps
CPU time 1.99 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:04 PM PDT 24
Peak memory 206356 kb
Host smart-c9ad4d8f-ba15-4016-81ab-9e435a10a2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42888
13453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4288813453
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.991283006
Short name T2021
Test name
Test status
Simulation time 190360728 ps
CPU time 0.84 seconds
Started Jul 06 05:23:58 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206156 kb
Host smart-feec02ff-57a0-4860-ba88-3a3299651cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99128
3006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.991283006
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3276016315
Short name T1695
Test name
Test status
Simulation time 145512574 ps
CPU time 0.81 seconds
Started Jul 06 05:23:58 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206196 kb
Host smart-3817e357-2f9f-497a-af5c-72b743f56258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
16315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3276016315
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1413439050
Short name T880
Test name
Test status
Simulation time 179592701 ps
CPU time 0.88 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206176 kb
Host smart-338dcab2-839d-4811-b61d-69b3600b93f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14134
39050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1413439050
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.2986708195
Short name T2638
Test name
Test status
Simulation time 7770211351 ps
CPU time 52.82 seconds
Started Jul 06 05:23:57 PM PDT 24
Finished Jul 06 05:24:50 PM PDT 24
Peak memory 206444 kb
Host smart-def1b9bc-1ca7-48f7-b83d-09bf467f9a84
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2986708195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.2986708195
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3053973314
Short name T2509
Test name
Test status
Simulation time 210593365 ps
CPU time 0.91 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206196 kb
Host smart-6173e092-9d6f-4650-a549-24c15a9d6a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30539
73314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3053973314
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.2037328729
Short name T636
Test name
Test status
Simulation time 23324171973 ps
CPU time 22.94 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:25 PM PDT 24
Peak memory 206256 kb
Host smart-e6caf97e-3314-4ac0-90d0-446a1a9710a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
28729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.2037328729
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1779601678
Short name T2384
Test name
Test status
Simulation time 3316245778 ps
CPU time 4.35 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 206180 kb
Host smart-698909e9-7882-4e53-b585-4bdf3dfbc5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
01678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1779601678
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3702220076
Short name T976
Test name
Test status
Simulation time 7215808938 ps
CPU time 48.36 seconds
Started Jul 06 05:24:03 PM PDT 24
Finished Jul 06 05:24:51 PM PDT 24
Peak memory 206436 kb
Host smart-7a70d266-0ea4-487c-bedb-cbcdededa1d7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3702220076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3702220076
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3074372528
Short name T689
Test name
Test status
Simulation time 244559524 ps
CPU time 0.93 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206204 kb
Host smart-43d494b2-9ab0-4aec-886a-135738dd1464
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3074372528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3074372528
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.49598838
Short name T822
Test name
Test status
Simulation time 189200284 ps
CPU time 0.94 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206200 kb
Host smart-b127e6ae-7999-4f07-8bb6-c01b2fecdb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49598
838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.49598838
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3000864451
Short name T794
Test name
Test status
Simulation time 5990225317 ps
CPU time 40.99 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:44 PM PDT 24
Peak memory 206444 kb
Host smart-acbacdb3-a516-4476-9b1e-df9d93e11436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
64451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3000864451
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3240215250
Short name T2044
Test name
Test status
Simulation time 3069272515 ps
CPU time 28.04 seconds
Started Jul 06 05:24:00 PM PDT 24
Finished Jul 06 05:24:29 PM PDT 24
Peak memory 206468 kb
Host smart-dad8aa65-013f-4447-a8a7-4572dc8433ad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3240215250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3240215250
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3224818871
Short name T1385
Test name
Test status
Simulation time 151075810 ps
CPU time 0.79 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206196 kb
Host smart-c643d103-a0b9-4717-bf81-6201cf513b11
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3224818871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3224818871
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2949507617
Short name T320
Test name
Test status
Simulation time 142123540 ps
CPU time 0.82 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206176 kb
Host smart-992c74f5-3298-4093-ba10-2adf39658920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29495
07617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2949507617
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2944348217
Short name T2435
Test name
Test status
Simulation time 209094413 ps
CPU time 0.97 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206200 kb
Host smart-1d7ddaea-934d-46c2-9d3e-a9adf3cf6dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
48217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2944348217
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3348495178
Short name T2413
Test name
Test status
Simulation time 201811136 ps
CPU time 0.86 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206108 kb
Host smart-c807e075-1ada-4e05-9ce7-0f532825e63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33484
95178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3348495178
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.951191964
Short name T941
Test name
Test status
Simulation time 157059502 ps
CPU time 0.83 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 206200 kb
Host smart-1f229849-2245-4ee9-8639-93a13f21b0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95119
1964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.951191964
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1587063996
Short name T1191
Test name
Test status
Simulation time 177843129 ps
CPU time 0.79 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:02 PM PDT 24
Peak memory 206164 kb
Host smart-0836bbb5-a689-4da3-8f93-d8eead584c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
63996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1587063996
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.939524397
Short name T2180
Test name
Test status
Simulation time 186249035 ps
CPU time 0.84 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:02 PM PDT 24
Peak memory 206116 kb
Host smart-e55b32c6-815c-4e91-b2d4-a2578a11304f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93952
4397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.939524397
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2181620660
Short name T2520
Test name
Test status
Simulation time 247448954 ps
CPU time 1.09 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206088 kb
Host smart-c7fefb8c-6fd4-401e-99b6-22e34caeaabb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2181620660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2181620660
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3372078024
Short name T1418
Test name
Test status
Simulation time 143807262 ps
CPU time 0.76 seconds
Started Jul 06 05:24:00 PM PDT 24
Finished Jul 06 05:24:01 PM PDT 24
Peak memory 206220 kb
Host smart-82064394-262a-43ee-96b7-bceb59147a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33720
78024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3372078024
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1867257935
Short name T2458
Test name
Test status
Simulation time 66544809 ps
CPU time 0.72 seconds
Started Jul 06 05:23:58 PM PDT 24
Finished Jul 06 05:23:59 PM PDT 24
Peak memory 206196 kb
Host smart-a4f76d91-e9c2-4d13-a56e-1509f247776c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
57935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1867257935
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.753922791
Short name T1990
Test name
Test status
Simulation time 18615285899 ps
CPU time 40.54 seconds
Started Jul 06 05:23:59 PM PDT 24
Finished Jul 06 05:24:40 PM PDT 24
Peak memory 206532 kb
Host smart-76f2b3c9-78ab-4212-ad93-eac3b9c0444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75392
2791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.753922791
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2478768377
Short name T2020
Test name
Test status
Simulation time 166351996 ps
CPU time 0.82 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206220 kb
Host smart-9a183945-6210-457d-8bf7-86bbad36f4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24787
68377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2478768377
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1882812892
Short name T1024
Test name
Test status
Simulation time 220984076 ps
CPU time 1.01 seconds
Started Jul 06 05:24:01 PM PDT 24
Finished Jul 06 05:24:02 PM PDT 24
Peak memory 206188 kb
Host smart-8f0f2386-6d60-4579-9b01-855095a28229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18828
12892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1882812892
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2858824268
Short name T2397
Test name
Test status
Simulation time 7544184940 ps
CPU time 68.98 seconds
Started Jul 06 05:24:04 PM PDT 24
Finished Jul 06 05:25:13 PM PDT 24
Peak memory 206524 kb
Host smart-6d52c33d-342b-44ac-8185-fdfd62557ecc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2858824268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2858824268
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3718843731
Short name T574
Test name
Test status
Simulation time 11593827717 ps
CPU time 221.17 seconds
Started Jul 06 05:24:03 PM PDT 24
Finished Jul 06 05:27:44 PM PDT 24
Peak memory 206512 kb
Host smart-97bc0ff7-9481-49ac-b36f-63bc9395228b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3718843731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3718843731
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1436005203
Short name T494
Test name
Test status
Simulation time 13034929346 ps
CPU time 68.51 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:25:20 PM PDT 24
Peak memory 206424 kb
Host smart-85383370-1cd3-46aa-ba66-8728192cc9bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1436005203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1436005203
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.4045637272
Short name T407
Test name
Test status
Simulation time 158463109 ps
CPU time 0.82 seconds
Started Jul 06 05:24:00 PM PDT 24
Finished Jul 06 05:24:02 PM PDT 24
Peak memory 206188 kb
Host smart-9913a424-c415-4002-a545-445ba273bd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
37272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.4045637272
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2426616757
Short name T731
Test name
Test status
Simulation time 167203756 ps
CPU time 0.79 seconds
Started Jul 06 05:24:06 PM PDT 24
Finished Jul 06 05:24:07 PM PDT 24
Peak memory 205980 kb
Host smart-ac878e38-7d24-45b7-8124-827c518d25e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
16757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2426616757
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2179452612
Short name T2621
Test name
Test status
Simulation time 158590914 ps
CPU time 0.79 seconds
Started Jul 06 05:24:03 PM PDT 24
Finished Jul 06 05:24:04 PM PDT 24
Peak memory 206200 kb
Host smart-adb48e22-8ae1-466c-b8ef-80feff144fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
52612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2179452612
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1642612416
Short name T1071
Test name
Test status
Simulation time 167709696 ps
CPU time 0.78 seconds
Started Jul 06 05:24:04 PM PDT 24
Finished Jul 06 05:24:05 PM PDT 24
Peak memory 206172 kb
Host smart-e419440b-e716-47df-ad1c-9fed3f2f31c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
12416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1642612416
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2144377547
Short name T847
Test name
Test status
Simulation time 148138010 ps
CPU time 0.79 seconds
Started Jul 06 05:24:04 PM PDT 24
Finished Jul 06 05:24:05 PM PDT 24
Peak memory 206164 kb
Host smart-bcbc2d93-f25f-4e29-9b67-2f3cc7965c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21443
77547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2144377547
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3538991405
Short name T2410
Test name
Test status
Simulation time 232759922 ps
CPU time 0.94 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:04 PM PDT 24
Peak memory 206192 kb
Host smart-272f4a17-9dd9-4e14-a843-786b96e6e35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35389
91405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3538991405
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.911871028
Short name T724
Test name
Test status
Simulation time 4359539391 ps
CPU time 122.95 seconds
Started Jul 06 05:24:05 PM PDT 24
Finished Jul 06 05:26:08 PM PDT 24
Peak memory 206516 kb
Host smart-ce814e44-7754-4af2-98c4-692c271fcbce
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=911871028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.911871028
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2253207076
Short name T878
Test name
Test status
Simulation time 174253321 ps
CPU time 0.84 seconds
Started Jul 06 05:24:04 PM PDT 24
Finished Jul 06 05:24:05 PM PDT 24
Peak memory 206168 kb
Host smart-784fee68-2aba-4c43-bef9-cc24ff88a0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
07076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2253207076
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1182738725
Short name T2637
Test name
Test status
Simulation time 188695853 ps
CPU time 0.88 seconds
Started Jul 06 05:24:02 PM PDT 24
Finished Jul 06 05:24:03 PM PDT 24
Peak memory 206188 kb
Host smart-817bd6c2-ad60-42c2-bfde-603b4aaa032d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11827
38725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1182738725
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.424744242
Short name T1219
Test name
Test status
Simulation time 825525610 ps
CPU time 1.92 seconds
Started Jul 06 05:24:12 PM PDT 24
Finished Jul 06 05:24:14 PM PDT 24
Peak memory 206424 kb
Host smart-e06c1641-2770-4b8a-a534-55a508ac8017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
4242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.424744242
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2624017519
Short name T2463
Test name
Test status
Simulation time 4630135256 ps
CPU time 32.02 seconds
Started Jul 06 05:24:05 PM PDT 24
Finished Jul 06 05:24:37 PM PDT 24
Peak memory 206484 kb
Host smart-996739dc-0c63-4a2b-94c7-4181f65e7040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26240
17519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2624017519
Directory /workspace/9.usbdev_streaming_out/latest
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