Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	85172	1		T1	3		T2	3		T3	3
all_values[1]	85172	1		T1	3		T2	3		T3	3
all_values[2]	85172	1		T1	3		T2	3		T3	3
all_values[3]	85172	1		T1	3		T2	3		T3	3
all_values[4]	85172	1		T1	3		T2	3		T3	3
all_values[5]	85172	1		T1	3		T2	3		T3	3
all_values[6]	85172	1		T1	3		T2	3		T3	3
all_values[7]	85172	1		T1	3		T2	3		T3	3
all_values[8]	85172	1		T1	3		T2	3		T3	3
all_values[9]	85172	1		T1	3		T2	3		T3	3
all_values[10]	85172	1		T1	3		T2	3		T3	3
all_values[11]	85172	1		T1	3		T2	3		T3	3
all_values[12]	85172	1		T1	3		T2	3		T3	3
all_values[13]	85172	1		T1	3		T2	3		T3	3
all_values[14]	85172	1		T1	3		T2	3		T3	3
all_values[15]	85172	1		T1	3		T2	3		T3	3
all_values[16]	85172	1		T1	3		T2	3		T3	3
all_values[17]	85172	1		T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1526382	1		T1	54		T2	54		T3	54
auto[1]	6714	1		T27	4		T30	3		T7	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1528182	1		T1	54		T2	54		T3	54
auto[1]	4914	1		T234	66		T230	128		T231	79

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84202	1		T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	155	1		T230	6		T231	1		T233	5
all_values[0]	auto[1]	auto[0]	691	1		T27	4		T30	3		T20	3
all_values[0]	auto[1]	auto[1]	124	1		T230	2		T231	4		T233	1
all_values[1]	auto[0]	auto[0]	83360	1		T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	148	1		T234	1		T230	7		T231	3
all_values[1]	auto[1]	auto[0]	1513	1		T7	2		T8	2		T47	3
all_values[1]	auto[1]	auto[1]	151	1		T234	3		T230	1		T233	6
all_values[2]	auto[0]	auto[0]	84773	1		T1	3		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	163	1		T234	3		T230	3		T231	4
all_values[2]	auto[1]	auto[0]	122	1		T37	2		T41	2		T42	2
all_values[2]	auto[1]	auto[1]	114	1		T230	3		T231	1		T233	3
all_values[3]	auto[0]	auto[0]	83483	1		T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	129	1		T230	4		T233	6		T322	3
all_values[3]	auto[1]	auto[0]	1429	1		T65	1395		T234	3		T230	2
all_values[3]	auto[1]	auto[1]	131	1		T230	2		T231	5		T233	2
all_values[4]	auto[0]	auto[0]	84870	1		T1	3		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	144	1		T234	4		T230	2		T231	5
all_values[4]	auto[1]	auto[0]	25	1		T66	2		T233	2		T323	1
all_values[4]	auto[1]	auto[1]	133	1		T230	6		T233	4		T322	1
all_values[5]	auto[0]	auto[0]	84887	1		T1	3		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	147	1		T234	5		T230	4		T231	2
all_values[5]	auto[1]	auto[0]	27	1		T233	1		T323	1		T324	1
all_values[5]	auto[1]	auto[1]	111	1		T230	4		T231	3		T233	3
all_values[6]	auto[0]	auto[0]	84870	1		T1	3		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	146	1		T234	4		T230	2		T233	5
all_values[6]	auto[1]	auto[0]	22	1		T316	2		T323	1		T318	2
all_values[6]	auto[1]	auto[1]	134	1		T234	1		T230	6		T231	4
all_values[7]	auto[0]	auto[0]	84863	1		T1	3		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	164	1		T234	2		T230	4		T231	2
all_values[7]	auto[1]	auto[0]	23	1		T48	2		T49	2		T233	1
all_values[7]	auto[1]	auto[1]	122	1		T234	3		T230	4		T231	3
all_values[8]	auto[0]	auto[0]	84875	1		T1	3		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	134	1		T230	1		T231	3		T233	6
all_values[8]	auto[1]	auto[0]	44	1		T51	11		T230	1		T322	1
all_values[8]	auto[1]	auto[1]	119	1		T234	5		T230	6		T231	2
all_values[9]	auto[0]	auto[0]	84843	1		T1	3		T2	3		T3	3
all_values[9]	auto[0]	auto[1]	123	1		T234	1		T230	2		T231	2
all_values[9]	auto[1]	auto[0]	52	1		T61	5		T62	5		T63	5
all_values[9]	auto[1]	auto[1]	154	1		T234	3		T230	5		T231	3
all_values[10]	auto[0]	auto[0]	84868	1		T1	3		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	162	1		T234	2		T230	3		T233	6
all_values[10]	auto[1]	auto[0]	17	1		T324	1		T318	1		T319	1
all_values[10]	auto[1]	auto[1]	125	1		T234	3		T230	4		T231	5
all_values[11]	auto[0]	auto[0]	84771	1		T1	3		T2	3		T3	3
all_values[11]	auto[0]	auto[1]	128	1		T230	5		T231	1		T233	4
all_values[11]	auto[1]	auto[0]	128	1		T46	2		T72	2		T73	2
all_values[11]	auto[1]	auto[1]	145	1		T234	5		T230	3		T231	3
all_values[12]	auto[0]	auto[0]	84860	1		T1	3		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	134	1		T234	5		T230	4		T231	1
all_values[12]	auto[1]	auto[0]	38	1		T75	3		T76	3		T77	3
all_values[12]	auto[1]	auto[1]	140	1		T230	4		T231	4		T322	3
all_values[13]	auto[0]	auto[0]	84877	1		T1	3		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	112	1		T234	1		T230	3		T231	3
all_values[13]	auto[1]	auto[0]	38	1		T234	1		T230	2		T322	1
all_values[13]	auto[1]	auto[1]	145	1		T234	3		T230	1		T231	1
all_values[14]	auto[0]	auto[0]	84864	1		T1	3		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	140	1		T234	4		T230	1		T231	2
all_values[14]	auto[1]	auto[0]	21	1		T316	1		T324	1		T325	1
all_values[14]	auto[1]	auto[1]	147	1		T234	1		T230	7		T231	3
all_values[15]	auto[0]	auto[0]	84885	1		T1	3		T2	3		T3	3
all_values[15]	auto[0]	auto[1]	126	1		T230	3		T233	7		T323	4
all_values[15]	auto[1]	auto[0]	31	1		T234	2		T231	1		T233	1
all_values[15]	auto[1]	auto[1]	130	1		T230	5		T231	4		T232	3
all_values[16]	auto[0]	auto[0]	84852	1		T1	3		T2	3		T3	3
all_values[16]	auto[0]	auto[1]	120	1		T234	4		T231	1		T233	2
all_values[16]	auto[1]	auto[0]	59	1		T69	8		T70	8		T71	8
all_values[16]	auto[1]	auto[1]	141	1		T230	4		T231	4		T233	4
all_values[17]	auto[0]	auto[0]	84874	1		T1	3		T2	3		T3	3
all_values[17]	auto[0]	auto[1]	130	1		T230	6		T233	6		T322	2
all_values[17]	auto[1]	auto[0]	25	1		T54	2		T55	2		T56	2
all_values[17]	auto[1]	auto[1]	143	1		T234	3		T230	1		T233	2