Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	85172	1		T1	3		T2	3		T3	3
all_pins[1]	85172	1		T1	3		T2	3		T3	3
all_pins[2]	85172	1		T1	3		T2	3		T3	3
all_pins[3]	85172	1		T1	3		T2	3		T3	3
all_pins[4]	85172	1		T1	3		T2	3		T3	3
all_pins[5]	85172	1		T1	3		T2	3		T3	3
all_pins[6]	85172	1		T1	3		T2	3		T3	3
all_pins[7]	85172	1		T1	3		T2	3		T3	3
all_pins[8]	85172	1		T1	3		T2	3		T3	3
all_pins[9]	85172	1		T1	3		T2	3		T3	3
all_pins[10]	85172	1		T1	3		T2	3		T3	3
all_pins[11]	85172	1		T1	3		T2	3		T3	3
all_pins[12]	85172	1		T1	3		T2	3		T3	3
all_pins[13]	85172	1		T1	3		T2	3		T3	3
all_pins[14]	85172	1		T1	3		T2	3		T3	3
all_pins[15]	85172	1		T1	3		T2	3		T3	3
all_pins[16]	85172	1		T1	3		T2	3		T3	3
all_pins[17]	85172	1		T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1530845	1		T1	54		T2	54		T3	54
values[0x1]	2251	1		T27	1		T7	1		T8	1
transitions[0x0=>0x1]	1983	1		T27	1		T7	1		T8	1
transitions[0x1=>0x0]	1999	1		T27	1		T7	1		T8	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85060	1		T1	3		T2	3		T3	3
all_pins[0]	values[0x1]	112	1		T27	1		T81	1		T326	1
all_pins[0]	transitions[0x0=>0x1]	104	1		T27	1		T81	1		T326	1
all_pins[0]	transitions[0x1=>0x0]	1003	1		T7	1		T8	1		T47	1
all_pins[1]	values[0x0]	84161	1		T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	1011	1		T7	1		T8	1		T47	1
all_pins[1]	transitions[0x0=>0x1]	993	1		T7	1		T8	1		T47	1
all_pins[1]	transitions[0x1=>0x0]	99	1		T37	1		T41	1		T42	1
all_pins[2]	values[0x0]	85055	1		T1	3		T2	3		T3	3
all_pins[2]	values[0x1]	117	1		T37	1		T41	1		T42	1
all_pins[2]	transitions[0x0=>0x1]	96	1		T37	1		T41	1		T42	1
all_pins[2]	transitions[0x1=>0x0]	37	1		T65	1		T231	1		T233	1
all_pins[3]	values[0x0]	85114	1		T1	3		T2	3		T3	3
all_pins[3]	values[0x1]	58	1		T65	1		T231	1		T233	1
all_pins[3]	transitions[0x0=>0x1]	39	1		T65	1		T231	1		T327	1
all_pins[3]	transitions[0x1=>0x0]	44	1		T66	1		T233	2		T322	1
all_pins[4]	values[0x0]	85109	1		T1	3		T2	3		T3	3
all_pins[4]	values[0x1]	63	1		T66	1		T233	3		T322	1
all_pins[4]	transitions[0x0=>0x1]	49	1		T66	1		T233	2		T322	1
all_pins[4]	transitions[0x1=>0x0]	42	1		T231	2		T233	1		T327	2
all_pins[5]	values[0x0]	85116	1		T1	3		T2	3		T3	3
all_pins[5]	values[0x1]	56	1		T231	2		T233	2		T327	2
all_pins[5]	transitions[0x0=>0x1]	44	1		T233	1		T327	2		T316	4
all_pins[5]	transitions[0x1=>0x0]	45	1		T234	1		T230	2		T231	1
all_pins[6]	values[0x0]	85115	1		T1	3		T2	3		T3	3
all_pins[6]	values[0x1]	57	1		T234	1		T230	2		T231	3
all_pins[6]	transitions[0x0=>0x1]	48	1		T234	1		T230	2		T231	2
all_pins[6]	transitions[0x1=>0x0]	45	1		T48	1		T49	1		T233	2
all_pins[7]	values[0x0]	85118	1		T1	3		T2	3		T3	3
all_pins[7]	values[0x1]	54	1		T48	1		T49	1		T231	1
all_pins[7]	transitions[0x0=>0x1]	40	1		T48	1		T49	1		T231	1
all_pins[7]	transitions[0x1=>0x0]	38	1		T51	1		T234	1		T230	3
all_pins[8]	values[0x0]	85120	1		T1	3		T2	3		T3	3
all_pins[8]	values[0x1]	52	1		T51	1		T234	1		T230	3
all_pins[8]	transitions[0x0=>0x1]	41	1		T51	1		T234	1		T230	1
all_pins[8]	transitions[0x1=>0x0]	84	1		T61	2		T62	2		T63	2
all_pins[9]	values[0x0]	85077	1		T1	3		T2	3		T3	3
all_pins[9]	values[0x1]	95	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	79	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	37	1		T231	1		T233	1		T323	1
all_pins[10]	values[0x0]	85119	1		T1	3		T2	3		T3	3
all_pins[10]	values[0x1]	53	1		T230	3		T231	1		T233	1
all_pins[10]	transitions[0x0=>0x1]	44	1		T230	3		T231	1		T233	1
all_pins[10]	transitions[0x1=>0x0]	111	1		T46	1		T72	1		T73	1
all_pins[11]	values[0x0]	85052	1		T1	3		T2	3		T3	3
all_pins[11]	values[0x1]	120	1		T46	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	107	1		T46	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	55	1		T75	1		T76	1		T77	1
all_pins[12]	values[0x0]	85104	1		T1	3		T2	3		T3	3
all_pins[12]	values[0x1]	68	1		T75	1		T76	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T75	1		T76	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	60	1		T234	2		T233	2		T322	3
all_pins[13]	values[0x0]	85097	1		T1	3		T2	3		T3	3
all_pins[13]	values[0x1]	75	1		T234	2		T231	1		T233	2
all_pins[13]	transitions[0x0=>0x1]	53	1		T234	2		T231	1		T233	2
all_pins[13]	transitions[0x1=>0x0]	48	1		T230	2		T231	2		T233	2
all_pins[14]	values[0x0]	85102	1		T1	3		T2	3		T3	3
all_pins[14]	values[0x1]	70	1		T230	2		T231	2		T233	2
all_pins[14]	transitions[0x0=>0x1]	57	1		T233	2		T327	1		T324	2
all_pins[14]	transitions[0x1=>0x0]	46	1		T230	1		T231	1		T232	2
all_pins[15]	values[0x0]	85113	1		T1	3		T2	3		T3	3
all_pins[15]	values[0x1]	59	1		T230	3		T231	3		T232	2
all_pins[15]	transitions[0x0=>0x1]	42	1		T230	2		T232	2		T327	3
all_pins[15]	transitions[0x1=>0x0]	60	1		T69	4		T70	4		T71	4
all_pins[16]	values[0x0]	85095	1		T1	3		T2	3		T3	3
all_pins[16]	values[0x1]	77	1		T69	4		T70	4		T71	4
all_pins[16]	transitions[0x0=>0x1]	67	1		T69	4		T70	4		T71	4
all_pins[16]	transitions[0x1=>0x0]	44	1		T54	1		T55	1		T56	1
all_pins[17]	values[0x0]	85118	1		T1	3		T2	3		T3	3
all_pins[17]	values[0x1]	54	1		T54	1		T55	1		T56	1
all_pins[17]	transitions[0x0=>0x1]	27	1		T54	1		T55	1		T56	1
all_pins[17]	transitions[0x1=>0x0]	101	1		T27	1		T81	1		T326	1