Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T234	4		T230	7		T231	4
all_values[1]	275	1		T234	4		T230	7		T231	4
all_values[2]	275	1		T234	4		T230	7		T231	4
all_values[3]	275	1		T234	4		T230	7		T231	4
all_values[4]	275	1		T234	4		T230	7		T231	4
all_values[5]	275	1		T234	4		T230	7		T231	4
all_values[6]	275	1		T234	4		T230	7		T231	4
all_values[7]	275	1		T234	4		T230	7		T231	4
all_values[8]	275	1		T234	4		T230	7		T231	4
all_values[9]	275	1		T234	4		T230	7		T231	4
all_values[10]	275	1		T234	4		T230	7		T231	4
all_values[11]	275	1		T234	4		T230	7		T231	4
all_values[12]	275	1		T234	4		T230	7		T231	4
all_values[13]	275	1		T234	4		T230	7		T231	4
all_values[14]	275	1		T234	4		T230	7		T231	4
all_values[15]	275	1		T234	4		T230	7		T231	4
all_values[16]	275	1		T234	4		T230	7		T231	4
all_values[17]	275	1		T234	4		T230	7		T231	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2731	1		T234	53		T230	64		T231	41
auto[1]	2219	1		T234	19		T230	62		T231	31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	878	1		T234	21		T230	16		T231	10
auto[1]	4072	1		T234	51		T230	110		T231	62

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2912	1		T234	48		T230	65		T231	45
auto[1]	2038	1		T234	24		T230	61		T231	27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	32	1		T234	4		T233	2		T318	2
all_values[0]	auto[0]	auto[0]	auto[1]	66	1		T230	2		T233	3		T232	2
all_values[0]	auto[0]	auto[1]	auto[0]	11	1		T232	1		T323	1		T328	1
all_values[0]	auto[0]	auto[1]	auto[1]	42	1		T231	1		T322	2		T327	1
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T230	4		T231	3		T233	1
all_values[0]	auto[1]	auto[1]	auto[1]	61	1		T230	1		T233	1		T322	2
all_values[1]	auto[0]	auto[0]	auto[0]	20	1		T234	1		T231	1		T322	2
all_values[1]	auto[0]	auto[0]	auto[1]	58	1		T234	1		T230	3		T231	1
all_values[1]	auto[0]	auto[1]	auto[0]	6	1		T231	1		T329	1		T330	2
all_values[1]	auto[0]	auto[1]	auto[1]	59	1		T234	1		T233	4		T327	1
all_values[1]	auto[1]	auto[0]	auto[1]	76	1		T234	1		T230	4		T233	1
all_values[1]	auto[1]	auto[1]	auto[1]	56	1		T231	1		T233	1		T327	2
all_values[2]	auto[0]	auto[0]	auto[0]	33	1		T234	1		T230	2		T322	2
all_values[2]	auto[0]	auto[0]	auto[1]	77	1		T234	1		T230	1		T231	3
all_values[2]	auto[0]	auto[1]	auto[0]	13	1		T234	1		T320	1		T331	2
all_values[2]	auto[0]	auto[1]	auto[1]	47	1		T230	2		T233	1		T322	1
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T231	1		T233	2		T232	1
all_values[2]	auto[1]	auto[1]	auto[1]	45	1		T234	1		T230	2		T233	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T234	3		T230	1		T322	1
all_values[3]	auto[0]	auto[0]	auto[1]	53	1		T230	1		T233	2		T322	2
all_values[3]	auto[0]	auto[1]	auto[0]	26	1		T234	1		T230	1		T232	1
all_values[3]	auto[0]	auto[1]	auto[1]	57	1		T230	3		T231	3		T323	1
all_values[3]	auto[1]	auto[0]	auto[1]	54	1		T230	1		T231	1		T233	3
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T233	2		T232	1		T327	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1		T234	1		T233	1		T316	4
all_values[4]	auto[0]	auto[0]	auto[1]	64	1		T234	1		T231	3		T322	2
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T233	2		T323	1		T332	3
all_values[4]	auto[0]	auto[1]	auto[1]	61	1		T230	3		T233	1		T323	1
all_values[4]	auto[1]	auto[0]	auto[1]	66	1		T234	2		T230	2		T231	1
all_values[4]	auto[1]	auto[1]	auto[1]	40	1		T230	2		T233	2		T322	2
all_values[5]	auto[0]	auto[0]	auto[0]	46	1		T233	1		T322	1		T232	1
all_values[5]	auto[0]	auto[0]	auto[1]	62	1		T234	1		T230	1		T233	1
all_values[5]	auto[0]	auto[1]	auto[0]	15	1		T323	1		T320	1		T328	1
all_values[5]	auto[0]	auto[1]	auto[1]	45	1		T230	3		T231	1		T233	1
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T234	3		T230	2		T231	3
all_values[5]	auto[1]	auto[1]	auto[1]	40	1		T230	1		T233	3		T316	2
all_values[6]	auto[0]	auto[0]	auto[0]	25	1		T231	1		T322	1		T316	1
all_values[6]	auto[0]	auto[0]	auto[1]	59	1		T234	1		T230	1		T233	1
all_values[6]	auto[0]	auto[1]	auto[0]	17	1		T316	1		T323	1		T318	2
all_values[6]	auto[0]	auto[1]	auto[1]	58	1		T234	2		T230	2		T231	2
all_values[6]	auto[1]	auto[0]	auto[1]	60	1		T234	1		T230	2		T233	2
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T230	2		T231	1		T233	4
all_values[7]	auto[0]	auto[0]	auto[0]	24	1		T233	2		T322	1		T316	1
all_values[7]	auto[0]	auto[0]	auto[1]	69	1		T234	1		T230	3		T231	1
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T232	1		T333	2		T329	1
all_values[7]	auto[0]	auto[1]	auto[1]	50	1		T234	1		T230	2		T231	1
all_values[7]	auto[1]	auto[0]	auto[1]	70	1		T234	2		T230	1		T231	2
all_values[7]	auto[1]	auto[1]	auto[1]	49	1		T230	1		T233	2		T232	2
all_values[8]	auto[0]	auto[0]	auto[0]	41	1		T230	1		T233	1		T232	2
all_values[8]	auto[0]	auto[0]	auto[1]	50	1		T231	1		T233	3		T322	1
all_values[8]	auto[0]	auto[1]	auto[0]	26	1		T322	1		T318	1		T320	5
all_values[8]	auto[0]	auto[1]	auto[1]	51	1		T234	3		T230	2		T231	1
all_values[8]	auto[1]	auto[0]	auto[1]	68	1		T234	1		T230	1		T231	1
all_values[8]	auto[1]	auto[1]	auto[1]	39	1		T230	3		T231	1		T233	2
all_values[9]	auto[0]	auto[0]	auto[0]	25	1		T234	1		T230	1		T233	2
all_values[9]	auto[0]	auto[0]	auto[1]	48	1		T234	1		T230	1		T231	1
all_values[9]	auto[0]	auto[1]	auto[0]	20	1		T327	2		T331	1		T334	2
all_values[9]	auto[0]	auto[1]	auto[1]	63	1		T234	1		T230	1		T231	1
all_values[9]	auto[1]	auto[0]	auto[1]	63	1		T234	1		T230	2		T231	2
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T230	2		T322	2		T232	1
all_values[10]	auto[0]	auto[0]	auto[0]	27	1		T230	1		T233	1		T316	1
all_values[10]	auto[0]	auto[0]	auto[1]	69	1		T230	1		T233	3		T322	2
all_values[10]	auto[0]	auto[1]	auto[0]	10	1		T319	1		T329	1		T335	1
all_values[10]	auto[0]	auto[1]	auto[1]	56	1		T234	1		T230	1		T231	3
all_values[10]	auto[1]	auto[0]	auto[1]	71	1		T234	3		T230	3		T231	1
all_values[10]	auto[1]	auto[1]	auto[1]	42	1		T230	1		T233	2		T327	1
all_values[11]	auto[0]	auto[0]	auto[0]	27	1		T231	1		T327	1		T316	2
all_values[11]	auto[0]	auto[0]	auto[1]	57	1		T230	1		T231	1		T233	3
all_values[11]	auto[0]	auto[1]	auto[0]	21	1		T232	4		T327	1		T317	2
all_values[11]	auto[0]	auto[1]	auto[1]	57	1		T234	2		T230	1		T231	1
all_values[11]	auto[1]	auto[0]	auto[1]	46	1		T234	1		T230	2		T231	1
all_values[11]	auto[1]	auto[1]	auto[1]	67	1		T234	1		T230	3		T233	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1		T233	3		T327	1		T332	1
all_values[12]	auto[0]	auto[0]	auto[1]	55	1		T234	2		T230	1		T233	1
all_values[12]	auto[0]	auto[1]	auto[0]	18	1		T233	1		T232	1		T325	2
all_values[12]	auto[0]	auto[1]	auto[1]	58	1		T230	2		T231	2		T322	1
all_values[12]	auto[1]	auto[0]	auto[1]	69	1		T234	2		T230	2		T231	1
all_values[12]	auto[1]	auto[1]	auto[1]	44	1		T230	2		T231	1		T322	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1		T234	1		T230	2		T231	1
all_values[13]	auto[0]	auto[0]	auto[1]	45	1		T234	1		T230	1		T231	1
all_values[13]	auto[0]	auto[1]	auto[0]	27	1		T230	2		T322	1		T232	4
all_values[13]	auto[0]	auto[1]	auto[1]	60	1		T234	1		T231	1		T322	1
all_values[13]	auto[1]	auto[0]	auto[1]	50	1		T234	1		T233	3		T327	1
all_values[13]	auto[1]	auto[1]	auto[1]	57	1		T230	2		T231	1		T233	3
all_values[14]	auto[0]	auto[0]	auto[0]	23	1		T233	1		T322	2		T232	1
all_values[14]	auto[0]	auto[0]	auto[1]	53	1		T234	2		T231	1		T233	2
all_values[14]	auto[0]	auto[1]	auto[0]	13	1		T325	2		T328	1		T333	1
all_values[14]	auto[0]	auto[1]	auto[1]	64	1		T230	4		T231	1		T322	1
all_values[14]	auto[1]	auto[0]	auto[1]	70	1		T234	2		T230	1		T231	2
all_values[14]	auto[1]	auto[1]	auto[1]	52	1		T230	2		T233	2		T322	1
all_values[15]	auto[0]	auto[0]	auto[0]	41	1		T234	2		T231	1		T233	1
all_values[15]	auto[0]	auto[0]	auto[1]	48	1		T233	3		T323	1		T317	1
all_values[15]	auto[0]	auto[1]	auto[0]	22	1		T234	2		T325	5		T319	2
all_values[15]	auto[0]	auto[1]	auto[1]	51	1		T230	2		T231	2		T232	1
all_values[15]	auto[1]	auto[0]	auto[1]	67	1		T230	4		T233	3		T323	2
all_values[15]	auto[1]	auto[1]	auto[1]	46	1		T230	1		T231	1		T232	1
all_values[16]	auto[0]	auto[0]	auto[0]	35	1		T234	1		T230	2		T233	1
all_values[16]	auto[0]	auto[0]	auto[1]	46	1		T234	2		T322	1		T232	1
all_values[16]	auto[0]	auto[1]	auto[0]	26	1		T230	2		T233	1		T327	2
all_values[16]	auto[0]	auto[1]	auto[1]	58	1		T230	1		T231	2		T233	2
all_values[16]	auto[1]	auto[0]	auto[1]	52	1		T234	1		T231	1		T233	2
all_values[16]	auto[1]	auto[1]	auto[1]	58	1		T230	2		T231	1		T233	1
all_values[17]	auto[0]	auto[0]	auto[0]	34	1		T234	2		T230	1		T231	3
all_values[17]	auto[0]	auto[0]	auto[1]	57	1		T230	3		T233	2		T232	2
all_values[17]	auto[0]	auto[1]	auto[0]	14	1		T231	1		T324	1		T332	2
all_values[17]	auto[0]	auto[1]	auto[1]	61	1		T234	1		T233	2		T322	2
all_values[17]	auto[1]	auto[0]	auto[1]	60	1		T234	1		T230	2		T233	3
all_values[17]	auto[1]	auto[1]	auto[1]	49	1		T230	1		T327	1		T316	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal