Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.81 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2814
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T2757 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1169928954 Jul 07 04:49:05 PM PDT 24 Jul 07 04:49:09 PM PDT 24 316438006 ps
T2758 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1960419498 Jul 07 04:49:10 PM PDT 24 Jul 07 04:49:13 PM PDT 24 207847008 ps
T2759 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3689144678 Jul 07 04:49:35 PM PDT 24 Jul 07 04:49:36 PM PDT 24 50295571 ps
T2760 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1742257883 Jul 07 04:49:12 PM PDT 24 Jul 07 04:49:18 PM PDT 24 712081889 ps
T2761 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3107856127 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:11 PM PDT 24 106010812 ps
T2762 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4254047558 Jul 07 04:49:17 PM PDT 24 Jul 07 04:49:19 PM PDT 24 191475831 ps
T2763 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1882823495 Jul 07 04:49:35 PM PDT 24 Jul 07 04:49:36 PM PDT 24 84447494 ps
T2764 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3255879618 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:11 PM PDT 24 323240375 ps
T2765 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2156847636 Jul 07 04:49:05 PM PDT 24 Jul 07 04:49:06 PM PDT 24 107192061 ps
T2766 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2436956137 Jul 07 04:49:20 PM PDT 24 Jul 07 04:49:21 PM PDT 24 49426246 ps
T2767 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2840516542 Jul 07 04:49:23 PM PDT 24 Jul 07 04:49:25 PM PDT 24 157776017 ps
T2768 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.743394312 Jul 07 04:49:12 PM PDT 24 Jul 07 04:49:16 PM PDT 24 231876199 ps
T293 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1783772422 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:09 PM PDT 24 90587844 ps
T2769 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1576371919 Jul 07 04:49:35 PM PDT 24 Jul 07 04:49:37 PM PDT 24 175524369 ps
T294 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3367725161 Jul 07 04:49:03 PM PDT 24 Jul 07 04:49:05 PM PDT 24 154456261 ps
T295 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3260806023 Jul 07 04:49:02 PM PDT 24 Jul 07 04:49:08 PM PDT 24 676146064 ps
T2770 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3094279843 Jul 07 04:48:58 PM PDT 24 Jul 07 04:49:01 PM PDT 24 202524633 ps
T2771 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2720050272 Jul 07 04:49:36 PM PDT 24 Jul 07 04:49:38 PM PDT 24 53151956 ps
T2772 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1033207640 Jul 07 04:49:35 PM PDT 24 Jul 07 04:49:36 PM PDT 24 47793311 ps
T2773 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.520381926 Jul 07 04:49:29 PM PDT 24 Jul 07 04:49:32 PM PDT 24 414849778 ps
T2774 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3398153287 Jul 07 04:49:15 PM PDT 24 Jul 07 04:49:16 PM PDT 24 82184594 ps
T2775 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3188466733 Jul 07 04:49:28 PM PDT 24 Jul 07 04:49:29 PM PDT 24 37707416 ps
T2776 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2823775959 Jul 07 04:49:42 PM PDT 24 Jul 07 04:49:43 PM PDT 24 38486263 ps
T321 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3517684242 Jul 07 04:49:18 PM PDT 24 Jul 07 04:49:19 PM PDT 24 193263867 ps
T2777 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3409211999 Jul 07 04:49:33 PM PDT 24 Jul 07 04:49:34 PM PDT 24 45941850 ps
T2778 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1812200288 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:10 PM PDT 24 102875020 ps
T2779 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.57017953 Jul 07 04:49:39 PM PDT 24 Jul 07 04:49:40 PM PDT 24 36638359 ps
T338 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1101221431 Jul 07 04:49:26 PM PDT 24 Jul 07 04:49:32 PM PDT 24 1122807849 ps
T2780 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1872583820 Jul 07 04:49:38 PM PDT 24 Jul 07 04:49:39 PM PDT 24 66491160 ps
T2781 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4195024640 Jul 07 04:49:34 PM PDT 24 Jul 07 04:49:35 PM PDT 24 42374143 ps
T2782 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2056876000 Jul 07 04:49:26 PM PDT 24 Jul 07 04:49:27 PM PDT 24 62534087 ps
T2783 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2287366467 Jul 07 04:49:32 PM PDT 24 Jul 07 04:49:35 PM PDT 24 661055966 ps
T2784 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.388966598 Jul 07 04:49:17 PM PDT 24 Jul 07 04:49:19 PM PDT 24 94737630 ps
T2785 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.56793217 Jul 07 04:49:11 PM PDT 24 Jul 07 04:49:13 PM PDT 24 109501443 ps
T2786 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3243907825 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:09 PM PDT 24 124278904 ps
T2787 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2580592730 Jul 07 04:49:06 PM PDT 24 Jul 07 04:49:08 PM PDT 24 112248983 ps
T2788 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4228140205 Jul 07 04:48:58 PM PDT 24 Jul 07 04:49:03 PM PDT 24 789745027 ps
T2789 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1378419257 Jul 07 04:49:19 PM PDT 24 Jul 07 04:49:20 PM PDT 24 115052305 ps
T2790 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.754420452 Jul 07 04:49:39 PM PDT 24 Jul 07 04:49:40 PM PDT 24 46229850 ps
T2791 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3164125894 Jul 07 04:49:34 PM PDT 24 Jul 07 04:49:36 PM PDT 24 106545092 ps
T2792 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4212351498 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:09 PM PDT 24 94663729 ps
T2793 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3656553978 Jul 07 04:49:38 PM PDT 24 Jul 07 04:49:39 PM PDT 24 58347004 ps
T2794 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3795642565 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:10 PM PDT 24 85720839 ps
T2795 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2717801285 Jul 07 04:49:12 PM PDT 24 Jul 07 04:49:16 PM PDT 24 604188573 ps
T2796 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1862512469 Jul 07 04:49:28 PM PDT 24 Jul 07 04:49:30 PM PDT 24 63354533 ps
T2797 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.903610493 Jul 07 04:49:04 PM PDT 24 Jul 07 04:49:13 PM PDT 24 1443156472 ps
T2798 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3431848018 Jul 07 04:49:25 PM PDT 24 Jul 07 04:49:28 PM PDT 24 152889428 ps
T2799 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4172056471 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:08 PM PDT 24 116925242 ps
T2800 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1442234326 Jul 07 04:49:07 PM PDT 24 Jul 07 04:49:08 PM PDT 24 41382796 ps
T2801 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1044345824 Jul 07 04:49:05 PM PDT 24 Jul 07 04:49:08 PM PDT 24 184369373 ps
T2802 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.660131540 Jul 07 04:49:38 PM PDT 24 Jul 07 04:49:39 PM PDT 24 46047566 ps
T2803 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3138944941 Jul 07 04:49:24 PM PDT 24 Jul 07 04:49:27 PM PDT 24 670258750 ps
T2804 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3117324342 Jul 07 04:49:31 PM PDT 24 Jul 07 04:49:33 PM PDT 24 221893843 ps
T2805 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2401772459 Jul 07 04:49:24 PM PDT 24 Jul 07 04:49:26 PM PDT 24 116134442 ps
T2806 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3835439342 Jul 07 04:49:06 PM PDT 24 Jul 07 04:49:15 PM PDT 24 1386424147 ps
T2807 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.63573448 Jul 07 04:49:29 PM PDT 24 Jul 07 04:49:30 PM PDT 24 35760912 ps
T2808 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2006137152 Jul 07 04:49:38 PM PDT 24 Jul 07 04:49:39 PM PDT 24 109327050 ps
T2809 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1614287429 Jul 07 04:49:41 PM PDT 24 Jul 07 04:49:42 PM PDT 24 44153340 ps
T2810 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4054862741 Jul 07 04:48:58 PM PDT 24 Jul 07 04:49:00 PM PDT 24 158756236 ps
T2811 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3828490062 Jul 07 04:49:10 PM PDT 24 Jul 07 04:49:11 PM PDT 24 62904853 ps
T2812 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3895323655 Jul 07 04:49:24 PM PDT 24 Jul 07 04:49:25 PM PDT 24 61138956 ps
T2813 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4180280321 Jul 07 04:49:16 PM PDT 24 Jul 07 04:49:19 PM PDT 24 351987666 ps
T2814 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3263081349 Jul 07 04:49:12 PM PDT 24 Jul 07 04:49:14 PM PDT 24 40275191 ps
T340 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2204060152 Jul 07 04:49:18 PM PDT 24 Jul 07 04:49:21 PM PDT 24 638862128 ps

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.819814014
Short name T17
Test name
Test status
Simulation time 886953879 ps
CPU time 2.1 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:23 PM PDT 24
Peak memory 206376 kb
Host smart-55572882-a082-49ef-8231-52a919d062ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81981
4014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.819814014
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3943189225
Short name T230
Test name
Test status
Simulation time 48702368 ps
CPU time 0.7 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:49:43 PM PDT 24
Peak memory 205460 kb
Host smart-26f6deea-9e2b-44a5-b82f-33f3f3a01108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3943189225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3943189225
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.365609148
Short name T8
Test name
Test status
Simulation time 3794406516 ps
CPU time 4.9 seconds
Started Jul 07 05:25:11 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206172 kb
Host smart-58e0cac4-ba69-4839-ac49-6efb625834a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=365609148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.365609148
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3175035413
Short name T6
Test name
Test status
Simulation time 6634078584 ps
CPU time 62.71 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 206392 kb
Host smart-52e81b48-5bf1-4016-bac9-81040feb22e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3175035413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3175035413
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2773617706
Short name T227
Test name
Test status
Simulation time 878821007 ps
CPU time 4.89 seconds
Started Jul 07 04:48:57 PM PDT 24
Finished Jul 07 04:49:03 PM PDT 24
Peak memory 205792 kb
Host smart-22ac7dc2-ebe2-4e61-b34c-40db6b2d1a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2773617706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2773617706
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2975085202
Short name T94
Test name
Test status
Simulation time 304767344 ps
CPU time 1.14 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:23 PM PDT 24
Peak memory 206204 kb
Host smart-1c86f07d-26e9-448b-9310-4b40b8579b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29750
85202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2975085202
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.557088822
Short name T233
Test name
Test status
Simulation time 38792515 ps
CPU time 0.67 seconds
Started Jul 07 04:49:37 PM PDT 24
Finished Jul 07 04:49:38 PM PDT 24
Peak memory 205656 kb
Host smart-6a793988-f7cb-45ae-b899-9b84b5eeea9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=557088822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.557088822
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2401029873
Short name T108
Test name
Test status
Simulation time 164676803 ps
CPU time 0.92 seconds
Started Jul 07 05:21:26 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 206028 kb
Host smart-95b0ece3-918e-4d60-b906-8a0f5ef53149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24010
29873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2401029873
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.537432622
Short name T7
Test name
Test status
Simulation time 13334304976 ps
CPU time 12.31 seconds
Started Jul 07 05:24:57 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 206164 kb
Host smart-d8d71101-cc60-4af7-a771-71f82ff2a551
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=537432622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.537432622
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.305784978
Short name T19
Test name
Test status
Simulation time 231232263 ps
CPU time 0.89 seconds
Started Jul 07 05:20:23 PM PDT 24
Finished Jul 07 05:20:25 PM PDT 24
Peak memory 206184 kb
Host smart-c92ec6be-3523-4806-ba75-28714154fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
4978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.305784978
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4067008409
Short name T257
Test name
Test status
Simulation time 275892201 ps
CPU time 2.6 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:29 PM PDT 24
Peak memory 221848 kb
Host smart-9be96891-32ae-4a93-9c82-1245e020a2ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4067008409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.4067008409
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2237986097
Short name T42
Test name
Test status
Simulation time 138085946 ps
CPU time 0.78 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206112 kb
Host smart-6d597677-fc47-4517-97d8-34f59561938b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22379
86097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2237986097
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3074247944
Short name T39
Test name
Test status
Simulation time 416742211 ps
CPU time 1.24 seconds
Started Jul 07 05:18:58 PM PDT 24
Finished Jul 07 05:18:59 PM PDT 24
Peak memory 223992 kb
Host smart-e211b563-5260-4dfd-bd8d-3a067c8dc98a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3074247944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3074247944
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3677887593
Short name T113
Test name
Test status
Simulation time 261690388 ps
CPU time 0.97 seconds
Started Jul 07 05:21:47 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206140 kb
Host smart-8c6843a9-c1d5-4059-ae97-b1f8bce1ddba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
87593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3677887593
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1491624974
Short name T24
Test name
Test status
Simulation time 39992353 ps
CPU time 0.68 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:24:34 PM PDT 24
Peak memory 206192 kb
Host smart-d772f225-2af9-4f24-b19f-f1a0e9dc42be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14916
24974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1491624974
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.3489822213
Short name T5
Test name
Test status
Simulation time 8661915329 ps
CPU time 61.01 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:24:57 PM PDT 24
Peak memory 206484 kb
Host smart-b39500b4-8247-42c3-8416-e62f22016c66
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3489822213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3489822213
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3530829372
Short name T325
Test name
Test status
Simulation time 103422794 ps
CPU time 0.82 seconds
Started Jul 07 04:49:18 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 205604 kb
Host smart-5e0bd316-1d65-4edc-b26a-511a7c4b18f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3530829372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3530829372
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.10202779
Short name T282
Test name
Test status
Simulation time 70714586 ps
CPU time 0.86 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:28 PM PDT 24
Peak memory 205628 kb
Host smart-b8c75185-a71c-48a0-89bf-b35f496e07bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=10202779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.10202779
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3346755435
Short name T96
Test name
Test status
Simulation time 12638242237 ps
CPU time 116.67 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206220 kb
Host smart-34d62438-bff6-4ae2-8d2c-c8dee8aee882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33467
55435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3346755435
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.437672399
Short name T13
Test name
Test status
Simulation time 13413491983 ps
CPU time 12.45 seconds
Started Jul 07 05:21:15 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 206244 kb
Host smart-bd6c1267-f473-40a7-a930-4a4d7368e848
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=437672399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.437672399
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2350453495
Short name T79
Test name
Test status
Simulation time 306405047 ps
CPU time 1.03 seconds
Started Jul 07 05:18:52 PM PDT 24
Finished Jul 07 05:18:53 PM PDT 24
Peak memory 206180 kb
Host smart-3f7bde96-a633-4e00-9a7a-b5e56dba53d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23504
53495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2350453495
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.391621315
Short name T118
Test name
Test status
Simulation time 329246641 ps
CPU time 1.19 seconds
Started Jul 07 05:18:38 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 206196 kb
Host smart-9244fd0a-7fd2-49f3-b59c-418caf02536c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39162
1315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.391621315
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2993118484
Short name T45
Test name
Test status
Simulation time 20156613101 ps
CPU time 20.6 seconds
Started Jul 07 05:18:55 PM PDT 24
Finished Jul 07 05:19:16 PM PDT 24
Peak memory 206248 kb
Host smart-128cb40b-fa2d-4339-be3e-0396ffbf12bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29931
18484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2993118484
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3080721417
Short name T2750
Test name
Test status
Simulation time 56704251 ps
CPU time 0.71 seconds
Started Jul 07 04:49:17 PM PDT 24
Finished Jul 07 04:49:18 PM PDT 24
Peak memory 205528 kb
Host smart-cc7b4d2a-78ae-4e81-89a0-eb8b0790b6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3080721417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3080721417
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3974516856
Short name T93
Test name
Test status
Simulation time 142718698 ps
CPU time 0.77 seconds
Started Jul 07 05:21:17 PM PDT 24
Finished Jul 07 05:21:18 PM PDT 24
Peak memory 206112 kb
Host smart-4bee7b75-6278-43ee-971c-85a433d1fef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39745
16856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3974516856
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.58603151
Short name T326
Test name
Test status
Simulation time 163398390 ps
CPU time 0.79 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:23:53 PM PDT 24
Peak memory 206120 kb
Host smart-8427cb96-49bc-4922-acad-6bbc6933ae8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58603
151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.58603151
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2327826937
Short name T190
Test name
Test status
Simulation time 9904404312 ps
CPU time 45.3 seconds
Started Jul 07 05:20:08 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206396 kb
Host smart-774fe4d7-635b-43e2-bb8c-56bac2a02133
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2327826937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2327826937
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1101221431
Short name T338
Test name
Test status
Simulation time 1122807849 ps
CPU time 5.43 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:32 PM PDT 24
Peak memory 205888 kb
Host smart-aa662fd5-f9db-429e-b720-f8aca1331ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1101221431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1101221431
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3250025889
Short name T318
Test name
Test status
Simulation time 45655091 ps
CPU time 0.72 seconds
Started Jul 07 04:48:58 PM PDT 24
Finished Jul 07 04:48:59 PM PDT 24
Peak memory 205548 kb
Host smart-2202628b-9291-4ac5-ac30-36f4496ccaa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3250025889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3250025889
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1374692617
Short name T175
Test name
Test status
Simulation time 7975868050 ps
CPU time 207.82 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206488 kb
Host smart-82324b81-15db-4941-87cc-933d3f75e818
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1374692617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1374692617
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/27.usbdev_device_address.944913347
Short name T97
Test name
Test status
Simulation time 17974923184 ps
CPU time 34.1 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:24:10 PM PDT 24
Peak memory 206456 kb
Host smart-1b70ec36-3e7b-4dc3-9dda-77f6bb15649c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94491
3347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.944913347
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3687687556
Short name T70
Test name
Test status
Simulation time 462605029 ps
CPU time 1.38 seconds
Started Jul 07 05:18:33 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 206192 kb
Host smart-f75414e8-b753-4d3d-b8b4-1374d3da0c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876
87556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3687687556
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1882823495
Short name T2763
Test name
Test status
Simulation time 84447494 ps
CPU time 0.86 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 205636 kb
Host smart-8b18924f-20f6-4a96-9bb1-ea34f5ddc416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1882823495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1882823495
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2907586580
Short name T589
Test name
Test status
Simulation time 53619114 ps
CPU time 0.73 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:19:16 PM PDT 24
Peak memory 206144 kb
Host smart-709eef5a-1a60-4a77-8d28-b4ec29f2dc03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2907586580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2907586580
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3215577276
Short name T260
Test name
Test status
Simulation time 233021999 ps
CPU time 2.57 seconds
Started Jul 07 04:49:32 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 214112 kb
Host smart-d7580fc5-e714-4c5b-9ef5-260df45d7c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3215577276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3215577276
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3367725161
Short name T294
Test name
Test status
Simulation time 154456261 ps
CPU time 1.1 seconds
Started Jul 07 04:49:03 PM PDT 24
Finished Jul 07 04:49:05 PM PDT 24
Peak memory 205792 kb
Host smart-38c19902-f4f3-46db-a42a-a6f3848e79a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3367725161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3367725161
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2994560540
Short name T51
Test name
Test status
Simulation time 267414647 ps
CPU time 1.08 seconds
Started Jul 07 05:18:53 PM PDT 24
Finished Jul 07 05:18:55 PM PDT 24
Peak memory 206192 kb
Host smart-67c9abf7-e2f8-4893-b903-54113c362642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
60540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2994560540
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1841449917
Short name T86
Test name
Test status
Simulation time 144692094 ps
CPU time 0.77 seconds
Started Jul 07 05:18:31 PM PDT 24
Finished Jul 07 05:18:33 PM PDT 24
Peak memory 206180 kb
Host smart-24eecf1c-d99a-440d-b386-486f3e1ba5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18414
49917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1841449917
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1715138844
Short name T341
Test name
Test status
Simulation time 643112375 ps
CPU time 3.06 seconds
Started Jul 07 04:49:06 PM PDT 24
Finished Jul 07 04:49:10 PM PDT 24
Peak memory 205796 kb
Host smart-06fe4fca-a868-4b65-9462-52281d1a18af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1715138844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1715138844
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3796566202
Short name T336
Test name
Test status
Simulation time 892427700 ps
CPU time 4.98 seconds
Started Jul 07 04:49:24 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 205824 kb
Host smart-76c10af3-0719-49c2-8772-ba918a312ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3796566202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3796566202
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1884248418
Short name T247
Test name
Test status
Simulation time 789261594 ps
CPU time 3.16 seconds
Started Jul 07 04:49:23 PM PDT 24
Finished Jul 07 04:49:26 PM PDT 24
Peak memory 206192 kb
Host smart-ffb07821-e6dc-4947-a847-254c551b586e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1884248418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1884248418
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3000883676
Short name T330
Test name
Test status
Simulation time 43885066 ps
CPU time 0.75 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 205624 kb
Host smart-d652094d-c723-4372-b8c4-154d5dbf130e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3000883676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3000883676
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1142058736
Short name T172
Test name
Test status
Simulation time 1552065335 ps
CPU time 3.25 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:23 PM PDT 24
Peak memory 206392 kb
Host smart-1b42ce2a-ef85-4d07-99e4-66931de8befb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11420
58736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1142058736
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1518187050
Short name T54
Test name
Test status
Simulation time 149442085 ps
CPU time 0.78 seconds
Started Jul 07 05:18:59 PM PDT 24
Finished Jul 07 05:19:00 PM PDT 24
Peak memory 206204 kb
Host smart-a4fa4fb2-13a4-43f8-a10d-598b98a7d61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15181
87050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1518187050
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.49561132
Short name T937
Test name
Test status
Simulation time 41916661 ps
CPU time 0.68 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:21:47 PM PDT 24
Peak memory 206096 kb
Host smart-afc29b34-2c96-40ce-996e-dcf9e47388a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49561
132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.49561132
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.4164571933
Short name T80
Test name
Test status
Simulation time 222112367 ps
CPU time 1.01 seconds
Started Jul 07 05:19:32 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206184 kb
Host smart-739037c7-3b04-465f-b61b-516867d1d96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645
71933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.4164571933
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3180027499
Short name T697
Test name
Test status
Simulation time 157788559 ps
CPU time 0.78 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206184 kb
Host smart-273d049d-11f5-4a9c-be4a-8fe087a27da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31800
27499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3180027499
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1538453260
Short name T220
Test name
Test status
Simulation time 4477455244 ps
CPU time 5.09 seconds
Started Jul 07 05:21:30 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206372 kb
Host smart-4fc6fed9-97c4-4179-be1f-bdcaaa02464e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1538453260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1538453260
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2992530765
Short name T61
Test name
Test status
Simulation time 137873768 ps
CPU time 0.79 seconds
Started Jul 07 05:19:04 PM PDT 24
Finished Jul 07 05:19:04 PM PDT 24
Peak memory 206188 kb
Host smart-3119acf7-0385-4514-9ace-8c318843c7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29925
30765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2992530765
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1034850829
Short name T542
Test name
Test status
Simulation time 197546032 ps
CPU time 1.67 seconds
Started Jul 07 05:22:01 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206448 kb
Host smart-fecb7215-0571-4b14-b4f5-b554121b9686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10348
50829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1034850829
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3026263583
Short name T180
Test name
Test status
Simulation time 1477527997 ps
CPU time 2.92 seconds
Started Jul 07 05:22:37 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206312 kb
Host smart-ad8e8b88-3ffc-4314-b928-99505e991633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262
63583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3026263583
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3341263821
Short name T4
Test name
Test status
Simulation time 3661746092 ps
CPU time 103.33 seconds
Started Jul 07 05:22:53 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206400 kb
Host smart-0ae7425e-6620-4ec9-b7b2-9907bb6fdd48
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3341263821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3341263821
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1771398339
Short name T176
Test name
Test status
Simulation time 8261943991 ps
CPU time 122.47 seconds
Started Jul 07 05:20:53 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206488 kb
Host smart-189fde45-b4de-4580-b8bc-dbf2ce33ff23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1771398339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1771398339
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1224764285
Short name T65
Test name
Test status
Simulation time 4164475699 ps
CPU time 9.1 seconds
Started Jul 07 05:18:35 PM PDT 24
Finished Jul 07 05:18:44 PM PDT 24
Peak memory 206380 kb
Host smart-beec8e8b-4472-4234-bc0b-d45be08abd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12247
64285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1224764285
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2929062210
Short name T66
Test name
Test status
Simulation time 169440645 ps
CPU time 0.81 seconds
Started Jul 07 05:18:37 PM PDT 24
Finished Jul 07 05:18:38 PM PDT 24
Peak memory 206184 kb
Host smart-37e8cb18-69b7-4166-969e-6e12edbd901f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29290
62210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2929062210
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3519363461
Short name T76
Test name
Test status
Simulation time 232692505 ps
CPU time 0.87 seconds
Started Jul 07 05:18:55 PM PDT 24
Finished Jul 07 05:18:56 PM PDT 24
Peak memory 206120 kb
Host smart-182c4828-5b9b-4469-9f31-a45a847dc676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35193
63461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3519363461
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1185578747
Short name T49
Test name
Test status
Simulation time 234335085 ps
CPU time 0.92 seconds
Started Jul 07 05:19:33 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206184 kb
Host smart-7e8eadf9-d7b4-4698-a31d-6287d24990e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11855
78747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1185578747
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1001135860
Short name T128
Test name
Test status
Simulation time 207541127 ps
CPU time 0.86 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206188 kb
Host smart-88f0e2c3-d542-4b21-b814-ce7e5145c68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10011
35860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1001135860
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.2217326271
Short name T52
Test name
Test status
Simulation time 383876897 ps
CPU time 1.12 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:53 PM PDT 24
Peak memory 206132 kb
Host smart-d33332ff-175c-456e-9443-4e00c9a6d2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22173
26271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.2217326271
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1723758750
Short name T101
Test name
Test status
Simulation time 22039343196 ps
CPU time 38.46 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:19:51 PM PDT 24
Peak memory 206372 kb
Host smart-99a7bd93-7c63-4d88-bc00-d3f4f418dd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
58750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1723758750
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1662362662
Short name T121
Test name
Test status
Simulation time 5344863798 ps
CPU time 50.32 seconds
Started Jul 07 05:21:11 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206484 kb
Host smart-7b2420b6-1136-4cd2-bb6f-3caa89214ed3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1662362662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1662362662
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.486115336
Short name T158
Test name
Test status
Simulation time 205337988 ps
CPU time 0.81 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206184 kb
Host smart-d6b5c028-f09e-4315-ada5-d70c5eb2e015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48611
5336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.486115336
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4002038549
Short name T148
Test name
Test status
Simulation time 211593865 ps
CPU time 0.94 seconds
Started Jul 07 05:21:24 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 206120 kb
Host smart-4e62fa6a-96fb-4a3c-a0f5-e6606216bd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40020
38549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4002038549
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1573083749
Short name T151
Test name
Test status
Simulation time 248459226 ps
CPU time 0.89 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 206188 kb
Host smart-26b1c33f-7630-45a1-b3f0-acf7d5cc718d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15730
83749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1573083749
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1225811319
Short name T2400
Test name
Test status
Simulation time 11800145689 ps
CPU time 26.86 seconds
Started Jul 07 05:21:47 PM PDT 24
Finished Jul 07 05:22:14 PM PDT 24
Peak memory 206484 kb
Host smart-f426fb8b-8c01-4154-9c2c-570ec3b4b42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12258
11319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1225811319
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1321708009
Short name T2532
Test name
Test status
Simulation time 213945654 ps
CPU time 0.9 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:21:54 PM PDT 24
Peak memory 206112 kb
Host smart-f054e9bb-6ed9-40d0-9fc9-2e1a6127ce01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13217
08009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1321708009
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2745547274
Short name T145
Test name
Test status
Simulation time 200310960 ps
CPU time 0.88 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206216 kb
Host smart-073bedde-f1e8-4242-9b04-de7e094e31f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27455
47274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2745547274
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.26917215
Short name T240
Test name
Test status
Simulation time 7802987474 ps
CPU time 73.66 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206520 kb
Host smart-cc49dc1e-e04d-4bda-afda-8a00979a7a20
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=26917215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.26917215
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2499291607
Short name T203
Test name
Test status
Simulation time 473989119 ps
CPU time 1.47 seconds
Started Jul 07 05:22:18 PM PDT 24
Finished Jul 07 05:22:20 PM PDT 24
Peak memory 206372 kb
Host smart-fdcaf490-7e08-46f5-8bf9-971b8b3788a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24992
91607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2499291607
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2655765175
Short name T141
Test name
Test status
Simulation time 192776249 ps
CPU time 0.83 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206156 kb
Host smart-e49f4061-5994-479a-8200-539b4ca13069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
65175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2655765175
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.377941332
Short name T2209
Test name
Test status
Simulation time 200510355 ps
CPU time 0.92 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206184 kb
Host smart-daf94d1b-d1e1-4b03-99db-14a80559da97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37794
1332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.377941332
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1065845538
Short name T198
Test name
Test status
Simulation time 153662101 ps
CPU time 0.76 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206164 kb
Host smart-9040f11b-85eb-4974-8574-964ff8e7f965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10658
45538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1065845538
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3736742539
Short name T132
Test name
Test status
Simulation time 203014901 ps
CPU time 0.87 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206116 kb
Host smart-d687b2ab-a6c4-499d-8c85-a6652062e59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37367
42539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3736742539
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3814526011
Short name T138
Test name
Test status
Simulation time 189151540 ps
CPU time 0.84 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206120 kb
Host smart-9efa6b7f-c3b9-4a82-aafc-205542d94b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38145
26011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3814526011
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2756296398
Short name T146
Test name
Test status
Simulation time 176657940 ps
CPU time 0.83 seconds
Started Jul 07 05:24:07 PM PDT 24
Finished Jul 07 05:24:08 PM PDT 24
Peak memory 206124 kb
Host smart-1819f75f-7858-43e1-b181-fbcdb7cbca17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27562
96398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2756296398
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1169928954
Short name T2757
Test name
Test status
Simulation time 316438006 ps
CPU time 3.83 seconds
Started Jul 07 04:49:05 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205856 kb
Host smart-b4ef4171-8399-4bc1-8332-8b5ad050a03a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1169928954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1169928954
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4228140205
Short name T2788
Test name
Test status
Simulation time 789745027 ps
CPU time 4.7 seconds
Started Jul 07 04:48:58 PM PDT 24
Finished Jul 07 04:49:03 PM PDT 24
Peak memory 205852 kb
Host smart-2270fba6-0795-45ac-b53a-b55d77d147aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4228140205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4228140205
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.11593064
Short name T288
Test name
Test status
Simulation time 59211451 ps
CPU time 0.81 seconds
Started Jul 07 04:49:01 PM PDT 24
Finished Jul 07 04:49:02 PM PDT 24
Peak memory 205648 kb
Host smart-a4d9acab-ba24-4fef-8521-eda65c5d459c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=11593064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.11593064
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3094279843
Short name T2770
Test name
Test status
Simulation time 202524633 ps
CPU time 2.13 seconds
Started Jul 07 04:48:58 PM PDT 24
Finished Jul 07 04:49:01 PM PDT 24
Peak memory 214040 kb
Host smart-2d06c5bd-8172-458e-a456-8c808984cc03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094279843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3094279843
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2774788306
Short name T290
Test name
Test status
Simulation time 124834726 ps
CPU time 0.84 seconds
Started Jul 07 04:48:59 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 206064 kb
Host smart-1281e094-0366-4378-974c-066691e9376c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2774788306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2774788306
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4054862741
Short name T2810
Test name
Test status
Simulation time 158756236 ps
CPU time 1.48 seconds
Started Jul 07 04:48:58 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 222216 kb
Host smart-d8e4dd13-6047-4923-99e8-17c7d65e02e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4054862741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4054862741
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2496912381
Short name T2744
Test name
Test status
Simulation time 171219521 ps
CPU time 3.89 seconds
Started Jul 07 04:49:00 PM PDT 24
Finished Jul 07 04:49:04 PM PDT 24
Peak memory 205788 kb
Host smart-50646912-3f1a-4347-bb91-30acf93cc531
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2496912381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2496912381
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2694010108
Short name T2718
Test name
Test status
Simulation time 83288517 ps
CPU time 1.17 seconds
Started Jul 07 04:49:03 PM PDT 24
Finished Jul 07 04:49:05 PM PDT 24
Peak memory 205764 kb
Host smart-5fc7cdb1-0125-44df-afb3-02bae4bcdb99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2694010108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2694010108
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.595820476
Short name T242
Test name
Test status
Simulation time 114876423 ps
CPU time 2.73 seconds
Started Jul 07 04:48:57 PM PDT 24
Finished Jul 07 04:49:00 PM PDT 24
Peak memory 214080 kb
Host smart-a7355bcd-dff6-478d-8f3b-955ce7d463ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=595820476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.595820476
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3243907825
Short name T2786
Test name
Test status
Simulation time 124278904 ps
CPU time 2.01 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205768 kb
Host smart-71790b57-d418-41e2-8fcf-f2732eace415
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3243907825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3243907825
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.903610493
Short name T2797
Test name
Test status
Simulation time 1443156472 ps
CPU time 8.3 seconds
Started Jul 07 04:49:04 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 205820 kb
Host smart-6608f57b-a192-4465-a320-ce4445f85aba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=903610493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.903610493
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2156847636
Short name T2765
Test name
Test status
Simulation time 107192061 ps
CPU time 0.83 seconds
Started Jul 07 04:49:05 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 205616 kb
Host smart-a013088c-97fe-491e-91a9-73cba7a0f52e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2156847636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2156847636
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4172056471
Short name T2799
Test name
Test status
Simulation time 116925242 ps
CPU time 1.32 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 215836 kb
Host smart-29593c21-0334-43ba-b0e9-ed6c15225f7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172056471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.4172056471
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2231193728
Short name T2721
Test name
Test status
Simulation time 56936659 ps
CPU time 0.89 seconds
Started Jul 07 04:49:01 PM PDT 24
Finished Jul 07 04:49:02 PM PDT 24
Peak memory 205660 kb
Host smart-6caec16f-d826-42b0-9a1f-a366d4edaac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2231193728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2231193728
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1098924870
Short name T327
Test name
Test status
Simulation time 52404958 ps
CPU time 0.72 seconds
Started Jul 07 04:49:05 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 205636 kb
Host smart-e8f75725-5456-4a2a-9975-c3b1cf9c0a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098924870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1098924870
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2201229441
Short name T287
Test name
Test status
Simulation time 102903690 ps
CPU time 1.49 seconds
Started Jul 07 04:49:01 PM PDT 24
Finished Jul 07 04:49:03 PM PDT 24
Peak memory 214020 kb
Host smart-3f880af9-25c7-4d70-aa39-d745442ec06a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2201229441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2201229441
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.362478439
Short name T2716
Test name
Test status
Simulation time 106332679 ps
CPU time 2.57 seconds
Started Jul 07 04:49:06 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205804 kb
Host smart-0f97a7ee-9155-4bf8-851e-4cb77d4f64d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=362478439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.362478439
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2680220942
Short name T2746
Test name
Test status
Simulation time 107628782 ps
CPU time 1.21 seconds
Started Jul 07 04:49:02 PM PDT 24
Finished Jul 07 04:49:04 PM PDT 24
Peak memory 205724 kb
Host smart-a64f8807-9afa-4b68-b3b3-984944a3edac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2680220942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2680220942
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3255879618
Short name T2764
Test name
Test status
Simulation time 323240375 ps
CPU time 3.18 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 214052 kb
Host smart-cff7ed56-6ca8-45e0-919b-fb8541f373f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3255879618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3255879618
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.518239186
Short name T2745
Test name
Test status
Simulation time 185645408 ps
CPU time 1.97 seconds
Started Jul 07 04:49:21 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 214088 kb
Host smart-3334627a-dfd7-4788-8a3a-c4366fd2c950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518239186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.518239186
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2436956137
Short name T2766
Test name
Test status
Simulation time 49426246 ps
CPU time 0.84 seconds
Started Jul 07 04:49:20 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 205628 kb
Host smart-f9de6875-ffe0-4a03-bf37-f744321ce8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2436956137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2436956137
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2028487906
Short name T324
Test name
Test status
Simulation time 112616775 ps
CPU time 0.75 seconds
Started Jul 07 04:49:22 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 205692 kb
Host smart-db32f654-eff1-4ad1-98bb-db042a5701c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2028487906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2028487906
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4006242342
Short name T301
Test name
Test status
Simulation time 265971399 ps
CPU time 1.69 seconds
Started Jul 07 04:49:21 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 205784 kb
Host smart-8e034908-7fac-4f80-826e-318cae5fd1ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4006242342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4006242342
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4115438053
Short name T2719
Test name
Test status
Simulation time 156941762 ps
CPU time 2.24 seconds
Started Jul 07 04:49:20 PM PDT 24
Finished Jul 07 04:49:22 PM PDT 24
Peak memory 213996 kb
Host smart-9ee38725-dbae-4f68-abc0-521f553117d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4115438053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4115438053
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.54803143
Short name T311
Test name
Test status
Simulation time 2238110711 ps
CPU time 6.89 seconds
Started Jul 07 04:49:19 PM PDT 24
Finished Jul 07 04:49:26 PM PDT 24
Peak memory 205868 kb
Host smart-746933c2-cb99-421a-95df-13d0e6d07ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=54803143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.54803143
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3431848018
Short name T2798
Test name
Test status
Simulation time 152889428 ps
CPU time 2.32 seconds
Started Jul 07 04:49:25 PM PDT 24
Finished Jul 07 04:49:28 PM PDT 24
Peak memory 214072 kb
Host smart-0fe85013-2935-4373-9d7c-2119f3dabc8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431848018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3431848018
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3895323655
Short name T2812
Test name
Test status
Simulation time 61138956 ps
CPU time 1.02 seconds
Started Jul 07 04:49:24 PM PDT 24
Finished Jul 07 04:49:25 PM PDT 24
Peak memory 205844 kb
Host smart-dd648de1-465b-4099-8b41-f132d73f59be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3895323655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3895323655
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3188466733
Short name T2775
Test name
Test status
Simulation time 37707416 ps
CPU time 0.69 seconds
Started Jul 07 04:49:28 PM PDT 24
Finished Jul 07 04:49:29 PM PDT 24
Peak memory 205620 kb
Host smart-437336b9-956c-4146-8590-11dcd14df011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188466733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3188466733
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.896009659
Short name T315
Test name
Test status
Simulation time 192229326 ps
CPU time 1.23 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:27 PM PDT 24
Peak memory 205844 kb
Host smart-c289ce3b-b3d2-4fd6-a720-7383e0d6aef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=896009659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.896009659
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1507296599
Short name T256
Test name
Test status
Simulation time 179369142 ps
CPU time 1.92 seconds
Started Jul 07 04:49:21 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 206308 kb
Host smart-6f0ca102-5888-488c-89fd-a097364d9051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1507296599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1507296599
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3707168641
Short name T266
Test name
Test status
Simulation time 320641535 ps
CPU time 2.47 seconds
Started Jul 07 04:49:22 PM PDT 24
Finished Jul 07 04:49:25 PM PDT 24
Peak memory 205760 kb
Host smart-959bd54e-de8a-42d2-b92f-a40c2bbf4051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3707168641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3707168641
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2056876000
Short name T2782
Test name
Test status
Simulation time 62534087 ps
CPU time 1.23 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:27 PM PDT 24
Peak memory 213940 kb
Host smart-ab27d94f-ba9e-4798-a01a-4a91c0a3bc0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056876000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2056876000
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1033207640
Short name T2772
Test name
Test status
Simulation time 47793311 ps
CPU time 0.68 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 205172 kb
Host smart-e01b11fc-e362-4d8d-b96b-d2b6173b87c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1033207640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1033207640
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.941055860
Short name T299
Test name
Test status
Simulation time 94000307 ps
CPU time 1.16 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:27 PM PDT 24
Peak memory 205824 kb
Host smart-287c541a-5b3f-4baa-843e-272f885ea3dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=941055860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.941055860
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3138944941
Short name T2803
Test name
Test status
Simulation time 670258750 ps
CPU time 2.88 seconds
Started Jul 07 04:49:24 PM PDT 24
Finished Jul 07 04:49:27 PM PDT 24
Peak memory 205896 kb
Host smart-5a56f2e5-c7d6-45d9-b1d6-3fc2caf9883c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3138944941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3138944941
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2840516542
Short name T2767
Test name
Test status
Simulation time 157776017 ps
CPU time 1.86 seconds
Started Jul 07 04:49:23 PM PDT 24
Finished Jul 07 04:49:25 PM PDT 24
Peak memory 214092 kb
Host smart-daac6493-f691-44ff-9958-76c85505b34d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840516542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2840516542
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.263621908
Short name T285
Test name
Test status
Simulation time 50187004 ps
CPU time 1.02 seconds
Started Jul 07 04:49:29 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 205780 kb
Host smart-41b169a0-b2db-4f75-bada-0b27caafb692
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=263621908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.263621908
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3031519607
Short name T335
Test name
Test status
Simulation time 100228564 ps
CPU time 0.79 seconds
Started Jul 07 04:49:25 PM PDT 24
Finished Jul 07 04:49:26 PM PDT 24
Peak memory 205588 kb
Host smart-56d43429-b68c-488f-afbd-cbeb05172057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031519607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3031519607
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2401772459
Short name T2805
Test name
Test status
Simulation time 116134442 ps
CPU time 1.63 seconds
Started Jul 07 04:49:24 PM PDT 24
Finished Jul 07 04:49:26 PM PDT 24
Peak memory 205896 kb
Host smart-71ff2d98-267c-454f-84e5-6775ae68e332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2401772459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2401772459
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2429792469
Short name T2726
Test name
Test status
Simulation time 204898835 ps
CPU time 2.38 seconds
Started Jul 07 04:49:28 PM PDT 24
Finished Jul 07 04:49:31 PM PDT 24
Peak memory 205916 kb
Host smart-a2e07b87-bd36-4983-9830-97d9d2692905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2429792469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2429792469
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.827245132
Short name T2754
Test name
Test status
Simulation time 77999883 ps
CPU time 1.52 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 213684 kb
Host smart-e1f5a436-a507-4bc2-a0b0-d343ada22018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827245132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.827245132
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1274242604
Short name T2728
Test name
Test status
Simulation time 60903327 ps
CPU time 0.88 seconds
Started Jul 07 04:49:28 PM PDT 24
Finished Jul 07 04:49:29 PM PDT 24
Peak memory 205664 kb
Host smart-ca860ab9-de20-4bea-9c41-d20736ca7d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1274242604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1274242604
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3218481717
Short name T328
Test name
Test status
Simulation time 67938948 ps
CPU time 0.7 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 205632 kb
Host smart-d6620dbf-4af5-4f4d-a8d6-be8b5e5ab9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3218481717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3218481717
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3164125894
Short name T2791
Test name
Test status
Simulation time 106545092 ps
CPU time 1.15 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 205836 kb
Host smart-549082dc-aee5-4913-a0d7-c1d3137a6539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3164125894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3164125894
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.319285626
Short name T2739
Test name
Test status
Simulation time 74351175 ps
CPU time 2.06 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 221984 kb
Host smart-7de4a8d7-a519-4db7-a83d-3e3a7b7aef08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=319285626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.319285626
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2599858392
Short name T2724
Test name
Test status
Simulation time 106927972 ps
CPU time 1.26 seconds
Started Jul 07 04:49:30 PM PDT 24
Finished Jul 07 04:49:32 PM PDT 24
Peak memory 214088 kb
Host smart-87bbbfce-9fe9-4dbd-84d2-f315d2c7e1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599858392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2599858392
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1862512469
Short name T2796
Test name
Test status
Simulation time 63354533 ps
CPU time 1.02 seconds
Started Jul 07 04:49:28 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 205924 kb
Host smart-a1b214e0-ae56-4c67-bc72-86807dffea78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1862512469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1862512469
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4195024640
Short name T2781
Test name
Test status
Simulation time 42374143 ps
CPU time 0.69 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 205632 kb
Host smart-bbd4724d-2613-4bed-b0cd-19ebf0251246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4195024640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.4195024640
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2788819864
Short name T2720
Test name
Test status
Simulation time 53484984 ps
CPU time 1 seconds
Started Jul 07 04:49:28 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 205784 kb
Host smart-d2268de4-77ce-47c3-a48a-0de50d625ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2788819864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2788819864
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2518650187
Short name T2735
Test name
Test status
Simulation time 224665520 ps
CPU time 3.29 seconds
Started Jul 07 04:49:26 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 214108 kb
Host smart-bb1f4ebc-138e-4ae1-adb8-45daa5c804ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2518650187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2518650187
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3236922460
Short name T226
Test name
Test status
Simulation time 200571709 ps
CPU time 1.97 seconds
Started Jul 07 04:49:29 PM PDT 24
Finished Jul 07 04:49:32 PM PDT 24
Peak memory 214068 kb
Host smart-666206aa-6467-4f2d-a404-1c4751399187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236922460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3236922460
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2171844755
Short name T2722
Test name
Test status
Simulation time 44710929 ps
CPU time 0.85 seconds
Started Jul 07 04:49:32 PM PDT 24
Finished Jul 07 04:49:33 PM PDT 24
Peak memory 205588 kb
Host smart-0fba5b4f-aa6b-430f-b1ff-ced39caeb085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2171844755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2171844755
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1408303103
Short name T2751
Test name
Test status
Simulation time 42494388 ps
CPU time 0.67 seconds
Started Jul 07 04:49:28 PM PDT 24
Finished Jul 07 04:49:29 PM PDT 24
Peak memory 205628 kb
Host smart-140736c4-2059-421a-a8ca-fbd2bc15cb4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1408303103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1408303103
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3117324342
Short name T2804
Test name
Test status
Simulation time 221893843 ps
CPU time 1.72 seconds
Started Jul 07 04:49:31 PM PDT 24
Finished Jul 07 04:49:33 PM PDT 24
Peak memory 205836 kb
Host smart-89e4367e-093f-4b3c-8ee5-b1b467c85b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3117324342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3117324342
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.991722346
Short name T2756
Test name
Test status
Simulation time 111867182 ps
CPU time 1.74 seconds
Started Jul 07 04:49:30 PM PDT 24
Finished Jul 07 04:49:32 PM PDT 24
Peak memory 221548 kb
Host smart-9f12ebf6-0cd8-47b5-b875-517a0d08c766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=991722346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.991722346
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.520381926
Short name T2773
Test name
Test status
Simulation time 414849778 ps
CPU time 2.86 seconds
Started Jul 07 04:49:29 PM PDT 24
Finished Jul 07 04:49:32 PM PDT 24
Peak memory 205812 kb
Host smart-b3aeab9a-661e-4e68-9ec2-0e182bbc84b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=520381926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.520381926
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2451499248
Short name T2738
Test name
Test status
Simulation time 89184309 ps
CPU time 2.1 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 214040 kb
Host smart-cd825c97-ed62-432d-8a61-5b2081507765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451499248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2451499248
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3655124331
Short name T297
Test name
Test status
Simulation time 73734629 ps
CPU time 0.9 seconds
Started Jul 07 04:49:33 PM PDT 24
Finished Jul 07 04:49:34 PM PDT 24
Peak memory 205916 kb
Host smart-db8f718a-19a8-4e28-b6c7-1ef419f016f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3655124331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3655124331
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.63573448
Short name T2807
Test name
Test status
Simulation time 35760912 ps
CPU time 0.64 seconds
Started Jul 07 04:49:29 PM PDT 24
Finished Jul 07 04:49:30 PM PDT 24
Peak memory 205600 kb
Host smart-31f059b2-8271-4686-b272-de97705d4b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63573448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.63573448
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1576371919
Short name T2769
Test name
Test status
Simulation time 175524369 ps
CPU time 1.65 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 205772 kb
Host smart-c3c93b26-21e4-4dee-be8b-4b0b191a3d1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1576371919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1576371919
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1657924620
Short name T225
Test name
Test status
Simulation time 707104157 ps
CPU time 4.36 seconds
Started Jul 07 04:49:29 PM PDT 24
Finished Jul 07 04:49:34 PM PDT 24
Peak memory 205764 kb
Host smart-d2e6e7c6-b97e-44b5-9869-9457b838ab4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1657924620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1657924620
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3951507475
Short name T2729
Test name
Test status
Simulation time 59105465 ps
CPU time 1.37 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 214116 kb
Host smart-4b239847-ea96-4958-8127-c48b2be4dfcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951507475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3951507475
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2880356563
Short name T304
Test name
Test status
Simulation time 58610012 ps
CPU time 0.88 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 205668 kb
Host smart-68c82f04-717e-452f-a0d2-667aeb41c813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2880356563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2880356563
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.972936736
Short name T300
Test name
Test status
Simulation time 147969197 ps
CPU time 1.57 seconds
Started Jul 07 04:49:33 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 205756 kb
Host smart-d9a80696-49df-4be5-800d-ec8583e8e47c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=972936736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.972936736
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.24512928
Short name T2736
Test name
Test status
Simulation time 78738366 ps
CPU time 2.15 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 221704 kb
Host smart-38312994-3ee8-4b69-a73a-b59f56f128a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=24512928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.24512928
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1739229343
Short name T267
Test name
Test status
Simulation time 282021212 ps
CPU time 2.39 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:38 PM PDT 24
Peak memory 205784 kb
Host smart-149ee9d7-c676-41b8-8562-3a01f37025cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1739229343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1739229343
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4136366573
Short name T2733
Test name
Test status
Simulation time 107530037 ps
CPU time 2.99 seconds
Started Jul 07 04:49:37 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 214024 kb
Host smart-55719fa9-024e-4133-ab2b-b3056470a3a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136366573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4136366573
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3512997638
Short name T296
Test name
Test status
Simulation time 67369446 ps
CPU time 0.93 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 205788 kb
Host smart-f4e22af4-ce9d-44ca-938e-e9eee31ce760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3512997638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3512997638
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2998961426
Short name T298
Test name
Test status
Simulation time 191320494 ps
CPU time 1.67 seconds
Started Jul 07 04:49:34 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 205852 kb
Host smart-d9f496ea-19fb-466a-b733-19277952bd76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2998961426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2998961426
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.844059562
Short name T258
Test name
Test status
Simulation time 106337368 ps
CPU time 3.07 seconds
Started Jul 07 04:49:33 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 214156 kb
Host smart-8523ab58-b2b2-4711-a340-336d5e13c017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844059562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.844059562
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2287366467
Short name T2783
Test name
Test status
Simulation time 661055966 ps
CPU time 2.93 seconds
Started Jul 07 04:49:32 PM PDT 24
Finished Jul 07 04:49:35 PM PDT 24
Peak memory 205840 kb
Host smart-fb062d40-7551-46ca-947b-d3b1283d6609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2287366467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2287366467
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2985610647
Short name T284
Test name
Test status
Simulation time 128727645 ps
CPU time 3.17 seconds
Started Jul 07 04:49:04 PM PDT 24
Finished Jul 07 04:49:07 PM PDT 24
Peak memory 205752 kb
Host smart-a4988e1c-73ec-4740-ad89-7136d915ab84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2985610647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2985610647
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3260806023
Short name T295
Test name
Test status
Simulation time 676146064 ps
CPU time 6.02 seconds
Started Jul 07 04:49:02 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 205812 kb
Host smart-5a80dc48-1172-4b53-9e1c-7f101a48c509
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3260806023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3260806023
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1556198218
Short name T2755
Test name
Test status
Simulation time 91860790 ps
CPU time 0.91 seconds
Started Jul 07 04:49:00 PM PDT 24
Finished Jul 07 04:49:02 PM PDT 24
Peak memory 205632 kb
Host smart-dcebec91-0632-4855-8c7b-87b8e7d08f72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1556198218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1556198218
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3025968786
Short name T241
Test name
Test status
Simulation time 58519630 ps
CPU time 1.27 seconds
Started Jul 07 04:49:06 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 213956 kb
Host smart-10293c15-1995-4cf4-9f3a-aef69676dedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025968786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3025968786
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1442234326
Short name T2800
Test name
Test status
Simulation time 41382796 ps
CPU time 0.7 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 205564 kb
Host smart-d69eace2-98c8-4470-98da-68d6e3d939b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1442234326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1442234326
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1044345824
Short name T2801
Test name
Test status
Simulation time 184369373 ps
CPU time 2.39 seconds
Started Jul 07 04:49:05 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 214452 kb
Host smart-f6b87636-6b84-4d46-ab17-384f862e1713
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1044345824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1044345824
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2089606087
Short name T2717
Test name
Test status
Simulation time 388287652 ps
CPU time 2.89 seconds
Started Jul 07 04:49:02 PM PDT 24
Finished Jul 07 04:49:05 PM PDT 24
Peak memory 205852 kb
Host smart-fd0d6be9-995e-416d-b0cc-aeee59911fe4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2089606087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2089606087
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2580592730
Short name T2787
Test name
Test status
Simulation time 112248983 ps
CPU time 1.15 seconds
Started Jul 07 04:49:06 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 205784 kb
Host smart-420dd8f2-0556-4960-83b2-ed2a4d953c53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2580592730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2580592730
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3574518182
Short name T259
Test name
Test status
Simulation time 116454683 ps
CPU time 1.56 seconds
Started Jul 07 04:49:05 PM PDT 24
Finished Jul 07 04:49:06 PM PDT 24
Peak memory 205860 kb
Host smart-b38c2a43-e278-45fa-bc72-9f44947a5956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3574518182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3574518182
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1240513548
Short name T314
Test name
Test status
Simulation time 464179125 ps
CPU time 3.04 seconds
Started Jul 07 04:49:05 PM PDT 24
Finished Jul 07 04:49:08 PM PDT 24
Peak memory 205792 kb
Host smart-11770b96-90ac-4b62-8bbe-949937634d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1240513548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1240513548
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3689144678
Short name T2759
Test name
Test status
Simulation time 50295571 ps
CPU time 0.69 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:36 PM PDT 24
Peak memory 205716 kb
Host smart-58555a61-0eed-4a09-9dba-0b4a2e3d31d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689144678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3689144678
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3141275091
Short name T316
Test name
Test status
Simulation time 45984006 ps
CPU time 0.71 seconds
Started Jul 07 04:49:35 PM PDT 24
Finished Jul 07 04:49:37 PM PDT 24
Peak memory 205572 kb
Host smart-caee9100-ad59-4ff1-a9c5-462d4dcea823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3141275091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3141275091
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2720050272
Short name T2771
Test name
Test status
Simulation time 53151956 ps
CPU time 0.67 seconds
Started Jul 07 04:49:36 PM PDT 24
Finished Jul 07 04:49:38 PM PDT 24
Peak memory 205632 kb
Host smart-4ae5080c-1558-4cd6-8005-ae69c0a70a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2720050272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2720050272
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3409211999
Short name T2777
Test name
Test status
Simulation time 45941850 ps
CPU time 0.71 seconds
Started Jul 07 04:49:33 PM PDT 24
Finished Jul 07 04:49:34 PM PDT 24
Peak memory 205688 kb
Host smart-d790dd85-2294-4234-a145-29d2d97d91ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3409211999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3409211999
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2630492681
Short name T320
Test name
Test status
Simulation time 46688109 ps
CPU time 0.75 seconds
Started Jul 07 04:49:33 PM PDT 24
Finished Jul 07 04:49:34 PM PDT 24
Peak memory 205600 kb
Host smart-251d7e42-da48-468c-91bc-ca8d6d37a6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2630492681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2630492681
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1559409355
Short name T2732
Test name
Test status
Simulation time 56345048 ps
CPU time 0.68 seconds
Started Jul 07 04:49:39 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 205632 kb
Host smart-cfbd49e4-9709-422a-9aa6-b57514e616fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1559409355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1559409355
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.107492543
Short name T2743
Test name
Test status
Simulation time 42630414 ps
CPU time 0.68 seconds
Started Jul 07 04:49:40 PM PDT 24
Finished Jul 07 04:49:41 PM PDT 24
Peak memory 205580 kb
Host smart-c7f3292a-fe88-450e-a5ef-a699872d1f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=107492543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.107492543
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.889537472
Short name T2737
Test name
Test status
Simulation time 111234816 ps
CPU time 0.76 seconds
Started Jul 07 04:49:39 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 205604 kb
Host smart-ca198f7a-f7f3-4143-9245-7739f098e5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=889537472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.889537472
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2433490309
Short name T2748
Test name
Test status
Simulation time 34847563 ps
CPU time 0.71 seconds
Started Jul 07 04:49:41 PM PDT 24
Finished Jul 07 04:49:42 PM PDT 24
Peak memory 205588 kb
Host smart-a6425906-97a0-4a0f-8f3b-470ae2e977da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2433490309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2433490309
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3795642565
Short name T2794
Test name
Test status
Simulation time 85720839 ps
CPU time 2.01 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:10 PM PDT 24
Peak memory 205844 kb
Host smart-45265a95-3711-4feb-bedb-ea59786875b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3795642565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3795642565
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3835439342
Short name T2806
Test name
Test status
Simulation time 1386424147 ps
CPU time 9.07 seconds
Started Jul 07 04:49:06 PM PDT 24
Finished Jul 07 04:49:15 PM PDT 24
Peak memory 205852 kb
Host smart-fb42eb92-33d7-4e4a-ac5e-c451c585c3a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3835439342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3835439342
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1783772422
Short name T293
Test name
Test status
Simulation time 90587844 ps
CPU time 0.85 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205588 kb
Host smart-24238e2b-f82a-48dd-9f45-f80910872d5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1783772422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1783772422
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3107856127
Short name T2761
Test name
Test status
Simulation time 106010812 ps
CPU time 3.16 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 214096 kb
Host smart-3113df06-11f6-4e73-b727-03b4b3061aa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107856127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3107856127
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4071459174
Short name T302
Test name
Test status
Simulation time 74219555 ps
CPU time 1.01 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205820 kb
Host smart-0df25128-fa91-49b3-9b32-8d081e4841c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4071459174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4071459174
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1333590316
Short name T232
Test name
Test status
Simulation time 36155276 ps
CPU time 0.66 seconds
Started Jul 07 04:49:08 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205652 kb
Host smart-07ffcf49-ef81-4b10-be37-1926200a1d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1333590316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1333590316
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1214064781
Short name T292
Test name
Test status
Simulation time 97271585 ps
CPU time 2.48 seconds
Started Jul 07 04:49:08 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 214052 kb
Host smart-5250cf2f-49a6-4e50-8f2b-73534b855ea2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1214064781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1214064781
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1812200288
Short name T2778
Test name
Test status
Simulation time 102875020 ps
CPU time 2.51 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:10 PM PDT 24
Peak memory 205772 kb
Host smart-498c999a-3918-475b-b850-981b3f361647
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1812200288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1812200288
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4212351498
Short name T2792
Test name
Test status
Simulation time 94663729 ps
CPU time 1.11 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:09 PM PDT 24
Peak memory 205688 kb
Host smart-ca9454f1-1ce7-432a-b7c3-67d6b7de8824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4212351498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4212351498
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.434034948
Short name T2742
Test name
Test status
Simulation time 274569172 ps
CPU time 3.71 seconds
Started Jul 07 04:49:07 PM PDT 24
Finished Jul 07 04:49:12 PM PDT 24
Peak memory 221872 kb
Host smart-d991444d-19c6-480d-a4d2-0af9f2808841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=434034948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.434034948
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.931776776
Short name T312
Test name
Test status
Simulation time 896463185 ps
CPU time 4.8 seconds
Started Jul 07 04:49:08 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 205852 kb
Host smart-e2ec6cca-d86e-4162-92c9-8a27bac49cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=931776776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.931776776
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1872583820
Short name T2780
Test name
Test status
Simulation time 66491160 ps
CPU time 0.7 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:39 PM PDT 24
Peak memory 205628 kb
Host smart-3fd5e594-7b24-4447-8c82-d0ea84bd1698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872583820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1872583820
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4221939451
Short name T332
Test name
Test status
Simulation time 34808421 ps
CPU time 0.69 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:38 PM PDT 24
Peak memory 205636 kb
Host smart-ae22659c-bf64-4a99-abda-39ab51ec2dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4221939451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4221939451
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3503688797
Short name T323
Test name
Test status
Simulation time 31803075 ps
CPU time 0.7 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:39 PM PDT 24
Peak memory 205584 kb
Host smart-eb485978-cb97-4ea3-9e41-b42f0dd2de58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3503688797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3503688797
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3372739971
Short name T317
Test name
Test status
Simulation time 69671064 ps
CPU time 0.73 seconds
Started Jul 07 04:49:41 PM PDT 24
Finished Jul 07 04:49:42 PM PDT 24
Peak memory 205612 kb
Host smart-a21320fa-a19d-45f8-a2d2-904d4c52467e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3372739971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3372739971
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2823775959
Short name T2776
Test name
Test status
Simulation time 38486263 ps
CPU time 0.69 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:49:43 PM PDT 24
Peak memory 205620 kb
Host smart-452902de-ad7b-439b-b518-6fab8180d21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2823775959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2823775959
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4183259336
Short name T331
Test name
Test status
Simulation time 56186934 ps
CPU time 0.65 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:39 PM PDT 24
Peak memory 205632 kb
Host smart-467f1b70-b9a6-4055-922b-996be2e770c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4183259336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4183259336
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1064785462
Short name T319
Test name
Test status
Simulation time 56240204 ps
CPU time 0.74 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:49:43 PM PDT 24
Peak memory 205416 kb
Host smart-0b676407-3045-4ad8-bf89-99e31930ec23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1064785462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1064785462
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.754420452
Short name T2790
Test name
Test status
Simulation time 46229850 ps
CPU time 0.71 seconds
Started Jul 07 04:49:39 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 205604 kb
Host smart-ecadf9d0-aae1-4d74-908e-d7ea20fdab02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=754420452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.754420452
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1818036314
Short name T2753
Test name
Test status
Simulation time 41887869 ps
CPU time 0.66 seconds
Started Jul 07 04:49:39 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 205628 kb
Host smart-8b94354e-eab4-49a5-be9c-a68146764906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818036314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1818036314
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2314559833
Short name T2740
Test name
Test status
Simulation time 180122816 ps
CPU time 2.21 seconds
Started Jul 07 04:49:10 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 205808 kb
Host smart-c820cbf7-d396-4eb0-a790-f00f18a2ca2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2314559833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2314559833
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1841150372
Short name T286
Test name
Test status
Simulation time 316840359 ps
CPU time 4.3 seconds
Started Jul 07 04:49:10 PM PDT 24
Finished Jul 07 04:49:15 PM PDT 24
Peak memory 205824 kb
Host smart-145443d4-2937-4771-a4a4-508145821500
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1841150372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1841150372
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.56793217
Short name T2785
Test name
Test status
Simulation time 109501443 ps
CPU time 0.94 seconds
Started Jul 07 04:49:11 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 205628 kb
Host smart-f6be71c8-93c2-4308-a4d3-7509e93129ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=56793217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.56793217
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1960419498
Short name T2758
Test name
Test status
Simulation time 207847008 ps
CPU time 2.01 seconds
Started Jul 07 04:49:10 PM PDT 24
Finished Jul 07 04:49:13 PM PDT 24
Peak memory 214104 kb
Host smart-92efbbf1-3ba9-4ce0-b514-a7a118d916bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960419498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1960419498
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2893787481
Short name T303
Test name
Test status
Simulation time 77955381 ps
CPU time 1.06 seconds
Started Jul 07 04:49:09 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 205800 kb
Host smart-6b54e11b-7bda-4db1-bc55-c8b552494676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2893787481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2893787481
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3828490062
Short name T2811
Test name
Test status
Simulation time 62904853 ps
CPU time 0.72 seconds
Started Jul 07 04:49:10 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 205628 kb
Host smart-e1909b0b-d1c9-4602-93ef-189a619becb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3828490062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3828490062
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3904262948
Short name T291
Test name
Test status
Simulation time 171873117 ps
CPU time 2.57 seconds
Started Jul 07 04:49:10 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 214040 kb
Host smart-51734371-1363-40b6-a511-285175850454
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3904262948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3904262948
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1742257883
Short name T2760
Test name
Test status
Simulation time 712081889 ps
CPU time 4.92 seconds
Started Jul 07 04:49:12 PM PDT 24
Finished Jul 07 04:49:18 PM PDT 24
Peak memory 205776 kb
Host smart-e461d8d5-32dc-4a92-8ab9-0ca54bbdf5b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1742257883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1742257883
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2602655903
Short name T2734
Test name
Test status
Simulation time 167784827 ps
CPU time 1.38 seconds
Started Jul 07 04:49:12 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 205780 kb
Host smart-e2f73706-217d-435d-89e0-717877733dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2602655903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2602655903
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3762693740
Short name T2747
Test name
Test status
Simulation time 203555859 ps
CPU time 2.69 seconds
Started Jul 07 04:49:06 PM PDT 24
Finished Jul 07 04:49:10 PM PDT 24
Peak memory 222064 kb
Host smart-95d44d43-1084-41b9-8f0f-62e973d88965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762693740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3762693740
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3300937737
Short name T337
Test name
Test status
Simulation time 711236875 ps
CPU time 3.08 seconds
Started Jul 07 04:49:11 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 205780 kb
Host smart-88091c35-2232-487e-8efb-529cdf315eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3300937737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3300937737
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2006137152
Short name T2808
Test name
Test status
Simulation time 109327050 ps
CPU time 0.78 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:39 PM PDT 24
Peak memory 206044 kb
Host smart-2fcec942-6337-4fc4-ad6f-d1525ddddc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2006137152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2006137152
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3656553978
Short name T2793
Test name
Test status
Simulation time 58347004 ps
CPU time 0.72 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:39 PM PDT 24
Peak memory 205624 kb
Host smart-9e0cefcc-2f83-4b2d-bd9a-7a040220215c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3656553978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3656553978
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1614287429
Short name T2809
Test name
Test status
Simulation time 44153340 ps
CPU time 0.7 seconds
Started Jul 07 04:49:41 PM PDT 24
Finished Jul 07 04:49:42 PM PDT 24
Peak memory 205620 kb
Host smart-c594d469-6856-4b22-ae01-61e419da5ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1614287429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1614287429
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.57017953
Short name T2779
Test name
Test status
Simulation time 36638359 ps
CPU time 0.68 seconds
Started Jul 07 04:49:39 PM PDT 24
Finished Jul 07 04:49:40 PM PDT 24
Peak memory 205648 kb
Host smart-973cd53c-8412-4911-9a3a-1d509ec75432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57017953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.57017953
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.660131540
Short name T2802
Test name
Test status
Simulation time 46047566 ps
CPU time 0.7 seconds
Started Jul 07 04:49:38 PM PDT 24
Finished Jul 07 04:49:39 PM PDT 24
Peak memory 205612 kb
Host smart-a0869de4-185a-4aff-9c13-ae050cf6d7ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=660131540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.660131540
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.730084268
Short name T234
Test name
Test status
Simulation time 36273101 ps
CPU time 0.62 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:49:53 PM PDT 24
Peak memory 205404 kb
Host smart-9427cbf7-5e14-4350-a196-1c63306a0c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=730084268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.730084268
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4260079323
Short name T322
Test name
Test status
Simulation time 40397228 ps
CPU time 0.67 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:49:50 PM PDT 24
Peak memory 205592 kb
Host smart-371343c8-2d5f-44f7-adc2-c6bf2f3756d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4260079323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4260079323
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2723239749
Short name T333
Test name
Test status
Simulation time 47927441 ps
CPU time 0.71 seconds
Started Jul 07 04:49:44 PM PDT 24
Finished Jul 07 04:49:45 PM PDT 24
Peak memory 205624 kb
Host smart-77ce85be-3177-445b-8354-96ae14eff16f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2723239749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2723239749
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3721108904
Short name T329
Test name
Test status
Simulation time 40522069 ps
CPU time 0.73 seconds
Started Jul 07 04:49:46 PM PDT 24
Finished Jul 07 04:49:47 PM PDT 24
Peak memory 205632 kb
Host smart-efd09115-2e6a-4b20-ab99-2e8f54b684c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3721108904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3721108904
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.837387155
Short name T231
Test name
Test status
Simulation time 69774774 ps
CPU time 0.75 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:49:43 PM PDT 24
Peak memory 205608 kb
Host smart-6c38baec-0ea7-4093-b661-32b82322d694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=837387155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.837387155
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.10613633
Short name T265
Test name
Test status
Simulation time 102806073 ps
CPU time 1.28 seconds
Started Jul 07 04:49:15 PM PDT 24
Finished Jul 07 04:49:17 PM PDT 24
Peak memory 214104 kb
Host smart-765d76dc-cb26-4a66-ac7c-0e20174589ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10613633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_
csr_mem_rw_with_rand_reset.10613633
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3263081349
Short name T2814
Test name
Test status
Simulation time 40275191 ps
CPU time 0.82 seconds
Started Jul 07 04:49:12 PM PDT 24
Finished Jul 07 04:49:14 PM PDT 24
Peak memory 205632 kb
Host smart-5062c6ed-f348-4bda-b4d7-7761417a9c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3263081349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3263081349
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3120156270
Short name T334
Test name
Test status
Simulation time 36210841 ps
CPU time 0.71 seconds
Started Jul 07 04:49:09 PM PDT 24
Finished Jul 07 04:49:11 PM PDT 24
Peak memory 205612 kb
Host smart-b80eb9a3-fc31-4071-8717-356dec11b4e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3120156270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3120156270
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.167074815
Short name T305
Test name
Test status
Simulation time 136833321 ps
CPU time 1.56 seconds
Started Jul 07 04:49:16 PM PDT 24
Finished Jul 07 04:49:18 PM PDT 24
Peak memory 205796 kb
Host smart-32998d06-7dff-4ab8-878a-00f65e8a06a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=167074815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.167074815
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.743394312
Short name T2768
Test name
Test status
Simulation time 231876199 ps
CPU time 3.02 seconds
Started Jul 07 04:49:12 PM PDT 24
Finished Jul 07 04:49:16 PM PDT 24
Peak memory 214044 kb
Host smart-8ec541c4-bee9-4e7d-9121-e26b15cc631a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=743394312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.743394312
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2717801285
Short name T2795
Test name
Test status
Simulation time 604188573 ps
CPU time 3.24 seconds
Started Jul 07 04:49:12 PM PDT 24
Finished Jul 07 04:49:16 PM PDT 24
Peak memory 205884 kb
Host smart-534bf3c3-fe45-470d-96fb-65be8e3dcc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2717801285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2717801285
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1831056725
Short name T313
Test name
Test status
Simulation time 92643284 ps
CPU time 1.26 seconds
Started Jul 07 04:49:14 PM PDT 24
Finished Jul 07 04:49:16 PM PDT 24
Peak memory 214068 kb
Host smart-bd5021e6-8af9-4582-921c-28389d4a870e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831056725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1831056725
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3293875475
Short name T283
Test name
Test status
Simulation time 76043419 ps
CPU time 1.04 seconds
Started Jul 07 04:49:16 PM PDT 24
Finished Jul 07 04:49:18 PM PDT 24
Peak memory 205768 kb
Host smart-98b86999-c536-4d72-9ff4-4d5cc1fa792b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3293875475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3293875475
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3517684242
Short name T321
Test name
Test status
Simulation time 193263867 ps
CPU time 1.62 seconds
Started Jul 07 04:49:18 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 205840 kb
Host smart-7b866f2f-e6e7-48d0-b025-59f88065fc16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3517684242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3517684242
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.4181100378
Short name T2723
Test name
Test status
Simulation time 143144060 ps
CPU time 2.09 seconds
Started Jul 07 04:49:17 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 205880 kb
Host smart-d274d4dc-281d-4d35-8580-61e00d5644f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4181100378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.4181100378
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4180280321
Short name T2813
Test name
Test status
Simulation time 351987666 ps
CPU time 2.83 seconds
Started Jul 07 04:49:16 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 205764 kb
Host smart-729136ba-9e86-420c-9034-f55b9f84391e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4180280321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.4180280321
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2572376346
Short name T310
Test name
Test status
Simulation time 305161454 ps
CPU time 2.1 seconds
Started Jul 07 04:49:14 PM PDT 24
Finished Jul 07 04:49:17 PM PDT 24
Peak memory 214072 kb
Host smart-c44e8adb-5460-495c-8cf8-0a2cb77152ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572376346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2572376346
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3398153287
Short name T2774
Test name
Test status
Simulation time 82184594 ps
CPU time 0.84 seconds
Started Jul 07 04:49:15 PM PDT 24
Finished Jul 07 04:49:16 PM PDT 24
Peak memory 205684 kb
Host smart-97d298e5-0ba6-4765-b0eb-e270cad071e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3398153287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3398153287
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4254047558
Short name T2762
Test name
Test status
Simulation time 191475831 ps
CPU time 1.67 seconds
Started Jul 07 04:49:17 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 205756 kb
Host smart-b4b187c1-9302-42f6-b055-ac60f1e05dff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4254047558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.4254047558
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3559853838
Short name T2727
Test name
Test status
Simulation time 113915732 ps
CPU time 3.03 seconds
Started Jul 07 04:49:18 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 221460 kb
Host smart-ec4c7d89-c90f-4101-ad66-98d15680311b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3559853838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3559853838
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3024166076
Short name T339
Test name
Test status
Simulation time 598425529 ps
CPU time 4.13 seconds
Started Jul 07 04:49:16 PM PDT 24
Finished Jul 07 04:49:20 PM PDT 24
Peak memory 205844 kb
Host smart-060a3bf2-2eef-455f-a524-fef930de742a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3024166076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3024166076
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1670249187
Short name T2730
Test name
Test status
Simulation time 91195683 ps
CPU time 1.32 seconds
Started Jul 07 04:49:19 PM PDT 24
Finished Jul 07 04:49:20 PM PDT 24
Peak memory 214088 kb
Host smart-b6fbdaff-5121-41cd-9fe1-949fd9623df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670249187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1670249187
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.195138364
Short name T289
Test name
Test status
Simulation time 43043840 ps
CPU time 0.85 seconds
Started Jul 07 04:49:16 PM PDT 24
Finished Jul 07 04:49:18 PM PDT 24
Peak memory 205628 kb
Host smart-fd6566e5-b150-489e-84b2-64e8e5e73707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=195138364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.195138364
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1378419257
Short name T2789
Test name
Test status
Simulation time 115052305 ps
CPU time 0.78 seconds
Started Jul 07 04:49:19 PM PDT 24
Finished Jul 07 04:49:20 PM PDT 24
Peak memory 205608 kb
Host smart-5adb3be8-938f-4899-b8b0-5d942f6f5637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1378419257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1378419257
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.388966598
Short name T2784
Test name
Test status
Simulation time 94737630 ps
CPU time 1.08 seconds
Started Jul 07 04:49:17 PM PDT 24
Finished Jul 07 04:49:19 PM PDT 24
Peak memory 205764 kb
Host smart-5f465c45-d3a1-45d0-aab3-3ed8b229630a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=388966598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.388966598
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1439339407
Short name T2725
Test name
Test status
Simulation time 203054991 ps
CPU time 2.69 seconds
Started Jul 07 04:49:18 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 221612 kb
Host smart-09d944c7-eef1-47e9-a24a-fc7d6b970db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1439339407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1439339407
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2204060152
Short name T340
Test name
Test status
Simulation time 638862128 ps
CPU time 2.92 seconds
Started Jul 07 04:49:18 PM PDT 24
Finished Jul 07 04:49:21 PM PDT 24
Peak memory 205772 kb
Host smart-b2da496c-b5d9-43c7-8b85-e3246dd4f93b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2204060152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2204060152
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3668789670
Short name T2749
Test name
Test status
Simulation time 96465593 ps
CPU time 1.22 seconds
Started Jul 07 04:49:21 PM PDT 24
Finished Jul 07 04:49:23 PM PDT 24
Peak memory 214488 kb
Host smart-3eea7e01-068b-4b02-ab3b-247a85ac4d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668789670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3668789670
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2100943210
Short name T243
Test name
Test status
Simulation time 86337727 ps
CPU time 1 seconds
Started Jul 07 04:49:20 PM PDT 24
Finished Jul 07 04:49:22 PM PDT 24
Peak memory 205808 kb
Host smart-b3140269-639a-4c86-b67b-0f752e1b57b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2100943210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2100943210
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1838242597
Short name T2741
Test name
Test status
Simulation time 43565234 ps
CPU time 0.74 seconds
Started Jul 07 04:49:23 PM PDT 24
Finished Jul 07 04:49:24 PM PDT 24
Peak memory 205580 kb
Host smart-d60ba8e6-9645-4eb6-8ab1-ff1dd5b2b60b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1838242597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1838242597
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1420312161
Short name T2731
Test name
Test status
Simulation time 201056704 ps
CPU time 1.65 seconds
Started Jul 07 04:49:20 PM PDT 24
Finished Jul 07 04:49:22 PM PDT 24
Peak memory 205776 kb
Host smart-3a72747d-a945-4aeb-9acf-9017a06c1ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1420312161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1420312161
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.702975607
Short name T248
Test name
Test status
Simulation time 165565397 ps
CPU time 2.51 seconds
Started Jul 07 04:49:14 PM PDT 24
Finished Jul 07 04:49:17 PM PDT 24
Peak memory 221308 kb
Host smart-03c982b5-11fb-4323-867e-c663d9611717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702975607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.702975607
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2790018022
Short name T2752
Test name
Test status
Simulation time 467561845 ps
CPU time 2.85 seconds
Started Jul 07 04:49:21 PM PDT 24
Finished Jul 07 04:49:24 PM PDT 24
Peak memory 205832 kb
Host smart-ef40064f-722c-4970-a86a-a78c782979ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2790018022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2790018022
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1128127619
Short name T1052
Test name
Test status
Simulation time 4225236907 ps
CPU time 4.7 seconds
Started Jul 07 05:18:26 PM PDT 24
Finished Jul 07 05:18:31 PM PDT 24
Peak memory 206212 kb
Host smart-c9dbe57f-55b8-4054-9e4b-3f09f47cb65a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1128127619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.1128127619
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.48468904
Short name T2154
Test name
Test status
Simulation time 13392080753 ps
CPU time 12.35 seconds
Started Jul 07 05:18:26 PM PDT 24
Finished Jul 07 05:18:38 PM PDT 24
Peak memory 206156 kb
Host smart-4a65d7b5-8700-4596-b10b-cba9f1197f7d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=48468904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.48468904
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1648956781
Short name T1695
Test name
Test status
Simulation time 23330451069 ps
CPU time 24 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:18:55 PM PDT 24
Peak memory 206220 kb
Host smart-9fdd54af-698b-444f-b69a-bc506f3653d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1648956781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.1648956781
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4280397832
Short name T691
Test name
Test status
Simulation time 157963074 ps
CPU time 0.79 seconds
Started Jul 07 05:18:35 PM PDT 24
Finished Jul 07 05:18:36 PM PDT 24
Peak memory 206120 kb
Host smart-48f3a736-7bf1-4eeb-8284-0023e550204f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42803
97832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4280397832
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.813880074
Short name T55
Test name
Test status
Simulation time 156416544 ps
CPU time 0.81 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:18:31 PM PDT 24
Peak memory 206148 kb
Host smart-a1d45c9d-1dbe-4132-b2f4-17d7baef2c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81388
0074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.813880074
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1160077620
Short name T74
Test name
Test status
Simulation time 160937924 ps
CPU time 0.77 seconds
Started Jul 07 05:18:31 PM PDT 24
Finished Jul 07 05:18:32 PM PDT 24
Peak memory 206208 kb
Host smart-86c6c39a-5879-4090-91ad-5ddfc0d2da96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11600
77620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1160077620
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2043430584
Short name T672
Test name
Test status
Simulation time 530944661 ps
CPU time 1.3 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:18:32 PM PDT 24
Peak memory 206112 kb
Host smart-9efbcb15-82cb-46a2-be4f-be574316ba3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20434
30584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2043430584
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2102379926
Short name T1335
Test name
Test status
Simulation time 19666173008 ps
CPU time 40.63 seconds
Started Jul 07 05:18:38 PM PDT 24
Finished Jul 07 05:19:19 PM PDT 24
Peak memory 206504 kb
Host smart-8e1ff376-8cfc-4d52-917a-e9b019d2b501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
79926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2102379926
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3811483133
Short name T1219
Test name
Test status
Simulation time 500589891 ps
CPU time 1.4 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:18:32 PM PDT 24
Peak memory 206132 kb
Host smart-5b7680a0-5b7d-4242-9866-64ae1d2e6db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
83133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3811483133
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.950069076
Short name T2119
Test name
Test status
Simulation time 149249655 ps
CPU time 0.77 seconds
Started Jul 07 05:18:35 PM PDT 24
Finished Jul 07 05:18:36 PM PDT 24
Peak memory 206116 kb
Host smart-e7d4748e-973d-406a-8fe8-45cb45fa5bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95006
9076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.950069076
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.566369691
Short name T1793
Test name
Test status
Simulation time 5183651376 ps
CPU time 43.25 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:19:13 PM PDT 24
Peak memory 206336 kb
Host smart-9eb2a6f3-8133-4f5e-a78c-48b95eaf82ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56636
9691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.566369691
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1322805929
Short name T1909
Test name
Test status
Simulation time 124804109 ps
CPU time 0.75 seconds
Started Jul 07 05:18:39 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 206188 kb
Host smart-19c0dd25-2d6a-43fd-8230-d454d8ad3104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
05929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1322805929
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3667154715
Short name T1088
Test name
Test status
Simulation time 823349486 ps
CPU time 2 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:18:33 PM PDT 24
Peak memory 206400 kb
Host smart-7ac6e49c-b2f6-4c33-ba5f-2fc1f2a9f4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36671
54715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3667154715
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.576160472
Short name T1066
Test name
Test status
Simulation time 302942095 ps
CPU time 2.21 seconds
Started Jul 07 05:18:32 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 206344 kb
Host smart-1f666d29-601b-476a-baac-0b47d13a4bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57616
0472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.576160472
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.4076803919
Short name T735
Test name
Test status
Simulation time 102192738985 ps
CPU time 152.58 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206680 kb
Host smart-a37edef6-5b26-40e2-8a70-b5f546a0ba5f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4076803919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.4076803919
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.1624364960
Short name T2401
Test name
Test status
Simulation time 98370969530 ps
CPU time 136.88 seconds
Started Jul 07 05:18:34 PM PDT 24
Finished Jul 07 05:20:51 PM PDT 24
Peak memory 206460 kb
Host smart-8c60d2ce-07c4-4084-8dfe-180d005c658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624364960 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1624364960
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1739274106
Short name T756
Test name
Test status
Simulation time 119095997186 ps
CPU time 150.18 seconds
Started Jul 07 05:18:34 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206432 kb
Host smart-a0ac9a3a-da7a-4935-8f3e-994d87a96a6c
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1739274106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1739274106
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2948625524
Short name T1173
Test name
Test status
Simulation time 91161696333 ps
CPU time 111.92 seconds
Started Jul 07 05:18:34 PM PDT 24
Finished Jul 07 05:20:27 PM PDT 24
Peak memory 206448 kb
Host smart-d1afbe45-98cc-434b-82e6-f1a5dcbda3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948625524 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2948625524
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.4130194243
Short name T1515
Test name
Test status
Simulation time 113184104642 ps
CPU time 140.13 seconds
Started Jul 07 05:18:37 PM PDT 24
Finished Jul 07 05:20:58 PM PDT 24
Peak memory 206404 kb
Host smart-de52c4e6-8443-4e68-8451-8ed2a2141544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41301
94243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.4130194243
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1435216265
Short name T2198
Test name
Test status
Simulation time 196728403 ps
CPU time 0.93 seconds
Started Jul 07 05:18:35 PM PDT 24
Finished Jul 07 05:18:36 PM PDT 24
Peak memory 206152 kb
Host smart-4344671d-6118-4157-b190-a061fc3b4e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
16265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1435216265
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3075533763
Short name T126
Test name
Test status
Simulation time 140136755 ps
CPU time 0.74 seconds
Started Jul 07 05:18:39 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 206180 kb
Host smart-c9b9c427-aaa4-4398-b446-76a52b39a4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
33763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3075533763
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3761060480
Short name T2040
Test name
Test status
Simulation time 240884278 ps
CPU time 0.92 seconds
Started Jul 07 05:18:37 PM PDT 24
Finished Jul 07 05:18:39 PM PDT 24
Peak memory 206180 kb
Host smart-2e4b142c-87c1-481c-a676-7b47423fdc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
60480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3761060480
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1209567071
Short name T1417
Test name
Test status
Simulation time 7124828374 ps
CPU time 49.87 seconds
Started Jul 07 05:18:39 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206484 kb
Host smart-c629b885-fa17-4a25-8ddf-feb8ffd48548
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1209567071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1209567071
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.4166093210
Short name T645
Test name
Test status
Simulation time 237321107 ps
CPU time 0.91 seconds
Started Jul 07 05:18:35 PM PDT 24
Finished Jul 07 05:18:36 PM PDT 24
Peak memory 206188 kb
Host smart-1e9ee522-bba6-4a37-a91d-a02207e1d103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41660
93210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.4166093210
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1726715143
Short name T71
Test name
Test status
Simulation time 487474167 ps
CPU time 1.35 seconds
Started Jul 07 05:18:35 PM PDT 24
Finished Jul 07 05:18:37 PM PDT 24
Peak memory 206208 kb
Host smart-98d6fa25-6bb3-4ce6-8d24-b1a4e98b635c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267
15143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1726715143
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.3793247064
Short name T1536
Test name
Test status
Simulation time 23279807005 ps
CPU time 22.85 seconds
Started Jul 07 05:18:40 PM PDT 24
Finished Jul 07 05:19:03 PM PDT 24
Peak memory 206228 kb
Host smart-1a341d81-b053-4a78-9042-0bc42d9f957b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932
47064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.3793247064
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3298044022
Short name T1156
Test name
Test status
Simulation time 3360314331 ps
CPU time 3.82 seconds
Started Jul 07 05:18:41 PM PDT 24
Finished Jul 07 05:18:45 PM PDT 24
Peak memory 206188 kb
Host smart-a6331c95-6758-4ee7-abfe-b97d2e3f9a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32980
44022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3298044022
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3577884259
Short name T980
Test name
Test status
Simulation time 9620662414 ps
CPU time 92.48 seconds
Started Jul 07 05:18:44 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206512 kb
Host smart-441f9ad2-f9c7-4391-9cec-eb6ed1f9bbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35778
84259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3577884259
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3036083056
Short name T849
Test name
Test status
Simulation time 3914334456 ps
CPU time 40.12 seconds
Started Jul 07 05:18:44 PM PDT 24
Finished Jul 07 05:19:25 PM PDT 24
Peak memory 206480 kb
Host smart-dd38baa0-7de8-4604-989f-70326cd14596
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3036083056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3036083056
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1511490061
Short name T2271
Test name
Test status
Simulation time 253256569 ps
CPU time 0.88 seconds
Started Jul 07 05:18:41 PM PDT 24
Finished Jul 07 05:18:42 PM PDT 24
Peak memory 206096 kb
Host smart-481cb70f-4374-4402-b8fc-a33d6b90f36d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1511490061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1511490061
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1731603563
Short name T868
Test name
Test status
Simulation time 237229640 ps
CPU time 0.87 seconds
Started Jul 07 05:18:39 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 206156 kb
Host smart-384fd387-e867-41db-99d8-d0766b0c4822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
03563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1731603563
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.4255543289
Short name T1204
Test name
Test status
Simulation time 4012809226 ps
CPU time 35.14 seconds
Started Jul 07 05:18:37 PM PDT 24
Finished Jul 07 05:19:13 PM PDT 24
Peak memory 206372 kb
Host smart-c63feb61-d21a-4915-8a2a-d24af6d630ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
43289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.4255543289
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2496503614
Short name T1049
Test name
Test status
Simulation time 5039090742 ps
CPU time 48.14 seconds
Started Jul 07 05:18:41 PM PDT 24
Finished Jul 07 05:19:30 PM PDT 24
Peak memory 206352 kb
Host smart-c9263682-0ff0-4550-bff4-29cfe7596677
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2496503614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2496503614
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2477719645
Short name T2378
Test name
Test status
Simulation time 149550557 ps
CPU time 0.78 seconds
Started Jul 07 05:18:39 PM PDT 24
Finished Jul 07 05:18:41 PM PDT 24
Peak memory 206188 kb
Host smart-396987f2-5e06-4795-bceb-cd80f82ccba2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2477719645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2477719645
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3944415510
Short name T386
Test name
Test status
Simulation time 137797605 ps
CPU time 0.8 seconds
Started Jul 07 05:18:53 PM PDT 24
Finished Jul 07 05:18:55 PM PDT 24
Peak memory 206120 kb
Host smart-4ad8b900-b0ca-4881-88d7-44f35dc43daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
15510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3944415510
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.964810549
Short name T69
Test name
Test status
Simulation time 479022294 ps
CPU time 1.25 seconds
Started Jul 07 05:18:47 PM PDT 24
Finished Jul 07 05:18:48 PM PDT 24
Peak memory 206180 kb
Host smart-177405d3-b341-4960-9987-1e3e904ccc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96481
0549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.964810549
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.531006508
Short name T1632
Test name
Test status
Simulation time 195982957 ps
CPU time 0.84 seconds
Started Jul 07 05:18:43 PM PDT 24
Finished Jul 07 05:18:44 PM PDT 24
Peak memory 206112 kb
Host smart-e78ef0dc-6aeb-4aef-b0f0-f0dc132ff2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53100
6508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.531006508
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1320546818
Short name T2173
Test name
Test status
Simulation time 193435568 ps
CPU time 0.85 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206168 kb
Host smart-f6b6a056-227b-456d-91b0-ac0a406e9879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
46818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1320546818
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.4179135066
Short name T1423
Test name
Test status
Simulation time 171788042 ps
CPU time 0.86 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206156 kb
Host smart-f8325d61-eb9d-4d7d-8264-9c773191e9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41791
35066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.4179135066
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2058443959
Short name T802
Test name
Test status
Simulation time 164790243 ps
CPU time 0.81 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206164 kb
Host smart-0dcb392f-12e1-4158-8a19-5df090e55c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584
43959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2058443959
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2283229757
Short name T1399
Test name
Test status
Simulation time 155327534 ps
CPU time 0.81 seconds
Started Jul 07 05:18:50 PM PDT 24
Finished Jul 07 05:18:51 PM PDT 24
Peak memory 206136 kb
Host smart-1f155aed-4f2b-42cc-873f-686f7fa39cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22832
29757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2283229757
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1616686286
Short name T1446
Test name
Test status
Simulation time 215767418 ps
CPU time 0.95 seconds
Started Jul 07 05:18:49 PM PDT 24
Finished Jul 07 05:18:50 PM PDT 24
Peak memory 206176 kb
Host smart-522149ef-48c0-4f17-9316-feead40a52ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1616686286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1616686286
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1644924535
Short name T1470
Test name
Test status
Simulation time 222792636 ps
CPU time 0.94 seconds
Started Jul 07 05:18:48 PM PDT 24
Finished Jul 07 05:18:50 PM PDT 24
Peak memory 206188 kb
Host smart-8ff272b2-dc23-410e-ae93-718b38ba070d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
24535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1644924535
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3652818255
Short name T594
Test name
Test status
Simulation time 222259320 ps
CPU time 0.95 seconds
Started Jul 07 05:18:48 PM PDT 24
Finished Jul 07 05:18:49 PM PDT 24
Peak memory 206092 kb
Host smart-5ed18aea-be47-4018-bf4a-df6680a9ec01
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3652818255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3652818255
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1866047103
Short name T2232
Test name
Test status
Simulation time 229419319 ps
CPU time 0.91 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206176 kb
Host smart-f209bc4f-feca-4aec-aebc-fea130e82cd5
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1866047103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1866047103
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2844285137
Short name T1607
Test name
Test status
Simulation time 155782815 ps
CPU time 0.81 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206160 kb
Host smart-4a676a76-823b-403b-a1d7-cf2e385895b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442
85137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2844285137
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3206142020
Short name T1887
Test name
Test status
Simulation time 70804240 ps
CPU time 0.7 seconds
Started Jul 07 05:18:55 PM PDT 24
Finished Jul 07 05:18:56 PM PDT 24
Peak memory 206184 kb
Host smart-8588de30-c389-4022-9388-47416f08b68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32061
42020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3206142020
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.4076713180
Short name T307
Test name
Test status
Simulation time 11419533256 ps
CPU time 27.85 seconds
Started Jul 07 05:18:52 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206536 kb
Host smart-a008493e-d25e-437d-995c-e9af55e29436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
13180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.4076713180
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1508641229
Short name T2237
Test name
Test status
Simulation time 191334635 ps
CPU time 0.86 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 206164 kb
Host smart-e0b8334b-5b69-4d58-af85-f8d997e5df94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15086
41229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1508641229
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2305171647
Short name T2466
Test name
Test status
Simulation time 236201005 ps
CPU time 0.89 seconds
Started Jul 07 05:18:49 PM PDT 24
Finished Jul 07 05:18:50 PM PDT 24
Peak memory 206188 kb
Host smart-6f90c2aa-3782-4fe7-877b-723d652dd95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23051
71647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2305171647
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1638160428
Short name T2380
Test name
Test status
Simulation time 10131543886 ps
CPU time 69.07 seconds
Started Jul 07 05:18:51 PM PDT 24
Finished Jul 07 05:20:00 PM PDT 24
Peak memory 206352 kb
Host smart-d9ed7878-a44f-4aa2-854c-a198c631f979
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1638160428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1638160428
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3045642719
Short name T815
Test name
Test status
Simulation time 12199709401 ps
CPU time 91.58 seconds
Started Jul 07 05:18:50 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206388 kb
Host smart-c6f30f5e-8d07-43a5-8835-c372d4d41e10
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3045642719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3045642719
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2087641107
Short name T1213
Test name
Test status
Simulation time 14467065594 ps
CPU time 302.78 seconds
Started Jul 07 05:18:50 PM PDT 24
Finished Jul 07 05:23:53 PM PDT 24
Peak memory 206364 kb
Host smart-dffc1944-65e2-4d1d-9305-9a4e45140570
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2087641107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2087641107
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2731864132
Short name T894
Test name
Test status
Simulation time 207904804 ps
CPU time 0.83 seconds
Started Jul 07 05:18:50 PM PDT 24
Finished Jul 07 05:18:51 PM PDT 24
Peak memory 206120 kb
Host smart-4e297094-79f9-4e20-8cf5-5d2820129c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318
64132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2731864132
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.750861549
Short name T1666
Test name
Test status
Simulation time 176357638 ps
CPU time 0.79 seconds
Started Jul 07 05:18:49 PM PDT 24
Finished Jul 07 05:18:50 PM PDT 24
Peak memory 206068 kb
Host smart-a10ecbeb-6c76-46aa-882a-37d448b5534c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75086
1549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.750861549
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.803042023
Short name T1834
Test name
Test status
Simulation time 221945187 ps
CPU time 0.83 seconds
Started Jul 07 05:18:53 PM PDT 24
Finished Jul 07 05:18:54 PM PDT 24
Peak memory 206196 kb
Host smart-1e4dc4ee-69c0-4cde-9bbe-efdbb2288932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80304
2023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.803042023
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.346589490
Short name T1085
Test name
Test status
Simulation time 308970373 ps
CPU time 1 seconds
Started Jul 07 05:18:55 PM PDT 24
Finished Jul 07 05:18:56 PM PDT 24
Peak memory 206188 kb
Host smart-ee8f9e5c-8107-40da-87df-b7e381d53ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34658
9490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.346589490
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1102870592
Short name T1445
Test name
Test status
Simulation time 155150954 ps
CPU time 0.78 seconds
Started Jul 07 05:18:58 PM PDT 24
Finished Jul 07 05:18:58 PM PDT 24
Peak memory 206176 kb
Host smart-6d80fe50-d1c0-4744-82eb-f928888d28c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
70592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1102870592
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1348949160
Short name T366
Test name
Test status
Simulation time 148087957 ps
CPU time 0.76 seconds
Started Jul 07 05:18:53 PM PDT 24
Finished Jul 07 05:18:54 PM PDT 24
Peak memory 206152 kb
Host smart-602e7d55-15b7-45a2-b4c2-cb7a8e25422b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
49160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1348949160
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3634787491
Short name T705
Test name
Test status
Simulation time 245970150 ps
CPU time 0.93 seconds
Started Jul 07 05:18:56 PM PDT 24
Finished Jul 07 05:18:57 PM PDT 24
Peak memory 206192 kb
Host smart-f72623b8-6b7d-4bb1-9a0f-634fb3c0ab74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36347
87491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3634787491
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3471586554
Short name T836
Test name
Test status
Simulation time 5182217544 ps
CPU time 37.35 seconds
Started Jul 07 05:18:54 PM PDT 24
Finished Jul 07 05:19:32 PM PDT 24
Peak memory 206420 kb
Host smart-71b51094-c307-4d11-90f5-8437716da03d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3471586554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3471586554
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2615042601
Short name T1045
Test name
Test status
Simulation time 217725331 ps
CPU time 0.85 seconds
Started Jul 07 05:18:56 PM PDT 24
Finished Jul 07 05:18:57 PM PDT 24
Peak memory 206192 kb
Host smart-06793e32-7fdc-492f-b4d0-450ecb03ea63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
42601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2615042601
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2969871458
Short name T114
Test name
Test status
Simulation time 174903686 ps
CPU time 0.83 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:19:15 PM PDT 24
Peak memory 206112 kb
Host smart-c27a292a-9d5c-4ab9-8f4e-ad9594975b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
71458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2969871458
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1588961440
Short name T407
Test name
Test status
Simulation time 311153034 ps
CPU time 1.06 seconds
Started Jul 07 05:18:59 PM PDT 24
Finished Jul 07 05:19:00 PM PDT 24
Peak memory 206188 kb
Host smart-49409c8b-79cc-4517-bdbf-db22ba43cac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15889
61440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1588961440
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.4239731687
Short name T1207
Test name
Test status
Simulation time 4722203478 ps
CPU time 33.77 seconds
Started Jul 07 05:19:00 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206496 kb
Host smart-d8c3fb96-9c0c-44de-8537-3b202e1abc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42397
31687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.4239731687
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3765057551
Short name T1341
Test name
Test status
Simulation time 16283231278 ps
CPU time 84.84 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:20:38 PM PDT 24
Peak memory 206368 kb
Host smart-fd19156d-8d41-4694-b066-6c210e6fc376
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3765057551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3765057551
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1132396984
Short name T888
Test name
Test status
Simulation time 73438883 ps
CPU time 0.71 seconds
Started Jul 07 05:19:17 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206216 kb
Host smart-dc282ed4-018a-465d-a3f8-a971defc0e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1132396984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1132396984
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.135856365
Short name T1374
Test name
Test status
Simulation time 3803977707 ps
CPU time 5.35 seconds
Started Jul 07 05:19:00 PM PDT 24
Finished Jul 07 05:19:06 PM PDT 24
Peak memory 206496 kb
Host smart-f7d0e5cd-e58a-4826-802a-293557da1ffb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=135856365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.135856365
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.4125080455
Short name T642
Test name
Test status
Simulation time 13321975661 ps
CPU time 11.85 seconds
Started Jul 07 05:18:58 PM PDT 24
Finished Jul 07 05:19:10 PM PDT 24
Peak memory 206344 kb
Host smart-f1c5bb47-dfd9-46f8-9e12-483798919efd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4125080455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.4125080455
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3711561914
Short name T2487
Test name
Test status
Simulation time 23309352415 ps
CPU time 21.58 seconds
Started Jul 07 05:18:56 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206460 kb
Host smart-142d18d9-309a-4ffe-9748-df1665d4ea11
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3711561914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3711561914
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2742986339
Short name T389
Test name
Test status
Simulation time 160357202 ps
CPU time 0.84 seconds
Started Jul 07 05:19:00 PM PDT 24
Finished Jul 07 05:19:01 PM PDT 24
Peak memory 206192 kb
Host smart-fb686aab-9983-4222-83bb-14cefa78997b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27429
86339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2742986339
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1510617016
Short name T1255
Test name
Test status
Simulation time 166811356 ps
CPU time 0.76 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:19:15 PM PDT 24
Peak memory 206116 kb
Host smart-25dcc656-d232-4ae9-9f13-da791db16c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15106
17016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1510617016
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2615588735
Short name T1301
Test name
Test status
Simulation time 229163310 ps
CPU time 0.93 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:19:14 PM PDT 24
Peak memory 206112 kb
Host smart-f99d5582-f1e3-45a8-8f90-989f84411230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26155
88735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2615588735
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1099627810
Short name T1833
Test name
Test status
Simulation time 1159707820 ps
CPU time 2.51 seconds
Started Jul 07 05:19:04 PM PDT 24
Finished Jul 07 05:19:07 PM PDT 24
Peak memory 206144 kb
Host smart-c65812ab-22b0-4537-8cb9-d16b0ba8ece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10996
27810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1099627810
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2232813765
Short name T1186
Test name
Test status
Simulation time 360551054 ps
CPU time 1.21 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:19:15 PM PDT 24
Peak memory 206116 kb
Host smart-1f52f386-7f47-4e69-9767-ab2d75badf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22328
13765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2232813765
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.659932578
Short name T1565
Test name
Test status
Simulation time 155377218 ps
CPU time 0.77 seconds
Started Jul 07 05:19:05 PM PDT 24
Finished Jul 07 05:19:06 PM PDT 24
Peak memory 206164 kb
Host smart-0d39f28f-618d-486d-b4f8-21388346cbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65993
2578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.659932578
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2181354059
Short name T2093
Test name
Test status
Simulation time 30695578 ps
CPU time 0.64 seconds
Started Jul 07 05:19:04 PM PDT 24
Finished Jul 07 05:19:05 PM PDT 24
Peak memory 206036 kb
Host smart-0423bb52-3592-4d78-91a3-de9ad1c545ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
54059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2181354059
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.493798142
Short name T2408
Test name
Test status
Simulation time 1086254701 ps
CPU time 2.59 seconds
Started Jul 07 05:19:15 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206248 kb
Host smart-c23b75c6-2cfa-4f92-b2df-5257ce9415ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49379
8142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.493798142
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2100325820
Short name T1484
Test name
Test status
Simulation time 298411947 ps
CPU time 2.19 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:19:17 PM PDT 24
Peak memory 206356 kb
Host smart-a18187b4-a9fe-4ce1-a250-35bdf80d3362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21003
25820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2100325820
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.297400760
Short name T512
Test name
Test status
Simulation time 87228932901 ps
CPU time 106.5 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 206348 kb
Host smart-60cd4fc0-2f96-40da-a031-e3184c500a7d
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=297400760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.297400760
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1939246351
Short name T2026
Test name
Test status
Simulation time 91213690496 ps
CPU time 130.36 seconds
Started Jul 07 05:19:04 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206464 kb
Host smart-248d38e6-1b0f-4c4b-ac25-ce3ee8e81cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939246351 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1939246351
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3176378485
Short name T1513
Test name
Test status
Simulation time 93116858182 ps
CPU time 112.51 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206332 kb
Host smart-bdf4acca-550a-4e6f-8791-47da4c07243e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3176378485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3176378485
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3552464722
Short name T2298
Test name
Test status
Simulation time 96161759401 ps
CPU time 161.25 seconds
Started Jul 07 05:19:08 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206388 kb
Host smart-dcdba9d7-f78a-44a9-8849-96466ffa8ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552464722 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3552464722
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2804254969
Short name T1027
Test name
Test status
Simulation time 100141574787 ps
CPU time 140.74 seconds
Started Jul 07 05:19:09 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206692 kb
Host smart-b7299577-bfcd-4120-8328-7655d5b9c250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
54969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2804254969
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.4121180288
Short name T1780
Test name
Test status
Simulation time 207999600 ps
CPU time 0.91 seconds
Started Jul 07 05:19:07 PM PDT 24
Finished Jul 07 05:19:08 PM PDT 24
Peak memory 206192 kb
Host smart-4535550b-ae32-4400-ace1-0bb2cda61d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41211
80288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.4121180288
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4226401085
Short name T1359
Test name
Test status
Simulation time 165853418 ps
CPU time 0.81 seconds
Started Jul 07 05:19:05 PM PDT 24
Finished Jul 07 05:19:07 PM PDT 24
Peak memory 206164 kb
Host smart-0b739b65-1e4d-4b63-bb79-877783ad6b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42264
01085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4226401085
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1550346772
Short name T440
Test name
Test status
Simulation time 209066979 ps
CPU time 0.9 seconds
Started Jul 07 05:19:09 PM PDT 24
Finished Jul 07 05:19:10 PM PDT 24
Peak memory 206184 kb
Host smart-87f80d08-6e7b-4188-b92d-85451f441924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15503
46772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1550346772
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3354473571
Short name T2005
Test name
Test status
Simulation time 6437463092 ps
CPU time 178.65 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:22:05 PM PDT 24
Peak memory 206496 kb
Host smart-3367ccca-0d85-4d95-a727-2b90d1b8a88c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3354473571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3354473571
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3111761527
Short name T306
Test name
Test status
Simulation time 177043903 ps
CPU time 0.81 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:19:07 PM PDT 24
Peak memory 206116 kb
Host smart-332b9ec0-39fb-4d6a-b115-724c30714b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
61527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3111761527
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.710521173
Short name T1541
Test name
Test status
Simulation time 23337579763 ps
CPU time 25.92 seconds
Started Jul 07 05:19:08 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206496 kb
Host smart-3ebb6f67-61e8-4155-8cb5-dbf7f04587e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71052
1173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.710521173
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.750497245
Short name T1342
Test name
Test status
Simulation time 3277027038 ps
CPU time 3.61 seconds
Started Jul 07 05:19:07 PM PDT 24
Finished Jul 07 05:19:11 PM PDT 24
Peak memory 206180 kb
Host smart-70d96d07-5b3a-43df-b33d-09aa87f99cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75049
7245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.750497245
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2705745971
Short name T749
Test name
Test status
Simulation time 9140521102 ps
CPU time 69.52 seconds
Started Jul 07 05:19:10 PM PDT 24
Finished Jul 07 05:20:20 PM PDT 24
Peak memory 206504 kb
Host smart-05a77011-6236-47d2-9d57-5123f0d6e959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27057
45971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2705745971
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2294506792
Short name T1588
Test name
Test status
Simulation time 3909519041 ps
CPU time 106.55 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206404 kb
Host smart-3394cd0d-3f90-4615-b2c1-88820e8bfe3d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2294506792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2294506792
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1728896521
Short name T2220
Test name
Test status
Simulation time 233843667 ps
CPU time 0.9 seconds
Started Jul 07 05:19:07 PM PDT 24
Finished Jul 07 05:19:09 PM PDT 24
Peak memory 206044 kb
Host smart-80f34d25-731d-44d7-ac68-3e335cf52f49
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1728896521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1728896521
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4003699820
Short name T1792
Test name
Test status
Simulation time 202548288 ps
CPU time 0.86 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:19:07 PM PDT 24
Peak memory 206116 kb
Host smart-07592206-3aaf-4994-9b36-5a5c80febb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40036
99820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4003699820
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.462914933
Short name T2296
Test name
Test status
Simulation time 4297040006 ps
CPU time 38.92 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:19:45 PM PDT 24
Peak memory 206468 kb
Host smart-ce3a4663-d88a-45e4-89e5-84959986e772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46291
4933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.462914933
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.596424312
Short name T1705
Test name
Test status
Simulation time 5195860406 ps
CPU time 147.76 seconds
Started Jul 07 05:19:10 PM PDT 24
Finished Jul 07 05:21:38 PM PDT 24
Peak memory 206420 kb
Host smart-3a3b3352-3807-4454-8cb8-20fbcd0aefe9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=596424312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.596424312
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.714540721
Short name T2684
Test name
Test status
Simulation time 189097161 ps
CPU time 0.82 seconds
Started Jul 07 05:19:08 PM PDT 24
Finished Jul 07 05:19:09 PM PDT 24
Peak memory 206100 kb
Host smart-1840ca16-4866-4922-b0d7-6be25e69f5d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=714540721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.714540721
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3454605823
Short name T2110
Test name
Test status
Simulation time 178712918 ps
CPU time 0.8 seconds
Started Jul 07 05:19:10 PM PDT 24
Finished Jul 07 05:19:11 PM PDT 24
Peak memory 206184 kb
Host smart-1811355c-390b-441b-a917-709835270cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34546
05823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3454605823
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1284112474
Short name T129
Test name
Test status
Simulation time 216294908 ps
CPU time 0.85 seconds
Started Jul 07 05:19:08 PM PDT 24
Finished Jul 07 05:19:09 PM PDT 24
Peak memory 206132 kb
Host smart-b65a7f37-908c-4efe-997a-183bc539d7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
12474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1284112474
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.4191126377
Short name T2169
Test name
Test status
Simulation time 191638157 ps
CPU time 0.83 seconds
Started Jul 07 05:19:06 PM PDT 24
Finished Jul 07 05:19:07 PM PDT 24
Peak memory 206184 kb
Host smart-75b33347-0d5f-4d4c-ba4e-c0c0df95abef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41911
26377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.4191126377
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1803872226
Short name T609
Test name
Test status
Simulation time 184056579 ps
CPU time 0.82 seconds
Started Jul 07 05:19:08 PM PDT 24
Finished Jul 07 05:19:09 PM PDT 24
Peak memory 206120 kb
Host smart-339a073c-d025-40aa-921a-8c35c896d454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18038
72226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1803872226
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2218071165
Short name T2404
Test name
Test status
Simulation time 198131430 ps
CPU time 0.82 seconds
Started Jul 07 05:19:09 PM PDT 24
Finished Jul 07 05:19:10 PM PDT 24
Peak memory 206164 kb
Host smart-4e3d0bed-20cd-4266-9465-7e72d6340752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22180
71165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2218071165
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2077205214
Short name T1840
Test name
Test status
Simulation time 147537086 ps
CPU time 0.77 seconds
Started Jul 07 05:19:15 PM PDT 24
Finished Jul 07 05:19:16 PM PDT 24
Peak memory 206188 kb
Host smart-858137f5-0c79-48a9-80ab-b09994defb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
05214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2077205214
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3201051331
Short name T704
Test name
Test status
Simulation time 259148888 ps
CPU time 1 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:19:14 PM PDT 24
Peak memory 206184 kb
Host smart-d07071ba-1e45-4bef-a2da-68894b7e1276
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3201051331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3201051331
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1077380929
Short name T171
Test name
Test status
Simulation time 253840124 ps
CPU time 0.98 seconds
Started Jul 07 05:19:15 PM PDT 24
Finished Jul 07 05:19:16 PM PDT 24
Peak memory 206188 kb
Host smart-667af991-edee-4f28-9387-adca82c7c10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10773
80929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1077380929
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3947431405
Short name T1727
Test name
Test status
Simulation time 140294837 ps
CPU time 0.77 seconds
Started Jul 07 05:19:11 PM PDT 24
Finished Jul 07 05:19:12 PM PDT 24
Peak memory 206152 kb
Host smart-b99f2ea5-80fe-4798-8b8b-9fafa084bbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
31405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3947431405
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.4285027666
Short name T599
Test name
Test status
Simulation time 90169604 ps
CPU time 0.71 seconds
Started Jul 07 05:19:12 PM PDT 24
Finished Jul 07 05:19:13 PM PDT 24
Peak memory 206132 kb
Host smart-f54e60a4-d9b9-4eda-a90d-d2281af61028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850
27666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.4285027666
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2508239414
Short name T2081
Test name
Test status
Simulation time 6804467857 ps
CPU time 14.5 seconds
Started Jul 07 05:19:13 PM PDT 24
Finished Jul 07 05:19:28 PM PDT 24
Peak memory 206480 kb
Host smart-f7b0c7e0-270e-482c-9fd5-2e6dfe748036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25082
39414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2508239414
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.59934698
Short name T2010
Test name
Test status
Simulation time 190340824 ps
CPU time 0.85 seconds
Started Jul 07 05:19:10 PM PDT 24
Finished Jul 07 05:19:12 PM PDT 24
Peak memory 206116 kb
Host smart-657681eb-0603-467d-a3d1-874a9a003e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59934
698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.59934698
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.520932758
Short name T938
Test name
Test status
Simulation time 203899117 ps
CPU time 0.86 seconds
Started Jul 07 05:19:10 PM PDT 24
Finished Jul 07 05:19:11 PM PDT 24
Peak memory 206076 kb
Host smart-c0b024e9-de52-4128-b166-d32d07a5ec51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52093
2758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.520932758
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2514341603
Short name T1795
Test name
Test status
Simulation time 17188639515 ps
CPU time 473 seconds
Started Jul 07 05:19:10 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 206436 kb
Host smart-6ce1586b-654b-4c2d-a27f-d8db0ae8e47c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2514341603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2514341603
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.4144565908
Short name T177
Test name
Test status
Simulation time 6082398511 ps
CPU time 49.56 seconds
Started Jul 07 05:19:15 PM PDT 24
Finished Jul 07 05:20:05 PM PDT 24
Peak memory 206412 kb
Host smart-01b28e31-4be5-45b4-9079-17a6b8266bbd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4144565908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.4144565908
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1030996624
Short name T2025
Test name
Test status
Simulation time 16038338100 ps
CPU time 325.85 seconds
Started Jul 07 05:19:12 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206448 kb
Host smart-93012fd9-5f8a-4246-add2-5013e074da30
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1030996624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1030996624
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.393474072
Short name T1010
Test name
Test status
Simulation time 199718953 ps
CPU time 0.89 seconds
Started Jul 07 05:19:11 PM PDT 24
Finished Jul 07 05:19:12 PM PDT 24
Peak memory 206152 kb
Host smart-911ae0ab-6849-4889-8fd4-e26c1cbf0d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39347
4072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.393474072
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2589196090
Short name T1340
Test name
Test status
Simulation time 151762038 ps
CPU time 0.79 seconds
Started Jul 07 05:19:11 PM PDT 24
Finished Jul 07 05:19:12 PM PDT 24
Peak memory 206184 kb
Host smart-6029cd27-cc64-4335-9abd-dbb43d81c5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25891
96090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2589196090
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1106261019
Short name T72
Test name
Test status
Simulation time 180885913 ps
CPU time 0.8 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:19 PM PDT 24
Peak memory 206184 kb
Host smart-64cf01dd-9d5c-40f3-806b-5e637e7760a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
61019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1106261019
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2430969545
Short name T1669
Test name
Test status
Simulation time 156235196 ps
CPU time 0.84 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206188 kb
Host smart-6ea0dc24-09f2-42ca-8e9d-68afea91ef82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24309
69545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2430969545
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.124798864
Short name T224
Test name
Test status
Simulation time 289101506 ps
CPU time 1.17 seconds
Started Jul 07 05:19:16 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 223956 kb
Host smart-69154110-845f-42c1-b6dd-0fb706d18bde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=124798864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.124798864
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.198412059
Short name T53
Test name
Test status
Simulation time 449160166 ps
CPU time 1.39 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206212 kb
Host smart-4b736d3f-ca64-49a9-8694-cecc1fa8fe93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19841
2059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.198412059
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3188761996
Short name T209
Test name
Test status
Simulation time 209884165 ps
CPU time 0.91 seconds
Started Jul 07 05:19:17 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206192 kb
Host smart-847df607-f704-4104-823c-955a97fddccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
61996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3188761996
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2942961179
Short name T1973
Test name
Test status
Simulation time 164290564 ps
CPU time 0.79 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:19 PM PDT 24
Peak memory 206036 kb
Host smart-247a9a95-a846-4cda-b167-7293e01a9c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29429
61179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2942961179
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.894026804
Short name T1047
Test name
Test status
Simulation time 150102880 ps
CPU time 0.8 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206188 kb
Host smart-75179a24-e15b-4559-b381-69b6faa14915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89402
6804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.894026804
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1670328640
Short name T1862
Test name
Test status
Simulation time 241097165 ps
CPU time 1.04 seconds
Started Jul 07 05:19:15 PM PDT 24
Finished Jul 07 05:19:17 PM PDT 24
Peak memory 206112 kb
Host smart-6a43bd36-d75b-41b7-8d3c-92110495c8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16703
28640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1670328640
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3780807561
Short name T1072
Test name
Test status
Simulation time 5503253012 ps
CPU time 146.36 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206492 kb
Host smart-12dba19d-931b-4f2c-adfe-424ea6a76672
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3780807561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3780807561
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4116319705
Short name T2681
Test name
Test status
Simulation time 201731885 ps
CPU time 0.81 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206120 kb
Host smart-a60ff231-8b14-46ab-bccf-fadd287a7014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41163
19705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4116319705
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.545388138
Short name T773
Test name
Test status
Simulation time 148939490 ps
CPU time 0.76 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:19:16 PM PDT 24
Peak memory 206204 kb
Host smart-ee05253d-1264-47e2-8f55-fce1b3b1816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54538
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.545388138
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.887033040
Short name T449
Test name
Test status
Simulation time 505386389 ps
CPU time 1.38 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206156 kb
Host smart-b727f672-175f-434e-bdfc-adc465729373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88703
3040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.887033040
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2846805201
Short name T1124
Test name
Test status
Simulation time 4843440778 ps
CPU time 140.3 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206752 kb
Host smart-0eaa3365-ed5a-46ff-9208-69eed0f4cdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28468
05201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2846805201
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1076969362
Short name T204
Test name
Test status
Simulation time 14269056329 ps
CPU time 366.64 seconds
Started Jul 07 05:19:19 PM PDT 24
Finished Jul 07 05:25:26 PM PDT 24
Peak memory 206412 kb
Host smart-509b5f3c-fabc-403e-8549-d82c451747cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1076969362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1076969362
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1173947570
Short name T1036
Test name
Test status
Simulation time 46264036 ps
CPU time 0.75 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206264 kb
Host smart-222d18b1-730c-4580-a591-674c158f7653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1173947570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1173947570
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1166012220
Short name T694
Test name
Test status
Simulation time 4218200527 ps
CPU time 5.47 seconds
Started Jul 07 05:21:10 PM PDT 24
Finished Jul 07 05:21:16 PM PDT 24
Peak memory 206280 kb
Host smart-dff5d7c2-95c2-481f-a9ad-80d4ada4f1cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1166012220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1166012220
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2827504603
Short name T991
Test name
Test status
Simulation time 13313032471 ps
CPU time 13.48 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206104 kb
Host smart-eee5df82-705d-4048-ac99-b264614b8ecf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2827504603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2827504603
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3945484947
Short name T2529
Test name
Test status
Simulation time 23304008603 ps
CPU time 29.35 seconds
Started Jul 07 05:21:10 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206264 kb
Host smart-9476bc87-3484-4b33-9897-f8246c425b28
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3945484947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3945484947
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1386811647
Short name T480
Test name
Test status
Simulation time 208094180 ps
CPU time 0.86 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:08 PM PDT 24
Peak memory 206192 kb
Host smart-383ec3b3-75f5-4ccc-be15-76fca57908d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13868
11647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1386811647
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.923581103
Short name T2606
Test name
Test status
Simulation time 169734461 ps
CPU time 0.83 seconds
Started Jul 07 05:21:11 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 206196 kb
Host smart-42e78d31-b378-47b1-9ff9-326f1738dbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92358
1103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.923581103
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1730651277
Short name T759
Test name
Test status
Simulation time 487914089 ps
CPU time 1.48 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206144 kb
Host smart-cad7e43b-6b08-4fc0-b7b8-4cf6a6db79ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17306
51277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1730651277
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1376561827
Short name T1729
Test name
Test status
Simulation time 1296714119 ps
CPU time 2.73 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:10 PM PDT 24
Peak memory 206428 kb
Host smart-75970e1d-9f66-4cc4-9557-9f18d1ea9130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13765
61827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1376561827
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2732455252
Short name T1418
Test name
Test status
Simulation time 7047738546 ps
CPU time 13.5 seconds
Started Jul 07 05:21:11 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 206232 kb
Host smart-d63abb4e-ae41-426a-b67c-1fb5737c658c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324
55252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2732455252
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2422627151
Short name T214
Test name
Test status
Simulation time 434221270 ps
CPU time 1.2 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:09 PM PDT 24
Peak memory 206188 kb
Host smart-a804c98f-a8b7-4212-a89c-aee7c6b26997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226
27151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2422627151
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.607484436
Short name T1829
Test name
Test status
Simulation time 142452562 ps
CPU time 0.75 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:08 PM PDT 24
Peak memory 206208 kb
Host smart-21e35164-b428-4b7b-8b2b-52c230cf6efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60748
4436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.607484436
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.709301049
Short name T2022
Test name
Test status
Simulation time 41075416 ps
CPU time 0.68 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:13 PM PDT 24
Peak memory 206104 kb
Host smart-fd735f97-4c47-4101-a54c-84eba64ad9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70930
1049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.709301049
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1167087510
Short name T91
Test name
Test status
Simulation time 781327792 ps
CPU time 1.91 seconds
Started Jul 07 05:21:14 PM PDT 24
Finished Jul 07 05:21:16 PM PDT 24
Peak memory 206368 kb
Host smart-0c1b52d5-8477-455a-ac76-b8afff088882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
87510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1167087510
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.147393183
Short name T632
Test name
Test status
Simulation time 302536117 ps
CPU time 2.17 seconds
Started Jul 07 05:21:10 PM PDT 24
Finished Jul 07 05:21:13 PM PDT 24
Peak memory 206428 kb
Host smart-704423c1-5852-4484-90a4-8cae0b1d5632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
3183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.147393183
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2872004475
Short name T1234
Test name
Test status
Simulation time 235919949 ps
CPU time 0.88 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206124 kb
Host smart-ebf7ed51-e73d-408f-a67e-07909a5fc2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28720
04475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2872004475
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.227454228
Short name T873
Test name
Test status
Simulation time 157332959 ps
CPU time 0.75 seconds
Started Jul 07 05:21:20 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206104 kb
Host smart-92aa91d5-043c-4530-8284-ba4eec9f4792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
4228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.227454228
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3429523838
Short name T2615
Test name
Test status
Simulation time 198187373 ps
CPU time 0.89 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:13 PM PDT 24
Peak memory 206128 kb
Host smart-e3ea14a8-0250-4c7a-af10-2f5649d60db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34295
23838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3429523838
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3016207473
Short name T635
Test name
Test status
Simulation time 207424695 ps
CPU time 0.93 seconds
Started Jul 07 05:21:11 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 206188 kb
Host smart-be4ba7f0-c9ba-416d-99f7-cc0e56177e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30162
07473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3016207473
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3508605523
Short name T269
Test name
Test status
Simulation time 23294163110 ps
CPU time 24.24 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206188 kb
Host smart-33ac1319-96a1-4c68-9aef-1f1b7d57a484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35086
05523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3508605523
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1416756330
Short name T510
Test name
Test status
Simulation time 3300494792 ps
CPU time 3.74 seconds
Started Jul 07 05:21:13 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206264 kb
Host smart-2c018985-0cc4-46b4-983b-836a6f7e0e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14167
56330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1416756330
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3783424541
Short name T1362
Test name
Test status
Simulation time 9360423438 ps
CPU time 65.86 seconds
Started Jul 07 05:21:15 PM PDT 24
Finished Jul 07 05:22:21 PM PDT 24
Peak memory 205864 kb
Host smart-f4dbf255-b3f3-4791-85fb-3d9333ba20d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834
24541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3783424541
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.958421712
Short name T909
Test name
Test status
Simulation time 5882649618 ps
CPU time 162.88 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206424 kb
Host smart-06eb5a20-d944-4b64-9239-cae4a1087419
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=958421712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.958421712
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1018557111
Short name T900
Test name
Test status
Simulation time 301355069 ps
CPU time 0.93 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206108 kb
Host smart-111b7ad7-4075-4cad-b977-e478cf6d6070
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1018557111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1018557111
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.4099120381
Short name T1510
Test name
Test status
Simulation time 187934740 ps
CPU time 0.89 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206156 kb
Host smart-8b9592bc-ffcb-4acf-acb2-96e9b4d62f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40991
20381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.4099120381
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.4193088754
Short name T162
Test name
Test status
Simulation time 4959052791 ps
CPU time 38.86 seconds
Started Jul 07 05:21:11 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 206524 kb
Host smart-c9bfb9ec-caef-4fb6-92bc-ec3022e4d3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41930
88754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.4193088754
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.267500575
Short name T706
Test name
Test status
Simulation time 2920384562 ps
CPU time 77.6 seconds
Started Jul 07 05:21:13 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206428 kb
Host smart-07079006-6006-440f-9392-3f6aaf6c4920
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=267500575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.267500575
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1076214559
Short name T899
Test name
Test status
Simulation time 159888976 ps
CPU time 0.81 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:13 PM PDT 24
Peak memory 206184 kb
Host smart-b762eacb-a27b-45c1-8989-b59179949b5b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1076214559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1076214559
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2211283624
Short name T393
Test name
Test status
Simulation time 200554647 ps
CPU time 0.9 seconds
Started Jul 07 05:21:15 PM PDT 24
Finished Jul 07 05:21:16 PM PDT 24
Peak memory 205568 kb
Host smart-cb0d98bb-6a12-48a4-9d3d-813b6c0b4ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22112
83624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2211283624
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2847376394
Short name T1032
Test name
Test status
Simulation time 201369483 ps
CPU time 0.86 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206112 kb
Host smart-444681ab-1c91-43ef-913a-4b3daf9fa564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28473
76394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2847376394
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1267011177
Short name T990
Test name
Test status
Simulation time 183475806 ps
CPU time 0.86 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206184 kb
Host smart-796838b0-5de7-44ac-a7f4-419b34728026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
11177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1267011177
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.4076455946
Short name T2572
Test name
Test status
Simulation time 174275331 ps
CPU time 0.84 seconds
Started Jul 07 05:21:20 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206116 kb
Host smart-b3b839e9-1ee4-4ef4-8fd6-d5eb8da9ebb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40764
55946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.4076455946
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1750630490
Short name T2188
Test name
Test status
Simulation time 175138523 ps
CPU time 0.81 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:13 PM PDT 24
Peak memory 206152 kb
Host smart-5ac982f6-3073-4eab-9cb2-0517d2df8ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
30490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1750630490
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1340089556
Short name T2206
Test name
Test status
Simulation time 225597283 ps
CPU time 0.86 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206080 kb
Host smart-017e9ed5-cac3-4c61-8abd-a3d954dc2d68
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1340089556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1340089556
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3868116798
Short name T1621
Test name
Test status
Simulation time 39560305 ps
CPU time 0.66 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206108 kb
Host smart-f8c8d265-887e-4de7-bfb2-27876a71b06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681
16798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3868116798
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.243210122
Short name T1136
Test name
Test status
Simulation time 16386550499 ps
CPU time 37.72 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:54 PM PDT 24
Peak memory 206536 kb
Host smart-187ac39a-6c8c-4cec-91bb-f5a6518a8836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24321
0122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.243210122
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.711940912
Short name T1724
Test name
Test status
Simulation time 162149364 ps
CPU time 0.8 seconds
Started Jul 07 05:21:17 PM PDT 24
Finished Jul 07 05:21:18 PM PDT 24
Peak memory 206164 kb
Host smart-2bd28ae3-a589-43e2-aea4-f807396a2f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71194
0912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.711940912
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1241602418
Short name T979
Test name
Test status
Simulation time 255380006 ps
CPU time 0.89 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206100 kb
Host smart-2abfb72c-95ad-4aca-8d7b-44b00ac524d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12416
02418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1241602418
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2032209338
Short name T1096
Test name
Test status
Simulation time 214093011 ps
CPU time 0.85 seconds
Started Jul 07 05:21:17 PM PDT 24
Finished Jul 07 05:21:19 PM PDT 24
Peak memory 206128 kb
Host smart-f403b98c-3ba8-4d55-9fda-e0f40da4c98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
09338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2032209338
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.470983463
Short name T1634
Test name
Test status
Simulation time 234476769 ps
CPU time 0.93 seconds
Started Jul 07 05:21:18 PM PDT 24
Finished Jul 07 05:21:19 PM PDT 24
Peak memory 206120 kb
Host smart-4483f505-cf01-4c45-8105-77b1cd43d4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47098
3463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.470983463
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3569315188
Short name T1260
Test name
Test status
Simulation time 148307403 ps
CPU time 0.8 seconds
Started Jul 07 05:21:18 PM PDT 24
Finished Jul 07 05:21:19 PM PDT 24
Peak memory 206204 kb
Host smart-0d34220a-b11c-4d16-9e34-93119362ed12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35693
15188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3569315188
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.560870951
Short name T2611
Test name
Test status
Simulation time 190828334 ps
CPU time 0.84 seconds
Started Jul 07 05:21:13 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206068 kb
Host smart-0705d56f-564d-4977-ba2c-70c781751065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56087
0951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.560870951
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4169835916
Short name T1878
Test name
Test status
Simulation time 210054490 ps
CPU time 0.92 seconds
Started Jul 07 05:21:20 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206184 kb
Host smart-48d607ac-8177-4aca-90f5-c4d959916f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41698
35916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4169835916
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3368618097
Short name T2030
Test name
Test status
Simulation time 3048456769 ps
CPU time 28.96 seconds
Started Jul 07 05:21:15 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206484 kb
Host smart-e4afae90-33a0-4428-9f17-1c86db82aebf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3368618097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3368618097
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3167682454
Short name T1941
Test name
Test status
Simulation time 257610258 ps
CPU time 0.89 seconds
Started Jul 07 05:21:17 PM PDT 24
Finished Jul 07 05:21:18 PM PDT 24
Peak memory 206188 kb
Host smart-02a1e387-d6eb-452a-a097-5762522f3ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
82454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3167682454
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.336963980
Short name T420
Test name
Test status
Simulation time 170760791 ps
CPU time 0.81 seconds
Started Jul 07 05:21:17 PM PDT 24
Finished Jul 07 05:21:18 PM PDT 24
Peak memory 206156 kb
Host smart-3b5d265f-d5b6-471b-b67f-b471e39c49e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33696
3980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.336963980
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3039513329
Short name T1110
Test name
Test status
Simulation time 327368891 ps
CPU time 1.2 seconds
Started Jul 07 05:21:13 PM PDT 24
Finished Jul 07 05:21:14 PM PDT 24
Peak memory 206168 kb
Host smart-4041d89d-a301-4f70-87b8-8a9518791150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395
13329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3039513329
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1653583936
Short name T2159
Test name
Test status
Simulation time 5691295536 ps
CPU time 43.43 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206344 kb
Host smart-992adf63-6dd9-4652-8320-5123a905b657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16535
83936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1653583936
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3320061192
Short name T2196
Test name
Test status
Simulation time 71169653 ps
CPU time 0.69 seconds
Started Jul 07 05:21:30 PM PDT 24
Finished Jul 07 05:21:31 PM PDT 24
Peak memory 206076 kb
Host smart-52af53e5-b22f-4e42-93da-cfe0817403aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3320061192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3320061192
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2696498887
Short name T1882
Test name
Test status
Simulation time 3813406969 ps
CPU time 4.32 seconds
Started Jul 07 05:21:17 PM PDT 24
Finished Jul 07 05:21:22 PM PDT 24
Peak memory 206332 kb
Host smart-d02ca6fb-1fb4-4ead-bc87-545c6133effa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2696498887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2696498887
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3729776599
Short name T1368
Test name
Test status
Simulation time 23334036243 ps
CPU time 23.62 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:43 PM PDT 24
Peak memory 206148 kb
Host smart-b13e1c67-80ab-471b-9172-35367aab43b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3729776599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3729776599
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.826407816
Short name T2131
Test name
Test status
Simulation time 151644227 ps
CPU time 0.79 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206180 kb
Host smart-6193b7c4-6ce2-4a50-8998-45acd2d74a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82640
7816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.826407816
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3356389116
Short name T58
Test name
Test status
Simulation time 142023188 ps
CPU time 0.79 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206136 kb
Host smart-4d877a9c-47ff-4523-8cfa-b458119b953f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33563
89116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3356389116
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2638364858
Short name T210
Test name
Test status
Simulation time 456756516 ps
CPU time 1.55 seconds
Started Jul 07 05:21:16 PM PDT 24
Finished Jul 07 05:21:18 PM PDT 24
Peak memory 206188 kb
Host smart-83bd5b5c-adc2-44c9-865a-b249a8f9178b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
64858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2638364858
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3336477082
Short name T188
Test name
Test status
Simulation time 11563644996 ps
CPU time 19.16 seconds
Started Jul 07 05:21:21 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206448 kb
Host smart-6a2f1c78-2ec0-408a-82df-63bec88b3756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
77082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3336477082
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.4144289808
Short name T1343
Test name
Test status
Simulation time 408091682 ps
CPU time 1.31 seconds
Started Jul 07 05:21:21 PM PDT 24
Finished Jul 07 05:21:23 PM PDT 24
Peak memory 206164 kb
Host smart-0a633c1b-c035-48c8-be9a-496690b82791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41442
89808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.4144289808
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.4103021931
Short name T2210
Test name
Test status
Simulation time 141888728 ps
CPU time 0.77 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206088 kb
Host smart-a10d92d4-37d2-4570-8425-bb0a6976c4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41030
21931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.4103021931
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.797609789
Short name T1487
Test name
Test status
Simulation time 34369808 ps
CPU time 0.65 seconds
Started Jul 07 05:21:22 PM PDT 24
Finished Jul 07 05:21:23 PM PDT 24
Peak memory 206188 kb
Host smart-0820fa71-80f5-4450-933c-8620f84061f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79760
9789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.797609789
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1379221183
Short name T2540
Test name
Test status
Simulation time 943384362 ps
CPU time 2.22 seconds
Started Jul 07 05:21:21 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 206460 kb
Host smart-7ed718ec-3289-4c6e-b6d2-4d12cfcac4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13792
21183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1379221183
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.132217220
Short name T1382
Test name
Test status
Simulation time 340302954 ps
CPU time 2.01 seconds
Started Jul 07 05:21:18 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206628 kb
Host smart-187158ea-2ad3-4308-821b-bdcc25d2a6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13221
7220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.132217220
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3173179231
Short name T431
Test name
Test status
Simulation time 211149287 ps
CPU time 0.81 seconds
Started Jul 07 05:21:19 PM PDT 24
Finished Jul 07 05:21:20 PM PDT 24
Peak memory 206204 kb
Host smart-442075ef-0b2b-40c6-8866-f565e9213aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31731
79231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3173179231
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.462521577
Short name T1211
Test name
Test status
Simulation time 148259272 ps
CPU time 0.79 seconds
Started Jul 07 05:21:24 PM PDT 24
Finished Jul 07 05:21:26 PM PDT 24
Peak memory 206108 kb
Host smart-3eaac798-2301-470f-a0ff-52410db4bb2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46252
1577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.462521577
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1823570594
Short name T379
Test name
Test status
Simulation time 183807631 ps
CPU time 0.81 seconds
Started Jul 07 05:21:26 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 205896 kb
Host smart-4b022560-9d57-4a14-8c89-e72abe7f5083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18235
70594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1823570594
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1621804517
Short name T2634
Test name
Test status
Simulation time 211124756 ps
CPU time 0.89 seconds
Started Jul 07 05:21:24 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 206156 kb
Host smart-08a5cb35-e889-42f6-ae00-75652a6bdd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16218
04517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1621804517
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.4117520969
Short name T1611
Test name
Test status
Simulation time 23311546217 ps
CPU time 21.72 seconds
Started Jul 07 05:21:22 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206248 kb
Host smart-38dc1e4a-5b3c-4e21-996e-869a239ab28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41175
20969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.4117520969
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.717522853
Short name T928
Test name
Test status
Simulation time 3326214856 ps
CPU time 4.02 seconds
Started Jul 07 05:21:25 PM PDT 24
Finished Jul 07 05:21:29 PM PDT 24
Peak memory 206256 kb
Host smart-9309fdd8-29aa-4e18-bda3-641efe861da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71752
2853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.717522853
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3867284149
Short name T496
Test name
Test status
Simulation time 8673505977 ps
CPU time 242.9 seconds
Started Jul 07 05:21:26 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206540 kb
Host smart-6a04281e-fecd-4341-9af1-1f6cbe0fa27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38672
84149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3867284149
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3648516331
Short name T1590
Test name
Test status
Simulation time 7019447370 ps
CPU time 54.03 seconds
Started Jul 07 05:21:23 PM PDT 24
Finished Jul 07 05:22:17 PM PDT 24
Peak memory 206432 kb
Host smart-a5cb7571-58d2-4415-b138-a90ad59a5b45
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3648516331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3648516331
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.4201794866
Short name T2213
Test name
Test status
Simulation time 243357400 ps
CPU time 0.89 seconds
Started Jul 07 05:21:27 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 206104 kb
Host smart-c3ba07e8-1c0e-409c-8703-5671614fa772
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4201794866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.4201794866
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3394310292
Short name T1769
Test name
Test status
Simulation time 192375878 ps
CPU time 0.88 seconds
Started Jul 07 05:21:26 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 206188 kb
Host smart-9a9e3c97-afcd-4cfc-a9f1-7c61746882e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
10292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3394310292
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3582344379
Short name T1001
Test name
Test status
Simulation time 6356185034 ps
CPU time 44.13 seconds
Started Jul 07 05:21:24 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206380 kb
Host smart-efa9452c-c869-401f-95e6-bfd11501a7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35823
44379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3582344379
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1623890314
Short name T2533
Test name
Test status
Simulation time 4370906099 ps
CPU time 41.34 seconds
Started Jul 07 05:21:23 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206752 kb
Host smart-1b49a8c6-bc7c-4ead-919d-2f7a9ea003c0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1623890314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1623890314
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1870087396
Short name T2389
Test name
Test status
Simulation time 188662602 ps
CPU time 0.87 seconds
Started Jul 07 05:21:23 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 206152 kb
Host smart-730ea2fc-b26c-4544-99c2-fa646230d15a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1870087396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1870087396
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2573720573
Short name T1585
Test name
Test status
Simulation time 150063609 ps
CPU time 0.8 seconds
Started Jul 07 05:21:24 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 206192 kb
Host smart-9b64e395-fc59-4779-9603-cdd6caf8c895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737
20573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2573720573
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2008865130
Short name T1347
Test name
Test status
Simulation time 159427980 ps
CPU time 0.77 seconds
Started Jul 07 05:21:27 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 206184 kb
Host smart-94d6293a-814f-4313-afa9-4f491fe354ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
65130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2008865130
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1999483479
Short name T597
Test name
Test status
Simulation time 206220274 ps
CPU time 0.85 seconds
Started Jul 07 05:21:26 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 206032 kb
Host smart-f1080074-9cab-430c-9f5f-e64d8168ec36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19994
83479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1999483479
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.373456448
Short name T205
Test name
Test status
Simulation time 172982828 ps
CPU time 0.8 seconds
Started Jul 07 05:21:27 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 206188 kb
Host smart-0304696c-67d2-4438-a059-720cd6af72f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37345
6448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.373456448
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.910414780
Short name T1522
Test name
Test status
Simulation time 242868650 ps
CPU time 0.96 seconds
Started Jul 07 05:21:24 PM PDT 24
Finished Jul 07 05:21:26 PM PDT 24
Peak memory 206164 kb
Host smart-41eea02d-6c73-428d-bcc6-08e527f1c829
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=910414780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.910414780
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3223066219
Short name T2153
Test name
Test status
Simulation time 146255401 ps
CPU time 0.78 seconds
Started Jul 07 05:21:27 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 206184 kb
Host smart-c795b442-5edf-4d02-ac98-956c17233060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32230
66219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3223066219
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2975608146
Short name T1532
Test name
Test status
Simulation time 103435892 ps
CPU time 0.7 seconds
Started Jul 07 05:21:26 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 206024 kb
Host smart-9d26470a-a6c5-42ac-bc94-d4e055bb1cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29756
08146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2975608146
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4000611909
Short name T2243
Test name
Test status
Simulation time 13473755524 ps
CPU time 32.74 seconds
Started Jul 07 05:21:31 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206540 kb
Host smart-a200165e-d3e5-4baf-8451-6038c926f540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40006
11909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4000611909
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1474397298
Short name T918
Test name
Test status
Simulation time 190903583 ps
CPU time 0.89 seconds
Started Jul 07 05:21:31 PM PDT 24
Finished Jul 07 05:21:32 PM PDT 24
Peak memory 206120 kb
Host smart-9384829a-65e8-4837-926d-b955cb10b42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14743
97298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1474397298
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3997375996
Short name T1841
Test name
Test status
Simulation time 210871236 ps
CPU time 0.88 seconds
Started Jul 07 05:21:31 PM PDT 24
Finished Jul 07 05:21:32 PM PDT 24
Peak memory 206112 kb
Host smart-ec04a7ba-4ebb-4eec-9233-fb67c0ca42bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39973
75996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3997375996
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2107720607
Short name T533
Test name
Test status
Simulation time 200964931 ps
CPU time 0.87 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:33 PM PDT 24
Peak memory 206196 kb
Host smart-7b093b67-affb-46f4-8b55-8dde41d31d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21077
20607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2107720607
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.418664689
Short name T2505
Test name
Test status
Simulation time 171507217 ps
CPU time 0.83 seconds
Started Jul 07 05:21:31 PM PDT 24
Finished Jul 07 05:21:32 PM PDT 24
Peak memory 206200 kb
Host smart-f8a541f2-dcfd-44f8-b1f0-a7e3bb9767bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41866
4689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.418664689
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3976395106
Short name T2181
Test name
Test status
Simulation time 138051456 ps
CPU time 0.76 seconds
Started Jul 07 05:21:28 PM PDT 24
Finished Jul 07 05:21:29 PM PDT 24
Peak memory 206196 kb
Host smart-52ed810f-ae18-4f2b-aa1e-82e47844c2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39763
95106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3976395106
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1177741878
Short name T1686
Test name
Test status
Simulation time 184103711 ps
CPU time 0.81 seconds
Started Jul 07 05:21:29 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206120 kb
Host smart-498e89cf-d2a4-4419-8eb2-f714d05014f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777
41878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1177741878
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2624718420
Short name T2457
Test name
Test status
Simulation time 153059920 ps
CPU time 0.81 seconds
Started Jul 07 05:21:30 PM PDT 24
Finished Jul 07 05:21:31 PM PDT 24
Peak memory 206192 kb
Host smart-eae90279-297c-43e3-9c49-b4a67101371b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26247
18420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2624718420
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1368030544
Short name T1601
Test name
Test status
Simulation time 218590577 ps
CPU time 0.93 seconds
Started Jul 07 05:21:29 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206192 kb
Host smart-5010ca46-23b6-4465-9e82-b358ef490884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13680
30544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1368030544
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.4129927138
Short name T445
Test name
Test status
Simulation time 4995324203 ps
CPU time 49.64 seconds
Started Jul 07 05:21:29 PM PDT 24
Finished Jul 07 05:22:19 PM PDT 24
Peak memory 206452 kb
Host smart-df9c70ef-6233-47e4-9c20-a127e0e86619
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4129927138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.4129927138
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3300871860
Short name T2003
Test name
Test status
Simulation time 186083912 ps
CPU time 0.85 seconds
Started Jul 07 05:21:27 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 206156 kb
Host smart-86eb108d-49c4-4319-bb86-313ea75d709f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33008
71860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3300871860
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.150143771
Short name T1270
Test name
Test status
Simulation time 187341803 ps
CPU time 0.85 seconds
Started Jul 07 05:21:29 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206196 kb
Host smart-ea63f276-6b0a-4385-b504-ea547e605bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014
3771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.150143771
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.583589239
Short name T2013
Test name
Test status
Simulation time 217914779 ps
CPU time 0.86 seconds
Started Jul 07 05:21:35 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206220 kb
Host smart-086b60ce-2c96-4aaf-8f0e-b27475bd1132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58358
9239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.583589239
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3561981962
Short name T509
Test name
Test status
Simulation time 4748725996 ps
CPU time 33.81 seconds
Started Jul 07 05:21:31 PM PDT 24
Finished Jul 07 05:22:05 PM PDT 24
Peak memory 206456 kb
Host smart-6d8a2d5c-c063-48a8-a9fa-594ad4f85a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35619
81962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3561981962
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3918026940
Short name T2412
Test name
Test status
Simulation time 105353937 ps
CPU time 0.73 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206220 kb
Host smart-cc6724ba-3f43-4c9b-8126-525437f018bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3918026940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3918026940
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2675456071
Short name T2064
Test name
Test status
Simulation time 13429051187 ps
CPU time 14.6 seconds
Started Jul 07 05:21:30 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206352 kb
Host smart-d0358d85-6fc9-45a7-a22a-30b3a8631901
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2675456071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2675456071
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3297128875
Short name T1380
Test name
Test status
Simulation time 23404152313 ps
CPU time 26.5 seconds
Started Jul 07 05:21:35 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206268 kb
Host smart-0eb46e1c-32af-4ef6-8012-c3628c7bc057
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3297128875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.3297128875
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2364366488
Short name T451
Test name
Test status
Simulation time 164624147 ps
CPU time 0.81 seconds
Started Jul 07 05:21:29 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206040 kb
Host smart-5a7636ef-3b05-4e8e-be1c-6e97cf18654a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
66488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2364366488
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.969954098
Short name T1449
Test name
Test status
Simulation time 201283967 ps
CPU time 0.84 seconds
Started Jul 07 05:21:30 PM PDT 24
Finished Jul 07 05:21:31 PM PDT 24
Peak memory 206212 kb
Host smart-8d589966-2193-46d4-bc79-24ec0ed9e95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96995
4098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.969954098
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3651443901
Short name T119
Test name
Test status
Simulation time 656345444 ps
CPU time 1.74 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 206332 kb
Host smart-2c8804dc-3020-427e-a0ad-ba4a84e552e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36514
43901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3651443901
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.39199476
Short name T117
Test name
Test status
Simulation time 953973776 ps
CPU time 2.33 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206360 kb
Host smart-18f099c7-9960-4087-a220-f80128d9c794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.39199476
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.275508996
Short name T930
Test name
Test status
Simulation time 14106202028 ps
CPU time 26.5 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:59 PM PDT 24
Peak memory 206460 kb
Host smart-13910e45-0b41-413b-895d-999edbc3f7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27550
8996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.275508996
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.1937928828
Short name T1752
Test name
Test status
Simulation time 299279068 ps
CPU time 1.15 seconds
Started Jul 07 05:21:36 PM PDT 24
Finished Jul 07 05:21:37 PM PDT 24
Peak memory 206208 kb
Host smart-cf694e4d-206f-44c5-915c-f2894fa434fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
28828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.1937928828
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.4052304683
Short name T493
Test name
Test status
Simulation time 167161652 ps
CPU time 0.78 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206208 kb
Host smart-cf5bdb9d-5d51-4385-9ffd-89a4152e3cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40523
04683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.4052304683
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1646128015
Short name T2042
Test name
Test status
Simulation time 40753413 ps
CPU time 0.73 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206208 kb
Host smart-3ff8d728-8870-4c91-8741-12ca53d66464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461
28015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1646128015
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3318296492
Short name T1895
Test name
Test status
Simulation time 830886066 ps
CPU time 2.04 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206384 kb
Host smart-f6ead11c-dbec-4b5d-886a-744b5f76e13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33182
96492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3318296492
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1866829294
Short name T2489
Test name
Test status
Simulation time 160550682 ps
CPU time 1.21 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206440 kb
Host smart-d8dfba85-8e93-4e7b-9eae-1a310165ebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18668
29294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1866829294
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.163854096
Short name T2063
Test name
Test status
Simulation time 196369075 ps
CPU time 0.87 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206156 kb
Host smart-a482966e-7ea6-464b-b68c-3c369617276f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16385
4096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.163854096
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1010398218
Short name T2350
Test name
Test status
Simulation time 138711840 ps
CPU time 0.75 seconds
Started Jul 07 05:21:37 PM PDT 24
Finished Jul 07 05:21:38 PM PDT 24
Peak memory 206180 kb
Host smart-ec9a8573-1a27-419a-b3b4-ef7f2d3c5623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
98218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1010398218
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2681701104
Short name T1617
Test name
Test status
Simulation time 234808727 ps
CPU time 0.91 seconds
Started Jul 07 05:21:33 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 206112 kb
Host smart-00bf8ba6-fbdf-4971-bf65-496a4fc567dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26817
01104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2681701104
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1323638700
Short name T952
Test name
Test status
Simulation time 8430256494 ps
CPU time 63.84 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:22:39 PM PDT 24
Peak memory 206448 kb
Host smart-1c51731f-2fab-4209-880b-e3d429d6a963
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1323638700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1323638700
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1640244882
Short name T2269
Test name
Test status
Simulation time 212673312 ps
CPU time 0.93 seconds
Started Jul 07 05:21:31 PM PDT 24
Finished Jul 07 05:21:32 PM PDT 24
Peak memory 206188 kb
Host smart-384e4104-0ba3-4f57-899f-51e037438033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16402
44882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1640244882
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1871910344
Short name T2091
Test name
Test status
Simulation time 23329737664 ps
CPU time 22.6 seconds
Started Jul 07 05:21:32 PM PDT 24
Finished Jul 07 05:21:55 PM PDT 24
Peak memory 206248 kb
Host smart-a0552cc2-0450-49b4-ac8c-da32f70ff3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18719
10344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1871910344
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2910564675
Short name T1228
Test name
Test status
Simulation time 3329081228 ps
CPU time 4.63 seconds
Started Jul 07 05:21:33 PM PDT 24
Finished Jul 07 05:21:38 PM PDT 24
Peak memory 206280 kb
Host smart-a363dbb2-e110-4ba1-a55e-49885c4c2b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29105
64675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2910564675
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2412652471
Short name T1118
Test name
Test status
Simulation time 10407371315 ps
CPU time 299.26 seconds
Started Jul 07 05:21:35 PM PDT 24
Finished Jul 07 05:26:35 PM PDT 24
Peak memory 206456 kb
Host smart-8104ecda-ed22-4845-8591-c76b4263f853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126
52471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2412652471
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2560422979
Short name T2623
Test name
Test status
Simulation time 5268194557 ps
CPU time 137.38 seconds
Started Jul 07 05:21:35 PM PDT 24
Finished Jul 07 05:23:52 PM PDT 24
Peak memory 206428 kb
Host smart-d480fee3-90e1-44c3-97ac-0bda378e4a18
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2560422979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2560422979
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3443357050
Short name T1992
Test name
Test status
Simulation time 281507308 ps
CPU time 0.96 seconds
Started Jul 07 05:21:36 PM PDT 24
Finished Jul 07 05:21:37 PM PDT 24
Peak memory 206204 kb
Host smart-2acdaf3e-6d66-4a25-917d-3da26bf811a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3443357050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3443357050
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.247518570
Short name T949
Test name
Test status
Simulation time 185433014 ps
CPU time 0.87 seconds
Started Jul 07 05:21:37 PM PDT 24
Finished Jul 07 05:21:38 PM PDT 24
Peak memory 206188 kb
Host smart-67f829e3-2b49-4673-900e-a0c9b209f043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751
8570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.247518570
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2493712834
Short name T404
Test name
Test status
Simulation time 3257568026 ps
CPU time 88.21 seconds
Started Jul 07 05:21:33 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206468 kb
Host smart-382445f7-1317-4264-afeb-266624616752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24937
12834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2493712834
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.446131030
Short name T2598
Test name
Test status
Simulation time 6476226159 ps
CPU time 46.25 seconds
Started Jul 07 05:21:33 PM PDT 24
Finished Jul 07 05:22:19 PM PDT 24
Peak memory 206428 kb
Host smart-5435b9a8-49b7-4ca7-a8bd-3e8bc4e11934
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=446131030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.446131030
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.870940087
Short name T1105
Test name
Test status
Simulation time 177161831 ps
CPU time 0.83 seconds
Started Jul 07 05:21:36 PM PDT 24
Finished Jul 07 05:21:37 PM PDT 24
Peak memory 205776 kb
Host smart-cdaa9c83-09f6-44d0-ae8a-e6c83ee459e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=870940087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.870940087
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1417526750
Short name T1604
Test name
Test status
Simulation time 154642205 ps
CPU time 0.77 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206184 kb
Host smart-87a2b8fd-7c6a-4a6c-a1fc-386c411458d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14175
26750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1417526750
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3766599073
Short name T600
Test name
Test status
Simulation time 176947518 ps
CPU time 0.9 seconds
Started Jul 07 05:21:35 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206180 kb
Host smart-fb90fb5c-3297-4bdc-b893-09de953ace3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37665
99073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3766599073
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2507696599
Short name T1042
Test name
Test status
Simulation time 164133160 ps
CPU time 0.83 seconds
Started Jul 07 05:21:36 PM PDT 24
Finished Jul 07 05:21:37 PM PDT 24
Peak memory 205860 kb
Host smart-1ba7ca39-bf70-4a5d-8d75-5d1b6ab18d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25076
96599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2507696599
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3634675083
Short name T2630
Test name
Test status
Simulation time 193371187 ps
CPU time 0.88 seconds
Started Jul 07 05:21:33 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 206240 kb
Host smart-9b2d631a-e397-4737-8e32-0f781de33239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36346
75083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3634675083
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1208058458
Short name T947
Test name
Test status
Simulation time 190644539 ps
CPU time 0.85 seconds
Started Jul 07 05:21:34 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206160 kb
Host smart-25967726-4cf3-41ea-820d-f4f0b1da0ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12080
58458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1208058458
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.634295918
Short name T1904
Test name
Test status
Simulation time 227508902 ps
CPU time 0.9 seconds
Started Jul 07 05:21:38 PM PDT 24
Finished Jul 07 05:21:39 PM PDT 24
Peak memory 206064 kb
Host smart-df582bf7-093b-4c49-aaa4-86d1c6f1ca5f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=634295918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.634295918
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3785628926
Short name T221
Test name
Test status
Simulation time 142002874 ps
CPU time 0.76 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206180 kb
Host smart-d70771e8-54e7-443d-8798-6c6cbf647f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37856
28926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3785628926
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3433805949
Short name T26
Test name
Test status
Simulation time 39410824 ps
CPU time 0.66 seconds
Started Jul 07 05:21:38 PM PDT 24
Finished Jul 07 05:21:39 PM PDT 24
Peak memory 206036 kb
Host smart-2b82bd8b-617d-4eb0-9948-9f751d9e3627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34338
05949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3433805949
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2351230074
Short name T278
Test name
Test status
Simulation time 12234772311 ps
CPU time 27.05 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206488 kb
Host smart-88924409-2336-4765-8600-4ade7a93255c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
30074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2351230074
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.830968857
Short name T2437
Test name
Test status
Simulation time 173320072 ps
CPU time 0.82 seconds
Started Jul 07 05:21:38 PM PDT 24
Finished Jul 07 05:21:39 PM PDT 24
Peak memory 206084 kb
Host smart-c09b64f4-80b6-4652-8feb-b4638362712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83096
8857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.830968857
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1784484619
Short name T1636
Test name
Test status
Simulation time 260945598 ps
CPU time 0.95 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:41 PM PDT 24
Peak memory 206440 kb
Host smart-52b2a678-97a6-405a-adb3-c1222cb437f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17844
84619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1784484619
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2610394716
Short name T2414
Test name
Test status
Simulation time 252362386 ps
CPU time 0.91 seconds
Started Jul 07 05:21:39 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206164 kb
Host smart-d798e21d-d08e-4cfe-a036-823f8d1dbfd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26103
94716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2610394716
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.948630491
Short name T1171
Test name
Test status
Simulation time 161934133 ps
CPU time 0.79 seconds
Started Jul 07 05:21:43 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206188 kb
Host smart-47dce2ed-78b3-4b48-a285-45312e21a2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94863
0491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.948630491
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.582643873
Short name T860
Test name
Test status
Simulation time 156126354 ps
CPU time 0.78 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206144 kb
Host smart-a576b5b5-7cbd-4ca4-b41e-f595a1df8c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58264
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.582643873
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.989064516
Short name T758
Test name
Test status
Simulation time 147748734 ps
CPU time 0.77 seconds
Started Jul 07 05:21:39 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206184 kb
Host smart-6425e38e-22ad-40b1-a34e-cd57ff24c98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98906
4516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.989064516
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2618625054
Short name T1421
Test name
Test status
Simulation time 146323482 ps
CPU time 0.76 seconds
Started Jul 07 05:21:39 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206184 kb
Host smart-bbb4d6c1-ed52-43fb-8991-fa911535133b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26186
25054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2618625054
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2121145033
Short name T2070
Test name
Test status
Simulation time 194340618 ps
CPU time 0.92 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206180 kb
Host smart-bfdc4341-970c-480c-84ae-86513832cd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21211
45033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2121145033
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1745837261
Short name T1140
Test name
Test status
Simulation time 4870609514 ps
CPU time 131.49 seconds
Started Jul 07 05:21:37 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 206528 kb
Host smart-92272efa-ef2b-4b61-b6f3-f978bdc5e7dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1745837261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1745837261
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.648540058
Short name T2602
Test name
Test status
Simulation time 188480067 ps
CPU time 0.84 seconds
Started Jul 07 05:21:38 PM PDT 24
Finished Jul 07 05:21:39 PM PDT 24
Peak memory 206196 kb
Host smart-8b26a685-4894-47f4-a848-ea74c303035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64854
0058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.648540058
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.680892365
Short name T2386
Test name
Test status
Simulation time 152744302 ps
CPU time 0.78 seconds
Started Jul 07 05:21:42 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206188 kb
Host smart-ed93c4b0-2941-4431-9be1-bfa670fa22e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68089
2365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.680892365
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.344274800
Short name T935
Test name
Test status
Simulation time 548158449 ps
CPU time 1.37 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206188 kb
Host smart-412a3740-f62b-4d0d-9c23-b05d0185fc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34427
4800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.344274800
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.709492293
Short name T1566
Test name
Test status
Simulation time 7489682175 ps
CPU time 216.1 seconds
Started Jul 07 05:21:36 PM PDT 24
Finished Jul 07 05:25:12 PM PDT 24
Peak memory 206492 kb
Host smart-4613e436-238d-457c-b661-5ddc55710fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70949
2293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.709492293
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3683149708
Short name T217
Test name
Test status
Simulation time 34478608 ps
CPU time 0.7 seconds
Started Jul 07 05:21:47 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206228 kb
Host smart-4d9ae99d-142b-4c5e-9e6a-21ce12b8f757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3683149708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3683149708
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1254872702
Short name T1691
Test name
Test status
Simulation time 4491250362 ps
CPU time 5.19 seconds
Started Jul 07 05:21:43 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206404 kb
Host smart-7167cec5-d53f-444d-931f-aa43830d5893
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1254872702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.1254872702
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.121298399
Short name T708
Test name
Test status
Simulation time 13317881838 ps
CPU time 15.24 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 206416 kb
Host smart-f51ca533-cb8f-4fad-99e6-718dd32b94e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=121298399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.121298399
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2766150883
Short name T246
Test name
Test status
Simulation time 23358947101 ps
CPU time 26.96 seconds
Started Jul 07 05:21:42 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206420 kb
Host smart-74b1d81a-d558-4c9d-ba89-a3a72a7f2d56
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2766150883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2766150883
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.430839423
Short name T2225
Test name
Test status
Simulation time 173987983 ps
CPU time 0.85 seconds
Started Jul 07 05:21:37 PM PDT 24
Finished Jul 07 05:21:37 PM PDT 24
Peak memory 206032 kb
Host smart-94781159-c170-405f-82f8-a76d3badf774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43083
9423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.430839423
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.351581279
Short name T1400
Test name
Test status
Simulation time 148622568 ps
CPU time 0.76 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:43 PM PDT 24
Peak memory 206184 kb
Host smart-a5397a91-d47e-4ec9-9b99-7db30c511c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35158
1279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.351581279
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3062067780
Short name T2551
Test name
Test status
Simulation time 521538310 ps
CPU time 1.73 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206420 kb
Host smart-f2d22a62-4941-43c3-858a-3f8fd9932d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
67780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3062067780
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1704943940
Short name T520
Test name
Test status
Simulation time 571080591 ps
CPU time 1.52 seconds
Started Jul 07 05:21:43 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206188 kb
Host smart-94c540fe-3075-47b3-b0ca-83b22071c542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17049
43940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1704943940
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1107701919
Short name T1702
Test name
Test status
Simulation time 11234044245 ps
CPU time 23.01 seconds
Started Jul 07 05:21:37 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206376 kb
Host smart-d633dd63-49c1-4384-999e-4b5a039e4b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11077
01919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1107701919
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1928094211
Short name T1073
Test name
Test status
Simulation time 485555867 ps
CPU time 1.32 seconds
Started Jul 07 05:21:36 PM PDT 24
Finished Jul 07 05:21:38 PM PDT 24
Peak memory 206112 kb
Host smart-1556fdfc-f723-4702-83d1-2df667db1ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19280
94211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1928094211
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.290563203
Short name T607
Test name
Test status
Simulation time 139995097 ps
CPU time 0.76 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:41 PM PDT 24
Peak memory 206168 kb
Host smart-437aa62b-eac3-45cc-9079-8d8ea5faef20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056
3203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.290563203
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1584401739
Short name T2668
Test name
Test status
Simulation time 46861429 ps
CPU time 0.68 seconds
Started Jul 07 05:21:40 PM PDT 24
Finished Jul 07 05:21:41 PM PDT 24
Peak memory 206112 kb
Host smart-9db50a03-b9f9-43cf-9281-2a20204d5a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
01739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1584401739
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1691678276
Short name T835
Test name
Test status
Simulation time 823509755 ps
CPU time 1.9 seconds
Started Jul 07 05:21:39 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206448 kb
Host smart-5fd4ac70-5148-4cc6-b5ce-ef46a66752c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16916
78276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1691678276
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.729807639
Short name T1132
Test name
Test status
Simulation time 359447362 ps
CPU time 2.27 seconds
Started Jul 07 05:21:45 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206428 kb
Host smart-bcff3ee5-8163-4af0-b778-7e859e3ed163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72980
7639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.729807639
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1145690583
Short name T655
Test name
Test status
Simulation time 187961872 ps
CPU time 0.79 seconds
Started Jul 07 05:21:45 PM PDT 24
Finished Jul 07 05:21:46 PM PDT 24
Peak memory 206184 kb
Host smart-baf09693-cf7b-4204-a16b-a68db05a69f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11456
90583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1145690583
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3372746322
Short name T1121
Test name
Test status
Simulation time 144196030 ps
CPU time 0.77 seconds
Started Jul 07 05:21:42 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206112 kb
Host smart-288e02fa-de5e-4d08-87ac-673efb59e9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
46322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3372746322
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4054174300
Short name T1935
Test name
Test status
Simulation time 181372795 ps
CPU time 0.84 seconds
Started Jul 07 05:21:44 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206184 kb
Host smart-2baf329c-161a-40d0-a3f1-fc65bbd7b3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
74300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4054174300
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.454234947
Short name T109
Test name
Test status
Simulation time 9023723515 ps
CPU time 252.99 seconds
Started Jul 07 05:21:43 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206472 kb
Host smart-7340729d-9581-401f-aaae-9421d82f6d7b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=454234947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.454234947
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.433194183
Short name T615
Test name
Test status
Simulation time 217211933 ps
CPU time 0.89 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206184 kb
Host smart-2d99aa4c-56e8-4acd-a46c-648a0a3a3ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43319
4183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.433194183
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.850154439
Short name T455
Test name
Test status
Simulation time 23320605282 ps
CPU time 21.7 seconds
Started Jul 07 05:21:44 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206180 kb
Host smart-5c58237b-2388-4475-80b1-025836a42bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85015
4439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.850154439
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3122451439
Short name T1146
Test name
Test status
Simulation time 3358354522 ps
CPU time 3.67 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206184 kb
Host smart-903af4a6-5efb-4ebd-bdbd-f6153ba2921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
51439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3122451439
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3423687695
Short name T1456
Test name
Test status
Simulation time 11498169542 ps
CPU time 82.07 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206416 kb
Host smart-75cafc06-b63d-4872-bfc2-069316c92c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34236
87695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3423687695
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1772966210
Short name T1921
Test name
Test status
Simulation time 3722111087 ps
CPU time 36.06 seconds
Started Jul 07 05:21:45 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206476 kb
Host smart-28718623-5509-455c-980d-47458c2f7928
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1772966210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1772966210
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.268402432
Short name T917
Test name
Test status
Simulation time 246003268 ps
CPU time 0.92 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206132 kb
Host smart-1cbcb610-d143-45b7-a48f-13e16df6ba4f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=268402432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.268402432
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.97045252
Short name T1985
Test name
Test status
Simulation time 212717021 ps
CPU time 0.96 seconds
Started Jul 07 05:21:49 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 206144 kb
Host smart-012ecc17-4ab0-461a-b481-3a1d7f9f15c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97045
252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.97045252
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.973007905
Short name T2656
Test name
Test status
Simulation time 3994076888 ps
CPU time 37.56 seconds
Started Jul 07 05:21:42 PM PDT 24
Finished Jul 07 05:22:20 PM PDT 24
Peak memory 206468 kb
Host smart-3ad4da17-46b2-4c3d-a149-b8aedd975652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97300
7905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.973007905
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3624628147
Short name T2441
Test name
Test status
Simulation time 4372549480 ps
CPU time 124.32 seconds
Started Jul 07 05:21:44 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206436 kb
Host smart-05bca1fd-5c1f-48ff-8660-7b6c8822db19
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3624628147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3624628147
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3676520373
Short name T1104
Test name
Test status
Simulation time 190191525 ps
CPU time 0.93 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:43 PM PDT 24
Peak memory 206140 kb
Host smart-ae8fc8b8-f0a0-4333-9265-3d7909883494
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3676520373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3676520373
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.571047771
Short name T1721
Test name
Test status
Simulation time 161535087 ps
CPU time 0.84 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:43 PM PDT 24
Peak memory 206172 kb
Host smart-97e64601-fea4-427c-a500-ac5bab23be70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57104
7771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.571047771
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.431653092
Short name T2137
Test name
Test status
Simulation time 162680975 ps
CPU time 0.86 seconds
Started Jul 07 05:21:45 PM PDT 24
Finished Jul 07 05:21:46 PM PDT 24
Peak memory 206180 kb
Host smart-213b179d-9078-4c3b-8681-4e516c940365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43165
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.431653092
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3013885074
Short name T2123
Test name
Test status
Simulation time 155066350 ps
CPU time 0.78 seconds
Started Jul 07 05:21:41 PM PDT 24
Finished Jul 07 05:21:43 PM PDT 24
Peak memory 206196 kb
Host smart-c1da538b-b507-4555-b840-21b52aa32eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
85074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3013885074
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1987690293
Short name T2369
Test name
Test status
Simulation time 181428510 ps
CPU time 0.9 seconds
Started Jul 07 05:21:43 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206168 kb
Host smart-eaae59c9-3bde-470f-80e9-a32ec7d2721e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19876
90293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1987690293
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3688224985
Short name T187
Test name
Test status
Simulation time 180739828 ps
CPU time 0.79 seconds
Started Jul 07 05:21:44 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206120 kb
Host smart-effe914d-f538-460f-a70b-adc8f43a6ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36882
24985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3688224985
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.1189363799
Short name T1261
Test name
Test status
Simulation time 300366254 ps
CPU time 1.02 seconds
Started Jul 07 05:21:44 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206416 kb
Host smart-5bd758ef-2d39-443f-94b7-0c90214a3344
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1189363799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.1189363799
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.240839727
Short name T1606
Test name
Test status
Simulation time 135072345 ps
CPU time 0.72 seconds
Started Jul 07 05:21:48 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206180 kb
Host smart-a3432da7-4898-4d1d-85e5-1cdc13bd7103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
9727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.240839727
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.642945411
Short name T430
Test name
Test status
Simulation time 165772440 ps
CPU time 0.78 seconds
Started Jul 07 05:21:49 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 206224 kb
Host smart-4425711c-2918-48e2-a411-1fc366bd1eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64294
5411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.642945411
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3505452192
Short name T2008
Test name
Test status
Simulation time 164471938 ps
CPU time 0.84 seconds
Started Jul 07 05:21:47 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206192 kb
Host smart-f75d53fe-960e-4f7a-aa76-e9e97d7dee92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
52192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3505452192
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2322147956
Short name T2713
Test name
Test status
Simulation time 201468260 ps
CPU time 0.94 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:21:53 PM PDT 24
Peak memory 206188 kb
Host smart-719bc297-15f2-4c9c-ab6a-367861b5d559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
47956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2322147956
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3130867698
Short name T2165
Test name
Test status
Simulation time 186071922 ps
CPU time 0.79 seconds
Started Jul 07 05:21:47 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206208 kb
Host smart-e05b461c-8d1b-4ead-8e3c-49ea69905415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31308
67698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3130867698
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3498976708
Short name T1436
Test name
Test status
Simulation time 157212002 ps
CPU time 0.74 seconds
Started Jul 07 05:21:48 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 205084 kb
Host smart-c71f184d-0348-43d2-9e9c-1dad64f13888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34989
76708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3498976708
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.501519095
Short name T1927
Test name
Test status
Simulation time 156209375 ps
CPU time 0.77 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:21:47 PM PDT 24
Peak memory 206436 kb
Host smart-c350c499-de17-4ee7-8f4e-1343f4cc4372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50151
9095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.501519095
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1048752909
Short name T1844
Test name
Test status
Simulation time 163240940 ps
CPU time 0.8 seconds
Started Jul 07 05:21:48 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 206148 kb
Host smart-38002df0-3de6-4f0d-9035-a5c63f23ecc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10487
52909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1048752909
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.453343933
Short name T384
Test name
Test status
Simulation time 243434086 ps
CPU time 1.01 seconds
Started Jul 07 05:21:47 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206116 kb
Host smart-01cf9128-140b-4c38-986e-ca3e413662f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45334
3933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.453343933
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3100286364
Short name T646
Test name
Test status
Simulation time 4019061687 ps
CPU time 38.19 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206516 kb
Host smart-b02978e0-bed1-42ca-9ef6-07983baf7e45
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3100286364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3100286364
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2184787284
Short name T618
Test name
Test status
Simulation time 190839237 ps
CPU time 0.85 seconds
Started Jul 07 05:21:54 PM PDT 24
Finished Jul 07 05:21:56 PM PDT 24
Peak memory 206120 kb
Host smart-7deb14ba-cdfc-4535-8d77-aeec0f199e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
87284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2184787284
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4189218179
Short name T763
Test name
Test status
Simulation time 178390239 ps
CPU time 0.85 seconds
Started Jul 07 05:21:48 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206148 kb
Host smart-551ae3fc-9dca-4716-a047-3c7c3f349f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
18179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4189218179
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.4154636325
Short name T580
Test name
Test status
Simulation time 575724594 ps
CPU time 1.49 seconds
Started Jul 07 05:21:50 PM PDT 24
Finished Jul 07 05:21:52 PM PDT 24
Peak memory 206148 kb
Host smart-28e7b008-b0bf-434e-8919-0c6f7dc428d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41546
36325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.4154636325
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1175616272
Short name T1771
Test name
Test status
Simulation time 8012948019 ps
CPU time 226.19 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206492 kb
Host smart-ca80fce0-15e1-4aa0-8858-636158ed9065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11756
16272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1175616272
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2250125681
Short name T782
Test name
Test status
Simulation time 55076014 ps
CPU time 0.7 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:21:59 PM PDT 24
Peak memory 206148 kb
Host smart-a716b95a-9dee-477f-a7f4-99c73d1dd312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2250125681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2250125681
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3923540666
Short name T1977
Test name
Test status
Simulation time 4135055845 ps
CPU time 4.83 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:21:51 PM PDT 24
Peak memory 206436 kb
Host smart-2187306b-ced1-48b0-b7ed-6a0c7dc6dbe3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3923540666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3923540666
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1743967152
Short name T590
Test name
Test status
Simulation time 13364128126 ps
CPU time 12.62 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:22:05 PM PDT 24
Peak memory 206420 kb
Host smart-4339d5a9-e52f-4c9f-9282-0ac20665fa76
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1743967152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1743967152
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1492974441
Short name T2440
Test name
Test status
Simulation time 23324945073 ps
CPU time 21.84 seconds
Started Jul 07 05:21:48 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 205100 kb
Host smart-9fe46dbc-351b-42fb-a35a-f4726615e7b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1492974441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1492974441
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.386432160
Short name T1595
Test name
Test status
Simulation time 156365984 ps
CPU time 0.79 seconds
Started Jul 07 05:21:50 PM PDT 24
Finished Jul 07 05:21:51 PM PDT 24
Peak memory 206204 kb
Host smart-2353b5b4-21c9-4c19-8a60-884497841163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38643
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.386432160
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3167831491
Short name T2229
Test name
Test status
Simulation time 190310036 ps
CPU time 0.82 seconds
Started Jul 07 05:21:46 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206184 kb
Host smart-a163f986-f2c8-4926-8543-5b008a8fd412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
31491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3167831491
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2529002408
Short name T1439
Test name
Test status
Simulation time 385054275 ps
CPU time 1.24 seconds
Started Jul 07 05:21:54 PM PDT 24
Finished Jul 07 05:21:56 PM PDT 24
Peak memory 206120 kb
Host smart-081d1506-33c0-4b7f-aef1-976445dd497a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25290
02408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2529002408
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1991563525
Short name T2696
Test name
Test status
Simulation time 584577296 ps
CPU time 1.69 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:21:54 PM PDT 24
Peak memory 206196 kb
Host smart-d6944331-32df-4ed3-b302-908461826db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915
63525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1991563525
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.413515374
Short name T2076
Test name
Test status
Simulation time 18008066255 ps
CPU time 32.69 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206416 kb
Host smart-01a79e57-aff0-4fc7-8cf6-fcb30132377b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41351
5374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.413515374
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2400207830
Short name T1800
Test name
Test status
Simulation time 413462824 ps
CPU time 1.29 seconds
Started Jul 07 05:21:55 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 206120 kb
Host smart-1819c1b3-4c2e-49d3-a887-fd65fbd00b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24002
07830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2400207830
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.826322004
Short name T653
Test name
Test status
Simulation time 165333954 ps
CPU time 0.79 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:21:52 PM PDT 24
Peak memory 206068 kb
Host smart-0f7a8f92-533a-4ef9-b82d-91b9b42c8094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82632
2004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.826322004
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1826702680
Short name T1177
Test name
Test status
Simulation time 56575573 ps
CPU time 0.76 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:21:55 PM PDT 24
Peak memory 206200 kb
Host smart-47be3257-b011-4f4f-aa09-83d0dcfb6136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18267
02680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1826702680
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3423592105
Short name T1610
Test name
Test status
Simulation time 887569788 ps
CPU time 2.35 seconds
Started Jul 07 05:21:54 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 206384 kb
Host smart-66a9508e-8c8f-41b0-abe0-b0721c7c1ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
92105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3423592105
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3588021219
Short name T2139
Test name
Test status
Simulation time 151896620 ps
CPU time 1.1 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:21:53 PM PDT 24
Peak memory 206336 kb
Host smart-0bcc1b42-74c4-4277-8b8f-d5a80d46ce7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35880
21219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3588021219
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2111770753
Short name T1181
Test name
Test status
Simulation time 186407695 ps
CPU time 0.82 seconds
Started Jul 07 05:21:50 PM PDT 24
Finished Jul 07 05:21:51 PM PDT 24
Peak memory 206196 kb
Host smart-afad44b8-93cb-4eb1-a69c-95ac980017da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
70753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2111770753
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.427898843
Short name T1920
Test name
Test status
Simulation time 237100858 ps
CPU time 0.86 seconds
Started Jul 07 05:21:55 PM PDT 24
Finished Jul 07 05:21:56 PM PDT 24
Peak memory 206108 kb
Host smart-a8d92b04-cb1e-4c8f-a5b2-9197c224f0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42789
8843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.427898843
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.549229717
Short name T1201
Test name
Test status
Simulation time 227980862 ps
CPU time 0.95 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:21:54 PM PDT 24
Peak memory 206112 kb
Host smart-1b4551c0-e0c1-430d-a664-c8bbe938cde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54922
9717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.549229717
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.722393197
Short name T262
Test name
Test status
Simulation time 4971607372 ps
CPU time 37.55 seconds
Started Jul 07 05:21:49 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206480 kb
Host smart-d2b52463-b969-4cd9-a22c-fed8ddbc9aca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=722393197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.722393197
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.4116247559
Short name T2531
Test name
Test status
Simulation time 217434330 ps
CPU time 0.86 seconds
Started Jul 07 05:21:50 PM PDT 24
Finished Jul 07 05:21:51 PM PDT 24
Peak memory 206200 kb
Host smart-0a980f20-201e-45e1-a3ac-4170cb435958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41162
47559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.4116247559
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3275409580
Short name T840
Test name
Test status
Simulation time 23389563553 ps
CPU time 21.09 seconds
Started Jul 07 05:21:55 PM PDT 24
Finished Jul 07 05:22:17 PM PDT 24
Peak memory 206176 kb
Host smart-1a3b8286-9bbf-42bb-ac87-d397a8b52709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
09580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3275409580
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3494742619
Short name T657
Test name
Test status
Simulation time 3366080262 ps
CPU time 3.65 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 206196 kb
Host smart-cd6e3b98-b15a-4fe0-90ff-e11e1a0b9a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
42619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3494742619
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.779397035
Short name T2190
Test name
Test status
Simulation time 9010867126 ps
CPU time 252.16 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206528 kb
Host smart-36f42c11-1262-4b46-b261-1067554d2b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77939
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.779397035
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3573618442
Short name T2029
Test name
Test status
Simulation time 4224530201 ps
CPU time 38.87 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206368 kb
Host smart-160a4c24-58ba-4530-b49d-498ceffc5b03
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3573618442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3573618442
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2599901237
Short name T920
Test name
Test status
Simulation time 252774654 ps
CPU time 0.95 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:21:53 PM PDT 24
Peak memory 205876 kb
Host smart-fc5f60ff-f5d3-4a3f-94a9-2dc3a1faa1ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2599901237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2599901237
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.379333204
Short name T726
Test name
Test status
Simulation time 183346992 ps
CPU time 0.85 seconds
Started Jul 07 05:21:56 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 206144 kb
Host smart-f0dc7f03-df96-488d-9d77-807642429848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37933
3204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.379333204
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3818891408
Short name T2381
Test name
Test status
Simulation time 5616603869 ps
CPU time 53.14 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:22:44 PM PDT 24
Peak memory 206376 kb
Host smart-d50b29be-e4f8-4d91-ae0f-b4c21519d02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
91408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3818891408
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.970551534
Short name T1855
Test name
Test status
Simulation time 6194739276 ps
CPU time 41.67 seconds
Started Jul 07 05:21:52 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206356 kb
Host smart-c58cbef9-a030-4798-ae85-fb20021ed516
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=970551534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.970551534
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.475327474
Short name T1028
Test name
Test status
Simulation time 167413445 ps
CPU time 0.83 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:21:54 PM PDT 24
Peak memory 206180 kb
Host smart-58e148bf-cce0-4dbf-82e1-52f003349ac3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=475327474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.475327474
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1628789657
Short name T788
Test name
Test status
Simulation time 139075199 ps
CPU time 0.77 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:21:52 PM PDT 24
Peak memory 206192 kb
Host smart-09957ec4-4013-4412-a064-538e9dffd8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287
89657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1628789657
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.151623330
Short name T656
Test name
Test status
Simulation time 168284727 ps
CPU time 0.77 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:21:55 PM PDT 24
Peak memory 206200 kb
Host smart-f4a43035-7ac5-4cdd-ad6c-4af78e6498e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15162
3330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.151623330
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3472835199
Short name T1029
Test name
Test status
Simulation time 169097411 ps
CPU time 0.77 seconds
Started Jul 07 05:21:51 PM PDT 24
Finished Jul 07 05:21:52 PM PDT 24
Peak memory 206152 kb
Host smart-289efe2b-3f0d-4ddc-b1ff-3d74725d55ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34728
35199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3472835199
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1543774026
Short name T1923
Test name
Test status
Simulation time 185519866 ps
CPU time 0.91 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:21:54 PM PDT 24
Peak memory 206192 kb
Host smart-0e515b42-a46e-4981-b752-539a64a9f629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15437
74026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1543774026
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2836582624
Short name T946
Test name
Test status
Simulation time 152322670 ps
CPU time 0.78 seconds
Started Jul 07 05:21:53 PM PDT 24
Finished Jul 07 05:21:55 PM PDT 24
Peak memory 206120 kb
Host smart-e650a738-426c-4de4-8cd6-4ca91b9e3339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28365
82624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2836582624
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1241716522
Short name T1743
Test name
Test status
Simulation time 252838911 ps
CPU time 0.94 seconds
Started Jul 07 05:21:55 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 206084 kb
Host smart-01c67b83-de2e-4431-887a-f35119684993
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1241716522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1241716522
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3632115615
Short name T2205
Test name
Test status
Simulation time 145420581 ps
CPU time 0.77 seconds
Started Jul 07 05:21:59 PM PDT 24
Finished Jul 07 05:22:01 PM PDT 24
Peak memory 206236 kb
Host smart-02f9c0a1-7008-494a-9358-0d0921dbcca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36321
15615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3632115615
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1590524623
Short name T2172
Test name
Test status
Simulation time 44477722 ps
CPU time 0.67 seconds
Started Jul 07 05:21:57 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 206184 kb
Host smart-0b99bc44-d2ee-47f8-adb7-ac64f5e98bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15905
24623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1590524623
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.438949250
Short name T976
Test name
Test status
Simulation time 14268861448 ps
CPU time 29.16 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206580 kb
Host smart-be426c3e-1f96-4756-937a-485c02105752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43894
9250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.438949250
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.265518313
Short name T2164
Test name
Test status
Simulation time 179082762 ps
CPU time 0.83 seconds
Started Jul 07 05:21:57 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 206204 kb
Host smart-faef0a2e-baa7-4366-a0fc-b285d6fb5aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551
8313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.265518313
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.352257131
Short name T2495
Test name
Test status
Simulation time 234907092 ps
CPU time 0.91 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:21:59 PM PDT 24
Peak memory 206152 kb
Host smart-5dbd7ee7-ca16-4429-b442-52942fc907a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35225
7131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.352257131
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2525674314
Short name T2557
Test name
Test status
Simulation time 161095890 ps
CPU time 0.8 seconds
Started Jul 07 05:22:00 PM PDT 24
Finished Jul 07 05:22:01 PM PDT 24
Peak memory 206044 kb
Host smart-e1023887-76ea-48d0-b65f-d2afc465170f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
74314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2525674314
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.290307238
Short name T1872
Test name
Test status
Simulation time 149645828 ps
CPU time 0.81 seconds
Started Jul 07 05:21:56 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 206168 kb
Host smart-9af9b63c-54a2-4a52-951f-9cb6c99de6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29030
7238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.290307238
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4032178717
Short name T680
Test name
Test status
Simulation time 178156814 ps
CPU time 0.8 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206180 kb
Host smart-5fbead64-108c-4808-8e13-e7d27efcfd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40321
78717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4032178717
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.449655119
Short name T82
Test name
Test status
Simulation time 196161781 ps
CPU time 0.82 seconds
Started Jul 07 05:21:56 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 206436 kb
Host smart-637c4982-dffb-4090-82f4-3a04bcbecee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44965
5119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.449655119
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.834570034
Short name T1239
Test name
Test status
Simulation time 177577470 ps
CPU time 0.82 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:21:59 PM PDT 24
Peak memory 206172 kb
Host smart-1759aa4f-23e1-4c51-92da-4ea964ef2abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83457
0034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.834570034
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2053369194
Short name T1945
Test name
Test status
Simulation time 246696278 ps
CPU time 1.08 seconds
Started Jul 07 05:21:59 PM PDT 24
Finished Jul 07 05:22:01 PM PDT 24
Peak memory 206208 kb
Host smart-6f34f72f-c8db-47ce-b54f-5b52402360f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20533
69194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2053369194
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1977281944
Short name T1055
Test name
Test status
Simulation time 3997201631 ps
CPU time 38.36 seconds
Started Jul 07 05:21:55 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206316 kb
Host smart-78062a96-124d-4f7a-a490-1c73c9b41f4b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1977281944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1977281944
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.697300271
Short name T719
Test name
Test status
Simulation time 189398208 ps
CPU time 0.85 seconds
Started Jul 07 05:21:57 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 206184 kb
Host smart-50c07c3c-90de-48e1-8600-2403e2b38849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69730
0271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.697300271
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.93291663
Short name T879
Test name
Test status
Simulation time 204089807 ps
CPU time 0.84 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206200 kb
Host smart-5b78d3c2-5324-4ac0-ba2b-548a5822ef64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93291
663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.93291663
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1519668393
Short name T2655
Test name
Test status
Simulation time 285512071 ps
CPU time 1.07 seconds
Started Jul 07 05:22:01 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 206100 kb
Host smart-deac4b4e-8f2b-434c-a9b3-6e3441538344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196
68393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1519668393
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3987719959
Short name T1929
Test name
Test status
Simulation time 5750588142 ps
CPU time 155.62 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206452 kb
Host smart-e4d0b3d2-16d1-489b-9854-d755bfa0b2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
19959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3987719959
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3756142350
Short name T559
Test name
Test status
Simulation time 33800270 ps
CPU time 0.64 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206180 kb
Host smart-0544e3ca-a7f4-4b91-a034-6b171ab28bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3756142350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3756142350
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2393838013
Short name T1870
Test name
Test status
Simulation time 4133772821 ps
CPU time 5.01 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 206344 kb
Host smart-717278ac-0bc1-431e-947d-824f8978bd53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2393838013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2393838013
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2597307208
Short name T229
Test name
Test status
Simulation time 13342668736 ps
CPU time 12.52 seconds
Started Jul 07 05:21:56 PM PDT 24
Finished Jul 07 05:22:09 PM PDT 24
Peak memory 206172 kb
Host smart-c2d05f09-747f-4ea6-98a1-c486615299a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2597307208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2597307208
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3735905378
Short name T767
Test name
Test status
Simulation time 23343720385 ps
CPU time 29.15 seconds
Started Jul 07 05:22:00 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206288 kb
Host smart-655534f7-f067-414b-be52-e0df2620061d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3735905378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3735905378
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.4260135395
Short name T2104
Test name
Test status
Simulation time 150434930 ps
CPU time 0.8 seconds
Started Jul 07 05:21:55 PM PDT 24
Finished Jul 07 05:21:56 PM PDT 24
Peak memory 206116 kb
Host smart-8820a524-59f5-4316-b6f6-0c4d642fb81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
35395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.4260135395
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3437280492
Short name T543
Test name
Test status
Simulation time 216436840 ps
CPU time 0.86 seconds
Started Jul 07 05:21:56 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 206192 kb
Host smart-0b23e42a-90f1-4667-a8b9-49e93f65bc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34372
80492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3437280492
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1106453784
Short name T2697
Test name
Test status
Simulation time 340763026 ps
CPU time 1.14 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206200 kb
Host smart-276b0e95-7250-44ae-983a-ac93a78828c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
53784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1106453784
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2602698896
Short name T554
Test name
Test status
Simulation time 505372773 ps
CPU time 1.41 seconds
Started Jul 07 05:21:58 PM PDT 24
Finished Jul 07 05:22:01 PM PDT 24
Peak memory 206132 kb
Host smart-2c75fb01-376f-4bda-91bc-b241899a2aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26026
98896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2602698896
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3532754170
Short name T1616
Test name
Test status
Simulation time 22707073839 ps
CPU time 42.5 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206424 kb
Host smart-54c4ed6f-f7e0-4ce3-94fc-b7a588892bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
54170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3532754170
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3844024519
Short name T517
Test name
Test status
Simulation time 363629383 ps
CPU time 1.26 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206188 kb
Host smart-4b07f4aa-1f83-447c-ae38-9c4fa1a16f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
24519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3844024519
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2294845809
Short name T2049
Test name
Test status
Simulation time 154081675 ps
CPU time 0.76 seconds
Started Jul 07 05:22:03 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206192 kb
Host smart-3147768a-b620-4a67-9da8-af5e96efdf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22948
45809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2294845809
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.232931448
Short name T654
Test name
Test status
Simulation time 98370782 ps
CPU time 0.73 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206140 kb
Host smart-0188cc8e-a029-43df-b5f1-2328eee54c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23293
1448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.232931448
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2727489706
Short name T834
Test name
Test status
Simulation time 855492946 ps
CPU time 1.9 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206448 kb
Host smart-9d8e9e2f-6c02-484a-bf37-710b896f48ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27274
89706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2727489706
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3426990769
Short name T2092
Test name
Test status
Simulation time 216357388 ps
CPU time 0.86 seconds
Started Jul 07 05:22:04 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206192 kb
Host smart-4d8c51d1-bb7a-4689-aa39-fd23c6072f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34269
90769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3426990769
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2808862289
Short name T579
Test name
Test status
Simulation time 168923519 ps
CPU time 0.74 seconds
Started Jul 07 05:22:03 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206192 kb
Host smart-4acbb2c4-d151-417b-93e2-f29e43212dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28088
62289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2808862289
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2729818856
Short name T2242
Test name
Test status
Simulation time 255627185 ps
CPU time 1.04 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206204 kb
Host smart-9dcc2661-6623-4dec-9186-bb45429c6778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298
18856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2729818856
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2217591896
Short name T1808
Test name
Test status
Simulation time 207693063 ps
CPU time 0.86 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206152 kb
Host smart-c01454db-f403-4653-a00a-127ff471842f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
91896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2217591896
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.220307447
Short name T2226
Test name
Test status
Simulation time 23328238046 ps
CPU time 24.17 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 206172 kb
Host smart-1d6c4692-21af-4bc5-ba92-68da16a17889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22030
7447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.220307447
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3524001798
Short name T1959
Test name
Test status
Simulation time 3352196299 ps
CPU time 4.32 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206268 kb
Host smart-2a09780c-e8f1-4c56-8e3f-63d24ad41543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35240
01798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3524001798
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.565038145
Short name T764
Test name
Test status
Simulation time 10939810085 ps
CPU time 109.11 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206508 kb
Host smart-b8f77aa8-acd7-42e5-acdb-18a425dabcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56503
8145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.565038145
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.704610360
Short name T581
Test name
Test status
Simulation time 4233107761 ps
CPU time 38.35 seconds
Started Jul 07 05:22:04 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206136 kb
Host smart-c7e84484-969a-4340-8ce5-d9f5b03ec7bf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=704610360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.704610360
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.653952234
Short name T1629
Test name
Test status
Simulation time 238304399 ps
CPU time 0.87 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206088 kb
Host smart-ff13db2b-cb3d-4c80-aa63-f940458fe7d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=653952234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.653952234
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3353417888
Short name T1076
Test name
Test status
Simulation time 206256002 ps
CPU time 0.85 seconds
Started Jul 07 05:21:59 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206188 kb
Host smart-3df66e60-c4e6-4290-b5c2-9f4bd69aecfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
17888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3353417888
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1911782581
Short name T2431
Test name
Test status
Simulation time 4808081812 ps
CPU time 126.25 seconds
Started Jul 07 05:22:07 PM PDT 24
Finished Jul 07 05:24:14 PM PDT 24
Peak memory 206444 kb
Host smart-de631dec-02e0-4190-a763-48cb23aadb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
82581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1911782581
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.812797754
Short name T616
Test name
Test status
Simulation time 5037131057 ps
CPU time 133.46 seconds
Started Jul 07 05:22:01 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206432 kb
Host smart-b6c7283b-eccc-4795-8caa-c76964936386
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=812797754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.812797754
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3181619587
Short name T898
Test name
Test status
Simulation time 156698816 ps
CPU time 0.78 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206164 kb
Host smart-e72a328a-a0b9-4bbe-8795-a1543df2b4b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3181619587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3181619587
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.158111597
Short name T2536
Test name
Test status
Simulation time 149183674 ps
CPU time 0.8 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:09 PM PDT 24
Peak memory 206128 kb
Host smart-f3e72fbc-36a6-4736-ab16-6cc9c18c027c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15811
1597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.158111597
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2178310283
Short name T903
Test name
Test status
Simulation time 187514539 ps
CPU time 0.9 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206136 kb
Host smart-4334b255-b819-4ade-b8ed-bc9821052757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21783
10283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2178310283
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.64623903
Short name T1976
Test name
Test status
Simulation time 165965742 ps
CPU time 0.78 seconds
Started Jul 07 05:22:07 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206104 kb
Host smart-8cd46146-0aa4-44e5-9784-0f2b1f79a48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64623
903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.64623903
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.4172273949
Short name T1472
Test name
Test status
Simulation time 158451296 ps
CPU time 0.78 seconds
Started Jul 07 05:22:04 PM PDT 24
Finished Jul 07 05:22:05 PM PDT 24
Peak memory 206184 kb
Host smart-aea8a867-f8e3-489a-89a6-1f3f755b3348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41722
73949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.4172273949
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3211182001
Short name T207
Test name
Test status
Simulation time 167907544 ps
CPU time 0.8 seconds
Started Jul 07 05:22:00 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206104 kb
Host smart-b8221af2-d997-4bea-b1db-a6e1d081c8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32111
82001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3211182001
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.744482353
Short name T2251
Test name
Test status
Simulation time 252887091 ps
CPU time 0.99 seconds
Started Jul 07 05:22:07 PM PDT 24
Finished Jul 07 05:22:09 PM PDT 24
Peak memory 206164 kb
Host smart-73f04901-17e7-4049-a56c-e7e0195aa2e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=744482353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.744482353
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3058775824
Short name T1568
Test name
Test status
Simulation time 140352360 ps
CPU time 0.76 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206184 kb
Host smart-5e4ee40f-d698-4ba1-807d-f8fb8edb07b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30587
75824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3058775824
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.977289386
Short name T1351
Test name
Test status
Simulation time 55795031 ps
CPU time 0.69 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 206188 kb
Host smart-643d5d77-f3b1-4d3a-b31a-faeff0f77683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97728
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.977289386
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1807265329
Short name T1280
Test name
Test status
Simulation time 7065726185 ps
CPU time 16.59 seconds
Started Jul 07 05:22:03 PM PDT 24
Finished Jul 07 05:22:20 PM PDT 24
Peak memory 206324 kb
Host smart-289711b3-bf1e-4e16-9b28-c881e89e40e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072
65329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1807265329
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1388351478
Short name T2392
Test name
Test status
Simulation time 178863342 ps
CPU time 0.84 seconds
Started Jul 07 05:22:00 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206196 kb
Host smart-90ff8bbe-ef2f-4522-af74-96fca55c74f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13883
51478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1388351478
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1197374082
Short name T1991
Test name
Test status
Simulation time 246992419 ps
CPU time 1 seconds
Started Jul 07 05:22:01 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 206184 kb
Host smart-c71f9cbd-d247-4424-844f-89716ac4f0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11973
74082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1197374082
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1389418395
Short name T1287
Test name
Test status
Simulation time 231539396 ps
CPU time 0.88 seconds
Started Jul 07 05:22:00 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206152 kb
Host smart-d44b821c-fd91-40f3-b671-2869f5054c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894
18395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1389418395
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1905071697
Short name T515
Test name
Test status
Simulation time 148451914 ps
CPU time 0.82 seconds
Started Jul 07 05:22:02 PM PDT 24
Finished Jul 07 05:22:04 PM PDT 24
Peak memory 206172 kb
Host smart-aa53f978-96f9-4a80-a987-c28858d74477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19050
71697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1905071697
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1181519428
Short name T1961
Test name
Test status
Simulation time 196534753 ps
CPU time 0.86 seconds
Started Jul 07 05:22:07 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206188 kb
Host smart-2589db59-42ec-4028-9ff2-29031812906b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11815
19428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1181519428
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2061782227
Short name T693
Test name
Test status
Simulation time 154482135 ps
CPU time 0.77 seconds
Started Jul 07 05:22:01 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206108 kb
Host smart-2679c94b-d9c8-4706-a120-01244b8a3f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
82227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2061782227
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.877461280
Short name T1144
Test name
Test status
Simulation time 210525806 ps
CPU time 0.81 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206112 kb
Host smart-32da3da9-9b72-49f2-9a89-41d67f2f4fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87746
1280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.877461280
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2741394479
Short name T2502
Test name
Test status
Simulation time 238534454 ps
CPU time 0.95 seconds
Started Jul 07 05:22:01 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 206164 kb
Host smart-1e17a0da-10b0-4355-91ce-f62e9770e6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
94479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2741394479
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1580736405
Short name T418
Test name
Test status
Simulation time 3313811816 ps
CPU time 86.04 seconds
Started Jul 07 05:22:07 PM PDT 24
Finished Jul 07 05:23:34 PM PDT 24
Peak memory 206404 kb
Host smart-a9a14fe3-ac85-43bc-b427-aa453cf1fbeb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1580736405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1580736405
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.356789890
Short name T812
Test name
Test status
Simulation time 169123382 ps
CPU time 0.77 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206108 kb
Host smart-c5b2f821-25ca-4b35-ae74-73f7d6c2d60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35678
9890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.356789890
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.490260737
Short name T1227
Test name
Test status
Simulation time 150606575 ps
CPU time 0.76 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206040 kb
Host smart-86cffa9e-5789-4df2-b06d-fb1ccf0d89ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49026
0737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.490260737
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2563257436
Short name T390
Test name
Test status
Simulation time 472914574 ps
CPU time 1.27 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206184 kb
Host smart-796f453b-9ee3-44d0-bdf3-e7d8bc94ebe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
57436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2563257436
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.180039576
Short name T819
Test name
Test status
Simulation time 7229952160 ps
CPU time 73.16 seconds
Started Jul 07 05:22:10 PM PDT 24
Finished Jul 07 05:23:23 PM PDT 24
Peak memory 206444 kb
Host smart-50270380-eb7a-43f2-a1d6-aa5218348e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003
9576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.180039576
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2334424062
Short name T1529
Test name
Test status
Simulation time 42678942 ps
CPU time 0.72 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206044 kb
Host smart-543a9f27-d58c-4e79-b17f-4d2b1c02cd64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2334424062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2334424062
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.482058903
Short name T1031
Test name
Test status
Simulation time 3504545772 ps
CPU time 4.35 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206436 kb
Host smart-0f779237-a4b2-43ef-962c-aea94a29e0ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=482058903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.482058903
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.94971368
Short name T2708
Test name
Test status
Simulation time 13377788560 ps
CPU time 12.69 seconds
Started Jul 07 05:22:10 PM PDT 24
Finished Jul 07 05:22:23 PM PDT 24
Peak memory 206232 kb
Host smart-090af594-7c97-4a17-8a0b-68e8eb167867
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=94971368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.94971368
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3263809973
Short name T778
Test name
Test status
Simulation time 23333585162 ps
CPU time 22.75 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206224 kb
Host smart-1588b4eb-b4c0-4268-af56-6a7c3379edb1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3263809973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3263809973
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3781679428
Short name T603
Test name
Test status
Simulation time 224341665 ps
CPU time 0.82 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206148 kb
Host smart-7524ac7b-b16b-4db7-a109-4e19ca6aba7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37816
79428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3781679428
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.268406773
Short name T60
Test name
Test status
Simulation time 158960060 ps
CPU time 0.85 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206108 kb
Host smart-28a41916-7324-4a4a-97fc-2c4fd1ca05f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26840
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.268406773
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.594039302
Short name T2037
Test name
Test status
Simulation time 487800218 ps
CPU time 1.62 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206044 kb
Host smart-7751cd61-fd44-4188-bd54-5360972c22fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59403
9302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.594039302
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3840978594
Short name T1020
Test name
Test status
Simulation time 660399597 ps
CPU time 1.56 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206400 kb
Host smart-f5b5ba32-cb54-4c9e-91dd-6ab39ab599eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38409
78594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3840978594
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3753120857
Short name T200
Test name
Test status
Simulation time 8310042747 ps
CPU time 15.23 seconds
Started Jul 07 05:22:10 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 206456 kb
Host smart-ede64631-ccec-4175-9dcb-81398f1b92ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37531
20857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3753120857
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1399099822
Short name T1934
Test name
Test status
Simulation time 497632983 ps
CPU time 1.62 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206156 kb
Host smart-91e00b06-90d0-4a59-a77a-1c37ce7bc97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
99822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1399099822
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2391939241
Short name T1310
Test name
Test status
Simulation time 169734125 ps
CPU time 0.83 seconds
Started Jul 07 05:22:05 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206200 kb
Host smart-402c19c1-e0b7-45d2-8f51-9ec95daa19ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23919
39241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2391939241
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.100877512
Short name T504
Test name
Test status
Simulation time 67773562 ps
CPU time 0.68 seconds
Started Jul 07 05:22:10 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206120 kb
Host smart-ade43b53-3f78-4449-bfc5-4dcfc006d5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
7512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.100877512
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.4165498908
Short name T249
Test name
Test status
Simulation time 909565404 ps
CPU time 2.15 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206424 kb
Host smart-4c55df21-a31d-4a89-bba8-f9558d2f4af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41654
98908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.4165498908
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.609819273
Short name T1153
Test name
Test status
Simulation time 217886173 ps
CPU time 1.39 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206384 kb
Host smart-f72d852a-9a05-4ef9-a445-2dc912ccf81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60981
9273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.609819273
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3195146059
Short name T1931
Test name
Test status
Simulation time 246312297 ps
CPU time 0.89 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:10 PM PDT 24
Peak memory 206032 kb
Host smart-3a95c74c-88bc-41bf-b21e-531ae21a2bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
46059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3195146059
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.361349313
Short name T481
Test name
Test status
Simulation time 141666906 ps
CPU time 0.78 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 206420 kb
Host smart-b665653b-2948-41f4-a579-caa6a1a0513a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36134
9313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.361349313
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2914441115
Short name T2062
Test name
Test status
Simulation time 228105456 ps
CPU time 0.89 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:09 PM PDT 24
Peak memory 206116 kb
Host smart-851af6ec-1237-4b41-8899-fcb16aa7842a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29144
41115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2914441115
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3363463569
Short name T955
Test name
Test status
Simulation time 163749356 ps
CPU time 0.81 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:07 PM PDT 24
Peak memory 206192 kb
Host smart-713d422f-9a68-43f5-973a-f6df232f336b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33634
63569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3363463569
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.4270871003
Short name T1707
Test name
Test status
Simulation time 23273630736 ps
CPU time 21.38 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206268 kb
Host smart-5c00d2aa-a6d4-44bb-ba7d-5c4d9b63a0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42708
71003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.4270871003
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2281904295
Short name T1097
Test name
Test status
Simulation time 3315150837 ps
CPU time 3.74 seconds
Started Jul 07 05:22:09 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206100 kb
Host smart-47313cf0-0c97-40ba-9125-661ce0adb17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22819
04295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2281904295
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.4126420004
Short name T2405
Test name
Test status
Simulation time 9029593936 ps
CPU time 257.43 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:26:26 PM PDT 24
Peak memory 206520 kb
Host smart-f8431bb6-edab-4566-a869-0df5d97385ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
20004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.4126420004
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3386881900
Short name T2421
Test name
Test status
Simulation time 4729855608 ps
CPU time 32.34 seconds
Started Jul 07 05:22:08 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206432 kb
Host smart-09b159f8-db91-4600-9aa9-01e9621a9e6d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3386881900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3386881900
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1123288978
Short name T2429
Test name
Test status
Simulation time 289519061 ps
CPU time 1.02 seconds
Started Jul 07 05:22:06 PM PDT 24
Finished Jul 07 05:22:08 PM PDT 24
Peak memory 205876 kb
Host smart-598cadbc-d5ad-485c-9be0-ed9087df89e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1123288978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1123288978
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2343468527
Short name T1408
Test name
Test status
Simulation time 189887814 ps
CPU time 0.87 seconds
Started Jul 07 05:22:11 PM PDT 24
Finished Jul 07 05:22:12 PM PDT 24
Peak memory 206152 kb
Host smart-cf32df6c-bc75-475e-8f3a-627386cb8094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23434
68527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2343468527
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2758082365
Short name T437
Test name
Test status
Simulation time 4588433030 ps
CPU time 32.36 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:22:46 PM PDT 24
Peak memory 206528 kb
Host smart-65008a40-b187-4432-b79b-cf8b5fac3913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
82365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2758082365
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1853787671
Short name T438
Test name
Test status
Simulation time 3727655835 ps
CPU time 103.76 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206444 kb
Host smart-89f79248-3d22-4d87-81ef-dbf6ccef14fe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1853787671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1853787671
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3940464521
Short name T1273
Test name
Test status
Simulation time 162990656 ps
CPU time 0.83 seconds
Started Jul 07 05:22:14 PM PDT 24
Finished Jul 07 05:22:15 PM PDT 24
Peak memory 206220 kb
Host smart-c6887684-b8f7-43cb-a1f0-6e6ec90259bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3940464521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3940464521
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.4243861758
Short name T1256
Test name
Test status
Simulation time 180524711 ps
CPU time 0.83 seconds
Started Jul 07 05:22:15 PM PDT 24
Finished Jul 07 05:22:16 PM PDT 24
Peak memory 206208 kb
Host smart-1206270d-c18d-414e-a684-ab7fd056454c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
61758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.4243861758
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3733573259
Short name T154
Test name
Test status
Simulation time 208617036 ps
CPU time 0.88 seconds
Started Jul 07 05:22:10 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206188 kb
Host smart-9ecf6df0-eb42-4806-96ba-5a8415f03aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37335
73259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3733573259
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.184648327
Short name T2218
Test name
Test status
Simulation time 189012476 ps
CPU time 0.85 seconds
Started Jul 07 05:22:11 PM PDT 24
Finished Jul 07 05:22:12 PM PDT 24
Peak memory 206152 kb
Host smart-c3a29399-601d-4ce9-86b6-e40b9470c5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18464
8327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.184648327
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3953257780
Short name T1284
Test name
Test status
Simulation time 228110478 ps
CPU time 0.84 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206192 kb
Host smart-29086fef-ab7d-47c2-919a-69aa35a55cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39532
57780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3953257780
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3464368591
Short name T565
Test name
Test status
Simulation time 168845491 ps
CPU time 0.83 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206064 kb
Host smart-b4e7ca65-6ba5-4195-909e-4461f1c84d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
68591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3464368591
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.396016105
Short name T2473
Test name
Test status
Simulation time 151434964 ps
CPU time 0.85 seconds
Started Jul 07 05:22:11 PM PDT 24
Finished Jul 07 05:22:12 PM PDT 24
Peak memory 206200 kb
Host smart-934d2600-071f-4d00-bd8d-84507725d8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39601
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.396016105
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3224962005
Short name T593
Test name
Test status
Simulation time 266432366 ps
CPU time 1.06 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:22:15 PM PDT 24
Peak memory 206176 kb
Host smart-c4ea4339-653f-4936-acd5-8126fcc446d1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3224962005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3224962005
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.406363297
Short name T2279
Test name
Test status
Simulation time 172503074 ps
CPU time 0.77 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:22:14 PM PDT 24
Peak memory 206196 kb
Host smart-2b14b1eb-262e-454e-ba89-9c4568f16428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636
3297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.406363297
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.878159066
Short name T1474
Test name
Test status
Simulation time 120625172 ps
CPU time 0.75 seconds
Started Jul 07 05:22:14 PM PDT 24
Finished Jul 07 05:22:15 PM PDT 24
Peak memory 205924 kb
Host smart-b525c069-5bc2-4ea0-a593-7e0f7e854faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87815
9066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.878159066
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3403773235
Short name T1349
Test name
Test status
Simulation time 13070017363 ps
CPU time 30.45 seconds
Started Jul 07 05:22:10 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206480 kb
Host smart-b764097c-43bb-49e0-97be-8a816b730dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
73235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3403773235
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2779707114
Short name T2161
Test name
Test status
Simulation time 206588214 ps
CPU time 0.82 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206036 kb
Host smart-7c0a590e-5c59-428a-8c98-fb5e045b08a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27797
07114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2779707114
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.116723133
Short name T798
Test name
Test status
Simulation time 198922326 ps
CPU time 0.79 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:27 PM PDT 24
Peak memory 206104 kb
Host smart-fc11947d-51be-4a4b-9b6c-2b791ce18332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11672
3133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.116723133
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1227573841
Short name T2445
Test name
Test status
Simulation time 205429052 ps
CPU time 0.86 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206444 kb
Host smart-9caf5d79-9bb2-44ec-bf13-06ec3637572d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12275
73841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1227573841
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3830793672
Short name T2370
Test name
Test status
Simulation time 169904569 ps
CPU time 0.91 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206236 kb
Host smart-89343181-7e15-4ab3-882d-b8d147486189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38307
93672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3830793672
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3374129074
Short name T2023
Test name
Test status
Simulation time 154982572 ps
CPU time 0.82 seconds
Started Jul 07 05:22:15 PM PDT 24
Finished Jul 07 05:22:16 PM PDT 24
Peak memory 206140 kb
Host smart-97aea023-f9b4-4b78-82b6-ce52b48bb460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33741
29074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3374129074
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1618952333
Short name T2546
Test name
Test status
Simulation time 151618044 ps
CPU time 0.81 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:22:14 PM PDT 24
Peak memory 206152 kb
Host smart-97a744fe-6c11-4db4-ae14-f852a4431108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16189
52333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1618952333
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2063380037
Short name T1462
Test name
Test status
Simulation time 149121851 ps
CPU time 0.89 seconds
Started Jul 07 05:22:14 PM PDT 24
Finished Jul 07 05:22:16 PM PDT 24
Peak memory 206192 kb
Host smart-0b67b79a-ad05-47ab-a1c0-bc3cf31c2ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20633
80037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2063380037
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2134211528
Short name T2294
Test name
Test status
Simulation time 201148263 ps
CPU time 0.88 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206108 kb
Host smart-eaafb7e3-0ac4-4f4a-9f4e-f397007c004e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342
11528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2134211528
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.658334576
Short name T376
Test name
Test status
Simulation time 4526584332 ps
CPU time 41.96 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206416 kb
Host smart-c3261359-034d-4394-a1f3-dc5adf3e1730
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=658334576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.658334576
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2848608934
Short name T638
Test name
Test status
Simulation time 158650388 ps
CPU time 0.75 seconds
Started Jul 07 05:22:14 PM PDT 24
Finished Jul 07 05:22:15 PM PDT 24
Peak memory 206188 kb
Host smart-fb697b5b-2d11-4df5-8751-4d56326325d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
08934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2848608934
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.740464691
Short name T1708
Test name
Test status
Simulation time 216318808 ps
CPU time 0.89 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206060 kb
Host smart-e8376366-b98b-4e54-8d46-6c64a66443be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74046
4691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.740464691
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3364190862
Short name T1697
Test name
Test status
Simulation time 870759614 ps
CPU time 1.86 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:22:15 PM PDT 24
Peak memory 206384 kb
Host smart-4bbdc824-1f7b-465b-8b11-2d36730e7bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
90862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3364190862
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1508140278
Short name T2274
Test name
Test status
Simulation time 7966192587 ps
CPU time 60.81 seconds
Started Jul 07 05:22:11 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206404 kb
Host smart-fcd53dd3-3fde-418a-9135-cd17cf30969e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15081
40278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1508140278
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3235502662
Short name T1582
Test name
Test status
Simulation time 71053119 ps
CPU time 0.7 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:27 PM PDT 24
Peak memory 206160 kb
Host smart-1b5b82da-51bb-4ba3-b671-e31c4d9a1d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3235502662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3235502662
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2786715797
Short name T775
Test name
Test status
Simulation time 4283731034 ps
CPU time 4.89 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206152 kb
Host smart-53133bbd-b3ef-430a-a714-662517a95439
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2786715797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2786715797
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3544856457
Short name T1012
Test name
Test status
Simulation time 13417661597 ps
CPU time 14.16 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 206152 kb
Host smart-b32dd00d-6420-40b1-a203-39ee8c1e1316
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3544856457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3544856457
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3885021603
Short name T11
Test name
Test status
Simulation time 23365923108 ps
CPU time 24.59 seconds
Started Jul 07 05:22:14 PM PDT 24
Finished Jul 07 05:22:39 PM PDT 24
Peak memory 205904 kb
Host smart-7d7138f0-21ee-4faf-a12a-c3d954645acd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3885021603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3885021603
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.359616067
Short name T2520
Test name
Test status
Simulation time 154894252 ps
CPU time 0.81 seconds
Started Jul 07 05:22:13 PM PDT 24
Finished Jul 07 05:22:15 PM PDT 24
Peak memory 206196 kb
Host smart-72c854c5-32e1-4313-a570-2047cd6dc30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
6067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.359616067
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.401506936
Short name T1986
Test name
Test status
Simulation time 136639326 ps
CPU time 0.78 seconds
Started Jul 07 05:22:12 PM PDT 24
Finished Jul 07 05:22:13 PM PDT 24
Peak memory 206196 kb
Host smart-ad626033-bc7e-4ec2-94e3-b85b349c12bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.401506936
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1058181330
Short name T1434
Test name
Test status
Simulation time 1399429409 ps
CPU time 2.93 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:24 PM PDT 24
Peak memory 206416 kb
Host smart-147cd2d3-aa98-4662-999a-d28a497f061c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581
81330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1058181330
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1960322108
Short name T1560
Test name
Test status
Simulation time 15059431760 ps
CPU time 25.79 seconds
Started Jul 07 05:22:16 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206344 kb
Host smart-025f59eb-c7bb-435f-9675-c99d9119fdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19603
22108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1960322108
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2498083457
Short name T2006
Test name
Test status
Simulation time 158263318 ps
CPU time 0.76 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206188 kb
Host smart-708ee93a-3b96-44d6-8290-9994a4bc6f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
83457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2498083457
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3915011827
Short name T2276
Test name
Test status
Simulation time 36270986 ps
CPU time 0.64 seconds
Started Jul 07 05:22:17 PM PDT 24
Finished Jul 07 05:22:18 PM PDT 24
Peak memory 206028 kb
Host smart-62b9e643-8937-4ab8-978a-40d444db94c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39150
11827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3915011827
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.18530203
Short name T1063
Test name
Test status
Simulation time 856967476 ps
CPU time 2.36 seconds
Started Jul 07 05:22:19 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206352 kb
Host smart-b217e713-a762-420f-8c7c-e7a33aee1219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18530
203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.18530203
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.20810530
Short name T1480
Test name
Test status
Simulation time 232870198 ps
CPU time 1.59 seconds
Started Jul 07 05:22:22 PM PDT 24
Finished Jul 07 05:22:24 PM PDT 24
Peak memory 206428 kb
Host smart-5feafa04-bfa2-4ff2-9cd5-3764fee9ad82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.20810530
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1008407672
Short name T2328
Test name
Test status
Simulation time 211645290 ps
CPU time 0.87 seconds
Started Jul 07 05:22:18 PM PDT 24
Finished Jul 07 05:22:19 PM PDT 24
Peak memory 206184 kb
Host smart-24741bb0-3d79-4ca6-bd19-349b7056e7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10084
07672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1008407672
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.476223447
Short name T1753
Test name
Test status
Simulation time 170068227 ps
CPU time 0.77 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:19 PM PDT 24
Peak memory 206032 kb
Host smart-9d783bc2-739c-4fe3-a2c6-faf59149a8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47622
3447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.476223447
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1587825081
Short name T2485
Test name
Test status
Simulation time 229559253 ps
CPU time 0.85 seconds
Started Jul 07 05:22:20 PM PDT 24
Finished Jul 07 05:22:21 PM PDT 24
Peak memory 206184 kb
Host smart-6d1098eb-b758-4e4b-974c-7116492d6d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15878
25081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1587825081
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.4024773441
Short name T1294
Test name
Test status
Simulation time 173592449 ps
CPU time 0.84 seconds
Started Jul 07 05:22:18 PM PDT 24
Finished Jul 07 05:22:20 PM PDT 24
Peak memory 206116 kb
Host smart-780071ec-3998-4cf4-aa47-719d4a59df41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40247
73441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.4024773441
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2925653975
Short name T2191
Test name
Test status
Simulation time 23309219809 ps
CPU time 23.61 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:50 PM PDT 24
Peak memory 206184 kb
Host smart-50fff255-1f2e-4564-b0b6-48f2749ff17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29256
53975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2925653975
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2327101830
Short name T2426
Test name
Test status
Simulation time 3315960755 ps
CPU time 3.84 seconds
Started Jul 07 05:22:22 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 206264 kb
Host smart-f46ba26f-6a8a-47be-8bde-3fecc5872104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23271
01830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2327101830
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.404846422
Short name T1232
Test name
Test status
Simulation time 9542917416 ps
CPU time 254.4 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 206432 kb
Host smart-3ff67a29-f084-4b09-b54f-d2ad35cfb997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
6422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.404846422
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1657678568
Short name T624
Test name
Test status
Simulation time 3586099458 ps
CPU time 25.54 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206360 kb
Host smart-9ba06921-907d-41cb-b594-5886ce78eda4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1657678568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1657678568
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.66222200
Short name T2132
Test name
Test status
Simulation time 255355724 ps
CPU time 0.94 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206100 kb
Host smart-17779dd5-f155-4445-9c18-c8b0b4aa6470
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=66222200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.66222200
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1184162206
Short name T1806
Test name
Test status
Simulation time 194246439 ps
CPU time 0.87 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:27 PM PDT 24
Peak memory 206124 kb
Host smart-5e694dfa-2f2f-4229-9d23-56cb1d3e4e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841
62206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1184162206
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1580621983
Short name T528
Test name
Test status
Simulation time 5940129907 ps
CPU time 162.26 seconds
Started Jul 07 05:22:16 PM PDT 24
Finished Jul 07 05:24:59 PM PDT 24
Peak memory 206400 kb
Host smart-d6358e51-669e-4007-b151-4f435f9fe84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
21983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1580621983
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3299378098
Short name T1783
Test name
Test status
Simulation time 6038542158 ps
CPU time 60 seconds
Started Jul 07 05:22:16 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206476 kb
Host smart-a30ab3ac-aae5-4059-b06b-77c1179d206a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3299378098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3299378098
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.356539
Short name T2573
Test name
Test status
Simulation time 180186059 ps
CPU time 0.82 seconds
Started Jul 07 05:22:20 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206168 kb
Host smart-4cfce201-4376-4045-8a6a-4015b75c31b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=356539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.356539
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2250377628
Short name T2513
Test name
Test status
Simulation time 190675443 ps
CPU time 0.79 seconds
Started Jul 07 05:22:16 PM PDT 24
Finished Jul 07 05:22:17 PM PDT 24
Peak memory 206116 kb
Host smart-e64437ad-fdbf-4b04-804f-40d0c8d5d9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
77628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2250377628
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3858981334
Short name T156
Test name
Test status
Simulation time 194673658 ps
CPU time 0.85 seconds
Started Jul 07 05:22:18 PM PDT 24
Finished Jul 07 05:22:19 PM PDT 24
Peak memory 206196 kb
Host smart-b03c0108-32bc-48fd-9cc4-3639b287bff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38589
81334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3858981334
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1102786988
Short name T1960
Test name
Test status
Simulation time 207689675 ps
CPU time 0.88 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206104 kb
Host smart-6db9e8eb-ea44-4d5f-9445-1db4e29406e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027
86988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1102786988
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2270615706
Short name T385
Test name
Test status
Simulation time 232795692 ps
CPU time 0.91 seconds
Started Jul 07 05:22:17 PM PDT 24
Finished Jul 07 05:22:18 PM PDT 24
Peak memory 206140 kb
Host smart-f1bcd9cd-e97f-4a75-99e4-fca905b40517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
15706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2270615706
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1495228606
Short name T713
Test name
Test status
Simulation time 186920990 ps
CPU time 0.85 seconds
Started Jul 07 05:22:19 PM PDT 24
Finished Jul 07 05:22:21 PM PDT 24
Peak memory 206148 kb
Host smart-5b09400f-2428-4f8f-854b-e4a643158465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14952
28606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1495228606
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.776085370
Short name T178
Test name
Test status
Simulation time 145690359 ps
CPU time 0.8 seconds
Started Jul 07 05:22:16 PM PDT 24
Finished Jul 07 05:22:17 PM PDT 24
Peak memory 206200 kb
Host smart-36173dc0-fed5-406f-a3cb-e5ccdb7eced5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77608
5370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.776085370
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2783456713
Short name T1251
Test name
Test status
Simulation time 251956723 ps
CPU time 1 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:27 PM PDT 24
Peak memory 206088 kb
Host smart-4321f622-c4cc-4398-8ad6-8a39faa594be
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2783456713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2783456713
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3836658262
Short name T1115
Test name
Test status
Simulation time 198659440 ps
CPU time 0.81 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206104 kb
Host smart-b732965f-3cac-4e9d-8edd-ed7ebd29bcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
58262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3836658262
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2520603965
Short name T2564
Test name
Test status
Simulation time 62963614 ps
CPU time 0.68 seconds
Started Jul 07 05:22:18 PM PDT 24
Finished Jul 07 05:22:19 PM PDT 24
Peak memory 206432 kb
Host smart-d4b2ce69-a4ed-4021-ae4d-c93eedf0962a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25206
03965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2520603965
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.4076641504
Short name T2432
Test name
Test status
Simulation time 8898318940 ps
CPU time 21.37 seconds
Started Jul 07 05:22:19 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206472 kb
Host smart-5533c1e8-caac-4013-bf5a-642390f1a3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40766
41504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.4076641504
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.367788071
Short name T2413
Test name
Test status
Simulation time 216651267 ps
CPU time 0.93 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206204 kb
Host smart-5eb3c598-efd0-4e6e-bba4-ffcff2ee6b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
8071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.367788071
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.649760650
Short name T1053
Test name
Test status
Simulation time 221030312 ps
CPU time 0.89 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:23 PM PDT 24
Peak memory 206176 kb
Host smart-7def68e8-ce4e-43e2-91ae-c6d3b0319afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64976
0650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.649760650
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.4020632205
Short name T383
Test name
Test status
Simulation time 181292859 ps
CPU time 0.85 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206104 kb
Host smart-8e79fc3e-9fca-49d7-bde0-d6c44c22b2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40206
32205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.4020632205
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2635632650
Short name T1626
Test name
Test status
Simulation time 177682000 ps
CPU time 0.82 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206184 kb
Host smart-f0e3092d-b235-49d0-bf2b-97727505e413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356
32650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2635632650
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.970969887
Short name T410
Test name
Test status
Simulation time 185798458 ps
CPU time 0.86 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:27 PM PDT 24
Peak memory 206188 kb
Host smart-278b200c-e594-4200-bd03-9fe448cbf722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97096
9887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.970969887
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1465062561
Short name T2083
Test name
Test status
Simulation time 157672593 ps
CPU time 0.8 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206204 kb
Host smart-fdff9a06-7d5f-47d6-8298-8ec92c9ef3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14650
62561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1465062561
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.435125448
Short name T720
Test name
Test status
Simulation time 158302609 ps
CPU time 0.78 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206188 kb
Host smart-9b696c0e-c6a3-4da6-94b8-86cd87a35878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43512
5448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.435125448
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3099449808
Short name T2301
Test name
Test status
Simulation time 305945540 ps
CPU time 1.03 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206168 kb
Host smart-16038d9a-8b87-46a0-901c-6058f484a115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
49808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3099449808
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2478655642
Short name T799
Test name
Test status
Simulation time 6413946839 ps
CPU time 45.52 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206428 kb
Host smart-2f406eef-3842-4131-8147-e44a4e66fbc0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2478655642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2478655642
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.863791177
Short name T948
Test name
Test status
Simulation time 160794046 ps
CPU time 0.78 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:27 PM PDT 24
Peak memory 206208 kb
Host smart-3953e944-ae8d-4e86-b387-2e12d81c6a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86379
1177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.863791177
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.138133690
Short name T1763
Test name
Test status
Simulation time 179339954 ps
CPU time 0.85 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 206184 kb
Host smart-ab6d2253-2972-49a9-a0d7-c86c46c0725e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13813
3690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.138133690
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1533978547
Short name T1567
Test name
Test status
Simulation time 855130724 ps
CPU time 1.94 seconds
Started Jul 07 05:22:27 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206280 kb
Host smart-856d2caa-83e3-4183-bf0c-c9cc8a53ad0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15339
78547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1533978547
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2680821650
Short name T2486
Test name
Test status
Simulation time 4507127754 ps
CPU time 42.3 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206416 kb
Host smart-df566088-72a2-4b95-8ea2-44b37419a6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808
21650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2680821650
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.2099697840
Short name T1476
Test name
Test status
Simulation time 113471785 ps
CPU time 0.78 seconds
Started Jul 07 05:22:31 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206216 kb
Host smart-63dfc25c-98bd-4ea2-8517-fadfe0112f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2099697840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2099697840
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3412656816
Short name T44
Test name
Test status
Simulation time 3779123798 ps
CPU time 5.16 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206452 kb
Host smart-b80baff4-3f1e-413d-b379-34b3696b75b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3412656816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3412656816
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3668623190
Short name T1722
Test name
Test status
Simulation time 13321944267 ps
CPU time 12.56 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206192 kb
Host smart-171a0bfc-bd28-498a-807a-e47ef76bd838
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3668623190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3668623190
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1152182287
Short name T889
Test name
Test status
Simulation time 23400659448 ps
CPU time 24.49 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:48 PM PDT 24
Peak memory 206500 kb
Host smart-fb5ee6ef-b0d5-4eb7-b6b8-3e509fde3fb7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1152182287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1152182287
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.4068217141
Short name T2460
Test name
Test status
Simulation time 199367967 ps
CPU time 0.84 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206116 kb
Host smart-e3c4411b-726b-47ac-90d8-aa6cbc0485b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40682
17141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.4068217141
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1566020113
Short name T1220
Test name
Test status
Simulation time 171789528 ps
CPU time 0.83 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 206196 kb
Host smart-ec059c56-0b3f-430b-ab3c-73812d9876d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15660
20113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1566020113
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3285907454
Short name T925
Test name
Test status
Simulation time 352461406 ps
CPU time 1.17 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:23 PM PDT 24
Peak memory 206440 kb
Host smart-56ecac7b-298d-47ae-bd0c-9923cedf0371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32859
07454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3285907454
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2296788501
Short name T2311
Test name
Test status
Simulation time 419559813 ps
CPU time 1.19 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206184 kb
Host smart-8aa7522e-b3db-4d1e-ac82-d20fef416c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22967
88501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2296788501
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.4285185979
Short name T1755
Test name
Test status
Simulation time 22598541873 ps
CPU time 38.29 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206456 kb
Host smart-45ac0b66-b909-4a35-bbbb-8d135f9d9e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
85979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.4285185979
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3926310815
Short name T1657
Test name
Test status
Simulation time 391749752 ps
CPU time 1.31 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206168 kb
Host smart-1aec4681-9914-466c-acf5-bf81036041db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39263
10815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3926310815
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1599824130
Short name T2118
Test name
Test status
Simulation time 175846942 ps
CPU time 0.8 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206184 kb
Host smart-cc120f14-6303-43df-b2fb-b075435427d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15998
24130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1599824130
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3106830990
Short name T1888
Test name
Test status
Simulation time 71006715 ps
CPU time 0.69 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206176 kb
Host smart-bd877007-6aea-4d2f-84c4-865ae3e07b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
30990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3106830990
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3576020352
Short name T1925
Test name
Test status
Simulation time 700775729 ps
CPU time 2.03 seconds
Started Jul 07 05:22:21 PM PDT 24
Finished Jul 07 05:22:23 PM PDT 24
Peak memory 206404 kb
Host smart-c24e1ee0-4705-42e1-a4ff-0ec6fd6263e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35760
20352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3576020352
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2531211176
Short name T486
Test name
Test status
Simulation time 360270687 ps
CPU time 2.13 seconds
Started Jul 07 05:22:26 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206360 kb
Host smart-d821f6b9-d786-4783-871d-c31ac073e557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25312
11176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2531211176
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.374172265
Short name T1511
Test name
Test status
Simulation time 233876982 ps
CPU time 0.89 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206184 kb
Host smart-40bfa705-9faa-46ec-b864-013d1e3fe351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37417
2265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.374172265
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2434678390
Short name T1205
Test name
Test status
Simulation time 173257488 ps
CPU time 0.79 seconds
Started Jul 07 05:22:25 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206180 kb
Host smart-4e96983f-d373-4406-83f2-0185fecbc08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24346
78390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2434678390
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1792844717
Short name T388
Test name
Test status
Simulation time 288211180 ps
CPU time 1.07 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:25 PM PDT 24
Peak memory 206184 kb
Host smart-84df1a07-01a2-4359-b0fc-0ecf431a15f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17928
44717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1792844717
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4271068602
Short name T1949
Test name
Test status
Simulation time 202865846 ps
CPU time 0.83 seconds
Started Jul 07 05:22:24 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206184 kb
Host smart-6c005b13-c6e7-4899-bae3-313eb4ce0633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42710
68602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4271068602
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.476550376
Short name T619
Test name
Test status
Simulation time 23308059318 ps
CPU time 24.96 seconds
Started Jul 07 05:22:23 PM PDT 24
Finished Jul 07 05:22:49 PM PDT 24
Peak memory 206232 kb
Host smart-daf83330-15ac-47ee-a7a9-cde1d5c58f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47655
0376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.476550376
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.399356610
Short name T523
Test name
Test status
Simulation time 3298601051 ps
CPU time 4.04 seconds
Started Jul 07 05:22:29 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206224 kb
Host smart-47a1a2c4-cde8-4c41-b570-2d6d5b0e042c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39935
6610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.399356610
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3757143161
Short name T2689
Test name
Test status
Simulation time 7888662181 ps
CPU time 206.3 seconds
Started Jul 07 05:22:29 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206520 kb
Host smart-bd253e49-3539-438a-9b8e-3e905a6be59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
43161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3757143161
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2794120647
Short name T2244
Test name
Test status
Simulation time 4541625502 ps
CPU time 32.73 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206356 kb
Host smart-c88eacf7-5c38-48a9-8962-6fc9944bbcd2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2794120647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2794120647
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3007793140
Short name T429
Test name
Test status
Simulation time 246966797 ps
CPU time 0.92 seconds
Started Jul 07 05:22:29 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206412 kb
Host smart-79814abf-fe44-465e-a3f5-6eb22ce02484
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3007793140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3007793140
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.611968423
Short name T762
Test name
Test status
Simulation time 182468163 ps
CPU time 0.83 seconds
Started Jul 07 05:22:35 PM PDT 24
Finished Jul 07 05:22:36 PM PDT 24
Peak memory 206100 kb
Host smart-79f273a1-46e6-4f55-a523-f5937616a8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61196
8423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.611968423
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3699401582
Short name T253
Test name
Test status
Simulation time 3541200435 ps
CPU time 96.94 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 206536 kb
Host smart-795586c9-6b27-4500-86dc-70b1866b366c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36994
01582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3699401582
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.4026946138
Short name T1980
Test name
Test status
Simulation time 4297969528 ps
CPU time 41.54 seconds
Started Jul 07 05:22:27 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206488 kb
Host smart-854b6b59-039a-4115-ad91-b198025355a9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4026946138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.4026946138
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.109262116
Short name T2589
Test name
Test status
Simulation time 173636406 ps
CPU time 0.86 seconds
Started Jul 07 05:22:31 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206144 kb
Host smart-f3489386-dc9f-44f2-b539-1c6fbb9b9859
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=109262116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.109262116
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3314230818
Short name T2314
Test name
Test status
Simulation time 151843693 ps
CPU time 0.83 seconds
Started Jul 07 05:22:30 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206100 kb
Host smart-233c551b-6611-4c58-b375-8e0ff92aa6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33142
30818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3314230818
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.358867495
Short name T1339
Test name
Test status
Simulation time 195541854 ps
CPU time 0.92 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206088 kb
Host smart-3282a0ee-2620-4485-a696-63e85d8d6170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35886
7495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.358867495
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3367352782
Short name T2041
Test name
Test status
Simulation time 157713372 ps
CPU time 0.78 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206136 kb
Host smart-c7a15c41-d80f-4e35-80f4-cc34fd178e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
52782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3367352782
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.739584450
Short name T1033
Test name
Test status
Simulation time 154229047 ps
CPU time 0.84 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:44 PM PDT 24
Peak memory 206184 kb
Host smart-0effa5fc-768c-488a-a9ab-7eec9e5d0eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73958
4450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.739584450
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.759475357
Short name T2566
Test name
Test status
Simulation time 145305668 ps
CPU time 0.8 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206144 kb
Host smart-25bc8031-8142-467c-8024-65771fa97eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75947
5357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.759475357
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2915037618
Short name T906
Test name
Test status
Simulation time 247384512 ps
CPU time 0.91 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206164 kb
Host smart-d840a69a-1c22-4e68-82f8-0b6e70e83a6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2915037618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2915037618
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.877145621
Short name T1271
Test name
Test status
Simulation time 155725664 ps
CPU time 0.76 seconds
Started Jul 07 05:22:29 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206192 kb
Host smart-5052aa08-bbdc-44fd-bb6a-2d7c9135d6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87714
5621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.877145621
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3883545834
Short name T1111
Test name
Test status
Simulation time 39670840 ps
CPU time 0.67 seconds
Started Jul 07 05:22:27 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206184 kb
Host smart-8292d9f2-defd-4595-a93e-9ba4a5c8a567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835
45834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3883545834
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.223886458
Short name T1790
Test name
Test status
Simulation time 7056426592 ps
CPU time 14.97 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:22:44 PM PDT 24
Peak memory 206412 kb
Host smart-e641530f-943f-4e6c-ad80-80469247a3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
6458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.223886458
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.265629276
Short name T2214
Test name
Test status
Simulation time 188320337 ps
CPU time 0.9 seconds
Started Jul 07 05:22:29 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206200 kb
Host smart-38d13e19-19ce-4166-b042-e68b1d06a040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26562
9276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.265629276
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.19103737
Short name T507
Test name
Test status
Simulation time 244653175 ps
CPU time 0.93 seconds
Started Jul 07 05:22:27 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206112 kb
Host smart-df94b96a-957c-4ca3-bfdd-5cca2539c141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.19103737
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3193446919
Short name T2306
Test name
Test status
Simulation time 186700719 ps
CPU time 0.82 seconds
Started Jul 07 05:22:28 PM PDT 24
Finished Jul 07 05:22:30 PM PDT 24
Peak memory 206068 kb
Host smart-42bde56d-f411-487c-8072-393f4cc52756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31934
46919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3193446919
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2335163630
Short name T683
Test name
Test status
Simulation time 156107510 ps
CPU time 0.79 seconds
Started Jul 07 05:22:27 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206132 kb
Host smart-b9d0b773-0e4e-4eea-ab4b-27ea4c925150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
63630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2335163630
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.738729084
Short name T530
Test name
Test status
Simulation time 162785744 ps
CPU time 0.77 seconds
Started Jul 07 05:22:29 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206208 kb
Host smart-5d97df90-2237-474f-abde-e12faa71a1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73872
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.738729084
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2789989829
Short name T744
Test name
Test status
Simulation time 207775101 ps
CPU time 0.87 seconds
Started Jul 07 05:22:26 PM PDT 24
Finished Jul 07 05:22:28 PM PDT 24
Peak memory 206200 kb
Host smart-6c441238-3898-40ad-84c3-6132a2479ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27899
89829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2789989829
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3878386723
Short name T1125
Test name
Test status
Simulation time 151493315 ps
CPU time 0.79 seconds
Started Jul 07 05:22:31 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206152 kb
Host smart-91f18d6f-1db7-4a9a-ba7f-1e87366e908b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38783
86723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3878386723
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4206984624
Short name T2348
Test name
Test status
Simulation time 248352233 ps
CPU time 0.95 seconds
Started Jul 07 05:22:31 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206196 kb
Host smart-b64b3101-f1b1-4f3e-99a1-02bbb9aa4bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42069
84624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4206984624
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.4060087447
Short name T1210
Test name
Test status
Simulation time 5458051787 ps
CPU time 150.87 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:25:04 PM PDT 24
Peak memory 206392 kb
Host smart-ba39cd9c-5a73-49dd-ae6d-e0979ea2882d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4060087447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.4060087447
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.410919305
Short name T2166
Test name
Test status
Simulation time 194819616 ps
CPU time 0.83 seconds
Started Jul 07 05:22:27 PM PDT 24
Finished Jul 07 05:22:29 PM PDT 24
Peak memory 206232 kb
Host smart-b65986bb-7f67-44d4-ba27-fc3905b8c699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41091
9305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.410919305
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1856565845
Short name T1665
Test name
Test status
Simulation time 161756587 ps
CPU time 0.8 seconds
Started Jul 07 05:22:30 PM PDT 24
Finished Jul 07 05:22:31 PM PDT 24
Peak memory 206188 kb
Host smart-fb0c02ec-d8b5-4b58-b971-c0961622ef92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
65845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1856565845
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1690071598
Short name T2282
Test name
Test status
Simulation time 658677890 ps
CPU time 1.65 seconds
Started Jul 07 05:22:36 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206184 kb
Host smart-6d2df5a0-696d-47ea-8183-1d06c77393ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
71598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1690071598
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3380564867
Short name T2610
Test name
Test status
Simulation time 7163742934 ps
CPU time 50.1 seconds
Started Jul 07 05:22:26 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206444 kb
Host smart-5a07fe83-1dc0-42f8-a928-7ae456616cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805
64867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3380564867
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.870023000
Short name T1845
Test name
Test status
Simulation time 40628074 ps
CPU time 0.66 seconds
Started Jul 07 05:22:37 PM PDT 24
Finished Jul 07 05:22:38 PM PDT 24
Peak memory 206196 kb
Host smart-2aff98e9-f771-4c54-a08f-76f089e87e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=870023000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.870023000
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1179820800
Short name T9
Test name
Test status
Simulation time 3870800324 ps
CPU time 5.35 seconds
Started Jul 07 05:22:30 PM PDT 24
Finished Jul 07 05:22:36 PM PDT 24
Peak memory 206360 kb
Host smart-a507f226-d0ce-438f-bbf4-d838c272b802
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1179820800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1179820800
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3736281959
Short name T1955
Test name
Test status
Simulation time 13324987787 ps
CPU time 13.35 seconds
Started Jul 07 05:22:33 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206224 kb
Host smart-da7a1275-b54e-42a1-bd21-a48230ee847a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3736281959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3736281959
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3420591622
Short name T771
Test name
Test status
Simulation time 23351694645 ps
CPU time 22.35 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:55 PM PDT 24
Peak memory 206488 kb
Host smart-7ddf497f-e48a-40c2-a319-bd98cee9b327
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3420591622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.3420591622
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.467535482
Short name T469
Test name
Test status
Simulation time 163704948 ps
CPU time 0.83 seconds
Started Jul 07 05:22:33 PM PDT 24
Finished Jul 07 05:22:35 PM PDT 24
Peak memory 206116 kb
Host smart-29336188-e1ba-40d0-91a3-3acaeb2ad168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46753
5482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.467535482
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3463805096
Short name T1231
Test name
Test status
Simulation time 186549356 ps
CPU time 0.81 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:33 PM PDT 24
Peak memory 206208 kb
Host smart-a4f951ab-7494-46e3-8b04-6c099fd46e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34638
05096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3463805096
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3610894966
Short name T1942
Test name
Test status
Simulation time 168636188 ps
CPU time 0.86 seconds
Started Jul 07 05:22:34 PM PDT 24
Finished Jul 07 05:22:35 PM PDT 24
Peak memory 206188 kb
Host smart-151c6bd3-7453-4ef7-aa89-f2f77328987c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108
94966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3610894966
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1653083993
Short name T206
Test name
Test status
Simulation time 1033582658 ps
CPU time 2.42 seconds
Started Jul 07 05:22:34 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206380 kb
Host smart-3f7c991c-0d1f-43b2-8df6-97177efe198a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16530
83993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1653083993
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1253770986
Short name T1641
Test name
Test status
Simulation time 22617110120 ps
CPU time 43.26 seconds
Started Jul 07 05:22:34 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206536 kb
Host smart-e95c7269-15ff-4159-93a3-b10ccce90204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
70986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1253770986
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3208864462
Short name T1782
Test name
Test status
Simulation time 353501217 ps
CPU time 1.15 seconds
Started Jul 07 05:22:33 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206120 kb
Host smart-ea7ba905-abaa-4c62-9c01-b2dc1d4bb693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32088
64462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3208864462
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_enable.163761920
Short name T513
Test name
Test status
Simulation time 52402125 ps
CPU time 0.67 seconds
Started Jul 07 05:22:31 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 206156 kb
Host smart-d043ef00-06ce-40a0-8b09-6c58bd2a9fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16376
1920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.163761920
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2836125152
Short name T1933
Test name
Test status
Simulation time 897145185 ps
CPU time 2.22 seconds
Started Jul 07 05:22:33 PM PDT 24
Finished Jul 07 05:22:35 PM PDT 24
Peak memory 206316 kb
Host smart-2d00ffc0-48d1-4bea-862b-3b282146270f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
25152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2836125152
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4222294172
Short name T458
Test name
Test status
Simulation time 330474104 ps
CPU time 2.08 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:35 PM PDT 24
Peak memory 206308 kb
Host smart-b7bba5d7-5954-4359-a019-71a39f0dd8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42222
94172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4222294172
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3342653760
Short name T1461
Test name
Test status
Simulation time 179781413 ps
CPU time 0.81 seconds
Started Jul 07 05:22:36 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206120 kb
Host smart-ff40959f-80f7-4c94-b6dc-8b884d94b72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
53760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3342653760
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1570517003
Short name T2552
Test name
Test status
Simulation time 150225789 ps
CPU time 0.89 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206104 kb
Host smart-db4037c0-0568-49e3-8e60-71439b4d4153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15705
17003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1570517003
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.338524986
Short name T1182
Test name
Test status
Simulation time 232091855 ps
CPU time 0.91 seconds
Started Jul 07 05:22:34 PM PDT 24
Finished Jul 07 05:22:35 PM PDT 24
Peak memory 206188 kb
Host smart-272e1c9b-28c3-4557-b3aa-6c2af721ff2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33852
4986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.338524986
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1653458026
Short name T2494
Test name
Test status
Simulation time 188284923 ps
CPU time 0.81 seconds
Started Jul 07 05:22:35 PM PDT 24
Finished Jul 07 05:22:36 PM PDT 24
Peak memory 206100 kb
Host smart-89841afb-6160-4855-b6cc-1889d53df49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
58026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1653458026
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3327546400
Short name T998
Test name
Test status
Simulation time 23286034969 ps
CPU time 23.09 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 205952 kb
Host smart-03f1828a-393c-4674-9efc-d1717b1bebff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33275
46400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3327546400
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1345576951
Short name T1298
Test name
Test status
Simulation time 3296173474 ps
CPU time 4.13 seconds
Started Jul 07 05:22:32 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206256 kb
Host smart-e6f184c7-4923-4a9b-9bad-067f7fb898a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
76951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1345576951
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.267945581
Short name T2302
Test name
Test status
Simulation time 5737041820 ps
CPU time 155.12 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 206560 kb
Host smart-ac6eaaa1-75a5-4d18-8594-e6f3d8bc1647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794
5581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.267945581
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.500399298
Short name T1183
Test name
Test status
Simulation time 7492799229 ps
CPU time 67.1 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:23:50 PM PDT 24
Peak memory 206456 kb
Host smart-a0c99907-757c-4b82-9c9b-6e8a881cfed6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=500399298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.500399298
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2166708831
Short name T2664
Test name
Test status
Simulation time 251043235 ps
CPU time 0.93 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206168 kb
Host smart-a70223ff-3316-4fcb-be5e-8e4e1d3c7ae7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2166708831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2166708831
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2110541493
Short name T1314
Test name
Test status
Simulation time 187791906 ps
CPU time 0.87 seconds
Started Jul 07 05:22:36 PM PDT 24
Finished Jul 07 05:22:38 PM PDT 24
Peak memory 206208 kb
Host smart-9476f39e-6027-4db0-ac83-14e0431b8d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
41493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2110541493
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2127611990
Short name T832
Test name
Test status
Simulation time 4678998395 ps
CPU time 35.87 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206448 kb
Host smart-d89f3d94-ad81-4202-8068-399cfcb67330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276
11990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2127611990
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3627159888
Short name T1493
Test name
Test status
Simulation time 4441266393 ps
CPU time 30.76 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206492 kb
Host smart-aac1efa3-0c7d-43d8-a043-cf6106420713
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3627159888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3627159888
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2650932693
Short name T1093
Test name
Test status
Simulation time 158298304 ps
CPU time 0.78 seconds
Started Jul 07 05:22:41 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206080 kb
Host smart-3b11dc5c-38b8-4b97-a248-102c6f189f5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2650932693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2650932693
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.150668911
Short name T362
Test name
Test status
Simulation time 194089270 ps
CPU time 0.79 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206192 kb
Host smart-f7f1d579-7bff-4425-be92-d1c0f5768f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
8911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.150668911
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2299717
Short name T1059
Test name
Test status
Simulation time 180792327 ps
CPU time 0.84 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:22:39 PM PDT 24
Peak memory 206148 kb
Host smart-d3a959de-2e8c-437c-8183-2dda88267bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22997
17 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2299717
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4003975905
Short name T929
Test name
Test status
Simulation time 175575075 ps
CPU time 0.8 seconds
Started Jul 07 05:22:36 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206100 kb
Host smart-5409cc68-24c8-47bb-a02f-e7fd684eb2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40039
75905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4003975905
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.597600601
Short name T659
Test name
Test status
Simulation time 192772958 ps
CPU time 0.86 seconds
Started Jul 07 05:22:36 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206200 kb
Host smart-9678ac95-0537-49a8-8d4e-0c1576c0109d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59760
0601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.597600601
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3312524348
Short name T2291
Test name
Test status
Simulation time 250951090 ps
CPU time 1 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206088 kb
Host smart-e9e1c928-04fb-488f-b0e2-d56a5858f304
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3312524348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3312524348
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.135568380
Short name T2484
Test name
Test status
Simulation time 137175675 ps
CPU time 0.84 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:22:39 PM PDT 24
Peak memory 206188 kb
Host smart-60a73c3b-24f5-49a2-9a5e-7e7773f0e1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
8380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.135568380
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3465017088
Short name T2622
Test name
Test status
Simulation time 28416901 ps
CPU time 0.68 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:44 PM PDT 24
Peak memory 206112 kb
Host smart-b7e2d34c-43f6-4597-a133-87c9c6c97b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34650
17088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3465017088
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.592954752
Short name T1405
Test name
Test status
Simulation time 7277664056 ps
CPU time 16.89 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206532 kb
Host smart-44acd114-21d5-4c61-a9d8-79f32c99ca69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59295
4752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.592954752
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1485816918
Short name T2211
Test name
Test status
Simulation time 207639207 ps
CPU time 0.88 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206044 kb
Host smart-4f35ab01-8aed-40a8-84d9-8313593367a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
16918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1485816918
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2400853963
Short name T1736
Test name
Test status
Simulation time 254780364 ps
CPU time 0.91 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206196 kb
Host smart-45c3543f-918f-470d-8d70-fae4498eb558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24008
53963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2400853963
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1313190823
Short name T728
Test name
Test status
Simulation time 193342236 ps
CPU time 0.82 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206152 kb
Host smart-74325073-f8f7-4ef1-825c-2d8229b490e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131
90823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1313190823
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3639040969
Short name T434
Test name
Test status
Simulation time 234249886 ps
CPU time 0.86 seconds
Started Jul 07 05:22:36 PM PDT 24
Finished Jul 07 05:22:37 PM PDT 24
Peak memory 206120 kb
Host smart-ef183409-aa26-42e9-b835-edcc46328137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
40969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3639040969
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3725831864
Short name T1757
Test name
Test status
Simulation time 180322115 ps
CPU time 0.8 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206180 kb
Host smart-5e665418-a366-48e2-a303-d580069f987c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
31864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3725831864
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3989837007
Short name T2482
Test name
Test status
Simulation time 152163698 ps
CPU time 0.76 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206160 kb
Host smart-c2c86897-6ce3-41c4-bd39-29fe6cf4e51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
37007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3989837007
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3282999679
Short name T753
Test name
Test status
Simulation time 147978721 ps
CPU time 0.88 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 206440 kb
Host smart-d248b181-0933-418b-8170-d3b370e39c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
99679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3282999679
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.136525622
Short name T2640
Test name
Test status
Simulation time 203447237 ps
CPU time 0.87 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206188 kb
Host smart-88068748-51b5-467f-9b80-e0bf7eb66a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13652
5622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.136525622
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1981756088
Short name T800
Test name
Test status
Simulation time 5670111967 ps
CPU time 157.37 seconds
Started Jul 07 05:22:37 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206480 kb
Host smart-02af98ea-1d9a-4c88-9bae-a93212c4c9e5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1981756088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1981756088
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3844545537
Short name T2031
Test name
Test status
Simulation time 144477260 ps
CPU time 0.79 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:44 PM PDT 24
Peak memory 206120 kb
Host smart-22321bee-ce22-4ab8-b982-f06c8676f3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445
45537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3844545537
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2097458709
Short name T2587
Test name
Test status
Simulation time 176600876 ps
CPU time 0.83 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:22:46 PM PDT 24
Peak memory 206160 kb
Host smart-8f6dfb27-6fe9-44ad-8ecc-db0112bbddda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20974
58709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2097458709
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1152469083
Short name T1701
Test name
Test status
Simulation time 440971791 ps
CPU time 1.33 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206188 kb
Host smart-86af7840-7c97-402c-b0aa-f78025aa1aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524
69083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1152469083
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.10461044
Short name T829
Test name
Test status
Simulation time 7966503044 ps
CPU time 58.32 seconds
Started Jul 07 05:22:37 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206404 kb
Host smart-963db934-8120-4953-a649-c3b272acf4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10461
044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.10461044
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.1966316544
Short name T1324
Test name
Test status
Simulation time 39265264 ps
CPU time 0.65 seconds
Started Jul 07 05:19:36 PM PDT 24
Finished Jul 07 05:19:37 PM PDT 24
Peak memory 206172 kb
Host smart-e63038e3-8dae-4229-99e4-382d2ba99048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1966316544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1966316544
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.98657901
Short name T553
Test name
Test status
Simulation time 3979022243 ps
CPU time 4.38 seconds
Started Jul 07 05:19:16 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206100 kb
Host smart-5818ef09-a1b0-43df-bbb8-c39e19b09c2e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=98657901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.98657901
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1507471979
Short name T1412
Test name
Test status
Simulation time 13421536581 ps
CPU time 12.48 seconds
Started Jul 07 05:19:16 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206240 kb
Host smart-3acd38b3-f552-49bf-aee6-6713700dd9c1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1507471979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1507471979
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.782207560
Short name T564
Test name
Test status
Simulation time 23327428412 ps
CPU time 23.59 seconds
Started Jul 07 05:19:18 PM PDT 24
Finished Jul 07 05:19:42 PM PDT 24
Peak memory 206160 kb
Host smart-50dac60c-e882-46c9-bdcb-79c4fd2029c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=782207560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.782207560
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.285183908
Short name T2012
Test name
Test status
Simulation time 145898481 ps
CPU time 0.74 seconds
Started Jul 07 05:19:14 PM PDT 24
Finished Jul 07 05:19:15 PM PDT 24
Peak memory 206140 kb
Host smart-9bf156a1-fba0-4dc1-ae1c-a5902611f852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
3908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.285183908
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3161663435
Short name T56
Test name
Test status
Simulation time 190646612 ps
CPU time 0.79 seconds
Started Jul 07 05:19:17 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206116 kb
Host smart-68016c2a-ad4f-4eb0-8307-e6a8d351ed4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
63435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3161663435
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3475587891
Short name T62
Test name
Test status
Simulation time 141647026 ps
CPU time 0.8 seconds
Started Jul 07 05:19:17 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206184 kb
Host smart-0cb2964f-6345-438a-95c7-268d4b772acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34755
87891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3475587891
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2809677802
Short name T967
Test name
Test status
Simulation time 155499962 ps
CPU time 0.78 seconds
Started Jul 07 05:19:17 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 206192 kb
Host smart-b40805fe-216c-460f-b59d-98d1b721d753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28096
77802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2809677802
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2250033323
Short name T880
Test name
Test status
Simulation time 215565677 ps
CPU time 0.99 seconds
Started Jul 07 05:19:20 PM PDT 24
Finished Jul 07 05:19:22 PM PDT 24
Peak memory 206180 kb
Host smart-0bacb481-5e7f-4456-b1f2-fcc6c23f384e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
33323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2250033323
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.651581015
Short name T2577
Test name
Test status
Simulation time 749063217 ps
CPU time 1.74 seconds
Started Jul 07 05:19:20 PM PDT 24
Finished Jul 07 05:19:22 PM PDT 24
Peak memory 206316 kb
Host smart-dacde717-7596-4a09-b7ba-476c6476061c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65158
1015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.651581015
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1937670338
Short name T1319
Test name
Test status
Simulation time 19867782687 ps
CPU time 34.87 seconds
Started Jul 07 05:19:25 PM PDT 24
Finished Jul 07 05:20:00 PM PDT 24
Peak memory 206424 kb
Host smart-77e725a3-39b5-4a19-843a-2978f2b7daf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376
70338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1937670338
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.15060730
Short name T2310
Test name
Test status
Simulation time 470141499 ps
CPU time 1.31 seconds
Started Jul 07 05:19:20 PM PDT 24
Finished Jul 07 05:19:22 PM PDT 24
Peak memory 206196 kb
Host smart-bc0b1cf4-36da-46d0-b4ba-4c1adf95a284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15060
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.15060730
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3639964313
Short name T1915
Test name
Test status
Simulation time 141808756 ps
CPU time 0.76 seconds
Started Jul 07 05:19:22 PM PDT 24
Finished Jul 07 05:19:23 PM PDT 24
Peak memory 206100 kb
Host smart-aeac9686-e263-46af-9217-16a1aa5d7d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36399
64313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3639964313
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.703811933
Short name T715
Test name
Test status
Simulation time 100323902 ps
CPU time 0.68 seconds
Started Jul 07 05:19:19 PM PDT 24
Finished Jul 07 05:19:20 PM PDT 24
Peak memory 206192 kb
Host smart-a3f7a99a-6758-4a7a-9672-50a3f8c00de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70381
1933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.703811933
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2839388607
Short name T1006
Test name
Test status
Simulation time 818213310 ps
CPU time 2.03 seconds
Started Jul 07 05:19:23 PM PDT 24
Finished Jul 07 05:19:25 PM PDT 24
Peak memory 206296 kb
Host smart-64d1deec-3ac1-4b9f-b506-231c21a6f0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28393
88607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2839388607
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2506373138
Short name T2498
Test name
Test status
Simulation time 236568228 ps
CPU time 1.33 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:19:30 PM PDT 24
Peak memory 206440 kb
Host smart-e6ce068e-82e5-4b14-aca7-2924cb146fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
73138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2506373138
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3070308294
Short name T2581
Test name
Test status
Simulation time 87187255798 ps
CPU time 122.05 seconds
Started Jul 07 05:19:19 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206408 kb
Host smart-d7b37b4a-0e55-464a-a2d4-84bab56f1ad3
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3070308294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3070308294
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.58489102
Short name T1391
Test name
Test status
Simulation time 88055676778 ps
CPU time 143.81 seconds
Started Jul 07 05:19:25 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 206360 kb
Host smart-e6212b3a-9894-4c29-8492-13f3382c7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58489102 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.58489102
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1578873552
Short name T625
Test name
Test status
Simulation time 118135813084 ps
CPU time 162.98 seconds
Started Jul 07 05:19:23 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206348 kb
Host smart-3822d0bf-20cd-4e53-8b55-e6bc538f809f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1578873552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1578873552
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1169439917
Short name T2163
Test name
Test status
Simulation time 86999068441 ps
CPU time 119.27 seconds
Started Jul 07 05:19:22 PM PDT 24
Finished Jul 07 05:21:21 PM PDT 24
Peak memory 206448 kb
Host smart-c9f44fd0-2744-4fb3-9c5d-4d39ad7377f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169439917 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1169439917
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3895824851
Short name T1507
Test name
Test status
Simulation time 88127609297 ps
CPU time 117.19 seconds
Started Jul 07 05:19:27 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 206456 kb
Host smart-f02a8619-7a59-4bf3-a45e-436a3d9f9f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
24851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3895824851
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2289254102
Short name T1199
Test name
Test status
Simulation time 228410766 ps
CPU time 0.9 seconds
Started Jul 07 05:19:24 PM PDT 24
Finished Jul 07 05:19:25 PM PDT 24
Peak memory 206148 kb
Host smart-5279b1cb-1212-4623-b938-282192154570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
54102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2289254102
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1992316811
Short name T452
Test name
Test status
Simulation time 222845502 ps
CPU time 0.82 seconds
Started Jul 07 05:19:25 PM PDT 24
Finished Jul 07 05:19:26 PM PDT 24
Peak memory 206124 kb
Host smart-c928bec4-d3d0-421e-a178-5c03b9d32572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19923
16811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1992316811
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3767818622
Short name T2033
Test name
Test status
Simulation time 231384015 ps
CPU time 0.92 seconds
Started Jul 07 05:19:26 PM PDT 24
Finished Jul 07 05:19:27 PM PDT 24
Peak memory 206140 kb
Host smart-c9911778-e50f-40bc-be27-10787e133196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
18622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3767818622
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.4249675164
Short name T703
Test name
Test status
Simulation time 5569826009 ps
CPU time 39.03 seconds
Started Jul 07 05:19:27 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 206436 kb
Host smart-21675759-2a9b-4a09-80a7-8b1fd384a8da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4249675164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.4249675164
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1763673828
Short name T2636
Test name
Test status
Simulation time 179785194 ps
CPU time 0.87 seconds
Started Jul 07 05:19:22 PM PDT 24
Finished Jul 07 05:19:23 PM PDT 24
Peak memory 206112 kb
Host smart-f381e2f4-0150-47c0-a693-7d7e65a5618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17636
73828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1763673828
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.416141751
Short name T977
Test name
Test status
Simulation time 23350250563 ps
CPU time 25.91 seconds
Started Jul 07 05:19:26 PM PDT 24
Finished Jul 07 05:19:52 PM PDT 24
Peak memory 206252 kb
Host smart-b3e826c6-e232-4e66-b7da-c459a8a6c695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41614
1751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.416141751
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.281710321
Short name T1114
Test name
Test status
Simulation time 3320771440 ps
CPU time 4.01 seconds
Started Jul 07 05:19:24 PM PDT 24
Finished Jul 07 05:19:28 PM PDT 24
Peak memory 205956 kb
Host smart-a9a6c2e9-93b2-46ce-9193-437ca454c5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
0321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.281710321
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1942022463
Short name T1654
Test name
Test status
Simulation time 11062966113 ps
CPU time 82.16 seconds
Started Jul 07 05:19:22 PM PDT 24
Finished Jul 07 05:20:45 PM PDT 24
Peak memory 206436 kb
Host smart-34630f93-0287-45f9-afb7-00754881fdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
22463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1942022463
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2959238949
Short name T1643
Test name
Test status
Simulation time 4651688570 ps
CPU time 129.89 seconds
Started Jul 07 05:19:24 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 206436 kb
Host smart-17c69533-92c6-4d67-b6b9-8e7f51936772
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2959238949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2959238949
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2909023512
Short name T2
Test name
Test status
Simulation time 244082399 ps
CPU time 0.92 seconds
Started Jul 07 05:19:23 PM PDT 24
Finished Jul 07 05:19:24 PM PDT 24
Peak memory 206176 kb
Host smart-5270e6a1-ec92-4d42-81d1-4e68c2b2bd0f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2909023512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2909023512
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.904892612
Short name T2591
Test name
Test status
Simulation time 191775302 ps
CPU time 0.86 seconds
Started Jul 07 05:19:26 PM PDT 24
Finished Jul 07 05:19:27 PM PDT 24
Peak memory 206188 kb
Host smart-84645128-d921-4b19-a24a-917bb78bf4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90489
2612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.904892612
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.906512461
Short name T2387
Test name
Test status
Simulation time 4631400763 ps
CPU time 125.54 seconds
Started Jul 07 05:19:24 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206468 kb
Host smart-d3dfd8de-2699-4ed7-bf29-ea166791648a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90651
2461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.906512461
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1709886976
Short name T2303
Test name
Test status
Simulation time 6642010395 ps
CPU time 47.14 seconds
Started Jul 07 05:19:25 PM PDT 24
Finished Jul 07 05:20:12 PM PDT 24
Peak memory 206476 kb
Host smart-1663862f-cdf4-4c34-887b-c30e4cc51905
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1709886976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1709886976
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1519992785
Short name T2138
Test name
Test status
Simulation time 149529611 ps
CPU time 0.76 seconds
Started Jul 07 05:19:25 PM PDT 24
Finished Jul 07 05:19:26 PM PDT 24
Peak memory 206200 kb
Host smart-b75c117c-d742-4170-9e18-ea9923c2ab61
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1519992785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1519992785
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2612373106
Short name T497
Test name
Test status
Simulation time 149757987 ps
CPU time 0.77 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206196 kb
Host smart-fb7297ce-02eb-4981-ab2b-fcc0e0734c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
73106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2612373106
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3817094103
Short name T144
Test name
Test status
Simulation time 185034394 ps
CPU time 0.86 seconds
Started Jul 07 05:19:26 PM PDT 24
Finished Jul 07 05:19:27 PM PDT 24
Peak memory 206168 kb
Host smart-bd689ffa-2130-4ff6-883c-12736ed62d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38170
94103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3817094103
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3113383769
Short name T1906
Test name
Test status
Simulation time 157071699 ps
CPU time 0.83 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206196 kb
Host smart-76f4fc38-c1d0-4307-86c1-eb01f6db2203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31133
83769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3113383769
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3686078957
Short name T2373
Test name
Test status
Simulation time 183668335 ps
CPU time 0.81 seconds
Started Jul 07 05:19:27 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206200 kb
Host smart-797a2268-e044-4361-9fe3-f829107d1a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
78957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3686078957
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4037951611
Short name T685
Test name
Test status
Simulation time 201901306 ps
CPU time 0.86 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206200 kb
Host smart-e344378b-0664-4d92-a21b-36110554e3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40379
51611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4037951611
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1738058930
Short name T2439
Test name
Test status
Simulation time 152147696 ps
CPU time 0.8 seconds
Started Jul 07 05:19:24 PM PDT 24
Finished Jul 07 05:19:25 PM PDT 24
Peak memory 206128 kb
Host smart-767c04b8-2fb2-4c2b-8e38-d62f05836f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380
58930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1738058930
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3984732590
Short name T1531
Test name
Test status
Simulation time 252145075 ps
CPU time 0.96 seconds
Started Jul 07 05:19:29 PM PDT 24
Finished Jul 07 05:19:31 PM PDT 24
Peak memory 206112 kb
Host smart-5fa68aa5-5ff1-4303-a6e1-828ae7e6e7d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3984732590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3984732590
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.4036633098
Short name T1370
Test name
Test status
Simulation time 198175421 ps
CPU time 0.86 seconds
Started Jul 07 05:19:33 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206140 kb
Host smart-cc9b403b-2999-405a-abd7-fca5f54abc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
33098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.4036633098
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3709476980
Short name T518
Test name
Test status
Simulation time 40898634 ps
CPU time 0.66 seconds
Started Jul 07 05:19:32 PM PDT 24
Finished Jul 07 05:19:33 PM PDT 24
Peak memory 206180 kb
Host smart-f70c7ca4-d92f-4ca9-a48c-b1fc0cbf6863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37094
76980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3709476980
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.569023255
Short name T308
Test name
Test status
Simulation time 5728811599 ps
CPU time 12.7 seconds
Started Jul 07 05:19:30 PM PDT 24
Finished Jul 07 05:19:43 PM PDT 24
Peak memory 206464 kb
Host smart-e5b3f089-1af8-4ed6-9928-e96acf771e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56902
3255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.569023255
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4160252843
Short name T2079
Test name
Test status
Simulation time 159623128 ps
CPU time 0.88 seconds
Started Jul 07 05:19:30 PM PDT 24
Finished Jul 07 05:19:32 PM PDT 24
Peak memory 206208 kb
Host smart-b03b76fe-101a-402d-ab69-4ed91f63ffdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
52843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4160252843
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.249660915
Short name T960
Test name
Test status
Simulation time 228709573 ps
CPU time 0.89 seconds
Started Jul 07 05:19:30 PM PDT 24
Finished Jul 07 05:19:31 PM PDT 24
Peak memory 206176 kb
Host smart-d4b3c8d5-7c81-4b85-8852-547ac3b661cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24966
0915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.249660915
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1272977645
Short name T1019
Test name
Test status
Simulation time 11034042439 ps
CPU time 50.72 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:20:19 PM PDT 24
Peak memory 206396 kb
Host smart-f8a34118-4215-4266-816e-91d245e90985
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1272977645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1272977645
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1539654288
Short name T195
Test name
Test status
Simulation time 4936519989 ps
CPU time 120.77 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:21:29 PM PDT 24
Peak memory 206520 kb
Host smart-481623f5-2869-4c99-aa6b-a8599e09526b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1539654288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1539654288
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.4082194912
Short name T1475
Test name
Test status
Simulation time 8499998955 ps
CPU time 37.95 seconds
Started Jul 07 05:19:27 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 206472 kb
Host smart-d43d73fd-3eb6-4407-98be-86d17a6bea02
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4082194912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.4082194912
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1311173170
Short name T2694
Test name
Test status
Simulation time 228423290 ps
CPU time 0.86 seconds
Started Jul 07 05:19:27 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206200 kb
Host smart-66caa1b1-0762-4e55-832c-c7564e851237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
73170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1311173170
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.101476389
Short name T1916
Test name
Test status
Simulation time 205165502 ps
CPU time 0.84 seconds
Started Jul 07 05:19:30 PM PDT 24
Finished Jul 07 05:19:31 PM PDT 24
Peak memory 206184 kb
Host smart-fd1e650d-522a-4164-a119-a4c9a5aaba20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10147
6389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.101476389
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1589419074
Short name T2275
Test name
Test status
Simulation time 199173808 ps
CPU time 0.83 seconds
Started Jul 07 05:19:32 PM PDT 24
Finished Jul 07 05:19:33 PM PDT 24
Peak memory 206188 kb
Host smart-ebdb81b8-a81a-4a85-85e2-676dc6a3ca52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15894
19074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1589419074
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3104261665
Short name T75
Test name
Test status
Simulation time 187358914 ps
CPU time 0.82 seconds
Started Jul 07 05:19:28 PM PDT 24
Finished Jul 07 05:19:29 PM PDT 24
Peak memory 206116 kb
Host smart-86496ca7-356f-4002-adf7-cb0b1c9aa039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31042
61665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3104261665
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3165124496
Short name T236
Test name
Test status
Simulation time 222950588 ps
CPU time 1.15 seconds
Started Jul 07 05:19:35 PM PDT 24
Finished Jul 07 05:19:37 PM PDT 24
Peak memory 223628 kb
Host smart-90d90f45-0a12-490c-976b-b2c059cfe097
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3165124496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3165124496
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.621796153
Short name T50
Test name
Test status
Simulation time 474119381 ps
CPU time 1.37 seconds
Started Jul 07 05:19:26 PM PDT 24
Finished Jul 07 05:19:28 PM PDT 24
Peak memory 206068 kb
Host smart-e3dbe594-0395-4639-9b97-f70d1ab12701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62179
6153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.621796153
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3180401010
Short name T2176
Test name
Test status
Simulation time 180060563 ps
CPU time 0.81 seconds
Started Jul 07 05:19:30 PM PDT 24
Finished Jul 07 05:19:31 PM PDT 24
Peak memory 206120 kb
Host smart-9f1b4ab2-1c59-49af-9d9b-67537e05757c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31804
01010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3180401010
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2332687018
Short name T2559
Test name
Test status
Simulation time 152500611 ps
CPU time 0.78 seconds
Started Jul 07 05:19:33 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206136 kb
Host smart-ebe71514-5fd8-422f-a7ff-21b4c565f40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23326
87018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2332687018
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3878174140
Short name T105
Test name
Test status
Simulation time 147573181 ps
CPU time 0.79 seconds
Started Jul 07 05:19:27 PM PDT 24
Finished Jul 07 05:19:28 PM PDT 24
Peak memory 206156 kb
Host smart-217d93ea-2bb3-4631-a08e-93bf8385cbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
74140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3878174140
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1154796016
Short name T414
Test name
Test status
Simulation time 281497454 ps
CPU time 1.06 seconds
Started Jul 07 05:19:34 PM PDT 24
Finished Jul 07 05:19:35 PM PDT 24
Peak memory 206116 kb
Host smart-c65209a0-f4ee-4309-8108-10847ecf044b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547
96016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1154796016
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.4099594681
Short name T2449
Test name
Test status
Simulation time 4775289081 ps
CPU time 127.92 seconds
Started Jul 07 05:19:34 PM PDT 24
Finished Jul 07 05:21:42 PM PDT 24
Peak memory 206492 kb
Host smart-c52929f8-0fe4-4486-8daa-916e20b4c7a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4099594681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4099594681
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2063204664
Short name T2239
Test name
Test status
Simulation time 157387956 ps
CPU time 0.81 seconds
Started Jul 07 05:19:32 PM PDT 24
Finished Jul 07 05:19:33 PM PDT 24
Peak memory 206164 kb
Host smart-49a29334-2776-4a39-8eee-ec7c8b0bb716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
04664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2063204664
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1833666789
Short name T456
Test name
Test status
Simulation time 236966692 ps
CPU time 0.9 seconds
Started Jul 07 05:19:32 PM PDT 24
Finished Jul 07 05:19:34 PM PDT 24
Peak memory 206164 kb
Host smart-aee03bcd-83d8-435c-8c69-1cccc53f8392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
66789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1833666789
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2852172047
Short name T484
Test name
Test status
Simulation time 250098488 ps
CPU time 0.96 seconds
Started Jul 07 05:19:34 PM PDT 24
Finished Jul 07 05:19:35 PM PDT 24
Peak memory 206152 kb
Host smart-d429b757-d0c2-44f9-9905-be9712de3101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28521
72047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2852172047
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.3476478873
Short name T2372
Test name
Test status
Simulation time 7128515189 ps
CPU time 199.26 seconds
Started Jul 07 05:19:33 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206496 kb
Host smart-e54c1469-2b61-4f64-9cba-2a6910b35387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34764
78873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3476478873
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.431999594
Short name T1062
Test name
Test status
Simulation time 10488642850 ps
CPU time 265.36 seconds
Started Jul 07 05:19:34 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206496 kb
Host smart-d78ab765-46ca-4209-bd07-36b056f03cbc
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=431999594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.431999594
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2146496198
Short name T1885
Test name
Test status
Simulation time 59975425 ps
CPU time 0.69 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206152 kb
Host smart-80695ae7-48a5-47ab-87d3-0e529ae53f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2146496198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2146496198
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1795090658
Short name T1746
Test name
Test status
Simulation time 3751735530 ps
CPU time 4.62 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:22:43 PM PDT 24
Peak memory 206440 kb
Host smart-d058136d-58f5-4c38-a7e0-a2f2dbb257a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1795090658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1795090658
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1296596420
Short name T1016
Test name
Test status
Simulation time 13338633608 ps
CPU time 12.98 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:52 PM PDT 24
Peak memory 206400 kb
Host smart-12c28e1f-3999-4ec7-81d6-865620b436f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1296596420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1296596420
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.560018564
Short name T1483
Test name
Test status
Simulation time 23369880823 ps
CPU time 23.6 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206220 kb
Host smart-c325dde4-9550-4da5-ad47-00d91a2b3ab8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=560018564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.560018564
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2175409294
Short name T2508
Test name
Test status
Simulation time 156910703 ps
CPU time 0.83 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206040 kb
Host smart-1de4f0bd-d1a9-48e2-bc7c-fd334c61ea13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754
09294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2175409294
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2534431515
Short name T59
Test name
Test status
Simulation time 162388566 ps
CPU time 0.79 seconds
Started Jul 07 05:22:38 PM PDT 24
Finished Jul 07 05:22:39 PM PDT 24
Peak memory 206120 kb
Host smart-29d8b3ad-3179-407c-b002-1af004aa2f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
31515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2534431515
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.398413424
Short name T193
Test name
Test status
Simulation time 444571679 ps
CPU time 1.47 seconds
Started Jul 07 05:22:37 PM PDT 24
Finished Jul 07 05:22:39 PM PDT 24
Peak memory 206188 kb
Host smart-af6fd695-68c6-4065-81ba-e673da234ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
3424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.398413424
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3630457522
Short name T98
Test name
Test status
Simulation time 7744761808 ps
CPU time 14.81 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:23:00 PM PDT 24
Peak memory 206472 kb
Host smart-75b40e87-f3b1-4c40-b607-54a60bfd5521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
57522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3630457522
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2546646334
Short name T521
Test name
Test status
Simulation time 425546911 ps
CPU time 1.33 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:22:46 PM PDT 24
Peak memory 206164 kb
Host smart-5d3f3694-a7f0-4552-8cdc-9e8cb3003995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25466
46334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2546646334
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3914774862
Short name T1956
Test name
Test status
Simulation time 135355251 ps
CPU time 0.77 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206152 kb
Host smart-b53f5a38-4bb3-4f6b-adf6-0f6884b08640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
74862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3914774862
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1965627612
Short name T669
Test name
Test status
Simulation time 38586278 ps
CPU time 0.66 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206204 kb
Host smart-abf76777-9a50-45aa-b96e-9b4ceb578d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
27612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1965627612
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.809242279
Short name T1162
Test name
Test status
Simulation time 716800558 ps
CPU time 1.99 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206448 kb
Host smart-904c4f8c-af92-494e-8e65-e91e1e571e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80924
2279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.809242279
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1246042005
Short name T631
Test name
Test status
Simulation time 273879153 ps
CPU time 1.62 seconds
Started Jul 07 05:22:39 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 206424 kb
Host smart-948bd11c-25f1-4e29-8669-c10c47fc610c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12460
42005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1246042005
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1726748426
Short name T500
Test name
Test status
Simulation time 175008899 ps
CPU time 0.91 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206160 kb
Host smart-0a752c24-c1be-481d-9002-cd0f25de54c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267
48426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1726748426
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4204237262
Short name T604
Test name
Test status
Simulation time 156110418 ps
CPU time 0.77 seconds
Started Jul 07 05:22:42 PM PDT 24
Finished Jul 07 05:22:43 PM PDT 24
Peak memory 206080 kb
Host smart-488519b6-0ac9-4e04-8666-5ce19aeba138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042
37262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4204237262
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.770364470
Short name T2507
Test name
Test status
Simulation time 241020129 ps
CPU time 0.91 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206196 kb
Host smart-e4635a87-b8e2-4b54-b2af-374a4a35e92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77036
4470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.770364470
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.3140735421
Short name T122
Test name
Test status
Simulation time 6025715560 ps
CPU time 60.68 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:23:46 PM PDT 24
Peak memory 206484 kb
Host smart-b3a6c61a-d65f-4662-a1b1-f219b600a736
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3140735421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.3140735421
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1210377797
Short name T1398
Test name
Test status
Simulation time 196926835 ps
CPU time 0.88 seconds
Started Jul 07 05:22:47 PM PDT 24
Finished Jul 07 05:22:48 PM PDT 24
Peak memory 206200 kb
Host smart-0340be67-7518-4425-85ca-ff67a5d20917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12103
77797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1210377797
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.2904120414
Short name T2106
Test name
Test status
Simulation time 23287074299 ps
CPU time 23.17 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206256 kb
Host smart-4323db4e-9b3d-4646-b7f0-3e5e60b21855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
20414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.2904120414
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1642074988
Short name T1900
Test name
Test status
Simulation time 3349322719 ps
CPU time 3.84 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206176 kb
Host smart-ca88f0ea-862b-4e4c-b202-430d5e15ac7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420
74988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1642074988
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.766558358
Short name T869
Test name
Test status
Simulation time 7962891404 ps
CPU time 73.21 seconds
Started Jul 07 05:22:41 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206524 kb
Host smart-af16c5d9-bdbb-47a5-9488-2856c20a4d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76655
8358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.766558358
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.586485915
Short name T2097
Test name
Test status
Simulation time 5537324816 ps
CPU time 51.47 seconds
Started Jul 07 05:22:47 PM PDT 24
Finished Jul 07 05:23:39 PM PDT 24
Peak memory 206408 kb
Host smart-76006127-85b6-420f-8e38-6ab61b9dfd76
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=586485915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.586485915
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3101271281
Short name T2475
Test name
Test status
Simulation time 256038744 ps
CPU time 0.93 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206044 kb
Host smart-1b8a5b08-5b40-41de-b1a4-bc27c93b19f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3101271281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3101271281
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1248074809
Short name T2677
Test name
Test status
Simulation time 229285554 ps
CPU time 0.91 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206200 kb
Host smart-8184de37-f573-4038-98d0-4749288a1ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12480
74809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1248074809
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1097219096
Short name T765
Test name
Test status
Simulation time 3519888374 ps
CPU time 104.75 seconds
Started Jul 07 05:22:41 PM PDT 24
Finished Jul 07 05:24:26 PM PDT 24
Peak memory 206728 kb
Host smart-18f27742-d939-4901-9238-42dd79b3d581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10972
19096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1097219096
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.393352844
Short name T1344
Test name
Test status
Simulation time 5415777715 ps
CPU time 153.81 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206340 kb
Host smart-4c3de332-3adf-4f1f-8ac0-7a1606b7aa9b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=393352844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.393352844
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1201394256
Short name T368
Test name
Test status
Simulation time 152423383 ps
CPU time 0.83 seconds
Started Jul 07 05:22:42 PM PDT 24
Finished Jul 07 05:22:43 PM PDT 24
Peak memory 206144 kb
Host smart-d847e8e1-10d0-411a-abc5-e06cb29d6d34
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1201394256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1201394256
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4147094165
Short name T797
Test name
Test status
Simulation time 160495516 ps
CPU time 0.8 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206132 kb
Host smart-87bb6563-db45-4f25-bc74-b3b4d57f7077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
94165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4147094165
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1135632367
Short name T2654
Test name
Test status
Simulation time 201511632 ps
CPU time 0.85 seconds
Started Jul 07 05:22:42 PM PDT 24
Finished Jul 07 05:22:43 PM PDT 24
Peak memory 206100 kb
Host smart-f334663a-e7fd-48f6-9a5a-5b8d10be5d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11356
32367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1135632367
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4085179235
Short name T1208
Test name
Test status
Simulation time 187495595 ps
CPU time 0.85 seconds
Started Jul 07 05:22:41 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206188 kb
Host smart-979ecda5-f74a-4356-be68-788dc9730ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851
79235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4085179235
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1263839586
Short name T1905
Test name
Test status
Simulation time 183333899 ps
CPU time 0.82 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206196 kb
Host smart-d897f83a-2e65-4e2b-9fcb-237c9f447a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12638
39586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1263839586
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2936516265
Short name T2459
Test name
Test status
Simulation time 170591793 ps
CPU time 0.8 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:22:46 PM PDT 24
Peak memory 206180 kb
Host smart-a9b1953b-cfba-4e6b-a1e2-5e0560b0cb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29365
16265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2936516265
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3728337893
Short name T1363
Test name
Test status
Simulation time 204453068 ps
CPU time 0.8 seconds
Started Jul 07 05:22:41 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206196 kb
Host smart-659ab02e-9bdc-4863-a267-e4e110a1e219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283
37893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3728337893
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.740593630
Short name T2394
Test name
Test status
Simulation time 266166637 ps
CPU time 0.96 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206136 kb
Host smart-e943a261-5883-480e-817f-b210eb9fc4ce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=740593630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.740593630
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1299372595
Short name T2604
Test name
Test status
Simulation time 139850782 ps
CPU time 0.81 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206204 kb
Host smart-db968e77-8620-492f-a86c-680ff9f495df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12993
72595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1299372595
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1781128803
Short name T1685
Test name
Test status
Simulation time 54720791 ps
CPU time 0.7 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:44 PM PDT 24
Peak memory 206212 kb
Host smart-ce4f6eff-406b-4163-98c4-429f898cc1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17811
28803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1781128803
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3257670619
Short name T276
Test name
Test status
Simulation time 23885492158 ps
CPU time 59.54 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:23:41 PM PDT 24
Peak memory 206476 kb
Host smart-50608a15-7574-48aa-8458-c6ce1a3a8026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
70619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3257670619
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1932661411
Short name T2140
Test name
Test status
Simulation time 205987250 ps
CPU time 0.88 seconds
Started Jul 07 05:22:47 PM PDT 24
Finished Jul 07 05:22:48 PM PDT 24
Peak memory 206120 kb
Host smart-d139b512-1b78-4af0-953e-1f267fc2b963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19326
61411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1932661411
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3477333229
Short name T1635
Test name
Test status
Simulation time 247071733 ps
CPU time 0.97 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206180 kb
Host smart-3c0fb8c0-7e61-4849-ae52-c41178bfbfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
33229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3477333229
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.525151485
Short name T2084
Test name
Test status
Simulation time 197268345 ps
CPU time 0.86 seconds
Started Jul 07 05:22:40 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206120 kb
Host smart-555250e1-8c67-429f-9dcf-d7ecde502674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52515
1485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.525151485
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.4160715281
Short name T587
Test name
Test status
Simulation time 175232095 ps
CPU time 0.87 seconds
Started Jul 07 05:22:41 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206232 kb
Host smart-3ba923b5-3ba8-4386-87f2-9e0a7339d626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41607
15281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.4160715281
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.526360443
Short name T2128
Test name
Test status
Simulation time 157960987 ps
CPU time 0.8 seconds
Started Jul 07 05:22:43 PM PDT 24
Finished Jul 07 05:22:45 PM PDT 24
Peak memory 206104 kb
Host smart-69ebb4b9-73bc-4de0-9542-10559f4519a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52636
0443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.526360443
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1928550397
Short name T994
Test name
Test status
Simulation time 147875866 ps
CPU time 0.81 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:49 PM PDT 24
Peak memory 206140 kb
Host smart-78d3bfee-d8cf-4e4b-830c-3fe03ba3e48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19285
50397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1928550397
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2688367224
Short name T2430
Test name
Test status
Simulation time 147747641 ps
CPU time 0.77 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206116 kb
Host smart-bcc29c2d-446e-46ae-9384-0978a7712155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26883
67224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2688367224
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3901980833
Short name T1061
Test name
Test status
Simulation time 186364410 ps
CPU time 0.84 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206184 kb
Host smart-fae26d21-5755-47a0-9871-736bace966ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39019
80833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3901980833
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1308809193
Short name T405
Test name
Test status
Simulation time 5151176665 ps
CPU time 52.2 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:23:40 PM PDT 24
Peak memory 206428 kb
Host smart-ab17c46b-e1f8-4f34-952f-465105e8331e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1308809193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1308809193
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1915644201
Short name T1827
Test name
Test status
Simulation time 160985041 ps
CPU time 0.83 seconds
Started Jul 07 05:22:49 PM PDT 24
Finished Jul 07 05:22:50 PM PDT 24
Peak memory 206208 kb
Host smart-03832817-479e-4d22-8cc2-b7b89d3847cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
44201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1915644201
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3459478791
Short name T2283
Test name
Test status
Simulation time 171592249 ps
CPU time 0.78 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:22:46 PM PDT 24
Peak memory 206196 kb
Host smart-80814322-4d5a-4cfa-9f25-d4668d589507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34594
78791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3459478791
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.647556752
Short name T548
Test name
Test status
Simulation time 1085072344 ps
CPU time 2.34 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206384 kb
Host smart-2a7374c9-decb-4bc6-b133-4c50d8c4de7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64755
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.647556752
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3077793029
Short name T1999
Test name
Test status
Simulation time 6665118045 ps
CPU time 47.7 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:23:34 PM PDT 24
Peak memory 206380 kb
Host smart-ee39ee60-2101-4248-8db8-e57ab234fdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
93029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3077793029
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.780405477
Short name T1865
Test name
Test status
Simulation time 46338578 ps
CPU time 0.67 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206492 kb
Host smart-9ed066d4-1231-4c2f-a932-b12d66c53189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=780405477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.780405477
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2792468875
Short name T1891
Test name
Test status
Simulation time 3955971356 ps
CPU time 4.63 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206476 kb
Host smart-fe5fd530-9e72-4584-a88d-9fb654f807fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2792468875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2792468875
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1312321118
Short name T1692
Test name
Test status
Simulation time 13460980022 ps
CPU time 12.57 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 206500 kb
Host smart-824c84c5-d45b-4c24-ae8d-348aaf504076
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1312321118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1312321118
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3026838014
Short name T1650
Test name
Test status
Simulation time 23414102147 ps
CPU time 23.96 seconds
Started Jul 07 05:22:49 PM PDT 24
Finished Jul 07 05:23:13 PM PDT 24
Peak memory 206468 kb
Host smart-634922c4-576d-4abc-abde-2ed5f73a3e65
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026838014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.3026838014
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3455678948
Short name T1613
Test name
Test status
Simulation time 175122986 ps
CPU time 0.84 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:49 PM PDT 24
Peak memory 206184 kb
Host smart-7a8bdf7a-6c2e-4914-82c3-19e1799fd474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34556
78948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3455678948
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.179812778
Short name T2427
Test name
Test status
Simulation time 153907754 ps
CPU time 0.8 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:22:48 PM PDT 24
Peak memory 206152 kb
Host smart-b056aebd-7706-4718-b07c-4023d14db651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
2778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.179812778
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1463941567
Short name T1553
Test name
Test status
Simulation time 194922452 ps
CPU time 0.96 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:52 PM PDT 24
Peak memory 206196 kb
Host smart-a13db925-e79c-4724-a4a5-f366994f701f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639
41567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1463941567
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3979194362
Short name T2538
Test name
Test status
Simulation time 1141986572 ps
CPU time 2.7 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:51 PM PDT 24
Peak memory 206304 kb
Host smart-80f53986-7875-4b90-a68b-78e4303fb1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
94362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3979194362
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3918085909
Short name T2193
Test name
Test status
Simulation time 21755694866 ps
CPU time 37.07 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206152 kb
Host smart-77bab1bc-40c3-4bd3-93af-2fd624a8eb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39180
85909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3918085909
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3832608675
Short name T1311
Test name
Test status
Simulation time 431859224 ps
CPU time 1.3 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:22:48 PM PDT 24
Peak memory 206036 kb
Host smart-e835a33a-e14f-47a6-a9ad-bd5c36456fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
08675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3832608675
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.4019468800
Short name T1215
Test name
Test status
Simulation time 168150203 ps
CPU time 0.83 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:22:46 PM PDT 24
Peak memory 206104 kb
Host smart-2419346e-47fd-4943-bf99-4d749e15fa82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40194
68800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.4019468800
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.703434510
Short name T251
Test name
Test status
Simulation time 40386407 ps
CPU time 0.69 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:22:51 PM PDT 24
Peak memory 206200 kb
Host smart-f9bbf1a0-9274-43ae-a5d2-9139ebdeb3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70343
4510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.703434510
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3558259756
Short name T1618
Test name
Test status
Simulation time 760099851 ps
CPU time 2.06 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206420 kb
Host smart-ba8ac3b5-8ebd-4109-b694-b2c0b7758243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582
59756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3558259756
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1764434163
Short name T212
Test name
Test status
Simulation time 209782093 ps
CPU time 1.96 seconds
Started Jul 07 05:22:45 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 206440 kb
Host smart-808c4e32-5828-45a3-9fca-d8fef2623023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644
34163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1764434163
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.4118948628
Short name T1082
Test name
Test status
Simulation time 201824997 ps
CPU time 0.81 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:49 PM PDT 24
Peak memory 206156 kb
Host smart-564050fd-e198-4753-ad37-432318298f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41189
48628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.4118948628
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2054496894
Short name T505
Test name
Test status
Simulation time 159045251 ps
CPU time 0.79 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:49 PM PDT 24
Peak memory 206192 kb
Host smart-3e7d45f4-742f-43ee-baa4-ff0362f7d2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544
96894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2054496894
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3451547186
Short name T984
Test name
Test status
Simulation time 226022278 ps
CPU time 0.97 seconds
Started Jul 07 05:22:46 PM PDT 24
Finished Jul 07 05:22:48 PM PDT 24
Peak memory 206152 kb
Host smart-39ddf411-554e-4c97-9df3-8fbf80b669f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34515
47186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3451547186
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.3768371166
Short name T1329
Test name
Test status
Simulation time 6120309223 ps
CPU time 57 seconds
Started Jul 07 05:22:44 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206328 kb
Host smart-4a4e7bba-29b2-43d6-bfd9-ed060f0e6eca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3768371166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.3768371166
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3874694192
Short name T970
Test name
Test status
Simulation time 225675652 ps
CPU time 0.87 seconds
Started Jul 07 05:22:48 PM PDT 24
Finished Jul 07 05:22:50 PM PDT 24
Peak memory 206108 kb
Host smart-7afc4149-43ba-4a08-be07-47cb0682e82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746
94192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3874694192
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1893589649
Short name T803
Test name
Test status
Simulation time 23307777732 ps
CPU time 27.28 seconds
Started Jul 07 05:22:47 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206180 kb
Host smart-bb479f0b-2c78-445e-8888-fc208701c34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18935
89649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1893589649
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3379831123
Short name T650
Test name
Test status
Simulation time 3320447700 ps
CPU time 3.91 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:55 PM PDT 24
Peak memory 206260 kb
Host smart-4bb44b62-0f05-4b11-99d5-68c0279b91d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33798
31123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3379831123
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1020619551
Short name T1911
Test name
Test status
Simulation time 7565413115 ps
CPU time 72.78 seconds
Started Jul 07 05:22:47 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206548 kb
Host smart-abfbb779-2faf-40c8-bce4-0aba62bc83d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
19551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1020619551
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1724303871
Short name T1050
Test name
Test status
Simulation time 5335511452 ps
CPU time 145.01 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 206456 kb
Host smart-cec73856-9766-4b63-9dc9-e3f57f5001b3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1724303871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1724303871
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.4219556616
Short name T1346
Test name
Test status
Simulation time 238808631 ps
CPU time 0.93 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206164 kb
Host smart-df2206d7-3c3f-4914-bb4e-cfd528dcef95
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4219556616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.4219556616
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.163726664
Short name T575
Test name
Test status
Simulation time 183479617 ps
CPU time 0.93 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206112 kb
Host smart-09438f69-6cbf-4138-bb68-36c8519b689d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16372
6664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.163726664
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.852360024
Short name T167
Test name
Test status
Simulation time 4874615601 ps
CPU time 47.14 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:23:39 PM PDT 24
Peak memory 206464 kb
Host smart-a06bd1bb-093d-4c6b-bd83-07fbd016bfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85236
0024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.852360024
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3527416027
Short name T1444
Test name
Test status
Simulation time 6230466750 ps
CPU time 172.57 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:25:45 PM PDT 24
Peak memory 206432 kb
Host smart-7ccb298a-714c-4260-8c38-2bfc0fd40cad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3527416027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3527416027
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3774446891
Short name T2512
Test name
Test status
Simulation time 227652060 ps
CPU time 0.85 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206136 kb
Host smart-cc22bf2a-6da8-4efa-902b-6a8788f42584
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3774446891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3774446891
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1951126014
Short name T637
Test name
Test status
Simulation time 140222594 ps
CPU time 0.77 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:52 PM PDT 24
Peak memory 206196 kb
Host smart-ceeb3181-2c5f-405b-afd5-8d067bb1d8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19511
26014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1951126014
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3801394629
Short name T2570
Test name
Test status
Simulation time 185966206 ps
CPU time 0.82 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206216 kb
Host smart-e221af31-4684-42ae-b1f9-bda1b87e2c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38013
94629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3801394629
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1754640384
Short name T106
Test name
Test status
Simulation time 185877250 ps
CPU time 0.82 seconds
Started Jul 07 05:22:53 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206180 kb
Host smart-3410678f-b160-4e41-900f-dfe76f060f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
40384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1754640384
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4146015959
Short name T1188
Test name
Test status
Simulation time 177730902 ps
CPU time 0.84 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:22:51 PM PDT 24
Peak memory 206176 kb
Host smart-12de66d7-2020-4591-a32f-a7da0d18a720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41460
15959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4146015959
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2202028077
Short name T692
Test name
Test status
Simulation time 161626824 ps
CPU time 0.8 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206184 kb
Host smart-c4ef5c90-ff6f-4042-8304-d4288ef35c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
28077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2202028077
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.702334697
Short name T1167
Test name
Test status
Simulation time 151254800 ps
CPU time 0.77 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206192 kb
Host smart-cb9732ab-e1b3-4f37-9ba9-1e340dce0c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70233
4697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.702334697
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3700309639
Short name T1501
Test name
Test status
Simulation time 224595453 ps
CPU time 0.99 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206124 kb
Host smart-e29ae185-5809-40fc-81b1-970e31cce47f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3700309639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3700309639
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1201033583
Short name T1874
Test name
Test status
Simulation time 172057818 ps
CPU time 0.8 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:52 PM PDT 24
Peak memory 206440 kb
Host smart-81abdc16-3996-4c08-9d09-83c969c11bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12010
33583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1201033583
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.895370181
Short name T1516
Test name
Test status
Simulation time 32584545 ps
CPU time 0.65 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206120 kb
Host smart-4e0a1c10-77db-46f7-a46f-1ab7f3495bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89537
0181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.895370181
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3719356602
Short name T1580
Test name
Test status
Simulation time 10565899139 ps
CPU time 22.5 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:23:13 PM PDT 24
Peak memory 206480 kb
Host smart-78678dee-a278-40b5-a5ca-9c3c2cfd10c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
56602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3719356602
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.4267801223
Short name T494
Test name
Test status
Simulation time 165066869 ps
CPU time 0.88 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:22:52 PM PDT 24
Peak memory 206196 kb
Host smart-c0bd6e4c-187d-4d3b-a9f8-dec43ff96b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42678
01223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.4267801223
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.4197021954
Short name T2098
Test name
Test status
Simulation time 165412940 ps
CPU time 0.79 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 205996 kb
Host smart-612fa9a7-5f41-4d95-bbe8-092cf82667d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
21954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.4197021954
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3338221634
Short name T2289
Test name
Test status
Simulation time 205269003 ps
CPU time 0.84 seconds
Started Jul 07 05:22:54 PM PDT 24
Finished Jul 07 05:22:55 PM PDT 24
Peak memory 206044 kb
Host smart-2c594119-362e-4e93-bb12-eac0256f2bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33382
21634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3338221634
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2677604562
Short name T1185
Test name
Test status
Simulation time 176091468 ps
CPU time 0.81 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206004 kb
Host smart-35df40fc-0f2c-49f0-a3d0-1676278ff13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
04562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2677604562
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3298869185
Short name T529
Test name
Test status
Simulation time 179436988 ps
CPU time 0.88 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206184 kb
Host smart-9bdf15bf-6ca7-4a27-9ba1-869435df918b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988
69185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3298869185
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.4167955283
Short name T2145
Test name
Test status
Simulation time 159676679 ps
CPU time 0.82 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206040 kb
Host smart-4de7d0b6-fca5-43ed-820b-6afcaac89a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41679
55283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.4167955283
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3189970212
Short name T1897
Test name
Test status
Simulation time 205650926 ps
CPU time 0.87 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:22:54 PM PDT 24
Peak memory 206184 kb
Host smart-a19f5ee4-e086-4417-a6b8-607756ac5d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31899
70212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3189970212
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.607378782
Short name T1898
Test name
Test status
Simulation time 241103187 ps
CPU time 1.03 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:22:53 PM PDT 24
Peak memory 206184 kb
Host smart-f98443ca-294b-4cec-a5a5-eec4e394594e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60737
8782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.607378782
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.806079165
Short name T1293
Test name
Test status
Simulation time 5382620643 ps
CPU time 38.57 seconds
Started Jul 07 05:22:52 PM PDT 24
Finished Jul 07 05:23:31 PM PDT 24
Peak memory 206436 kb
Host smart-aa074b1c-1473-4749-9d22-8e767f534574
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=806079165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.806079165
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2388707988
Short name T643
Test name
Test status
Simulation time 150381859 ps
CPU time 0.82 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:22:52 PM PDT 24
Peak memory 206068 kb
Host smart-d056a708-9b04-4c83-bc49-015b43b6bb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23887
07988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2388707988
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1056960872
Short name T1266
Test name
Test status
Simulation time 161139688 ps
CPU time 0.8 seconds
Started Jul 07 05:22:49 PM PDT 24
Finished Jul 07 05:22:51 PM PDT 24
Peak memory 206428 kb
Host smart-f362480c-14d6-434b-a299-94c30a1b1f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10569
60872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1056960872
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.2255488867
Short name T1383
Test name
Test status
Simulation time 1247024804 ps
CPU time 2.61 seconds
Started Jul 07 05:22:54 PM PDT 24
Finished Jul 07 05:22:57 PM PDT 24
Peak memory 206280 kb
Host smart-d3eb1fbb-52d1-479a-aece-34388b475e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22554
88867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.2255488867
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.692853603
Short name T1197
Test name
Test status
Simulation time 5911096124 ps
CPU time 53.27 seconds
Started Jul 07 05:22:50 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206380 kb
Host smart-a9ca455b-0af7-4332-9210-21fe2d11e05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69285
3603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.692853603
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.131880549
Short name T910
Test name
Test status
Simulation time 51553784 ps
CPU time 0.73 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206220 kb
Host smart-7c624b02-1a27-4c29-8be9-46ae119e2140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=131880549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.131880549
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2070026350
Short name T2121
Test name
Test status
Simulation time 4273892939 ps
CPU time 5.79 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 205840 kb
Host smart-57134d32-1fcc-4b91-a019-73c8b06a8ff8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2070026350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2070026350
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1091209973
Short name T2608
Test name
Test status
Simulation time 13345746118 ps
CPU time 14.62 seconds
Started Jul 07 05:22:51 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206148 kb
Host smart-86843f95-4a43-4e93-9162-b24cda7ab444
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1091209973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1091209973
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1328706605
Short name T1466
Test name
Test status
Simulation time 23500841039 ps
CPU time 25.38 seconds
Started Jul 07 05:22:54 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206468 kb
Host smart-8dec9ae9-3eaf-4b15-87d4-c648de97b005
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1328706605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1328706605
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.586868439
Short name T2339
Test name
Test status
Simulation time 158376257 ps
CPU time 0.85 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206116 kb
Host smart-67edf1aa-56e6-4048-a0b0-6fa6390a7b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58686
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.586868439
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2350980974
Short name T1554
Test name
Test status
Simulation time 192131117 ps
CPU time 0.86 seconds
Started Jul 07 05:22:58 PM PDT 24
Finished Jul 07 05:22:59 PM PDT 24
Peak memory 206144 kb
Host smart-8fcaa0e4-88b3-441b-85b6-efd6bc4550e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
80974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2350980974
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3367135004
Short name T1046
Test name
Test status
Simulation time 214162231 ps
CPU time 0.95 seconds
Started Jul 07 05:22:54 PM PDT 24
Finished Jul 07 05:22:55 PM PDT 24
Peak memory 206208 kb
Host smart-020d9d88-4d97-4372-b351-f7b0e41d5fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671
35004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3367135004
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.45886228
Short name T963
Test name
Test status
Simulation time 729716794 ps
CPU time 1.92 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:57 PM PDT 24
Peak memory 206420 kb
Host smart-a6a397fa-ee83-42fe-a2e4-c2e794b014c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45886
228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.45886228
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2258768497
Short name T1315
Test name
Test status
Simulation time 9959044035 ps
CPU time 21.34 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206452 kb
Host smart-89cb5c50-1ad2-419d-a86e-9f2797288532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22587
68497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2258768497
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1262134922
Short name T1283
Test name
Test status
Simulation time 422736967 ps
CPU time 1.3 seconds
Started Jul 07 05:22:56 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 206200 kb
Host smart-632047ed-1227-4376-b8c2-7cd6650992b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
34922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1262134922
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.163031075
Short name T473
Test name
Test status
Simulation time 147693600 ps
CPU time 0.8 seconds
Started Jul 07 05:22:57 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 206188 kb
Host smart-f3886f09-eb62-408d-8bc7-cf953e2cb4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16303
1075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.163031075
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3757241868
Short name T2082
Test name
Test status
Simulation time 81879007 ps
CPU time 0.72 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206192 kb
Host smart-2e2f67b4-face-454e-a9d8-2df251d55e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37572
41868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3757241868
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1933933216
Short name T964
Test name
Test status
Simulation time 907910839 ps
CPU time 2.19 seconds
Started Jul 07 05:22:57 PM PDT 24
Finished Jul 07 05:22:59 PM PDT 24
Peak memory 206364 kb
Host smart-5170c128-17c7-4320-82aa-310253232f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19339
33216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1933933216
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.54345467
Short name T856
Test name
Test status
Simulation time 288109525 ps
CPU time 2.19 seconds
Started Jul 07 05:22:56 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 206396 kb
Host smart-4b9d0c88-f860-422a-b532-2e559dae72dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54345
467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.54345467
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3640029758
Short name T1316
Test name
Test status
Simulation time 241578559 ps
CPU time 0.9 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206184 kb
Host smart-4880b292-c54e-4bb7-8349-8653e924d687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36400
29758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3640029758
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3285086764
Short name T2178
Test name
Test status
Simulation time 173227090 ps
CPU time 0.8 seconds
Started Jul 07 05:22:54 PM PDT 24
Finished Jul 07 05:22:55 PM PDT 24
Peak memory 206180 kb
Host smart-1b5e3fad-52d4-4994-a68e-d8aef4b00384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32850
86764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3285086764
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3868400358
Short name T1068
Test name
Test status
Simulation time 235603512 ps
CPU time 1.01 seconds
Started Jul 07 05:22:58 PM PDT 24
Finished Jul 07 05:22:59 PM PDT 24
Peak memory 206184 kb
Host smart-ea18e156-3afb-42cd-8b2c-a42c18c21010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38684
00358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3868400358
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.893509547
Short name T1180
Test name
Test status
Simulation time 240704282 ps
CPU time 0.9 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:22:57 PM PDT 24
Peak memory 205836 kb
Host smart-cf661e8d-272c-43e7-9e44-81bd601b6272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89350
9547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.893509547
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.2242004198
Short name T1876
Test name
Test status
Simulation time 23303040724 ps
CPU time 22.26 seconds
Started Jul 07 05:22:54 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206500 kb
Host smart-8787cfb5-e183-463e-89bd-84f27e3ac7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
04198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.2242004198
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1676211227
Short name T2714
Test name
Test status
Simulation time 3318877463 ps
CPU time 4.2 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:23:00 PM PDT 24
Peak memory 206236 kb
Host smart-433d31b3-c46d-4a53-b0e1-dd2a766bb778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
11227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1676211227
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.265739192
Short name T270
Test name
Test status
Simulation time 7755969526 ps
CPU time 222.86 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 206508 kb
Host smart-9eadbfd4-5674-4bb2-97ae-fc95bb12db5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26573
9192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.265739192
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.602417708
Short name T2032
Test name
Test status
Simulation time 242895215 ps
CPU time 1.02 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206088 kb
Host smart-647c2974-a31d-4b2b-9d83-ff65b34d153f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=602417708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.602417708
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2321801917
Short name T790
Test name
Test status
Simulation time 192296673 ps
CPU time 0.95 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206188 kb
Host smart-e346c7af-fb3d-4cae-81c2-d81f3f14a5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
01917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2321801917
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3351367210
Short name T2347
Test name
Test status
Simulation time 4457202166 ps
CPU time 31.63 seconds
Started Jul 07 05:22:55 PM PDT 24
Finished Jul 07 05:23:27 PM PDT 24
Peak memory 206468 kb
Host smart-e9d2e293-5498-4669-864b-acae4abd35b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
67210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3351367210
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1609664593
Short name T1673
Test name
Test status
Simulation time 4408865912 ps
CPU time 33.87 seconds
Started Jul 07 05:22:58 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206272 kb
Host smart-7efac4db-03cc-4994-a19c-2d7bb5f5d4cb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1609664593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1609664593
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.3666363026
Short name T238
Test name
Test status
Simulation time 153224968 ps
CPU time 0.83 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206144 kb
Host smart-ff4bfe6d-4ce0-49aa-9755-d4560f39c7d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3666363026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.3666363026
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3721990229
Short name T1122
Test name
Test status
Simulation time 147179306 ps
CPU time 0.77 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206188 kb
Host smart-d8b0a893-9f32-4819-9b65-b4dadbdeec91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37219
90229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3721990229
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.50789282
Short name T2627
Test name
Test status
Simulation time 233249669 ps
CPU time 0.88 seconds
Started Jul 07 05:22:59 PM PDT 24
Finished Jul 07 05:23:01 PM PDT 24
Peak memory 206180 kb
Host smart-60bfc477-f9d6-4d7e-aa8c-19ea6aaa87f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50789
282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.50789282
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.811874603
Short name T1074
Test name
Test status
Simulation time 193380995 ps
CPU time 0.89 seconds
Started Jul 07 05:22:59 PM PDT 24
Finished Jul 07 05:23:00 PM PDT 24
Peak memory 206112 kb
Host smart-b76d93b7-1d14-41ae-8554-c9143a5dbbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81187
4603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.811874603
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2227659412
Short name T2253
Test name
Test status
Simulation time 193119509 ps
CPU time 0.9 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206184 kb
Host smart-a18b4208-9aa5-40f2-a2d0-45c72df411b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22276
59412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2227659412
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1661927521
Short name T1574
Test name
Test status
Simulation time 241594608 ps
CPU time 0.85 seconds
Started Jul 07 05:23:00 PM PDT 24
Finished Jul 07 05:23:01 PM PDT 24
Peak memory 206184 kb
Host smart-bdad93f3-4581-427a-8ca8-5cd59ab86a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16619
27521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1661927521
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.458511051
Short name T2150
Test name
Test status
Simulation time 163075664 ps
CPU time 0.8 seconds
Started Jul 07 05:22:59 PM PDT 24
Finished Jul 07 05:23:00 PM PDT 24
Peak memory 206120 kb
Host smart-9f7fcd0b-4035-499c-a879-4e0e71552b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45851
1051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.458511051
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3501116756
Short name T460
Test name
Test status
Simulation time 205886450 ps
CPU time 0.86 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206152 kb
Host smart-05f720e8-1f1d-4fcd-a4fa-79d565898863
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3501116756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3501116756
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4020901594
Short name T661
Test name
Test status
Simulation time 150803808 ps
CPU time 0.8 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206112 kb
Host smart-5f5c70aa-2426-4bf8-939d-fdd47f61d4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40209
01594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4020901594
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.913415982
Short name T1857
Test name
Test status
Simulation time 50644326 ps
CPU time 0.68 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206216 kb
Host smart-4fe9b580-5552-4563-8c5f-cb083dc42cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91341
5982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.913415982
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.397252086
Short name T1524
Test name
Test status
Simulation time 19876288620 ps
CPU time 40.43 seconds
Started Jul 07 05:22:59 PM PDT 24
Finished Jul 07 05:23:39 PM PDT 24
Peak memory 206736 kb
Host smart-3325b2a8-6ce3-42b2-9927-f9226abd6223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
2086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.397252086
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1563913891
Short name T1846
Test name
Test status
Simulation time 153058681 ps
CPU time 0.8 seconds
Started Jul 07 05:22:57 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 206180 kb
Host smart-ce48ccfd-40f2-4089-9309-df21d1ab200a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15639
13891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1563913891
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3147270923
Short name T1760
Test name
Test status
Simulation time 228348893 ps
CPU time 0.92 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206108 kb
Host smart-ae8f730f-ec85-4e2a-9aac-5fd96a2a97ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
70923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3147270923
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1794965891
Short name T357
Test name
Test status
Simulation time 234044931 ps
CPU time 0.9 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206188 kb
Host smart-7acb6c84-05ce-4015-95c0-d5480381e9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
65891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1794965891
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2198130186
Short name T572
Test name
Test status
Simulation time 161361857 ps
CPU time 0.84 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206188 kb
Host smart-52f669c5-08db-456b-affa-28cbb0d717bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21981
30186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2198130186
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1578102753
Short name T663
Test name
Test status
Simulation time 147427166 ps
CPU time 0.81 seconds
Started Jul 07 05:23:01 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206180 kb
Host smart-48e48b1c-6739-427e-af6c-330451546a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15781
02753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1578102753
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.32426669
Short name T987
Test name
Test status
Simulation time 177570711 ps
CPU time 0.88 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206116 kb
Host smart-e36f8669-7c0c-4983-98e3-d280c95cf381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32426
669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.32426669
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.447554989
Short name T1564
Test name
Test status
Simulation time 146213764 ps
CPU time 0.81 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206184 kb
Host smart-47c0c47d-b4b1-460e-ab44-f811995e1804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44755
4989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.447554989
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1170860390
Short name T2582
Test name
Test status
Simulation time 236179665 ps
CPU time 0.98 seconds
Started Jul 07 05:23:03 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206204 kb
Host smart-43203a22-941d-4958-8dd1-efe30f24390d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11708
60390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1170860390
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3467090984
Short name T2065
Test name
Test status
Simulation time 4089292779 ps
CPU time 118.62 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:25:07 PM PDT 24
Peak memory 206512 kb
Host smart-c507820b-221e-491d-9d87-f0e2540f2e7d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3467090984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3467090984
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.744585215
Short name T1106
Test name
Test status
Simulation time 195782337 ps
CPU time 0.82 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206192 kb
Host smart-ba6d676b-ec62-4f46-b66c-1a71b3d02822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74458
5215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.744585215
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.292357919
Short name T738
Test name
Test status
Simulation time 208105361 ps
CPU time 0.85 seconds
Started Jul 07 05:23:05 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206140 kb
Host smart-e6018d07-555a-4139-ac2b-c8a379dda951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29235
7919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.292357919
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2801489391
Short name T2207
Test name
Test status
Simulation time 781565190 ps
CPU time 2.06 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206364 kb
Host smart-19fa0085-307d-4467-920f-680af644e257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
89391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2801489391
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3927762902
Short name T462
Test name
Test status
Simulation time 6136178556 ps
CPU time 170 seconds
Started Jul 07 05:23:04 PM PDT 24
Finished Jul 07 05:25:54 PM PDT 24
Peak memory 206420 kb
Host smart-40990f9d-3892-4ba0-9483-975523f05aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39277
62902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3927762902
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.247480978
Short name T2567
Test name
Test status
Simulation time 30054129 ps
CPU time 0.63 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:08 PM PDT 24
Peak memory 206156 kb
Host smart-dd5a4627-06f0-4778-9fe1-5abd55807bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=247480978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.247480978
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.361632792
Short name T2539
Test name
Test status
Simulation time 4262071151 ps
CPU time 5.65 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206336 kb
Host smart-6beec7c7-88b8-4548-bc87-b0085ca30df9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=361632792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.361632792
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2803445473
Short name T687
Test name
Test status
Simulation time 13307357221 ps
CPU time 12.55 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206436 kb
Host smart-c53fed70-e903-4651-ad17-8129e2180ded
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2803445473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2803445473
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3943362596
Short name T1463
Test name
Test status
Simulation time 23321900709 ps
CPU time 27.29 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:37 PM PDT 24
Peak memory 206220 kb
Host smart-898f5165-bef5-4c63-bc6d-ac113aee855c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3943362596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3943362596
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1568085293
Short name T915
Test name
Test status
Simulation time 158397995 ps
CPU time 0.88 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206196 kb
Host smart-7af40bb7-9431-46b5-96b5-6b7bffbe82fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15680
85293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1568085293
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1845020904
Short name T1644
Test name
Test status
Simulation time 172119432 ps
CPU time 0.79 seconds
Started Jul 07 05:23:05 PM PDT 24
Finished Jul 07 05:23:06 PM PDT 24
Peak memory 206120 kb
Host smart-13f65f22-7337-487e-ab9f-2c148048dcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18450
20904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1845020904
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3114608794
Short name T2524
Test name
Test status
Simulation time 475297916 ps
CPU time 1.36 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206196 kb
Host smart-d9b5b8fd-6036-4d37-b719-1268da84a7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31146
08794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3114608794
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3553992393
Short name T1913
Test name
Test status
Simulation time 311983350 ps
CPU time 1.07 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206184 kb
Host smart-a46b46b6-c748-4233-ac99-5d3c4ecdb029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35539
92393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3553992393
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1024177486
Short name T1051
Test name
Test status
Simulation time 15843350312 ps
CPU time 29.66 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206376 kb
Host smart-213237c8-a8f9-4ff4-90eb-d580d672f29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10241
77486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1024177486
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2781794054
Short name T1242
Test name
Test status
Simulation time 445477293 ps
CPU time 1.29 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:08 PM PDT 24
Peak memory 206196 kb
Host smart-169b8e74-a40e-4b40-9a58-8a2c5dbadcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27817
94054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2781794054
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2991385663
Short name T785
Test name
Test status
Simulation time 136891452 ps
CPU time 0.8 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206196 kb
Host smart-405ec063-0eb2-4629-bc74-d8e23a119902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
85663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2991385663
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1018047497
Short name T1751
Test name
Test status
Simulation time 35854485 ps
CPU time 0.69 seconds
Started Jul 07 05:23:04 PM PDT 24
Finished Jul 07 05:23:05 PM PDT 24
Peak memory 206108 kb
Host smart-f480f026-1ab0-4166-9ef9-d0e7f8e87a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
47497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1018047497
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.668688536
Short name T2371
Test name
Test status
Simulation time 969058153 ps
CPU time 2.16 seconds
Started Jul 07 05:23:04 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206384 kb
Host smart-3d934d05-a9a3-404b-a9f5-939ab40bbc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66868
8536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.668688536
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2051487134
Short name T211
Test name
Test status
Simulation time 172454835 ps
CPU time 1.56 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206360 kb
Host smart-0f947e03-cc58-47d3-a965-fdff8dd4f5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20514
87134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2051487134
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1612577804
Short name T1385
Test name
Test status
Simulation time 183405706 ps
CPU time 0.79 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206112 kb
Host smart-95d18c27-b4ac-486c-a223-b779bcf3d089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16125
77804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1612577804
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.520858103
Short name T605
Test name
Test status
Simulation time 136397265 ps
CPU time 0.75 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206196 kb
Host smart-501ab8ff-7c3f-47e7-bcee-7e63b70e0ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52085
8103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.520858103
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.551348889
Short name T2407
Test name
Test status
Simulation time 211375650 ps
CPU time 0.84 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206148 kb
Host smart-fb90e954-11f6-452d-9f98-dd11391b8144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55134
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.551348889
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1036327346
Short name T2259
Test name
Test status
Simulation time 5244555550 ps
CPU time 141.55 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206480 kb
Host smart-9a9474f6-aa1e-48b3-8350-611c2f9679f4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1036327346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1036327346
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2911880943
Short name T2272
Test name
Test status
Simulation time 162507260 ps
CPU time 0.79 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206152 kb
Host smart-e5f74850-ba3a-4eea-b0e3-fe90394f2ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29118
80943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2911880943
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.698311603
Short name T535
Test name
Test status
Simulation time 23336309630 ps
CPU time 21.26 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:30 PM PDT 24
Peak memory 206248 kb
Host smart-d6af8bb2-04d7-4aa7-92fd-069e1b2b2f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69831
1603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.698311603
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3342254669
Short name T442
Test name
Test status
Simulation time 3319877759 ps
CPU time 3.68 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206264 kb
Host smart-34d65041-f00b-4750-bb7b-11b5cdf4328b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33422
54669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3342254669
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.2786612406
Short name T1622
Test name
Test status
Simulation time 7930594957 ps
CPU time 57.28 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:24:05 PM PDT 24
Peak memory 206516 kb
Host smart-e53212ec-12d4-4c29-87f8-bb43a7fa92c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27866
12406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2786612406
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.581871076
Short name T1414
Test name
Test status
Simulation time 5093537836 ps
CPU time 45.77 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206520 kb
Host smart-000f3adc-a01f-43cd-8448-9ffddd98b607
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=581871076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.581871076
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1329221792
Short name T378
Test name
Test status
Simulation time 260608519 ps
CPU time 0.93 seconds
Started Jul 07 05:23:02 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 206148 kb
Host smart-63558f9f-2f2a-4727-b77e-018002ed127b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1329221792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1329221792
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2903982926
Short name T1008
Test name
Test status
Simulation time 240184918 ps
CPU time 0.96 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206188 kb
Host smart-2d7bdcef-471c-46e4-a9a4-4cf48906ca61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
82926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2903982926
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1298494757
Short name T901
Test name
Test status
Simulation time 5900486444 ps
CPU time 58.08 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206412 kb
Host smart-421231e1-716a-429a-a813-6e97377121d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12984
94757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1298494757
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3780638621
Short name T1807
Test name
Test status
Simulation time 4614803108 ps
CPU time 32.65 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 206392 kb
Host smart-e6060fc9-8322-4fe1-96cd-0f8ead050639
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3780638621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3780638621
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2865322844
Short name T2560
Test name
Test status
Simulation time 178348340 ps
CPU time 0.84 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206132 kb
Host smart-b1e785ab-c93d-495b-8545-6565125eb6cc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2865322844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2865322844
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2663087869
Short name T2665
Test name
Test status
Simulation time 174021577 ps
CPU time 0.88 seconds
Started Jul 07 05:23:04 PM PDT 24
Finished Jul 07 05:23:05 PM PDT 24
Peak memory 206112 kb
Host smart-e2c2b86b-8099-404c-84e0-1780b996827e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
87869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2663087869
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1173266402
Short name T153
Test name
Test status
Simulation time 193118904 ps
CPU time 0.83 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206112 kb
Host smart-9f59b1a6-d7db-4baf-ad39-07e0a6b3237b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11732
66402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1173266402
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2011191788
Short name T1645
Test name
Test status
Simulation time 176485731 ps
CPU time 0.82 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206112 kb
Host smart-9e8ab741-d3d7-49ea-890d-7efbdda828ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20111
91788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2011191788
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.127309721
Short name T2377
Test name
Test status
Simulation time 152724344 ps
CPU time 0.76 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:08 PM PDT 24
Peak memory 206112 kb
Host smart-6c34fd73-12e3-4544-82af-815fe843c7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12730
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.127309721
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4150659028
Short name T1954
Test name
Test status
Simulation time 161442490 ps
CPU time 0.8 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206132 kb
Host smart-7a0a8ae8-2ffa-410e-9c48-77560c2451e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
59028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4150659028
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1717617454
Short name T495
Test name
Test status
Simulation time 157117673 ps
CPU time 0.77 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:11 PM PDT 24
Peak memory 206200 kb
Host smart-eed613e4-a9f7-4a48-beb0-097252a0a731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17176
17454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1717617454
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1645938648
Short name T557
Test name
Test status
Simulation time 208751459 ps
CPU time 0.98 seconds
Started Jul 07 05:23:05 PM PDT 24
Finished Jul 07 05:23:06 PM PDT 24
Peak memory 206152 kb
Host smart-4d526b8f-0674-4f0e-a2ee-65945d682a8e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1645938648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1645938648
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3058264739
Short name T1508
Test name
Test status
Simulation time 146088705 ps
CPU time 0.79 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206064 kb
Host smart-ef2f951c-4cff-4a43-9e2b-f665669db0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
64739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3058264739
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2669611811
Short name T1064
Test name
Test status
Simulation time 46450672 ps
CPU time 0.67 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206180 kb
Host smart-0b054d5c-b5f1-436b-a81a-cb3c1027c72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
11811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2669611811
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.152145126
Short name T2179
Test name
Test status
Simulation time 13795771777 ps
CPU time 32.42 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206452 kb
Host smart-fc4e26b7-67bf-40ab-b616-b8d0c634b957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15214
5126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.152145126
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1034736554
Short name T855
Test name
Test status
Simulation time 197287555 ps
CPU time 0.88 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206212 kb
Host smart-fb40fc1b-49cd-4821-a036-3cf8d32ad86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
36554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1034736554
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3427262153
Short name T591
Test name
Test status
Simulation time 236611289 ps
CPU time 0.94 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206184 kb
Host smart-44e3af65-1a61-4b35-8289-4de646f926f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
62153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3427262153
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1124488808
Short name T1718
Test name
Test status
Simulation time 212795189 ps
CPU time 0.92 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:09 PM PDT 24
Peak memory 206240 kb
Host smart-431cd9ca-0fff-4555-9e1d-7c12fd607cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
88808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1124488808
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2026149536
Short name T745
Test name
Test status
Simulation time 174226678 ps
CPU time 0.83 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206120 kb
Host smart-6f65e9ca-2f77-43f6-b1c1-879c7850cca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20261
49536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2026149536
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2940900788
Short name T1672
Test name
Test status
Simulation time 161470129 ps
CPU time 0.8 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206096 kb
Host smart-ca22f9ae-a7e6-4296-984c-291c69e1b014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
00788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2940900788
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2749096555
Short name T2288
Test name
Test status
Simulation time 164512566 ps
CPU time 0.8 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:08 PM PDT 24
Peak memory 206112 kb
Host smart-5dde21b5-e005-44b4-9043-81574a299a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
96555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2749096555
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1513427951
Short name T1277
Test name
Test status
Simulation time 153055291 ps
CPU time 0.77 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:08 PM PDT 24
Peak memory 206204 kb
Host smart-42b04fed-c083-4532-a816-7d2e6d424c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
27951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1513427951
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3349726860
Short name T470
Test name
Test status
Simulation time 260204581 ps
CPU time 0.94 seconds
Started Jul 07 05:23:10 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206116 kb
Host smart-1009e57a-5dea-4aa8-922d-6944838f0633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33497
26860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3349726860
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3458468973
Short name T914
Test name
Test status
Simulation time 5616518292 ps
CPU time 39.84 seconds
Started Jul 07 05:23:10 PM PDT 24
Finished Jul 07 05:23:51 PM PDT 24
Peak memory 206352 kb
Host smart-f383e07d-7676-474f-8221-3d8ba9579496
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3458468973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3458468973
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3666058704
Short name T160
Test name
Test status
Simulation time 169178380 ps
CPU time 0.86 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206236 kb
Host smart-123514ad-642e-4076-b3ff-1195f3767a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36660
58704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3666058704
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.743817433
Short name T2666
Test name
Test status
Simulation time 170346716 ps
CPU time 0.81 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206164 kb
Host smart-32c9860a-a74e-4529-b0c4-f2aba17324ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74381
7433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.743817433
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2338703965
Short name T1710
Test name
Test status
Simulation time 701794996 ps
CPU time 1.71 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206404 kb
Host smart-3a13f042-f5fa-4ec2-9c62-922bdcde7036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
03965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2338703965
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1525829572
Short name T2267
Test name
Test status
Simulation time 5845509927 ps
CPU time 54.37 seconds
Started Jul 07 05:23:05 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206460 kb
Host smart-2f1ee145-f702-4e52-9fb9-54866ecff9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15258
29572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1525829572
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1511002494
Short name T789
Test name
Test status
Simulation time 54237230 ps
CPU time 0.71 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206184 kb
Host smart-2f689ecf-6963-47c4-85ef-f15ab63a53dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1511002494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1511002494
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3881412920
Short name T1548
Test name
Test status
Simulation time 3516514841 ps
CPU time 4.2 seconds
Started Jul 07 05:23:10 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206484 kb
Host smart-326be795-cf7e-4819-80b1-59a07e180a11
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3881412920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3881412920
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2928162707
Short name T629
Test name
Test status
Simulation time 13352317077 ps
CPU time 12.19 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206432 kb
Host smart-e76da82f-a07c-475c-a043-f454b4036eba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2928162707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2928162707
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2006571008
Short name T2357
Test name
Test status
Simulation time 23394189667 ps
CPU time 23.74 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:35 PM PDT 24
Peak memory 206488 kb
Host smart-10f6db3b-e735-4fd1-972b-0b4370eb5c49
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2006571008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2006571008
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3287233701
Short name T1527
Test name
Test status
Simulation time 154378483 ps
CPU time 0.9 seconds
Started Jul 07 05:23:08 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206180 kb
Host smart-7f098d9b-b685-4238-bbfd-d20e063d2529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32872
33701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3287233701
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.293949552
Short name T1696
Test name
Test status
Simulation time 161771815 ps
CPU time 0.8 seconds
Started Jul 07 05:23:06 PM PDT 24
Finished Jul 07 05:23:08 PM PDT 24
Peak memory 206200 kb
Host smart-d3e87faa-6f49-49ad-b3cf-16ccab86cf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29394
9552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.293949552
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.4075062765
Short name T1308
Test name
Test status
Simulation time 317608264 ps
CPU time 1.16 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:11 PM PDT 24
Peak memory 206120 kb
Host smart-bc61e061-29a3-4c4b-a6e6-ef66cc27957a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40750
62765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.4075062765
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.767730488
Short name T202
Test name
Test status
Simulation time 1149227319 ps
CPU time 2.67 seconds
Started Jul 07 05:23:07 PM PDT 24
Finished Jul 07 05:23:11 PM PDT 24
Peak memory 206404 kb
Host smart-360b526b-5e77-49ff-ba74-99b398470fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76773
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.767730488
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.232264522
Short name T2453
Test name
Test status
Simulation time 18307171313 ps
CPU time 33.11 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206448 kb
Host smart-c4aa9d22-608a-4900-a9d3-4cc7a590737f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23226
4522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.232264522
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3475353802
Short name T2329
Test name
Test status
Simulation time 495698093 ps
CPU time 1.42 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206124 kb
Host smart-26b46adf-b878-4621-9df4-a230e543e7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34753
53802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3475353802
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1584470091
Short name T2588
Test name
Test status
Simulation time 160101077 ps
CPU time 0.79 seconds
Started Jul 07 05:23:13 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206120 kb
Host smart-867513a8-610e-4e5d-8e7d-3b92401ee57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
70091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1584470091
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4177168839
Short name T1243
Test name
Test status
Simulation time 38984460 ps
CPU time 0.67 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206200 kb
Host smart-ca73417d-77bd-49e1-bad6-804c5f80048b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41771
68839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4177168839
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2077499229
Short name T842
Test name
Test status
Simulation time 753803956 ps
CPU time 2.1 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206368 kb
Host smart-26b4cc87-888d-4dcb-8c93-d32a1ff989ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
99229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2077499229
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3806096120
Short name T2080
Test name
Test status
Simulation time 342004573 ps
CPU time 2.12 seconds
Started Jul 07 05:23:12 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206412 kb
Host smart-546b64b2-5c39-4652-be84-39acb106ac8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38060
96120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3806096120
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.4242100712
Short name T2028
Test name
Test status
Simulation time 155858069 ps
CPU time 0.82 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206148 kb
Host smart-4174eaf6-de27-4215-af7b-2b7c8c5ea13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42421
00712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.4242100712
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1124071758
Short name T911
Test name
Test status
Simulation time 181945601 ps
CPU time 0.82 seconds
Started Jul 07 05:23:12 PM PDT 24
Finished Jul 07 05:23:13 PM PDT 24
Peak memory 205268 kb
Host smart-b4e647dc-3225-470a-8e94-8d3d17621140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
71758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1124071758
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1069287392
Short name T1491
Test name
Test status
Simulation time 171359917 ps
CPU time 0.79 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206204 kb
Host smart-6864ae53-7f29-4320-b1ee-d6165240fec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10692
87392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1069287392
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2582698430
Short name T2384
Test name
Test status
Simulation time 168516575 ps
CPU time 0.88 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206184 kb
Host smart-30a1b8c3-8e8f-4378-852f-480cab4d6b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25826
98430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2582698430
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1479614579
Short name T471
Test name
Test status
Simulation time 23292387025 ps
CPU time 26.17 seconds
Started Jul 07 05:23:10 PM PDT 24
Finished Jul 07 05:23:37 PM PDT 24
Peak memory 206504 kb
Host smart-f18f656a-821e-46e6-8c1a-66cbd7981f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14796
14579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1479614579
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1519984259
Short name T2061
Test name
Test status
Simulation time 3331783537 ps
CPU time 4.52 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206152 kb
Host smart-12835070-428a-4fbc-b349-5251d22ebf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199
84259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1519984259
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2184171533
Short name T1745
Test name
Test status
Simulation time 8675277059 ps
CPU time 234.31 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:27:10 PM PDT 24
Peak memory 206556 kb
Host smart-e26e2cd2-e3c5-4087-8930-f4c91876b4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21841
71533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2184171533
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1518732440
Short name T1794
Test name
Test status
Simulation time 5589972088 ps
CPU time 59.17 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:24:09 PM PDT 24
Peak memory 206356 kb
Host smart-3d3a44db-0cfd-4c20-9376-480c698d1a1b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1518732440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1518732440
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.411133458
Short name T1
Test name
Test status
Simulation time 241151751 ps
CPU time 0.91 seconds
Started Jul 07 05:23:10 PM PDT 24
Finished Jul 07 05:23:12 PM PDT 24
Peak memory 206096 kb
Host smart-9db4b7a6-1aad-42ef-a0d5-ca17fc85c5b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=411133458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.411133458
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2933624139
Short name T447
Test name
Test status
Simulation time 193251068 ps
CPU time 0.86 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:11 PM PDT 24
Peak memory 206232 kb
Host smart-ad5dd6b2-903a-42c6-8e4e-4565109cb342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29336
24139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2933624139
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2350613277
Short name T2667
Test name
Test status
Simulation time 6533728849 ps
CPU time 49.55 seconds
Started Jul 07 05:23:12 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206364 kb
Host smart-4452a853-2e6a-417f-8e6f-825f5c46efbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
13277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2350613277
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2442450063
Short name T1200
Test name
Test status
Simulation time 3997382257 ps
CPU time 112.43 seconds
Started Jul 07 05:23:11 PM PDT 24
Finished Jul 07 05:25:04 PM PDT 24
Peak memory 206368 kb
Host smart-8a6200a6-952b-425e-8565-b59199e565de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2442450063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2442450063
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.793461142
Short name T2273
Test name
Test status
Simulation time 235239322 ps
CPU time 0.86 seconds
Started Jul 07 05:23:12 PM PDT 24
Finished Jul 07 05:23:13 PM PDT 24
Peak memory 206176 kb
Host smart-246d80b5-385e-4f78-8a85-c718efd5f861
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=793461142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.793461142
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3730999455
Short name T1158
Test name
Test status
Simulation time 142118471 ps
CPU time 0.76 seconds
Started Jul 07 05:23:09 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206188 kb
Host smart-02a36e49-3277-44d7-9bee-eacf904bf0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309
99455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3730999455
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.791308992
Short name T107
Test name
Test status
Simulation time 236554634 ps
CPU time 0.86 seconds
Started Jul 07 05:23:13 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206164 kb
Host smart-5ccfb445-a83d-4c2a-b953-32f73bc98e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79130
8992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.791308992
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.4256978905
Short name T2113
Test name
Test status
Simulation time 231098429 ps
CPU time 0.94 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206164 kb
Host smart-9654a917-15eb-4e42-90a9-54ee647dece3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42569
78905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4256978905
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.4227403175
Short name T1438
Test name
Test status
Simulation time 156420244 ps
CPU time 0.79 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:19 PM PDT 24
Peak memory 206212 kb
Host smart-0710c317-ada7-4677-87ec-4615e521ae41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
03175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.4227403175
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2123990996
Short name T84
Test name
Test status
Simulation time 148309268 ps
CPU time 0.82 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206208 kb
Host smart-8a390955-7792-4752-b930-bd7829083c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21239
90996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2123990996
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1504008582
Short name T940
Test name
Test status
Simulation time 243484743 ps
CPU time 0.96 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206160 kb
Host smart-558fb24d-c043-462f-a824-7e7afca317c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1504008582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1504008582
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2072630221
Short name T1134
Test name
Test status
Simulation time 140332671 ps
CPU time 0.84 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206120 kb
Host smart-4b544d22-0b5a-4b6f-bda1-6318b5d1540d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726
30221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2072630221
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.589678130
Short name T32
Test name
Test status
Simulation time 47112812 ps
CPU time 0.7 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206096 kb
Host smart-11f1db0d-83b7-4bf1-82fc-da75d99d1bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58967
8130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.589678130
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3093518058
Short name T865
Test name
Test status
Simulation time 19002897442 ps
CPU time 39.13 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206496 kb
Host smart-09f94a9c-891e-43d0-86d4-bfb59db18c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30935
18058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3093518058
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3743237371
Short name T804
Test name
Test status
Simulation time 210547004 ps
CPU time 0.85 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206128 kb
Host smart-44445079-f4b1-4083-8be8-e346979862d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37432
37371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3743237371
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1656974064
Short name T567
Test name
Test status
Simulation time 248126505 ps
CPU time 0.96 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206204 kb
Host smart-c552567f-1dcf-4653-b6ef-73184188b253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16569
74064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1656974064
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2775103172
Short name T606
Test name
Test status
Simulation time 224098030 ps
CPU time 0.9 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206188 kb
Host smart-f7612cc2-5f87-4c58-b729-d64b4a21dd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27751
03172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2775103172
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.261581023
Short name T490
Test name
Test status
Simulation time 160274899 ps
CPU time 0.92 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206188 kb
Host smart-0e17c17c-c327-4de9-a0c3-ae7b3299630c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26158
1023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.261581023
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.467829854
Short name T1313
Test name
Test status
Simulation time 249256661 ps
CPU time 0.88 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206120 kb
Host smart-b32e04d5-5f3e-4392-99e3-36c5ad1bc4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46782
9854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.467829854
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2779589638
Short name T2368
Test name
Test status
Simulation time 155636400 ps
CPU time 0.78 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206164 kb
Host smart-50f07329-a11f-4613-aec7-c568d7857682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27795
89638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2779589638
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.468463789
Short name T793
Test name
Test status
Simulation time 150107917 ps
CPU time 0.79 seconds
Started Jul 07 05:23:12 PM PDT 24
Finished Jul 07 05:23:13 PM PDT 24
Peak memory 206200 kb
Host smart-ba64bbc8-134d-4910-b6e4-d6587f3a319e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46846
3789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.468463789
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4177519512
Short name T1788
Test name
Test status
Simulation time 261159094 ps
CPU time 1.09 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206116 kb
Host smart-2e2ed686-c2f7-4145-b799-481c98268dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41775
19512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4177519512
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3499493633
Short name T487
Test name
Test status
Simulation time 5002330765 ps
CPU time 47.77 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 206476 kb
Host smart-16313f08-1ce2-4152-a3a8-5d3a4c272d3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3499493633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3499493633
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3454644650
Short name T2478
Test name
Test status
Simulation time 180297555 ps
CPU time 0.88 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206200 kb
Host smart-fa46caae-dbf4-4c0a-b362-eed37067d185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34546
44650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3454644650
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.4104723472
Short name T1864
Test name
Test status
Simulation time 149945580 ps
CPU time 0.77 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206128 kb
Host smart-1529af1f-146c-4bc8-9d19-40827aaa1a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41047
23472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.4104723472
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1364389777
Short name T1505
Test name
Test status
Simulation time 1379385113 ps
CPU time 2.88 seconds
Started Jul 07 05:23:12 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206396 kb
Host smart-5c146d1b-5ba6-4561-b535-8aee19439b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13643
89777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1364389777
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2419404238
Short name T768
Test name
Test status
Simulation time 7593628028 ps
CPU time 215.35 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:26:50 PM PDT 24
Peak memory 206288 kb
Host smart-6bdd97b2-a231-4b42-ab76-238a7dac4f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
04238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2419404238
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.325104040
Short name T975
Test name
Test status
Simulation time 75035162 ps
CPU time 0.73 seconds
Started Jul 07 05:23:25 PM PDT 24
Finished Jul 07 05:23:26 PM PDT 24
Peak memory 206216 kb
Host smart-59139ae6-bcae-4bf6-872e-e10ca7f78d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=325104040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.325104040
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3398496770
Short name T827
Test name
Test status
Simulation time 4199784026 ps
CPU time 5.02 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206220 kb
Host smart-45e76e07-5780-4df6-84cb-be6cd2634011
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3398496770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3398496770
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3602075686
Short name T1482
Test name
Test status
Simulation time 13344903328 ps
CPU time 12.29 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:26 PM PDT 24
Peak memory 206344 kb
Host smart-65600a74-c020-4f22-ab6e-d19520f08316
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3602075686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3602075686
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2450945989
Short name T1975
Test name
Test status
Simulation time 23504124116 ps
CPU time 21.99 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:39 PM PDT 24
Peak memory 206472 kb
Host smart-272960c9-49a0-4a1d-816f-2db33f9a5eda
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2450945989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2450945989
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3700295116
Short name T1839
Test name
Test status
Simulation time 196239502 ps
CPU time 0.89 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206116 kb
Host smart-c762b167-870a-446a-a3de-69b95e8837d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37002
95116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3700295116
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4109544488
Short name T2305
Test name
Test status
Simulation time 145630064 ps
CPU time 0.76 seconds
Started Jul 07 05:23:14 PM PDT 24
Finished Jul 07 05:23:16 PM PDT 24
Peak memory 206188 kb
Host smart-308d8e04-e9e0-4044-9b5d-7b9734c6deac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095
44488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4109544488
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3053661551
Short name T2147
Test name
Test status
Simulation time 233385324 ps
CPU time 0.92 seconds
Started Jul 07 05:23:13 PM PDT 24
Finished Jul 07 05:23:14 PM PDT 24
Peak memory 206116 kb
Host smart-6ce7d058-bd31-4c21-b899-cb9d925c51bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30536
61551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3053661551
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_device_address.927203090
Short name T908
Test name
Test status
Simulation time 9620296919 ps
CPU time 18.37 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206500 kb
Host smart-f05dd01e-1c1c-4d54-8b13-4d78b226d82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92720
3090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.927203090
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.709676996
Short name T2607
Test name
Test status
Simulation time 492902255 ps
CPU time 1.4 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206136 kb
Host smart-1bf01a2b-1a2f-4192-8bf4-a92987847982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70967
6996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.709676996
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3886363719
Short name T710
Test name
Test status
Simulation time 140573105 ps
CPU time 0.77 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206128 kb
Host smart-e04eceae-aef7-4ed9-8468-82cd8a2f579a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
63719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3886363719
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.180230021
Short name T472
Test name
Test status
Simulation time 32320668 ps
CPU time 0.72 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206112 kb
Host smart-721274b6-f8dc-4839-bb5d-37e98b69650e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18023
0021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.180230021
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2890184360
Short name T380
Test name
Test status
Simulation time 909162492 ps
CPU time 2.22 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206332 kb
Host smart-3bdaf6f7-0634-4924-a02a-295d86452bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
84360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2890184360
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1636257007
Short name T912
Test name
Test status
Simulation time 179388216 ps
CPU time 1.24 seconds
Started Jul 07 05:23:15 PM PDT 24
Finished Jul 07 05:23:17 PM PDT 24
Peak memory 206308 kb
Host smart-c1ba03fe-5f1d-4ee9-9415-084d29879925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16362
57007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1636257007
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2233497123
Short name T1392
Test name
Test status
Simulation time 229845950 ps
CPU time 0.89 seconds
Started Jul 07 05:23:21 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206112 kb
Host smart-46bacdb6-488e-40f5-b9b8-d2a87cfa1ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22334
97123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2233497123
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.200577101
Short name T2341
Test name
Test status
Simulation time 150854611 ps
CPU time 0.75 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206096 kb
Host smart-01d34966-fe9b-4a7b-bc92-83678c1c9776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
7101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.200577101
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.451380010
Short name T2423
Test name
Test status
Simulation time 164706026 ps
CPU time 0.8 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206080 kb
Host smart-9bb2dae0-0452-40bf-9793-e374d35a19ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45138
0010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.451380010
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1258213630
Short name T2262
Test name
Test status
Simulation time 200286287 ps
CPU time 0.9 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:19 PM PDT 24
Peak memory 206204 kb
Host smart-f4379a8a-2222-4b84-83d4-a5b596c3284b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
13630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1258213630
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.2393108285
Short name T772
Test name
Test status
Simulation time 23266939924 ps
CPU time 22.08 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:41 PM PDT 24
Peak memory 206128 kb
Host smart-6e3e3877-71b8-4a3c-a0a9-c626a62bfd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
08285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.2393108285
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1626266646
Short name T1499
Test name
Test status
Simulation time 3323835926 ps
CPU time 3.89 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206216 kb
Host smart-c805dc46-81c9-4973-8618-d7ed5eccdb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16262
66646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1626266646
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.173174793
Short name T1850
Test name
Test status
Simulation time 10485813389 ps
CPU time 103.54 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 206796 kb
Host smart-58db9f83-ffbd-4e0b-8a76-1e9fee3c9e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17317
4793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.173174793
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.339702886
Short name T2057
Test name
Test status
Simulation time 6384348147 ps
CPU time 176.24 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206360 kb
Host smart-7790ebc7-faa9-4dce-a393-1477b257908e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=339702886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.339702886
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3883471742
Short name T1369
Test name
Test status
Simulation time 241487006 ps
CPU time 0.93 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206144 kb
Host smart-889a8d66-b03e-434e-b6ba-1d748350f3e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3883471742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3883471742
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2502402895
Short name T272
Test name
Test status
Simulation time 196935141 ps
CPU time 0.88 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206140 kb
Host smart-7c640f93-df1e-4d39-8ee6-867f09ade29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25024
02895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2502402895
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3254426874
Short name T1458
Test name
Test status
Simulation time 4771919165 ps
CPU time 136.92 seconds
Started Jul 07 05:23:21 PM PDT 24
Finished Jul 07 05:25:38 PM PDT 24
Peak memory 206460 kb
Host smart-586f30a2-86ef-4cfe-8fb9-41d2333551da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32544
26874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3254426874
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3173690236
Short name T1174
Test name
Test status
Simulation time 5151567733 ps
CPU time 39.01 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206460 kb
Host smart-eb0ebe31-79d4-4dfa-9f43-bb280b417a66
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3173690236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3173690236
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3064028204
Short name T3
Test name
Test status
Simulation time 178322802 ps
CPU time 0.81 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206164 kb
Host smart-cfddc72d-ff17-4ab2-86e4-48d7130b8f9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3064028204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3064028204
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2522478591
Short name T2361
Test name
Test status
Simulation time 162677937 ps
CPU time 0.82 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206120 kb
Host smart-10572f8d-cde2-45bc-86eb-53a17074f2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224
78591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2522478591
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3541675187
Short name T137
Test name
Test status
Simulation time 271995615 ps
CPU time 0.97 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206184 kb
Host smart-71e94bd5-fcc7-4ec9-9870-6689f3942343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35416
75187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3541675187
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3212538173
Short name T2710
Test name
Test status
Simulation time 194608483 ps
CPU time 0.93 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206176 kb
Host smart-a733aaff-d161-43c4-86be-48297c097164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
38173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3212538173
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.470805177
Short name T392
Test name
Test status
Simulation time 165705117 ps
CPU time 0.87 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 205896 kb
Host smart-a6086621-f926-432c-ad62-aed584b6814e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47080
5177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.470805177
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3454843572
Short name T943
Test name
Test status
Simulation time 152349490 ps
CPU time 0.77 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206188 kb
Host smart-ea7fe986-d912-435a-b03f-90f67c76665e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34548
43572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3454843572
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2117884476
Short name T1410
Test name
Test status
Simulation time 163812123 ps
CPU time 0.76 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206196 kb
Host smart-91217d19-d785-4ca8-992e-249347a4cc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
84476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2117884476
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.957239101
Short name T166
Test name
Test status
Simulation time 198117183 ps
CPU time 0.91 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 206020 kb
Host smart-290b3f5b-f982-483f-8515-f0905c626f92
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=957239101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.957239101
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.4158098892
Short name T22
Test name
Test status
Simulation time 212815117 ps
CPU time 0.89 seconds
Started Jul 07 05:23:21 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206188 kb
Host smart-6d01f5be-6074-4630-8132-e3a7fdd3382b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41580
98892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.4158098892
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2391736005
Short name T1330
Test name
Test status
Simulation time 31537606 ps
CPU time 0.69 seconds
Started Jul 07 05:23:21 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206192 kb
Host smart-337c347f-13f1-48f3-a407-736ab5564bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23917
36005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2391736005
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.7021338
Short name T1730
Test name
Test status
Simulation time 9011223202 ps
CPU time 18.7 seconds
Started Jul 07 05:23:20 PM PDT 24
Finished Jul 07 05:23:39 PM PDT 24
Peak memory 206540 kb
Host smart-555f34f9-4f64-44d0-8d74-2cf082c54018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70213
38 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.7021338
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3418798460
Short name T351
Test name
Test status
Simulation time 181430202 ps
CPU time 0.88 seconds
Started Jul 07 05:23:17 PM PDT 24
Finished Jul 07 05:23:19 PM PDT 24
Peak memory 206196 kb
Host smart-5cf913d3-3698-4ccb-8dee-73989cbcaecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
98460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3418798460
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3530306525
Short name T2490
Test name
Test status
Simulation time 191310839 ps
CPU time 0.83 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:23 PM PDT 24
Peak memory 206180 kb
Host smart-958c349d-31d4-4ef2-92f3-ccbae84a82db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
06525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3530306525
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3371309282
Short name T858
Test name
Test status
Simulation time 203864843 ps
CPU time 0.95 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206196 kb
Host smart-938e03bb-dc5d-4f61-ac61-d00b1717015d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
09282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3371309282
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3596777236
Short name T415
Test name
Test status
Simulation time 175573427 ps
CPU time 0.83 seconds
Started Jul 07 05:23:19 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206044 kb
Host smart-a80a35a9-8b12-46f3-a018-995a863bcbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35967
77236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3596777236
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3484865859
Short name T2651
Test name
Test status
Simulation time 225847343 ps
CPU time 0.86 seconds
Started Jul 07 05:23:18 PM PDT 24
Finished Jul 07 05:23:20 PM PDT 24
Peak memory 206204 kb
Host smart-621877c8-1f3f-4237-b7db-6a782e39d5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848
65859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3484865859
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2634765916
Short name T354
Test name
Test status
Simulation time 149593928 ps
CPU time 0.75 seconds
Started Jul 07 05:23:16 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 206196 kb
Host smart-c7b2961b-d368-46fa-898d-64a8425ad7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26347
65916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2634765916
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.4002715779
Short name T2661
Test name
Test status
Simulation time 153103255 ps
CPU time 0.76 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:23 PM PDT 24
Peak memory 206180 kb
Host smart-126fd189-2f93-4dbb-86eb-8d3c8b9cb25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40027
15779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.4002715779
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3436859910
Short name T2442
Test name
Test status
Simulation time 231544355 ps
CPU time 0.95 seconds
Started Jul 07 05:23:21 PM PDT 24
Finished Jul 07 05:23:22 PM PDT 24
Peak memory 206116 kb
Host smart-c01dc15f-0579-4939-90b9-ad0e32590370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34368
59910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3436859910
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.605712806
Short name T2011
Test name
Test status
Simulation time 4613287292 ps
CPU time 121.4 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206432 kb
Host smart-22932ae7-5e9e-4ebe-8856-8d1d15866493
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=605712806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.605712806
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.310561439
Short name T387
Test name
Test status
Simulation time 157946422 ps
CPU time 0.83 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206116 kb
Host smart-ea88ab0e-c6ba-4c0d-8a25-719b443e256b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31056
1439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.310561439
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3992724933
Short name T2497
Test name
Test status
Simulation time 174931936 ps
CPU time 0.89 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:23 PM PDT 24
Peak memory 206192 kb
Host smart-34a7d687-be90-4cf8-a6d0-ff4e3f8a3115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
24933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3992724933
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3431173560
Short name T18
Test name
Test status
Simulation time 708956537 ps
CPU time 1.68 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206304 kb
Host smart-ff3a1c08-04c8-465b-be69-621313773b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
73560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3431173560
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.157720832
Short name T1579
Test name
Test status
Simulation time 5160480364 ps
CPU time 36.3 seconds
Started Jul 07 05:23:23 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206500 kb
Host smart-4f70afe2-e928-4ada-b846-435e88c7982c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772
0832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.157720832
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.3659259359
Short name T1000
Test name
Test status
Simulation time 64929840 ps
CPU time 0.75 seconds
Started Jul 07 05:23:38 PM PDT 24
Finished Jul 07 05:23:38 PM PDT 24
Peak memory 206228 kb
Host smart-23398380-cfcd-447f-b707-863198c02fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3659259359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.3659259359
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.4027199837
Short name T904
Test name
Test status
Simulation time 3583396494 ps
CPU time 4.24 seconds
Started Jul 07 05:23:24 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206452 kb
Host smart-2f0a7f1a-3e3e-464f-a388-27d2ad6f5cd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4027199837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.4027199837
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.865338164
Short name T219
Test name
Test status
Simulation time 13338624846 ps
CPU time 13.73 seconds
Started Jul 07 05:23:21 PM PDT 24
Finished Jul 07 05:23:35 PM PDT 24
Peak memory 206112 kb
Host smart-9473a94e-e405-4660-b761-ee188979ce46
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=865338164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.865338164
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.373430042
Short name T2189
Test name
Test status
Simulation time 23341304006 ps
CPU time 21.44 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206388 kb
Host smart-19e9e2b0-e17d-4741-9b20-eb22b1cfa575
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=373430042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.373430042
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1622344808
Short name T2499
Test name
Test status
Simulation time 165560563 ps
CPU time 0.8 seconds
Started Jul 07 05:23:23 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206084 kb
Host smart-050dab72-98d9-4d96-9c7f-a1c77cefc69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16223
44808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1622344808
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3179160312
Short name T755
Test name
Test status
Simulation time 169705855 ps
CPU time 0.81 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206104 kb
Host smart-e3ce3208-fa6c-4bb8-9369-65f75b5d4377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31791
60312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3179160312
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2992829630
Short name T1184
Test name
Test status
Simulation time 251068739 ps
CPU time 0.96 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206216 kb
Host smart-1673fd34-4b9e-4be1-adb4-cc0d500b871e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29928
29630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2992829630
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1447041120
Short name T2299
Test name
Test status
Simulation time 740147425 ps
CPU time 1.93 seconds
Started Jul 07 05:23:25 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206456 kb
Host smart-426a30b2-9db8-4b83-9305-e95ec146a850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
41120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1447041120
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2540075468
Short name T2058
Test name
Test status
Simulation time 14557814364 ps
CPU time 28.12 seconds
Started Jul 07 05:23:24 PM PDT 24
Finished Jul 07 05:23:53 PM PDT 24
Peak memory 206512 kb
Host smart-53754999-e380-4822-b5b8-bd83ce3b8683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25400
75468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2540075468
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3510547250
Short name T1517
Test name
Test status
Simulation time 325469057 ps
CPU time 1.21 seconds
Started Jul 07 05:23:24 PM PDT 24
Finished Jul 07 05:23:26 PM PDT 24
Peak memory 206188 kb
Host smart-d3786bb6-a5cf-4243-97f7-d562c6a43314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35105
47250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3510547250
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1200008894
Short name T502
Test name
Test status
Simulation time 140023002 ps
CPU time 0.77 seconds
Started Jul 07 05:23:23 PM PDT 24
Finished Jul 07 05:23:25 PM PDT 24
Peak memory 206144 kb
Host smart-694e7566-fbf7-433b-a4f0-8a4151ca1c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
08894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1200008894
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1999606776
Short name T757
Test name
Test status
Simulation time 59303444 ps
CPU time 0.68 seconds
Started Jul 07 05:23:24 PM PDT 24
Finished Jul 07 05:23:25 PM PDT 24
Peak memory 206220 kb
Host smart-14cf0eb7-6b80-4592-8202-6522262cb1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19996
06776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1999606776
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1618344863
Short name T1435
Test name
Test status
Simulation time 902360553 ps
CPU time 2.11 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:25 PM PDT 24
Peak memory 206448 kb
Host smart-1d8f82c3-4627-4fc1-b7e4-816064263374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16183
44863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1618344863
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.882133537
Short name T1821
Test name
Test status
Simulation time 349526066 ps
CPU time 2.5 seconds
Started Jul 07 05:23:24 PM PDT 24
Finished Jul 07 05:23:27 PM PDT 24
Peak memory 206272 kb
Host smart-cd57d02a-24e2-4f92-8ba4-b17476dcec77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88213
3537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.882133537
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2341340846
Short name T527
Test name
Test status
Simulation time 221337433 ps
CPU time 0.92 seconds
Started Jul 07 05:23:22 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 206116 kb
Host smart-3aca057a-a38c-4c45-88aa-6b20e4d0cec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
40846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2341340846
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2468892560
Short name T2452
Test name
Test status
Simulation time 148048567 ps
CPU time 0.75 seconds
Started Jul 07 05:23:24 PM PDT 24
Finished Jul 07 05:23:25 PM PDT 24
Peak memory 206192 kb
Host smart-43b536a4-a66f-426d-aa30-a6edd5ea5906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24688
92560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2468892560
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3132705965
Short name T1084
Test name
Test status
Simulation time 206219695 ps
CPU time 0.88 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206148 kb
Host smart-e0f125f8-b41f-4a83-bb8c-8c66ccf98a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327
05965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3132705965
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.2320978995
Short name T2652
Test name
Test status
Simulation time 7840662253 ps
CPU time 217.48 seconds
Started Jul 07 05:23:23 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 206452 kb
Host smart-5ad34589-3660-44ad-a82c-5679316d21b6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2320978995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.2320978995
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.278124790
Short name T2333
Test name
Test status
Simulation time 233479414 ps
CPU time 0.94 seconds
Started Jul 07 05:23:31 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206164 kb
Host smart-1943d64e-b981-4844-8bdc-a29155f35c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812
4790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.278124790
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1702931523
Short name T688
Test name
Test status
Simulation time 23330844935 ps
CPU time 23.26 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:51 PM PDT 24
Peak memory 206172 kb
Host smart-9b49c65c-c9bf-4c93-9033-1aa9c73a5945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17029
31523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1702931523
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.4027982405
Short name T406
Test name
Test status
Simulation time 3273102680 ps
CPU time 4.17 seconds
Started Jul 07 05:23:29 PM PDT 24
Finished Jul 07 05:23:33 PM PDT 24
Peak memory 206264 kb
Host smart-ef9498e6-efb5-49a9-b833-c2f48f84860b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
82405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.4027982405
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.182279438
Short name T2510
Test name
Test status
Simulation time 5435859818 ps
CPU time 149.03 seconds
Started Jul 07 05:23:27 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 206428 kb
Host smart-87d2f794-69ad-45a0-9628-194a25d47974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18227
9438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.182279438
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1001110932
Short name T250
Test name
Test status
Simulation time 4153797706 ps
CPU time 40.97 seconds
Started Jul 07 05:23:25 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 206356 kb
Host smart-dc57ad0c-2a82-4068-912f-aff2df61c02a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1001110932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1001110932
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3382078778
Short name T754
Test name
Test status
Simulation time 238605429 ps
CPU time 0.91 seconds
Started Jul 07 05:23:31 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206144 kb
Host smart-85635c9a-8296-48fe-83fb-4cfdc1f39091
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3382078778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3382078778
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2143103185
Short name T373
Test name
Test status
Simulation time 207690636 ps
CPU time 0.9 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206116 kb
Host smart-a60fbd40-b10c-47a5-91cb-4105a8a7ec95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21431
03185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2143103185
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.332009181
Short name T399
Test name
Test status
Simulation time 4842253740 ps
CPU time 35.84 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206484 kb
Host smart-caa80467-199e-4929-80f2-09bddb7b06cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33200
9181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.332009181
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.586516233
Short name T2174
Test name
Test status
Simulation time 6731635250 ps
CPU time 60.95 seconds
Started Jul 07 05:23:27 PM PDT 24
Finished Jul 07 05:24:29 PM PDT 24
Peak memory 206324 kb
Host smart-fa465a8d-5f5f-4c1d-9f75-a92fdd6cca5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=586516233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.586516233
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4164358175
Short name T421
Test name
Test status
Simulation time 199906060 ps
CPU time 0.84 seconds
Started Jul 07 05:23:27 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206160 kb
Host smart-f325ef1d-ce1a-4ae8-8de7-50ec199ab4b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4164358175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4164358175
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1163298270
Short name T2069
Test name
Test status
Simulation time 157744415 ps
CPU time 0.77 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206104 kb
Host smart-9a0b91ca-7dcc-431e-87f4-ebb1a5ec085f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11632
98270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1163298270
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1295004967
Short name T143
Test name
Test status
Simulation time 197302978 ps
CPU time 0.84 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:27 PM PDT 24
Peak memory 206432 kb
Host smart-c4c6bd05-1c16-47dd-b39f-9c36d04e2112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
04967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1295004967
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4123678817
Short name T2542
Test name
Test status
Simulation time 155490925 ps
CPU time 0.76 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206128 kb
Host smart-e77cebd6-ceea-41d9-93e5-ef1e37496f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
78817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4123678817
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3348506585
Short name T748
Test name
Test status
Simulation time 216737646 ps
CPU time 0.77 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:27 PM PDT 24
Peak memory 206116 kb
Host smart-56f3ae5a-3526-4275-bc2b-268dc7516a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33485
06585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3348506585
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1080821540
Short name T2124
Test name
Test status
Simulation time 170307687 ps
CPU time 0.79 seconds
Started Jul 07 05:23:25 PM PDT 24
Finished Jul 07 05:23:26 PM PDT 24
Peak memory 206152 kb
Host smart-1befc12c-7350-45c0-9014-a27e6348af11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
21540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1080821540
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1876968737
Short name T905
Test name
Test status
Simulation time 164454265 ps
CPU time 0.75 seconds
Started Jul 07 05:23:30 PM PDT 24
Finished Jul 07 05:23:31 PM PDT 24
Peak memory 206188 kb
Host smart-db196ada-4e90-49d5-b4e9-fe0a49b57d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769
68737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1876968737
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.4033820590
Short name T2264
Test name
Test status
Simulation time 226179296 ps
CPU time 0.92 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206116 kb
Host smart-18f8c66f-99e4-4f7a-98a8-5e6c3e173ffc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4033820590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.4033820590
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.572638526
Short name T2095
Test name
Test status
Simulation time 165171011 ps
CPU time 0.82 seconds
Started Jul 07 05:23:31 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206140 kb
Host smart-1bf418cc-bec6-4a75-9e4f-ab18a1465f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57263
8526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.572638526
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.885116834
Short name T1577
Test name
Test status
Simulation time 72302684 ps
CPU time 0.68 seconds
Started Jul 07 05:23:27 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206100 kb
Host smart-61574b5d-0026-419f-a531-35ed9013b865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88511
6834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.885116834
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2187967927
Short name T1881
Test name
Test status
Simulation time 18495684181 ps
CPU time 37.63 seconds
Started Jul 07 05:23:30 PM PDT 24
Finished Jul 07 05:24:07 PM PDT 24
Peak memory 206516 kb
Host smart-17deff5e-1d49-455e-a69d-97aa3e4e7d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21879
67927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2187967927
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3059265885
Short name T1355
Test name
Test status
Simulation time 169610419 ps
CPU time 0.82 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206112 kb
Host smart-5fce6563-4a44-4773-aef2-276a012f29ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30592
65885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3059265885
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2421120716
Short name T1741
Test name
Test status
Simulation time 195668229 ps
CPU time 0.93 seconds
Started Jul 07 05:23:26 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206184 kb
Host smart-9d4f1d76-40dc-4b81-a136-fc8240dddc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
20716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2421120716
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1044107469
Short name T1112
Test name
Test status
Simulation time 175725765 ps
CPU time 0.86 seconds
Started Jul 07 05:23:29 PM PDT 24
Finished Jul 07 05:23:30 PM PDT 24
Peak memory 206116 kb
Host smart-1721629d-e876-4729-b0f5-60a47d3d0c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10441
07469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1044107469
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4046689731
Short name T761
Test name
Test status
Simulation time 188106359 ps
CPU time 0.95 seconds
Started Jul 07 05:23:31 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206208 kb
Host smart-8226efbd-1c96-4cc6-8812-d796fb3bd50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40466
89731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4046689731
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.906180805
Short name T2194
Test name
Test status
Simulation time 148747198 ps
CPU time 0.79 seconds
Started Jul 07 05:23:28 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 206188 kb
Host smart-62823944-dba5-49be-a4e9-c489067a606b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90618
0805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.906180805
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3003160571
Short name T2477
Test name
Test status
Simulation time 148732822 ps
CPU time 0.82 seconds
Started Jul 07 05:23:30 PM PDT 24
Finished Jul 07 05:23:31 PM PDT 24
Peak memory 206196 kb
Host smart-a09ae1b9-c942-4da8-acfa-adb81094a443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30031
60571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3003160571
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.281539995
Short name T479
Test name
Test status
Simulation time 187217342 ps
CPU time 0.79 seconds
Started Jul 07 05:23:25 PM PDT 24
Finished Jul 07 05:23:26 PM PDT 24
Peak memory 206200 kb
Host smart-f3fa91b5-069c-4709-83fc-bed087148d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28153
9995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.281539995
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1018032006
Short name T1919
Test name
Test status
Simulation time 241490553 ps
CPU time 0.97 seconds
Started Jul 07 05:23:27 PM PDT 24
Finished Jul 07 05:23:28 PM PDT 24
Peak memory 206100 kb
Host smart-3a1358c6-7cf2-4213-bec0-ab885dfe96e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
32006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1018032006
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.13613698
Short name T275
Test name
Test status
Simulation time 4053350796 ps
CPU time 114.89 seconds
Started Jul 07 05:23:32 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206448 kb
Host smart-6a306e8e-2efb-420b-b724-39b00ecf267e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=13613698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.13613698
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2865366781
Short name T1350
Test name
Test status
Simulation time 166408163 ps
CPU time 0.8 seconds
Started Jul 07 05:23:31 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206036 kb
Host smart-0e425a94-64cc-4a73-8583-ef87c0e8967a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28653
66781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2865366781
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.4200013565
Short name T1699
Test name
Test status
Simulation time 257851480 ps
CPU time 1.01 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206192 kb
Host smart-fc9f1d85-a626-4bae-bd52-b3b9c4dd4db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42000
13565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.4200013565
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1812566173
Short name T464
Test name
Test status
Simulation time 505434887 ps
CPU time 1.38 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206156 kb
Host smart-69673e17-7e40-4458-8b66-14ac6b8b4e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18125
66173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1812566173
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2422913236
Short name T884
Test name
Test status
Simulation time 6391838012 ps
CPU time 43.69 seconds
Started Jul 07 05:23:33 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206444 kb
Host smart-16759e11-817e-4228-99b2-6668c3e73c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
13236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2422913236
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2968179139
Short name T613
Test name
Test status
Simulation time 38626657 ps
CPU time 0.68 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206120 kb
Host smart-d610d318-4dac-4588-ac71-9bee8f4bb0aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2968179139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2968179139
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4075351213
Short name T2270
Test name
Test status
Simulation time 3785375858 ps
CPU time 4.51 seconds
Started Jul 07 05:23:36 PM PDT 24
Finished Jul 07 05:23:41 PM PDT 24
Peak memory 206240 kb
Host smart-3147e146-2aa1-4e3d-8f09-d16683d9f106
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4075351213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.4075351213
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1995029767
Short name T2204
Test name
Test status
Simulation time 13305669238 ps
CPU time 12.7 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:23:54 PM PDT 24
Peak memory 206200 kb
Host smart-f483fcc9-bd4f-444c-9b00-31b181d4a49c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1995029767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1995029767
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3822957503
Short name T2455
Test name
Test status
Simulation time 23346893774 ps
CPU time 21.91 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206352 kb
Host smart-fe779afe-35e4-416b-b48a-d93032aba652
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3822957503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3822957503
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.4130027519
Short name T576
Test name
Test status
Simulation time 217480883 ps
CPU time 0.83 seconds
Started Jul 07 05:23:34 PM PDT 24
Finished Jul 07 05:23:35 PM PDT 24
Peak memory 206184 kb
Host smart-1f3ae370-03a5-419b-b840-2119a20c63aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41300
27519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.4130027519
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2627065195
Short name T2001
Test name
Test status
Simulation time 206386635 ps
CPU time 0.84 seconds
Started Jul 07 05:23:39 PM PDT 24
Finished Jul 07 05:23:40 PM PDT 24
Peak memory 206188 kb
Host smart-a846ec10-192d-4171-9fe2-46089589eadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26270
65195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2627065195
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3068141837
Short name T1831
Test name
Test status
Simulation time 384973543 ps
CPU time 1.27 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:37 PM PDT 24
Peak memory 206068 kb
Host smart-08053305-348f-4526-8828-4a7c1d4fb3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
41837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3068141837
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.980622439
Short name T1571
Test name
Test status
Simulation time 1100131112 ps
CPU time 2.57 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206416 kb
Host smart-e1d6e61c-5768-4f9d-a1e5-6c0400dc517e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98062
2439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.980622439
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2822928977
Short name T617
Test name
Test status
Simulation time 364406766 ps
CPU time 1.22 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206188 kb
Host smart-be25a6b0-bc61-44d5-9711-aef65e175a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28229
28977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2822928977
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.4101969687
Short name T532
Test name
Test status
Simulation time 185520016 ps
CPU time 0.79 seconds
Started Jul 07 05:23:32 PM PDT 24
Finished Jul 07 05:23:33 PM PDT 24
Peak memory 206188 kb
Host smart-305e0cfc-36ff-4ee8-8a3d-0259c3a015b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41019
69687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4101969687
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1465106017
Short name T1694
Test name
Test status
Simulation time 36199288 ps
CPU time 0.66 seconds
Started Jul 07 05:23:31 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206188 kb
Host smart-6936a4ac-bf5e-4187-bd65-70544d9b5173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
06017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1465106017
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1613496399
Short name T2258
Test name
Test status
Simulation time 988221658 ps
CPU time 2.02 seconds
Started Jul 07 05:23:30 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206468 kb
Host smart-ce695168-872f-4767-903a-78380d1b1594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16134
96399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1613496399
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2660692048
Short name T2639
Test name
Test status
Simulation time 231005678 ps
CPU time 1.78 seconds
Started Jul 07 05:23:30 PM PDT 24
Finished Jul 07 05:23:32 PM PDT 24
Peak memory 206688 kb
Host smart-f0331d2a-188c-4ba1-9e6c-47da583c4867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26606
92048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2660692048
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.857686776
Short name T2406
Test name
Test status
Simulation time 193118209 ps
CPU time 0.89 seconds
Started Jul 07 05:23:30 PM PDT 24
Finished Jul 07 05:23:31 PM PDT 24
Peak memory 206196 kb
Host smart-31f17296-d93d-4683-8422-94011dfc7b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85768
6776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.857686776
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1621233429
Short name T1558
Test name
Test status
Simulation time 150671210 ps
CPU time 0.8 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206180 kb
Host smart-0b46860d-6e36-40af-a386-d6272b5fd54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16212
33429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1621233429
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1139786915
Short name T1281
Test name
Test status
Simulation time 200411218 ps
CPU time 0.91 seconds
Started Jul 07 05:23:37 PM PDT 24
Finished Jul 07 05:23:38 PM PDT 24
Peak memory 206032 kb
Host smart-7dc9a2ed-c82b-4de2-9241-cc49ad6b8bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
86915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1139786915
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1299952256
Short name T1982
Test name
Test status
Simulation time 8522737547 ps
CPU time 245.3 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:27:47 PM PDT 24
Peak memory 206488 kb
Host smart-89fb61be-f00d-4f9e-bc0d-ad07c4b6fbaf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1299952256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1299952256
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1705955850
Short name T2433
Test name
Test status
Simulation time 167311740 ps
CPU time 0.82 seconds
Started Jul 07 05:23:29 PM PDT 24
Finished Jul 07 05:23:30 PM PDT 24
Peak memory 206132 kb
Host smart-ec41b663-3b1a-4b80-b4fb-f6b0827e9737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17059
55850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1705955850
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.1569901823
Short name T630
Test name
Test status
Simulation time 23368794057 ps
CPU time 27.31 seconds
Started Jul 07 05:23:34 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206256 kb
Host smart-7be7bb5f-a9ac-48ef-b6b6-325948971931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15699
01823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1569901823
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1283308242
Short name T716
Test name
Test status
Simulation time 3341249287 ps
CPU time 4.03 seconds
Started Jul 07 05:23:32 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206260 kb
Host smart-f792965b-13b4-4ade-894a-32a02e610360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
08242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1283308242
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2126019189
Short name T1022
Test name
Test status
Simulation time 2722811822 ps
CPU time 74.79 seconds
Started Jul 07 05:23:50 PM PDT 24
Finished Jul 07 05:25:05 PM PDT 24
Peak memory 206424 kb
Host smart-81022262-7a78-4ad7-911b-e451a5297c8d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2126019189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2126019189
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3213826129
Short name T1693
Test name
Test status
Simulation time 239779377 ps
CPU time 0.93 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206176 kb
Host smart-e664a9cd-c82d-4eef-ad0a-a6c8b7a76467
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3213826129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3213826129
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1189697523
Short name T1133
Test name
Test status
Simulation time 220099598 ps
CPU time 0.89 seconds
Started Jul 07 05:23:35 PM PDT 24
Finished Jul 07 05:23:36 PM PDT 24
Peak memory 206188 kb
Host smart-f61f3a0f-366d-4ce6-ad81-2bb8f1a3c50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11896
97523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1189697523
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1277794070
Short name T1784
Test name
Test status
Simulation time 3630222575 ps
CPU time 99.62 seconds
Started Jul 07 05:23:47 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206428 kb
Host smart-bbface8b-8851-4fc0-bd6f-91f063705b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12777
94070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1277794070
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.4103505532
Short name T426
Test name
Test status
Simulation time 4194813766 ps
CPU time 40.43 seconds
Started Jul 07 05:23:47 PM PDT 24
Finished Jul 07 05:24:28 PM PDT 24
Peak memory 206428 kb
Host smart-76528369-204c-4725-893f-f26fd0c102f9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4103505532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.4103505532
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3054684093
Short name T2415
Test name
Test status
Simulation time 162847594 ps
CPU time 0.82 seconds
Started Jul 07 05:23:39 PM PDT 24
Finished Jul 07 05:23:40 PM PDT 24
Peak memory 206148 kb
Host smart-39964cdd-5b41-4920-aaba-624a5155276b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3054684093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3054684093
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2624479827
Short name T1620
Test name
Test status
Simulation time 145686893 ps
CPU time 0.75 seconds
Started Jul 07 05:23:34 PM PDT 24
Finished Jul 07 05:23:35 PM PDT 24
Peak memory 206200 kb
Host smart-53cc5d4e-738f-49d6-b0d7-8a40d1e169e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26244
79827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2624479827
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2675839648
Short name T135
Test name
Test status
Simulation time 179246232 ps
CPU time 0.86 seconds
Started Jul 07 05:23:33 PM PDT 24
Finished Jul 07 05:23:34 PM PDT 24
Peak memory 206180 kb
Host smart-ab0b86bf-058b-46e8-9b1f-3315b5d36b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
39648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2675839648
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1773165341
Short name T1791
Test name
Test status
Simulation time 177191423 ps
CPU time 0.86 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206180 kb
Host smart-e5ca5096-80b2-452c-9d1f-a8e648bf9c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17731
65341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1773165341
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1335834100
Short name T2683
Test name
Test status
Simulation time 177282241 ps
CPU time 0.78 seconds
Started Jul 07 05:23:49 PM PDT 24
Finished Jul 07 05:23:50 PM PDT 24
Peak memory 206188 kb
Host smart-f3919d0e-eb89-43b8-ab38-9627a5d6fc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13358
34100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1335834100
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2859624824
Short name T2659
Test name
Test status
Simulation time 207390515 ps
CPU time 0.85 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206192 kb
Host smart-7052ac8d-4a3f-4310-8a43-eacbc0a3e2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28596
24824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2859624824
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.563652637
Short name T2632
Test name
Test status
Simulation time 151583999 ps
CPU time 0.83 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206164 kb
Host smart-c6f8c892-9a0a-485f-8c06-4a5a191e7ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56365
2637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.563652637
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.737872845
Short name T1892
Test name
Test status
Simulation time 217139039 ps
CPU time 0.94 seconds
Started Jul 07 05:23:40 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206172 kb
Host smart-7761136a-004d-4ee5-b47d-7622a8c2ee2c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=737872845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.737872845
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3070457933
Short name T2054
Test name
Test status
Simulation time 161223054 ps
CPU time 0.74 seconds
Started Jul 07 05:23:39 PM PDT 24
Finished Jul 07 05:23:40 PM PDT 24
Peak memory 206184 kb
Host smart-4865fd61-bf16-4b59-95f6-3b06ee025e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704
57933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3070457933
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2178460607
Short name T2075
Test name
Test status
Simulation time 37993321 ps
CPU time 0.73 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:23:46 PM PDT 24
Peak memory 206208 kb
Host smart-a79b9868-501b-4dae-aa9c-e6db62cd9d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784
60607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2178460607
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3156576615
Short name T2358
Test name
Test status
Simulation time 14124813545 ps
CPU time 31.49 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206408 kb
Host smart-d7e05eca-dbba-44f3-aec0-e9d22ef1e78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31565
76615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3156576615
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3297627550
Short name T1479
Test name
Test status
Simulation time 210434003 ps
CPU time 0.86 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206208 kb
Host smart-663fb1b1-8a59-412c-99c2-209a241096c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32976
27550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3297627550
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2963401768
Short name T1003
Test name
Test status
Simulation time 202859180 ps
CPU time 0.9 seconds
Started Jul 07 05:23:37 PM PDT 24
Finished Jul 07 05:23:38 PM PDT 24
Peak memory 206184 kb
Host smart-5b290b9f-60de-48fc-8b89-b4f2e65e3bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
01768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2963401768
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.416455828
Short name T1625
Test name
Test status
Simulation time 255325154 ps
CPU time 0.88 seconds
Started Jul 07 05:23:32 PM PDT 24
Finished Jul 07 05:23:33 PM PDT 24
Peak memory 206232 kb
Host smart-906fe31e-09d2-4ee3-96f4-a4bdd9f51f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645
5828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.416455828
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.606939230
Short name T983
Test name
Test status
Simulation time 213384568 ps
CPU time 0.91 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206164 kb
Host smart-f363cd4c-5154-4d28-a28c-1e0da28fd779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60693
9230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.606939230
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.753936676
Short name T1843
Test name
Test status
Simulation time 165655483 ps
CPU time 0.78 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206200 kb
Host smart-fe5a90b7-634f-4d51-9aac-0ce7da879096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75393
6676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.753936676
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3134324236
Short name T1756
Test name
Test status
Simulation time 149310242 ps
CPU time 0.78 seconds
Started Jul 07 05:23:44 PM PDT 24
Finished Jul 07 05:23:46 PM PDT 24
Peak memory 206028 kb
Host smart-03639aab-1171-4f6d-9c2e-dcf45c062660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
24236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3134324236
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.136617544
Short name T801
Test name
Test status
Simulation time 148210280 ps
CPU time 0.77 seconds
Started Jul 07 05:23:51 PM PDT 24
Finished Jul 07 05:23:52 PM PDT 24
Peak memory 206192 kb
Host smart-d1fc429c-aa15-4ec3-9a69-a19c15901b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13661
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.136617544
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.168794616
Short name T1804
Test name
Test status
Simulation time 262744321 ps
CPU time 0.95 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206148 kb
Host smart-1ce9addd-f336-45a8-8104-3d5b46ee60b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
4616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.168794616
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.378147175
Short name T700
Test name
Test status
Simulation time 4238644811 ps
CPU time 34.76 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206416 kb
Host smart-0b659c05-bec2-4039-9099-55888e214529
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=378147175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.378147175
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1441545852
Short name T1411
Test name
Test status
Simulation time 180817740 ps
CPU time 0.8 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206192 kb
Host smart-ec3ba517-4857-4fb4-96be-b32304363ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14415
45852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1441545852
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.630683999
Short name T921
Test name
Test status
Simulation time 175766477 ps
CPU time 0.8 seconds
Started Jul 07 05:23:39 PM PDT 24
Finished Jul 07 05:23:40 PM PDT 24
Peak memory 206140 kb
Host smart-94eeac79-3b65-4afe-a550-5c97f80e2159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63068
3999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.630683999
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.819564458
Short name T2692
Test name
Test status
Simulation time 990784528 ps
CPU time 2.28 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:51 PM PDT 24
Peak memory 206440 kb
Host smart-45ea7ec9-fb87-426d-bb59-05faf8a84b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81956
4458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.819564458
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2458702859
Short name T2170
Test name
Test status
Simulation time 4679473361 ps
CPU time 127.23 seconds
Started Jul 07 05:23:40 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206528 kb
Host smart-dab34bba-eca9-4eca-b0a6-c3759bd60365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587
02859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2458702859
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.2030048151
Short name T2420
Test name
Test status
Simulation time 73501025 ps
CPU time 0.71 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:06 PM PDT 24
Peak memory 206016 kb
Host smart-4be20952-952d-4351-a182-89d557e02e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2030048151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2030048151
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3035001115
Short name T1409
Test name
Test status
Simulation time 3815358108 ps
CPU time 4.34 seconds
Started Jul 07 05:23:51 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206224 kb
Host smart-f8667a4b-3a93-4bec-a94e-69822d58a674
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3035001115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3035001115
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.4186325855
Short name T996
Test name
Test status
Simulation time 13323518440 ps
CPU time 12.32 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206236 kb
Host smart-690d440f-3312-4320-a46f-d8f53063c0c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4186325855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.4186325855
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.416968080
Short name T2648
Test name
Test status
Simulation time 23348140862 ps
CPU time 22.96 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:24:09 PM PDT 24
Peak memory 206192 kb
Host smart-e67d590d-8b69-4723-9d3e-b3f2e3c8d545
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=416968080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.416968080
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3032638369
Short name T2015
Test name
Test status
Simulation time 148345421 ps
CPU time 0.83 seconds
Started Jul 07 05:23:40 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206204 kb
Host smart-e50881e4-507a-4cfd-93ec-e7e5b3015c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
38369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3032638369
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1304853165
Short name T822
Test name
Test status
Simulation time 153440261 ps
CPU time 0.8 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206208 kb
Host smart-b2d33cda-0417-4bf6-b91f-8878cf5b5586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
53165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1304853165
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3722898001
Short name T2450
Test name
Test status
Simulation time 170292851 ps
CPU time 0.86 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206120 kb
Host smart-8a4f0b18-9e7c-4d3b-8178-58d9a18187ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
98001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3722898001
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3640185464
Short name T181
Test name
Test status
Simulation time 999842788 ps
CPU time 2.1 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:51 PM PDT 24
Peak memory 206348 kb
Host smart-4c142ad4-9ade-40a7-8678-d1b9422a7b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36401
85464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3640185464
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1247442923
Short name T1401
Test name
Test status
Simulation time 7060224395 ps
CPU time 14.41 seconds
Started Jul 07 05:23:40 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206496 kb
Host smart-3ea207dd-944c-41e8-ab99-ce425758aebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12474
42923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1247442923
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3931263062
Short name T1726
Test name
Test status
Simulation time 308728207 ps
CPU time 1.1 seconds
Started Jul 07 05:23:41 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206120 kb
Host smart-be83c164-8bd8-41db-b1d3-a9ba22288cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39312
63062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3931263062
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2083736159
Short name T2308
Test name
Test status
Simulation time 153020609 ps
CPU time 0.79 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206164 kb
Host smart-50a60d02-51e7-41bf-909f-6713fb7a1bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
36159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2083736159
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1573052222
Short name T640
Test name
Test status
Simulation time 49435714 ps
CPU time 0.67 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 206108 kb
Host smart-4f7b4bd2-1f0c-4edd-ad32-e64339688290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15730
52222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1573052222
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3633821302
Short name T1879
Test name
Test status
Simulation time 869478063 ps
CPU time 2.21 seconds
Started Jul 07 05:23:44 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206408 kb
Host smart-1f8e5893-1719-4398-bd62-c7b3b1f608e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338
21302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3633821302
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2127641961
Short name T1709
Test name
Test status
Simulation time 383617856 ps
CPU time 2.34 seconds
Started Jul 07 05:23:39 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 206324 kb
Host smart-1e08e887-05d7-4117-acdd-ead679763d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276
41961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2127641961
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3978071796
Short name T2614
Test name
Test status
Simulation time 217571768 ps
CPU time 0.86 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206184 kb
Host smart-1cace13a-f519-4c9b-8096-5fdb6ae0a256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39780
71796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3978071796
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3381770194
Short name T2336
Test name
Test status
Simulation time 165232686 ps
CPU time 0.79 seconds
Started Jul 07 05:23:47 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206152 kb
Host smart-79852f65-b4da-4296-a08f-3eab105edfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817
70194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3381770194
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2323866150
Short name T1936
Test name
Test status
Simulation time 219674679 ps
CPU time 0.89 seconds
Started Jul 07 05:23:36 PM PDT 24
Finished Jul 07 05:23:37 PM PDT 24
Peak memory 206116 kb
Host smart-6738db61-e0a3-4d84-bf59-35434743d8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238
66150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2323866150
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1120807755
Short name T1460
Test name
Test status
Simulation time 10156878388 ps
CPU time 73.65 seconds
Started Jul 07 05:23:38 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206432 kb
Host smart-7017b1a9-1a38-4e86-ad98-83d43e424cf0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1120807755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1120807755
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3550400672
Short name T1193
Test name
Test status
Simulation time 213701529 ps
CPU time 0.9 seconds
Started Jul 07 05:23:49 PM PDT 24
Finished Jul 07 05:23:50 PM PDT 24
Peak memory 206116 kb
Host smart-55e3da03-465b-4d7b-98d3-b8b3debdab2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35504
00672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3550400672
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3559552475
Short name T620
Test name
Test status
Simulation time 23294291629 ps
CPU time 30.72 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206180 kb
Host smart-b41189de-1025-4984-a99f-1b3691086e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
52475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3559552475
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.4089821887
Short name T1526
Test name
Test status
Simulation time 3343832420 ps
CPU time 4 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:51 PM PDT 24
Peak memory 206256 kb
Host smart-6d33406d-410d-443b-93b8-83e933c990ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40898
21887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.4089821887
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.577429963
Short name T1523
Test name
Test status
Simulation time 9154012788 ps
CPU time 258.27 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:28:02 PM PDT 24
Peak memory 206492 kb
Host smart-a1f385f8-9e5c-49bd-8e64-82cae9a287f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57742
9963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.577429963
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2802474155
Short name T427
Test name
Test status
Simulation time 4810925572 ps
CPU time 45.57 seconds
Started Jul 07 05:23:44 PM PDT 24
Finished Jul 07 05:24:30 PM PDT 24
Peak memory 206524 kb
Host smart-29569618-e098-45e7-a68a-389cf9b7f0ac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2802474155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2802474155
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1570179375
Short name T988
Test name
Test status
Simulation time 290480646 ps
CPU time 0.93 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206044 kb
Host smart-df82bffd-287e-4f2b-866b-b79e0bc7cfc0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1570179375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1570179375
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3783644224
Short name T2146
Test name
Test status
Simulation time 202035716 ps
CPU time 0.91 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206096 kb
Host smart-65b6fff1-4bfe-4910-a4f2-f379aa5a6ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37836
44224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3783644224
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.1504268291
Short name T2698
Test name
Test status
Simulation time 4281538511 ps
CPU time 114.27 seconds
Started Jul 07 05:23:44 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206416 kb
Host smart-3da3cc4e-b7b0-4de3-a51c-d2d0ad41553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15042
68291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.1504268291
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.660236934
Short name T2356
Test name
Test status
Simulation time 7460328112 ps
CPU time 54.02 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206696 kb
Host smart-0e8c40a9-b053-4d43-9f94-2a939b7972e4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=660236934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.660236934
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.3934579783
Short name T342
Test name
Test status
Simulation time 162194624 ps
CPU time 0.83 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206160 kb
Host smart-0a7ed6b5-9b98-43c0-ae2f-cddda117f909
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3934579783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3934579783
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3001873615
Short name T350
Test name
Test status
Simulation time 203245576 ps
CPU time 0.78 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:07 PM PDT 24
Peak memory 205940 kb
Host smart-f37af1d3-be81-4de0-8fe9-722052e18240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30018
73615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3001873615
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3083245821
Short name T2354
Test name
Test status
Simulation time 192870243 ps
CPU time 0.8 seconds
Started Jul 07 05:23:44 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206132 kb
Host smart-af219166-adf9-47f1-8ddc-ac2ae840a0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30832
45821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3083245821
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3800359170
Short name T1540
Test name
Test status
Simulation time 205304557 ps
CPU time 0.87 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206164 kb
Host smart-10cf3b62-db57-4bdf-966c-218df59e0780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38003
59170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3800359170
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3525169038
Short name T2365
Test name
Test status
Simulation time 152309758 ps
CPU time 0.76 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206088 kb
Host smart-1d77eaf2-7f81-4287-88ef-6dcac5d8e920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35251
69038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3525169038
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1229789977
Short name T1573
Test name
Test status
Simulation time 156714989 ps
CPU time 0.83 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206108 kb
Host smart-c5e52e44-de46-456e-8d48-4989f36f8cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
89977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1229789977
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1267050452
Short name T1681
Test name
Test status
Simulation time 181075376 ps
CPU time 0.79 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:23:53 PM PDT 24
Peak memory 206036 kb
Host smart-894b7c3c-1dd1-4a7d-9d24-1d25b23431a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
50452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1267050452
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3797077551
Short name T1081
Test name
Test status
Simulation time 220981366 ps
CPU time 0.91 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206080 kb
Host smart-93b3cb15-02e8-4757-b580-8f09765d5774
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3797077551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3797077551
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1691215483
Short name T1223
Test name
Test status
Simulation time 141545315 ps
CPU time 0.8 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 206164 kb
Host smart-b2d8112a-9eb8-464d-ba14-10aa66ef9239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16912
15483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1691215483
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4274262261
Short name T1247
Test name
Test status
Simulation time 59033051 ps
CPU time 0.65 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206180 kb
Host smart-69b750b3-f09c-44c2-bc06-acd2b7cd816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
62261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4274262261
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3925440672
Short name T2680
Test name
Test status
Simulation time 7243672367 ps
CPU time 16.39 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206408 kb
Host smart-618378b6-f95e-44b6-a9e0-c6814c6e2b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39254
40672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3925440672
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.868497043
Short name T1543
Test name
Test status
Simulation time 270169451 ps
CPU time 0.96 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:23:54 PM PDT 24
Peak memory 206140 kb
Host smart-5e2d67fb-1e6d-43c6-a9c6-2081f57568ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86849
7043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.868497043
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1776154715
Short name T2020
Test name
Test status
Simulation time 179652146 ps
CPU time 0.83 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206432 kb
Host smart-ffc12fe2-24ee-443e-aa61-e6530c6fa053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17761
54715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1776154715
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1456031708
Short name T1217
Test name
Test status
Simulation time 189782125 ps
CPU time 0.83 seconds
Started Jul 07 05:23:51 PM PDT 24
Finished Jul 07 05:23:52 PM PDT 24
Peak memory 206200 kb
Host smart-732ed1aa-74de-4908-9681-d690ff9f3087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
31708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1456031708
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3651147211
Short name T1735
Test name
Test status
Simulation time 173158280 ps
CPU time 0.83 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206180 kb
Host smart-c867d60e-97ee-48cb-9dbb-e33b956618f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36511
47211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3651147211
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2856620112
Short name T1067
Test name
Test status
Simulation time 142938103 ps
CPU time 0.78 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206192 kb
Host smart-db5294c6-e636-4633-a231-87c7150bf02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
20112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2856620112
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1385696317
Short name T1581
Test name
Test status
Simulation time 142331715 ps
CPU time 0.79 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206184 kb
Host smart-82e79d0b-9113-4030-9db8-7761bf245f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
96317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1385696317
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1843616319
Short name T598
Test name
Test status
Simulation time 215704692 ps
CPU time 0.91 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:43 PM PDT 24
Peak memory 206196 kb
Host smart-4158fa77-7408-452d-b505-84cc0ab50dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18436
16319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1843616319
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1363706816
Short name T1584
Test name
Test status
Simulation time 4218339042 ps
CPU time 39.52 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:24:22 PM PDT 24
Peak memory 206412 kb
Host smart-0bfd18bf-dd29-4307-85f2-2165da5d45b2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1363706816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1363706816
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1427218174
Short name T2086
Test name
Test status
Simulation time 171916192 ps
CPU time 0.82 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206116 kb
Host smart-6d8178cd-007b-4421-8b8f-d3bf6b6981dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
18174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1427218174
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2751209642
Short name T416
Test name
Test status
Simulation time 172752374 ps
CPU time 0.8 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206112 kb
Host smart-d32832e7-198b-44a8-b700-8aff37f3a330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27512
09642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2751209642
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.843018413
Short name T1147
Test name
Test status
Simulation time 1116502947 ps
CPU time 2.52 seconds
Started Jul 07 05:23:42 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206456 kb
Host smart-2fc81273-4121-48c0-b510-7a1fb3366a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84301
8413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.843018413
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2346573321
Short name T1798
Test name
Test status
Simulation time 3066385035 ps
CPU time 77.49 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206456 kb
Host smart-425e7843-0072-4fb9-bc2f-c431f7b2ae27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
73321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2346573321
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3444952771
Short name T1802
Test name
Test status
Simulation time 39198096 ps
CPU time 0.67 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:23:53 PM PDT 24
Peak memory 206224 kb
Host smart-dbd2dce5-6a02-4b85-a83c-c62af5b3cfa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3444952771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3444952771
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1444860570
Short name T2252
Test name
Test status
Simulation time 3731837906 ps
CPU time 4.31 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206456 kb
Host smart-60dee4dd-dd44-41d9-974c-5d2853f62ef2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1444860570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1444860570
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.929313869
Short name T1041
Test name
Test status
Simulation time 13406019816 ps
CPU time 12.99 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206484 kb
Host smart-b56c89d3-507e-43be-b0fd-9e4a14d9dff0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=929313869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.929313869
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.994946519
Short name T731
Test name
Test status
Simulation time 23353977542 ps
CPU time 24.34 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206124 kb
Host smart-b41783ba-2ef1-4a69-8212-7617cb0632e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=994946519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.994946519
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2355780218
Short name T1353
Test name
Test status
Simulation time 198470110 ps
CPU time 0.9 seconds
Started Jul 07 05:24:54 PM PDT 24
Finished Jul 07 05:24:56 PM PDT 24
Peak memory 205136 kb
Host smart-7c8e4af5-3117-4a81-af00-70361181416c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
80218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2355780218
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2547629818
Short name T666
Test name
Test status
Simulation time 189345366 ps
CPU time 0.78 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206160 kb
Host smart-995dbbc9-8284-4768-989a-c10dde6d4e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25476
29818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2547629818
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.975817566
Short name T57
Test name
Test status
Simulation time 335925613 ps
CPU time 1.31 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206188 kb
Host smart-77bbf9d0-eb96-47d4-b742-9401eea63fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97581
7566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.975817566
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2997461072
Short name T508
Test name
Test status
Simulation time 279238631 ps
CPU time 0.94 seconds
Started Jul 07 05:23:44 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206184 kb
Host smart-1ee7c491-913f-474d-955f-6e6c2623ba08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29974
61072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2997461072
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.4059332408
Short name T2219
Test name
Test status
Simulation time 18391432266 ps
CPU time 36.54 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:24:22 PM PDT 24
Peak memory 206500 kb
Host smart-ed79f906-728a-4ac2-91e6-bbdd50d5bd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40593
32408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.4059332408
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3485264752
Short name T1740
Test name
Test status
Simulation time 325031577 ps
CPU time 1.12 seconds
Started Jul 07 05:23:43 PM PDT 24
Finished Jul 07 05:23:45 PM PDT 24
Peak memory 206188 kb
Host smart-991c5dda-adf9-4328-8383-91562a14e838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34852
64752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3485264752
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2149607586
Short name T1591
Test name
Test status
Simulation time 202384572 ps
CPU time 0.81 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206224 kb
Host smart-a4679d6a-e889-4434-808a-ed2d5f7278ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21496
07586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2149607586
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2982263580
Short name T2349
Test name
Test status
Simulation time 42576532 ps
CPU time 0.64 seconds
Started Jul 07 05:23:50 PM PDT 24
Finished Jul 07 05:23:52 PM PDT 24
Peak memory 206036 kb
Host smart-ffe93555-f37a-414e-bb67-0947db7ce82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822
63580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2982263580
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.27840484
Short name T825
Test name
Test status
Simulation time 1038908594 ps
CPU time 2.71 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206316 kb
Host smart-82a3b7ae-bf4e-4f69-91db-8e025120ff1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27840
484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.27840484
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4149110856
Short name T2595
Test name
Test status
Simulation time 157698548 ps
CPU time 1.51 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:50 PM PDT 24
Peak memory 206440 kb
Host smart-5ec96a0c-839d-4ea9-a223-85055b05f17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41491
10856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4149110856
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3202766631
Short name T2183
Test name
Test status
Simulation time 232520895 ps
CPU time 0.92 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:50 PM PDT 24
Peak memory 206204 kb
Host smart-bdea80f0-d84d-4bf1-ba4d-77b792511da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32027
66631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3202766631
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1345775696
Short name T1761
Test name
Test status
Simulation time 145560127 ps
CPU time 0.77 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206192 kb
Host smart-eee0e034-b93a-4867-8284-f9a498c63cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457
75696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1345775696
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.166896680
Short name T2675
Test name
Test status
Simulation time 167372941 ps
CPU time 0.82 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206180 kb
Host smart-70cfa12e-b26b-4753-84d5-32f93f1f3033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16689
6680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.166896680
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1739540976
Short name T522
Test name
Test status
Simulation time 178651406 ps
CPU time 0.83 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206204 kb
Host smart-40c52294-fed1-4cf1-bf2a-fe16ef7aa07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17395
40976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1739540976
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1145939477
Short name T1089
Test name
Test status
Simulation time 23301683091 ps
CPU time 23.77 seconds
Started Jul 07 05:23:50 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206104 kb
Host smart-ccd360a3-167f-4ae1-a6dc-6a5d34598efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
39477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1145939477
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2255605333
Short name T402
Test name
Test status
Simulation time 3376712970 ps
CPU time 3.74 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206252 kb
Host smart-119b03fa-b19f-4f92-8793-07c892f0bc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22556
05333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2255605333
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3216713650
Short name T1754
Test name
Test status
Simulation time 9679025792 ps
CPU time 280.17 seconds
Started Jul 07 05:23:50 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 206524 kb
Host smart-8bd80f00-e37e-4711-8043-9696c485364f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
13650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3216713650
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.70968724
Short name T2195
Test name
Test status
Simulation time 4618032049 ps
CPU time 44.15 seconds
Started Jul 07 05:23:49 PM PDT 24
Finished Jul 07 05:24:34 PM PDT 24
Peak memory 206492 kb
Host smart-bd89b05f-e7bd-4b85-9f7d-9c1c0e26c2ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=70968724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.70968724
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2485994915
Short name T1332
Test name
Test status
Simulation time 261424488 ps
CPU time 0.94 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206044 kb
Host smart-685ec4c4-a70a-47af-9f96-39163521c96c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2485994915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2485994915
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3614414903
Short name T2596
Test name
Test status
Simulation time 213403021 ps
CPU time 0.95 seconds
Started Jul 07 05:23:48 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 206124 kb
Host smart-2f44b9ac-308c-4251-a225-4c60c8d0ec0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
14903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3614414903
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2379414118
Short name T1424
Test name
Test status
Simulation time 5633238622 ps
CPU time 54.18 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206460 kb
Host smart-e8175f8c-230e-40d4-8cdb-fc9f4443c2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
14118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2379414118
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.696859287
Short name T696
Test name
Test status
Simulation time 5548157560 ps
CPU time 53.59 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206404 kb
Host smart-04bdaf80-9593-4d10-bc6f-2dae6d8e3dd5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=696859287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.696859287
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2633335320
Short name T549
Test name
Test status
Simulation time 152846984 ps
CPU time 0.81 seconds
Started Jul 07 05:23:47 PM PDT 24
Finished Jul 07 05:23:49 PM PDT 24
Peak memory 206204 kb
Host smart-06314b5e-64fd-4c3a-bf26-6e0a528fe19d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2633335320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2633335320
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3530805357
Short name T857
Test name
Test status
Simulation time 145459777 ps
CPU time 0.75 seconds
Started Jul 07 05:23:49 PM PDT 24
Finished Jul 07 05:23:50 PM PDT 24
Peak memory 206044 kb
Host smart-e31eb0d0-cbb6-445c-beb8-6c762796aae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35308
05357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3530805357
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1389221286
Short name T2686
Test name
Test status
Simulation time 202411593 ps
CPU time 0.89 seconds
Started Jul 07 05:23:45 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 206164 kb
Host smart-3c7d2a67-3ebb-43bb-a71b-d7ad5f903e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13892
21286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1389221286
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3984327573
Short name T1630
Test name
Test status
Simulation time 168220017 ps
CPU time 0.79 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206108 kb
Host smart-3604e796-88f5-4837-a07d-fcf57ca2913a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39843
27573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3984327573
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3005700255
Short name T395
Test name
Test status
Simulation time 196464935 ps
CPU time 1.03 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206128 kb
Host smart-a856e126-890d-40ea-a57e-1d4fade9f0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
00255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3005700255
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2610145458
Short name T639
Test name
Test status
Simulation time 178762513 ps
CPU time 0.82 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 206204 kb
Host smart-d1bf47db-9f31-4daf-b361-c3cf3aca201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26101
45458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2610145458
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2594680764
Short name T2519
Test name
Test status
Simulation time 169638752 ps
CPU time 0.79 seconds
Started Jul 07 05:23:46 PM PDT 24
Finished Jul 07 05:23:48 PM PDT 24
Peak memory 205900 kb
Host smart-6f7312a6-f496-490c-99a8-404211122a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25946
80764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2594680764
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2257575227
Short name T1357
Test name
Test status
Simulation time 249739795 ps
CPU time 0.97 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:56 PM PDT 24
Peak memory 206172 kb
Host smart-fbea67f2-2b31-4311-a747-d02d30fda891
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2257575227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2257575227
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.4191947475
Short name T1371
Test name
Test status
Simulation time 150028172 ps
CPU time 0.79 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:23:53 PM PDT 24
Peak memory 206184 kb
Host smart-a5843676-a982-49fa-95b1-60cc5a46dbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41919
47475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.4191947475
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2528962011
Short name T1404
Test name
Test status
Simulation time 48904686 ps
CPU time 0.69 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206132 kb
Host smart-48a4fc40-fcfd-4020-a9cd-897bd4ef4430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
62011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2528962011
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3181887115
Short name T2331
Test name
Test status
Simulation time 15346093538 ps
CPU time 38.11 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:24:31 PM PDT 24
Peak memory 206428 kb
Host smart-1a306e08-8885-4ee2-8929-1fc6978b41cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818
87115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3181887115
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4270583414
Short name T2000
Test name
Test status
Simulation time 161377800 ps
CPU time 0.83 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206120 kb
Host smart-28341fbc-3ccd-45de-ad92-2b462a7f9078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
83414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4270583414
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.326224513
Short name T2584
Test name
Test status
Simulation time 202220150 ps
CPU time 0.94 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:56 PM PDT 24
Peak memory 206112 kb
Host smart-4609195f-e92d-43f6-93a8-e7f74816244b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622
4513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.326224513
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2116074470
Short name T934
Test name
Test status
Simulation time 185681454 ps
CPU time 0.82 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206152 kb
Host smart-ca4fb0c8-f27f-4bca-8399-30e0534c1ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
74470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2116074470
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1351362356
Short name T2096
Test name
Test status
Simulation time 168865976 ps
CPU time 0.81 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206192 kb
Host smart-90f80716-0f0b-4e31-a2df-2111a528871c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
62356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1351362356
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2865238579
Short name T73
Test name
Test status
Simulation time 171024015 ps
CPU time 0.84 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206156 kb
Host smart-68f3dcfd-07ce-4955-9241-b62f1d6e8868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28652
38579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2865238579
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4098896926
Short name T2067
Test name
Test status
Simulation time 154426846 ps
CPU time 0.77 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206200 kb
Host smart-e44c80d7-c5fc-4875-8958-76b12b3846bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40988
96926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4098896926
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2904280400
Short name T2260
Test name
Test status
Simulation time 166942808 ps
CPU time 0.86 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:54 PM PDT 24
Peak memory 206168 kb
Host smart-ec8259f0-10f1-490b-a823-b6df0d1e79da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29042
80400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2904280400
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1533539109
Short name T2072
Test name
Test status
Simulation time 230802308 ps
CPU time 0.9 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206116 kb
Host smart-a8a504aa-6ce2-4991-9263-5fbc05b4db6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335
39109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1533539109
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2982805525
Short name T972
Test name
Test status
Simulation time 7307489061 ps
CPU time 65.14 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:24:57 PM PDT 24
Peak memory 206332 kb
Host smart-bf08af54-8a5a-4528-befc-f1b2fa814b00
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2982805525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2982805525
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3365569097
Short name T1172
Test name
Test status
Simulation time 154349114 ps
CPU time 0.79 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 206200 kb
Host smart-e137badf-3976-422e-8d97-2f441c8c6428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33655
69097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3365569097
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2978849989
Short name T1387
Test name
Test status
Simulation time 184230761 ps
CPU time 0.79 seconds
Started Jul 07 05:24:12 PM PDT 24
Finished Jul 07 05:24:13 PM PDT 24
Peak memory 206112 kb
Host smart-cd4aa229-3410-4bbb-af7e-b41ed2567bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29788
49989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2978849989
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.677136673
Short name T1464
Test name
Test status
Simulation time 725551984 ps
CPU time 1.69 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206280 kb
Host smart-81d91d20-6335-485c-9265-bc0e69709800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67713
6673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.677136673
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3825503764
Short name T1952
Test name
Test status
Simulation time 5965549045 ps
CPU time 56.56 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206468 kb
Host smart-7afb838b-5a52-4b1d-ad58-3dae016bf1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
03764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3825503764
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2136052926
Short name T1597
Test name
Test status
Simulation time 46152886 ps
CPU time 0.66 seconds
Started Jul 07 05:19:52 PM PDT 24
Finished Jul 07 05:19:53 PM PDT 24
Peak memory 206172 kb
Host smart-5eb22d3a-311a-46f0-b865-59c11760272c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2136052926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2136052926
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2186078110
Short name T1779
Test name
Test status
Simulation time 4191991082 ps
CPU time 5.32 seconds
Started Jul 07 05:19:32 PM PDT 24
Finished Jul 07 05:19:38 PM PDT 24
Peak memory 206208 kb
Host smart-ef222e0d-67ce-4b3a-82e4-0d7cca25dedd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2186078110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2186078110
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1638543829
Short name T848
Test name
Test status
Simulation time 13528516144 ps
CPU time 14.99 seconds
Started Jul 07 05:19:37 PM PDT 24
Finished Jul 07 05:19:52 PM PDT 24
Peak memory 206480 kb
Host smart-8a5bf4c0-43fb-4524-9a19-d1c22b9e0445
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1638543829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1638543829
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2491168515
Short name T1787
Test name
Test status
Simulation time 23395229174 ps
CPU time 27.43 seconds
Started Jul 07 05:19:30 PM PDT 24
Finished Jul 07 05:19:58 PM PDT 24
Peak memory 206224 kb
Host smart-2fb3a913-c981-4f08-ac4e-0ac45802d64e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2491168515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.2491168515
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1762536534
Short name T1413
Test name
Test status
Simulation time 185347128 ps
CPU time 0.81 seconds
Started Jul 07 05:19:37 PM PDT 24
Finished Jul 07 05:19:38 PM PDT 24
Peak memory 206184 kb
Host smart-bef776b8-65c8-478d-b7e0-dc75b550554a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
36534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1762536534
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.4162720123
Short name T63
Test name
Test status
Simulation time 171742368 ps
CPU time 0.79 seconds
Started Jul 07 05:19:34 PM PDT 24
Finished Jul 07 05:19:36 PM PDT 24
Peak memory 206180 kb
Host smart-8b110d47-b402-463e-9d78-57e4f052c612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627
20123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.4162720123
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3232483618
Short name T2158
Test name
Test status
Simulation time 171618490 ps
CPU time 0.85 seconds
Started Jul 07 05:19:35 PM PDT 24
Finished Jul 07 05:19:36 PM PDT 24
Peak memory 205712 kb
Host smart-020a2f41-472a-4994-9eed-0343089207cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324
83618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3232483618
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1136626799
Short name T1849
Test name
Test status
Simulation time 519519061 ps
CPU time 1.54 seconds
Started Jul 07 05:19:42 PM PDT 24
Finished Jul 07 05:19:44 PM PDT 24
Peak memory 206380 kb
Host smart-1bcc47e9-4adb-49a0-a7ec-551459c8470a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11366
26799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1136626799
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1245015962
Short name T1442
Test name
Test status
Simulation time 781121666 ps
CPU time 1.83 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:49 PM PDT 24
Peak memory 206444 kb
Host smart-e8600c0c-7a8f-4163-8d26-986738a0668f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12450
15962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1245015962
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1196008762
Short name T100
Test name
Test status
Simulation time 18250960192 ps
CPU time 31.89 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:20:18 PM PDT 24
Peak memory 206352 kb
Host smart-f31ebd37-4668-4ea1-95c2-714bcbb57450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
08762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1196008762
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.654157897
Short name T1525
Test name
Test status
Simulation time 447614414 ps
CPU time 1.37 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206104 kb
Host smart-7b519e56-abb4-425d-ab4f-adce9ec4183f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65415
7897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.654157897
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.690884724
Short name T536
Test name
Test status
Simulation time 136677246 ps
CPU time 0.71 seconds
Started Jul 07 05:19:44 PM PDT 24
Finished Jul 07 05:19:44 PM PDT 24
Peak memory 206192 kb
Host smart-723c50bc-1cd9-4a3f-9870-fdc92f6b8585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69088
4724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.690884724
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2371478687
Short name T2578
Test name
Test status
Simulation time 39067506 ps
CPU time 0.66 seconds
Started Jul 07 05:19:42 PM PDT 24
Finished Jul 07 05:19:43 PM PDT 24
Peak memory 206140 kb
Host smart-e7090f5b-9bca-4bd4-93b8-dd5c60745a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714
78687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2371478687
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2861994833
Short name T699
Test name
Test status
Simulation time 959884218 ps
CPU time 2.21 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:50 PM PDT 24
Peak memory 206456 kb
Host smart-cf20bd0a-b429-4f12-8247-66ec9e44d59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
94833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2861994833
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.993265031
Short name T1768
Test name
Test status
Simulation time 179856253 ps
CPU time 1.89 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206400 kb
Host smart-767b8b0f-daf9-407f-baa0-6e723298b934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99326
5031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.993265031
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3637953751
Short name T1094
Test name
Test status
Simulation time 84174024691 ps
CPU time 131.64 seconds
Started Jul 07 05:19:48 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 206432 kb
Host smart-b81532f9-8328-4206-b019-d81dfdafadc2
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3637953751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3637953751
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.4022103533
Short name T1116
Test name
Test status
Simulation time 81306334795 ps
CPU time 121.27 seconds
Started Jul 07 05:19:44 PM PDT 24
Finished Jul 07 05:21:45 PM PDT 24
Peak memory 206448 kb
Host smart-f7505f00-76e4-4a9e-89a5-89a990ddcffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022103533 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.4022103533
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.230974725
Short name T1189
Test name
Test status
Simulation time 89109451875 ps
CPU time 132.37 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:21:59 PM PDT 24
Peak memory 206440 kb
Host smart-05828f7b-9d1a-4bdf-b26a-d239fb01fa69
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=230974725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.230974725
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1428429791
Short name T2332
Test name
Test status
Simulation time 90249977735 ps
CPU time 115.22 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:21:41 PM PDT 24
Peak memory 206452 kb
Host smart-e567cae8-24c9-4f5a-b569-333a97109ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428429791 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1428429791
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.4292957637
Short name T36
Test name
Test status
Simulation time 82147452064 ps
CPU time 129.14 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:21:55 PM PDT 24
Peak memory 206428 kb
Host smart-ca1b06b7-fe32-4e00-be08-93a71525cfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42929
57637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.4292957637
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.569050763
Short name T2385
Test name
Test status
Simulation time 238339675 ps
CPU time 0.93 seconds
Started Jul 07 05:19:41 PM PDT 24
Finished Jul 07 05:19:43 PM PDT 24
Peak memory 206440 kb
Host smart-e2a58a69-6d79-4c5e-a0f0-541708775644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56905
0763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.569050763
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3478304228
Short name T2367
Test name
Test status
Simulation time 167428609 ps
CPU time 0.76 seconds
Started Jul 07 05:19:42 PM PDT 24
Finished Jul 07 05:19:43 PM PDT 24
Peak memory 206188 kb
Host smart-d9d44799-db6f-4c82-ba1e-89a87ec0175c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34783
04228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3478304228
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1083689596
Short name T2521
Test name
Test status
Simulation time 171486226 ps
CPU time 0.87 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206152 kb
Host smart-400f3087-790c-4290-81b5-27efbdc3d831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10836
89596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1083689596
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2909528529
Short name T1367
Test name
Test status
Simulation time 262825565 ps
CPU time 0.99 seconds
Started Jul 07 05:19:42 PM PDT 24
Finished Jul 07 05:19:44 PM PDT 24
Peak memory 206112 kb
Host smart-b8f7ca92-be7a-496f-ae69-097c7d2c2fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
28529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2909528529
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2012447820
Short name T1823
Test name
Test status
Simulation time 23315125056 ps
CPU time 23.06 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 206280 kb
Host smart-6422d048-4eb5-4c04-86a5-513687805abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
47820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2012447820
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2981056251
Short name T2044
Test name
Test status
Simulation time 3276126440 ps
CPU time 3.87 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:50 PM PDT 24
Peak memory 206192 kb
Host smart-c579fb49-1693-4ce0-b80e-30e4cb310f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29810
56251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2981056251
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.570223794
Short name T2222
Test name
Test status
Simulation time 10031850008 ps
CPU time 90.9 seconds
Started Jul 07 05:19:44 PM PDT 24
Finished Jul 07 05:21:15 PM PDT 24
Peak memory 206440 kb
Host smart-2a0da371-c9a5-4356-b53c-e49cf64d6b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57022
3794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.570223794
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3447027440
Short name T1469
Test name
Test status
Simulation time 7084613852 ps
CPU time 64.45 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 206460 kb
Host smart-fe80bcf1-0c9f-41ca-acb5-c458d0000480
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3447027440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3447027440
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3013566757
Short name T1938
Test name
Test status
Simulation time 237025240 ps
CPU time 0.88 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206172 kb
Host smart-0b428115-ac6a-4b17-b3c0-5f12e1dbd079
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3013566757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3013566757
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.477275503
Short name T1337
Test name
Test status
Simulation time 198931953 ps
CPU time 0.94 seconds
Started Jul 07 05:19:42 PM PDT 24
Finished Jul 07 05:19:44 PM PDT 24
Peak memory 206200 kb
Host smart-8dd80051-0064-4583-bf80-5413be8d3fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47727
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.477275503
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1620354591
Short name T1758
Test name
Test status
Simulation time 6036823870 ps
CPU time 42.51 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:20:27 PM PDT 24
Peak memory 206216 kb
Host smart-2e743ec9-9498-4ecb-85ba-35ab8cc39867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16203
54591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1620354591
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1228810442
Short name T2263
Test name
Test status
Simulation time 4307263187 ps
CPU time 122.05 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 206368 kb
Host smart-74b5afda-0a1b-4ada-8d9a-30ffa2a387a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1228810442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1228810442
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1678561391
Short name T348
Test name
Test status
Simulation time 207226290 ps
CPU time 0.83 seconds
Started Jul 07 05:19:44 PM PDT 24
Finished Jul 07 05:19:45 PM PDT 24
Peak memory 206096 kb
Host smart-fcf77b27-18ac-4340-9c60-6dfaa34cd3d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1678561391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1678561391
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2404434069
Short name T1098
Test name
Test status
Simulation time 146733297 ps
CPU time 0.82 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:46 PM PDT 24
Peak memory 206124 kb
Host smart-bee1216a-6b96-4d8b-bd13-b7347e40984b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24044
34069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2404434069
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3587600694
Short name T2245
Test name
Test status
Simulation time 181037285 ps
CPU time 0.81 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206188 kb
Host smart-c4404f7d-0906-43de-81de-b84f91a26150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35876
00694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3587600694
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2608426622
Short name T578
Test name
Test status
Simulation time 185753822 ps
CPU time 0.81 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206132 kb
Host smart-b4393ed0-5ca9-46f1-8747-9a1d927834b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
26622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2608426622
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1441920942
Short name T534
Test name
Test status
Simulation time 228998022 ps
CPU time 0.88 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206120 kb
Host smart-8ada7070-f33d-4e7e-8143-314ef7ce54fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14419
20942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1441920942
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3950442162
Short name T1325
Test name
Test status
Simulation time 150322386 ps
CPU time 0.8 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206116 kb
Host smart-e2548063-f4dd-49f1-b43f-990193ac48da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
42162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3950442162
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2948122331
Short name T381
Test name
Test status
Simulation time 176041126 ps
CPU time 0.85 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:46 PM PDT 24
Peak memory 206140 kb
Host smart-356ccb46-f56d-4669-b0b7-bac6ff0d0f96
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2948122331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2948122331
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1992403937
Short name T1107
Test name
Test status
Simulation time 215666889 ps
CPU time 1 seconds
Started Jul 07 05:19:49 PM PDT 24
Finished Jul 07 05:19:51 PM PDT 24
Peak memory 206184 kb
Host smart-aaa4a130-864f-4f60-8e44-c30fb32b0687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
03937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1992403937
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2674615386
Short name T2688
Test name
Test status
Simulation time 143106882 ps
CPU time 0.74 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206184 kb
Host smart-9e13cb8a-9f5d-4e60-8a93-b7a7c9c563a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26746
15386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2674615386
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3042525078
Short name T891
Test name
Test status
Simulation time 40785482 ps
CPU time 0.63 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206192 kb
Host smart-c0695d6a-7ff3-468c-aec7-4b24827e150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
25078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3042525078
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.544085024
Short name T1477
Test name
Test status
Simulation time 13381314969 ps
CPU time 30.12 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:20:18 PM PDT 24
Peak memory 214608 kb
Host smart-badd134b-bbd7-4ce7-8b4f-ef431d0944a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54408
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.544085024
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1227390776
Short name T544
Test name
Test status
Simulation time 202144141 ps
CPU time 0.87 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206188 kb
Host smart-90931bb6-ef81-4cdf-8258-1641c811aa2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
90776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1227390776
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.409505389
Short name T586
Test name
Test status
Simulation time 219574383 ps
CPU time 0.84 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:49 PM PDT 24
Peak memory 206112 kb
Host smart-57f94e70-5b44-41f1-a1a4-eb86cf408ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40950
5389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.409505389
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.4072873127
Short name T43
Test name
Test status
Simulation time 6561921347 ps
CPU time 45.53 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:20:33 PM PDT 24
Peak memory 206516 kb
Host smart-779071ca-53d5-472e-a89d-da3607a63150
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4072873127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.4072873127
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3845653914
Short name T186
Test name
Test status
Simulation time 10906022587 ps
CPU time 201.43 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:23:07 PM PDT 24
Peak memory 206504 kb
Host smart-26a6464a-e050-43a9-8aed-5d5f5300c2b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3845653914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3845653914
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.327976324
Short name T1443
Test name
Test status
Simulation time 20189935542 ps
CPU time 116.26 seconds
Started Jul 07 05:19:50 PM PDT 24
Finished Jul 07 05:21:46 PM PDT 24
Peak memory 206508 kb
Host smart-52e4d0b3-e963-41ce-a9eb-903bffcf13c4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=327976324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.327976324
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.247615001
Short name T957
Test name
Test status
Simulation time 210843358 ps
CPU time 0.88 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206168 kb
Host smart-8f309776-0757-4f8b-85a2-1759a83d69af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24761
5001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.247615001
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.933523256
Short name T1195
Test name
Test status
Simulation time 162761330 ps
CPU time 0.79 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206188 kb
Host smart-f12d6e86-dc7c-43c5-9d90-32ce4aebfc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93352
3256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.933523256
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.4154751243
Short name T1988
Test name
Test status
Simulation time 174942535 ps
CPU time 0.77 seconds
Started Jul 07 05:19:45 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 206172 kb
Host smart-da400415-6475-4c43-ab57-e36c53166c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41547
51243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.4154751243
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2515913462
Short name T77
Test name
Test status
Simulation time 159790517 ps
CPU time 0.8 seconds
Started Jul 07 05:19:47 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206120 kb
Host smart-cf3e4ef3-fce7-40ca-a664-e84fb68aeb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159
13462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2515913462
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3506795354
Short name T235
Test name
Test status
Simulation time 953666864 ps
CPU time 1.84 seconds
Started Jul 07 05:19:49 PM PDT 24
Finished Jul 07 05:19:52 PM PDT 24
Peak memory 225048 kb
Host smart-84932524-f7fa-473e-8ffe-98020f2bf6e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3506795354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3506795354
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.407045933
Short name T2571
Test name
Test status
Simulation time 446974168 ps
CPU time 1.35 seconds
Started Jul 07 05:19:46 PM PDT 24
Finished Jul 07 05:19:48 PM PDT 24
Peak memory 206208 kb
Host smart-f2bf005e-bc62-4fb6-9d40-3b15d5fe0c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40704
5933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.407045933
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2518974595
Short name T1899
Test name
Test status
Simulation time 250197019 ps
CPU time 0.89 seconds
Started Jul 07 05:19:52 PM PDT 24
Finished Jul 07 05:19:53 PM PDT 24
Peak memory 206068 kb
Host smart-ac48315d-9f5f-452e-8594-045395073c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25189
74595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2518974595
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1155336056
Short name T355
Test name
Test status
Simulation time 157759011 ps
CPU time 0.77 seconds
Started Jul 07 05:19:57 PM PDT 24
Finished Jul 07 05:19:58 PM PDT 24
Peak memory 206180 kb
Host smart-4281d1a5-27dd-422d-bd48-c194829b4d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
36056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1155336056
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.348121181
Short name T1441
Test name
Test status
Simulation time 176737691 ps
CPU time 0.8 seconds
Started Jul 07 05:19:54 PM PDT 24
Finished Jul 07 05:19:55 PM PDT 24
Peak memory 206148 kb
Host smart-b9834103-1881-42d6-8503-59d9570838c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
1181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.348121181
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.610508246
Short name T30
Test name
Test status
Simulation time 191844634 ps
CPU time 0.87 seconds
Started Jul 07 05:19:53 PM PDT 24
Finished Jul 07 05:19:55 PM PDT 24
Peak memory 206144 kb
Host smart-6121276e-ad22-47b0-b47d-890f7b7b59c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61050
8246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.610508246
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2459842732
Short name T717
Test name
Test status
Simulation time 5286567723 ps
CPU time 38.02 seconds
Started Jul 07 05:19:52 PM PDT 24
Finished Jul 07 05:20:31 PM PDT 24
Peak memory 206436 kb
Host smart-ee9dca44-85b9-4fab-b492-55446a389c09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2459842732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2459842732
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1556585598
Short name T2563
Test name
Test status
Simulation time 219007652 ps
CPU time 0.88 seconds
Started Jul 07 05:19:50 PM PDT 24
Finished Jul 07 05:19:51 PM PDT 24
Peak memory 206152 kb
Host smart-bdb9e87f-1a72-4071-b156-836fc5cf5876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15565
85598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1556585598
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.297835281
Short name T1903
Test name
Test status
Simulation time 220137589 ps
CPU time 0.82 seconds
Started Jul 07 05:19:52 PM PDT 24
Finished Jul 07 05:19:53 PM PDT 24
Peak memory 206040 kb
Host smart-4b8be9d6-dd78-472e-a218-89d846f11e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29783
5281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.297835281
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2702905835
Short name T2045
Test name
Test status
Simulation time 1079361866 ps
CPU time 2.2 seconds
Started Jul 07 05:19:56 PM PDT 24
Finished Jul 07 05:19:59 PM PDT 24
Peak memory 206364 kb
Host smart-fa6df6b2-a0c8-4eca-9692-8ed42453335f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27029
05835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2702905835
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.486208560
Short name T1594
Test name
Test status
Simulation time 5091730166 ps
CPU time 138.99 seconds
Started Jul 07 05:19:56 PM PDT 24
Finished Jul 07 05:22:16 PM PDT 24
Peak memory 206496 kb
Host smart-9c2fd9b4-2713-4cbe-a21a-9b12ca2de43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48620
8560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.486208560
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3286702854
Short name T2112
Test name
Test status
Simulation time 7895271556 ps
CPU time 122.42 seconds
Started Jul 07 05:19:49 PM PDT 24
Finished Jul 07 05:21:52 PM PDT 24
Peak memory 206496 kb
Host smart-59d6066f-3e2c-4906-a137-5e81a235bd42
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3286702854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3286702854
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3438532256
Short name T584
Test name
Test status
Simulation time 34158701 ps
CPU time 0.65 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206224 kb
Host smart-82d915ff-2065-4fbe-abb4-79d2fdd237ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3438532256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3438532256
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3963740412
Short name T2312
Test name
Test status
Simulation time 3573302412 ps
CPU time 3.97 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206408 kb
Host smart-a44b64db-5e64-467e-b32e-816babc02b12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3963740412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3963740412
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.656057896
Short name T1521
Test name
Test status
Simulation time 13346087810 ps
CPU time 13.52 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:24:10 PM PDT 24
Peak memory 206244 kb
Host smart-9702835b-ae5c-4ed4-9c25-d0eb735e8a79
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=656057896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.656057896
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.469921167
Short name T2514
Test name
Test status
Simulation time 23404831275 ps
CPU time 27.81 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:24:26 PM PDT 24
Peak memory 206424 kb
Host smart-a2b5eb64-bcd2-45e8-b2ee-60b0af58feb8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=469921167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.469921167
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.427746340
Short name T2337
Test name
Test status
Simulation time 150073920 ps
CPU time 0.77 seconds
Started Jul 07 05:23:50 PM PDT 24
Finished Jul 07 05:23:51 PM PDT 24
Peak memory 206188 kb
Host smart-1ae6ba9b-5a11-4829-a413-9fc3639dbc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
6340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.427746340
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1938380424
Short name T1837
Test name
Test status
Simulation time 155982117 ps
CPU time 0.79 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206152 kb
Host smart-0c3023d2-cf98-4ff6-99ae-e29f066698d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19383
80424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1938380424
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1421874717
Short name T1137
Test name
Test status
Simulation time 514465303 ps
CPU time 1.46 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206396 kb
Host smart-a07ce5a1-6543-4948-818a-d6091fa0a2a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
74717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1421874717
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3444903314
Short name T1683
Test name
Test status
Simulation time 803002309 ps
CPU time 1.96 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:56 PM PDT 24
Peak memory 206448 kb
Host smart-a9891950-c5b8-4169-bb88-91c21eee6bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34449
03314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3444903314
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3016860617
Short name T2136
Test name
Test status
Simulation time 22578413742 ps
CPU time 37.11 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206372 kb
Host smart-21c47c76-2595-49bb-8487-b23bfd826d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30168
60617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3016860617
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3590693127
Short name T1331
Test name
Test status
Simulation time 388215783 ps
CPU time 1.33 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:56 PM PDT 24
Peak memory 206188 kb
Host smart-7c753f8f-58f7-4bcd-9490-20e2506af21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
93127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3590693127
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1421399080
Short name T839
Test name
Test status
Simulation time 197277821 ps
CPU time 0.83 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206200 kb
Host smart-b9940436-2162-4e6d-856a-3f0bd82070fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14213
99080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1421399080
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.775576529
Short name T1969
Test name
Test status
Simulation time 42580358 ps
CPU time 0.68 seconds
Started Jul 07 05:24:04 PM PDT 24
Finished Jul 07 05:24:05 PM PDT 24
Peak memory 206180 kb
Host smart-1099ceb7-6bec-4f51-96f2-5bd9ee714c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77557
6529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.775576529
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2800492996
Short name T1452
Test name
Test status
Simulation time 897250585 ps
CPU time 2.39 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:56 PM PDT 24
Peak memory 206440 kb
Host smart-a3b45c68-ff99-42a8-9157-bdddd7a6326b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28004
92996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2800492996
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.149774566
Short name T1537
Test name
Test status
Simulation time 287319450 ps
CPU time 2.16 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:23:56 PM PDT 24
Peak memory 206436 kb
Host smart-ff98a913-62cd-4a07-acb5-c9862e281898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14977
4566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.149774566
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2634879130
Short name T732
Test name
Test status
Simulation time 233987633 ps
CPU time 0.91 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206184 kb
Host smart-7e2f4851-c57a-4f51-92ce-ea16413ce260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
79130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2634879130
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2132355533
Short name T1257
Test name
Test status
Simulation time 181942398 ps
CPU time 0.83 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206156 kb
Host smart-460fc3a3-7ee7-498d-aae5-b0d332f53ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
55533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2132355533
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1717196362
Short name T1836
Test name
Test status
Simulation time 163085117 ps
CPU time 0.8 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206192 kb
Host smart-97042ae4-d13d-4cab-ba56-e4dd48b6004e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17171
96362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1717196362
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.517780586
Short name T363
Test name
Test status
Simulation time 227243414 ps
CPU time 0.94 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206184 kb
Host smart-1c04de86-a0ea-4ece-bf72-3adf8072960a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51778
0586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.517780586
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2525886439
Short name T794
Test name
Test status
Simulation time 23312595603 ps
CPU time 24.61 seconds
Started Jul 07 05:24:01 PM PDT 24
Finished Jul 07 05:24:26 PM PDT 24
Peak memory 206252 kb
Host smart-a70703e5-0644-49bb-9d06-2a05600665d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
86439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2525886439
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.4133369731
Short name T463
Test name
Test status
Simulation time 3283591577 ps
CPU time 4.62 seconds
Started Jul 07 05:23:52 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206228 kb
Host smart-a7fd9e21-39cc-4750-b4d0-9271c1be980c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41333
69731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.4133369731
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2696934291
Short name T2585
Test name
Test status
Simulation time 11652158339 ps
CPU time 109.85 seconds
Started Jul 07 05:23:54 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206472 kb
Host smart-26a40433-5cca-4da1-817b-491fb19c7aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
34291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2696934291
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3322192088
Short name T2055
Test name
Test status
Simulation time 7245312340 ps
CPU time 198.45 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:27:19 PM PDT 24
Peak memory 206468 kb
Host smart-8e1c9d33-578e-4d6e-b8cf-c67e70179ce4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3322192088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3322192088
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.4030055528
Short name T345
Test name
Test status
Simulation time 291781113 ps
CPU time 0.96 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206168 kb
Host smart-7edb39f3-8256-4b0b-9438-ed7403a0d0fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4030055528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.4030055528
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4155363438
Short name T1512
Test name
Test status
Simulation time 197542094 ps
CPU time 0.85 seconds
Started Jul 07 05:23:55 PM PDT 24
Finished Jul 07 05:23:57 PM PDT 24
Peak memory 206200 kb
Host smart-ebd6f03b-2af1-4300-bd26-718594d9cbae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
63438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4155363438
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.374744201
Short name T1154
Test name
Test status
Simulation time 6094464927 ps
CPU time 172.31 seconds
Started Jul 07 05:24:01 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 206468 kb
Host smart-3a475cc2-ba5a-4be3-a4ef-fb00094ee82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
4201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.374744201
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1386529012
Short name T1365
Test name
Test status
Simulation time 5227004222 ps
CPU time 48.11 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:54 PM PDT 24
Peak memory 206220 kb
Host smart-d180db5b-dbc0-4da7-a69e-63fb1787d3cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1386529012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1386529012
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.4238342287
Short name T614
Test name
Test status
Simulation time 216365399 ps
CPU time 0.86 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206104 kb
Host smart-a56ced27-3bd8-4195-8576-5066007adde2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4238342287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.4238342287
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.642402324
Short name T2364
Test name
Test status
Simulation time 142224826 ps
CPU time 0.83 seconds
Started Jul 07 05:23:57 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206196 kb
Host smart-0edb45da-12cf-4dc1-93d6-ac34104ac92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64240
2324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.642402324
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2786777879
Short name T2321
Test name
Test status
Simulation time 264014272 ps
CPU time 0.93 seconds
Started Jul 07 05:23:57 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206208 kb
Host smart-9fe698f6-3b6f-4996-bcdf-c22be3a86d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
77879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2786777879
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3664362991
Short name T1428
Test name
Test status
Simulation time 191166167 ps
CPU time 0.88 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206036 kb
Host smart-ba3d8e09-dbf3-4601-bce9-213b4ec0589b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
62991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3664362991
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2172825432
Short name T551
Test name
Test status
Simulation time 196525672 ps
CPU time 0.82 seconds
Started Jul 07 05:24:08 PM PDT 24
Finished Jul 07 05:24:10 PM PDT 24
Peak memory 206148 kb
Host smart-ff101f50-aea5-4059-a75e-b2af7ee9876c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21728
25432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2172825432
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3681996618
Short name T498
Test name
Test status
Simulation time 194235175 ps
CPU time 0.83 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206132 kb
Host smart-c24de48f-f7c8-4cda-940e-c06e00198c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819
96618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3681996618
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2060950713
Short name T2297
Test name
Test status
Simulation time 155540884 ps
CPU time 0.81 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206036 kb
Host smart-b23583b3-a3e8-4ae8-b2bd-542100d13403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20609
50713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2060950713
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3521819199
Short name T169
Test name
Test status
Simulation time 219548122 ps
CPU time 0.99 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206416 kb
Host smart-5ebb9608-12c6-4794-bb4b-8d8daa9ea6a0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3521819199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3521819199
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1148334844
Short name T1494
Test name
Test status
Simulation time 180418048 ps
CPU time 0.79 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206152 kb
Host smart-5a7544c7-9c34-46ac-81d8-924b7829743e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
34844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1148334844
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.384042224
Short name T1131
Test name
Test status
Simulation time 53792273 ps
CPU time 0.67 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206192 kb
Host smart-da730e9a-3b8a-4ee8-9a9c-288440856895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38404
2224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.384042224
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2338815262
Short name T2115
Test name
Test status
Simulation time 7330819636 ps
CPU time 17.63 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:29 PM PDT 24
Peak memory 206448 kb
Host smart-51f5c4c2-719e-4b8e-ab7b-43f380290142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23388
15262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2338815262
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3980242504
Short name T1282
Test name
Test status
Simulation time 179233177 ps
CPU time 0.89 seconds
Started Jul 07 05:23:57 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206200 kb
Host smart-b5186994-d510-4807-862d-24a1dd4c59fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802
42504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3980242504
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3298927462
Short name T816
Test name
Test status
Simulation time 255732874 ps
CPU time 0.91 seconds
Started Jul 07 05:23:57 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206200 kb
Host smart-ad6b18fd-c59c-4b85-be11-6750507c35a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
27462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3298927462
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1548400114
Short name T1781
Test name
Test status
Simulation time 157895350 ps
CPU time 0.78 seconds
Started Jul 07 05:23:53 PM PDT 24
Finished Jul 07 05:23:55 PM PDT 24
Peak memory 206204 kb
Host smart-363ae698-095b-4388-a654-5b33ce6a8c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15484
00114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1548400114
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2609946573
Short name T1373
Test name
Test status
Simulation time 192305873 ps
CPU time 0.83 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206128 kb
Host smart-762b110c-ab24-433a-bfc4-7ba6a46ea135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26099
46573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2609946573
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3043099470
Short name T1179
Test name
Test status
Simulation time 143118124 ps
CPU time 0.84 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206176 kb
Host smart-50ae9aa6-b2f0-4340-8129-21fbe8cd7e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
99470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3043099470
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1686731123
Short name T2671
Test name
Test status
Simulation time 194219092 ps
CPU time 0.86 seconds
Started Jul 07 05:24:04 PM PDT 24
Finished Jul 07 05:24:05 PM PDT 24
Peak memory 206148 kb
Host smart-029d1ddc-e150-44b0-aeb8-032a06b8c636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
31123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1686731123
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.172754498
Short name T2249
Test name
Test status
Simulation time 172884712 ps
CPU time 0.78 seconds
Started Jul 07 05:23:57 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206120 kb
Host smart-57e96dd7-f65c-4cd1-bc60-9b42f8f2a1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17275
4498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.172754498
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3808088679
Short name T1457
Test name
Test status
Simulation time 240178599 ps
CPU time 0.89 seconds
Started Jul 07 05:24:02 PM PDT 24
Finished Jul 07 05:24:03 PM PDT 24
Peak memory 206132 kb
Host smart-2e83a5ef-404c-4716-adf6-201d99088c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080
88679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3808088679
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.877921586
Short name T2488
Test name
Test status
Simulation time 3919480856 ps
CPU time 25.81 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206212 kb
Host smart-e037bc4c-eb28-4647-be58-251670e831f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=877921586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.877921586
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.546711437
Short name T561
Test name
Test status
Simulation time 142810801 ps
CPU time 0.83 seconds
Started Jul 07 05:23:56 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206204 kb
Host smart-687308f6-566c-4394-ae52-44d46bbec82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54671
1437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.546711437
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3673884428
Short name T1545
Test name
Test status
Simulation time 184251869 ps
CPU time 0.8 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:24:00 PM PDT 24
Peak memory 206156 kb
Host smart-a9fb1540-7317-48fb-ba3c-d3bb222af4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
84428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3673884428
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3242984032
Short name T1663
Test name
Test status
Simulation time 1095592246 ps
CPU time 2.55 seconds
Started Jul 07 05:23:57 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206144 kb
Host smart-bc9cd242-ad9e-4266-a755-96b21e2f50aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
84032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3242984032
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2540212628
Short name T1155
Test name
Test status
Simulation time 3581760195 ps
CPU time 30.86 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206248 kb
Host smart-ecfc1a20-e3b4-4e84-ad62-02e99fc869b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
12628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2540212628
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.709518045
Short name T2046
Test name
Test status
Simulation time 73472375 ps
CPU time 0.71 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206236 kb
Host smart-965528ec-73a3-440e-bcef-a47ed476e8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=709518045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.709518045
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.289929525
Short name T1676
Test name
Test status
Simulation time 3666884619 ps
CPU time 4.57 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206416 kb
Host smart-cb01af3a-8817-4376-aa87-7c7c18f869b8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=289929525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.289929525
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2512563294
Short name T1971
Test name
Test status
Simulation time 13404819430 ps
CPU time 13.8 seconds
Started Jul 07 05:24:04 PM PDT 24
Finished Jul 07 05:24:18 PM PDT 24
Peak memory 206228 kb
Host smart-0731faa1-8f51-4f7c-bf03-6f45372e61e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2512563294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2512563294
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.874519273
Short name T2148
Test name
Test status
Simulation time 23380493177 ps
CPU time 25.05 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 205984 kb
Host smart-a2454df0-4275-43f9-98c5-399fc73f1167
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=874519273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.874519273
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1921640584
Short name T1099
Test name
Test status
Simulation time 214273361 ps
CPU time 0.82 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:18 PM PDT 24
Peak memory 206112 kb
Host smart-aa7bd7fd-fc33-4eea-bb32-13439dfe78d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
40584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1921640584
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.131522642
Short name T1649
Test name
Test status
Simulation time 151341411 ps
CPU time 0.8 seconds
Started Jul 07 05:25:04 PM PDT 24
Finished Jul 07 05:25:06 PM PDT 24
Peak memory 204616 kb
Host smart-723e20a8-3a87-46c2-8b95-56f0a41cd743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13152
2642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.131522642
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2178743340
Short name T2515
Test name
Test status
Simulation time 513915821 ps
CPU time 1.94 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:24:03 PM PDT 24
Peak memory 206392 kb
Host smart-441f5726-deb3-40b5-a926-3353ae1caf9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21787
43340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2178743340
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.226932284
Short name T2039
Test name
Test status
Simulation time 784376013 ps
CPU time 2.13 seconds
Started Jul 07 05:24:01 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206384 kb
Host smart-d825c71e-9161-4253-a427-ffc89072d5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
2284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.226932284
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3625197410
Short name T1738
Test name
Test status
Simulation time 6129652409 ps
CPU time 13.01 seconds
Started Jul 07 05:24:04 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206444 kb
Host smart-80003e96-a42d-4910-9058-988b0e310774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36251
97410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3625197410
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.973910381
Short name T1877
Test name
Test status
Simulation time 366171054 ps
CPU time 1.15 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206124 kb
Host smart-14dd5b1b-5b75-4399-a03d-e897aedcc178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97391
0381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.973910381
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.620094602
Short name T1338
Test name
Test status
Simulation time 200783315 ps
CPU time 0.84 seconds
Started Jul 07 05:25:04 PM PDT 24
Finished Jul 07 05:25:06 PM PDT 24
Peak memory 204596 kb
Host smart-327aea31-b5ad-426c-93c0-56fe3de5d9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62009
4602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.620094602
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1821983313
Short name T506
Test name
Test status
Simulation time 90703164 ps
CPU time 0.7 seconds
Started Jul 07 05:24:05 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 206180 kb
Host smart-1f3a8cbd-24df-47d0-8fbb-11c6a09e4371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18219
83313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1821983313
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3833439140
Short name T927
Test name
Test status
Simulation time 802737696 ps
CPU time 1.91 seconds
Started Jul 07 05:24:01 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206292 kb
Host smart-e5161511-dd3a-48a3-8bd1-34f5df5b8a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
39140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3833439140
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1023820104
Short name T1416
Test name
Test status
Simulation time 261309666 ps
CPU time 1.96 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206428 kb
Host smart-85253a5c-26c1-4677-9b71-bf537d5378ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238
20104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1023820104
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.976895450
Short name T1869
Test name
Test status
Simulation time 292382515 ps
CPU time 0.96 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206176 kb
Host smart-50b651fe-76d3-442c-8ce8-3c381d8007eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97689
5450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.976895450
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.375711044
Short name T2638
Test name
Test status
Simulation time 134998170 ps
CPU time 0.72 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 205948 kb
Host smart-c74434be-f446-428d-a2ce-21c80f1c810f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
1044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.375711044
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3634271477
Short name T397
Test name
Test status
Simulation time 217236279 ps
CPU time 0.92 seconds
Started Jul 07 05:24:02 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206116 kb
Host smart-b3be013a-d25e-4d76-bcc6-b0f4e9ff28e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36342
71477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3634271477
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.667831105
Short name T2073
Test name
Test status
Simulation time 7480779041 ps
CPU time 68.85 seconds
Started Jul 07 05:24:01 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 206484 kb
Host smart-cc2ad54b-19e9-4dc0-bc33-63221e39057d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=667831105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.667831105
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.420835000
Short name T1080
Test name
Test status
Simulation time 199733232 ps
CPU time 0.85 seconds
Started Jul 07 05:24:04 PM PDT 24
Finished Jul 07 05:24:05 PM PDT 24
Peak memory 206184 kb
Host smart-f72ba064-e444-4d2e-9299-3d0bb037ef37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42083
5000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.420835000
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1407035400
Short name T623
Test name
Test status
Simulation time 23279500310 ps
CPU time 24.39 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 205996 kb
Host smart-92053251-dced-4860-93ce-0564e79d8d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
35400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1407035400
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2473421279
Short name T747
Test name
Test status
Simulation time 3317186300 ps
CPU time 3.45 seconds
Started Jul 07 05:25:45 PM PDT 24
Finished Jul 07 05:25:49 PM PDT 24
Peak memory 206000 kb
Host smart-99a4f31d-bb97-44bb-b9e1-c861fdf877b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
21279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2473421279
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3649006797
Short name T255
Test name
Test status
Simulation time 8345884595 ps
CPU time 207.43 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 206240 kb
Host smart-1bfd1c6b-2ead-4b7a-9601-c61ceb84a6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36490
06797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3649006797
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1677084340
Short name T1214
Test name
Test status
Simulation time 6163195912 ps
CPU time 156.27 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:28:12 PM PDT 24
Peak memory 206220 kb
Host smart-9069d592-caec-4532-9f66-c8143b2e837b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1677084340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1677084340
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.988107178
Short name T1322
Test name
Test status
Simulation time 255596888 ps
CPU time 1 seconds
Started Jul 07 05:24:03 PM PDT 24
Finished Jul 07 05:24:05 PM PDT 24
Peak memory 206176 kb
Host smart-f93610cc-bd6a-4350-8e5d-d9286a527c69
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=988107178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.988107178
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3976204025
Short name T2099
Test name
Test status
Simulation time 190866249 ps
CPU time 0.86 seconds
Started Jul 07 05:23:58 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 206088 kb
Host smart-48a6f38a-d76a-4345-aeab-f0ebe33dee3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39762
04025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3976204025
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2576838842
Short name T1502
Test name
Test status
Simulation time 4334578343 ps
CPU time 42.38 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:24:44 PM PDT 24
Peak memory 206448 kb
Host smart-8aaec1d0-be65-4da7-926c-eb301458a9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
38842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2576838842
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.252217688
Short name T2550
Test name
Test status
Simulation time 7849107218 ps
CPU time 54.93 seconds
Started Jul 07 05:24:02 PM PDT 24
Finished Jul 07 05:24:58 PM PDT 24
Peak memory 206480 kb
Host smart-e9644572-ac36-450c-85ea-60e2f17ab168
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=252217688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.252217688
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1784237967
Short name T2087
Test name
Test status
Simulation time 159642243 ps
CPU time 0.8 seconds
Started Jul 07 05:24:02 PM PDT 24
Finished Jul 07 05:24:03 PM PDT 24
Peak memory 205876 kb
Host smart-7b701cad-5a17-4be3-8f3b-d842989de845
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1784237967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1784237967
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.734981512
Short name T1488
Test name
Test status
Simulation time 152166001 ps
CPU time 0.82 seconds
Started Jul 07 05:24:02 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206044 kb
Host smart-fcc5eb2b-15d2-4f84-adc7-2b0d98e62102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73498
1512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.734981512
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3840972894
Short name T2592
Test name
Test status
Simulation time 170765626 ps
CPU time 0.82 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 205932 kb
Host smart-22e8cbce-f7c4-4394-9336-c728b26f33d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38409
72894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3840972894
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1059792688
Short name T1065
Test name
Test status
Simulation time 179512260 ps
CPU time 0.86 seconds
Started Jul 07 05:24:03 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206148 kb
Host smart-6253f34d-02f8-4ef1-a343-0a46e510c7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597
92688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1059792688
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2484251561
Short name T2397
Test name
Test status
Simulation time 223453253 ps
CPU time 0.88 seconds
Started Jul 07 05:23:59 PM PDT 24
Finished Jul 07 05:24:01 PM PDT 24
Peak memory 206168 kb
Host smart-e2a0168e-1f16-4c38-aec3-ef184a3f483a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24842
51561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2484251561
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3403876151
Short name T2480
Test name
Test status
Simulation time 171005255 ps
CPU time 0.79 seconds
Started Jul 07 05:24:00 PM PDT 24
Finished Jul 07 05:24:02 PM PDT 24
Peak memory 206124 kb
Host smart-0d317614-119a-4380-b1e1-1e588701216d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
76151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3403876151
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2461469259
Short name T2122
Test name
Test status
Simulation time 212145928 ps
CPU time 0.86 seconds
Started Jul 07 05:25:26 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 205936 kb
Host smart-9313941e-ce64-48d7-86c4-d8c3d09e34be
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2461469259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2461469259
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3671534006
Short name T541
Test name
Test status
Simulation time 171370226 ps
CPU time 0.8 seconds
Started Jul 07 05:24:18 PM PDT 24
Finished Jul 07 05:24:19 PM PDT 24
Peak memory 206132 kb
Host smart-972ef385-ad74-449e-985e-c40aba9816fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36715
34006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3671534006
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1208198386
Short name T1547
Test name
Test status
Simulation time 38381461 ps
CPU time 0.66 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206176 kb
Host smart-0b42a086-07af-4a89-ab63-be771acc0b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12081
98386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1208198386
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2591280199
Short name T2613
Test name
Test status
Simulation time 9374662624 ps
CPU time 21.64 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206732 kb
Host smart-9b991a25-b4c1-4399-9731-07f1368ef104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25912
80199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2591280199
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1390891185
Short name T1203
Test name
Test status
Simulation time 178445953 ps
CPU time 0.83 seconds
Started Jul 07 05:24:13 PM PDT 24
Finished Jul 07 05:24:14 PM PDT 24
Peak memory 206120 kb
Host smart-a80360ec-8491-4dbd-a551-e41e0378b4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13908
91185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1390891185
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.373171817
Short name T1716
Test name
Test status
Simulation time 158649128 ps
CPU time 0.81 seconds
Started Jul 07 05:24:08 PM PDT 24
Finished Jul 07 05:24:09 PM PDT 24
Peak memory 206180 kb
Host smart-91235166-e06e-4838-9015-461c765426b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
1817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.373171817
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3315050769
Short name T343
Test name
Test status
Simulation time 246650982 ps
CPU time 0.89 seconds
Started Jul 07 05:24:05 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 206432 kb
Host smart-9eb24602-8772-43af-9dc7-57726f32f14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33150
50769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3315050769
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1119212914
Short name T252
Test name
Test status
Simulation time 189912440 ps
CPU time 0.9 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206192 kb
Host smart-c5d6e36e-e25d-4a5e-86d3-deec0ce21a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192
12914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1119212914
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.121548732
Short name T1552
Test name
Test status
Simulation time 139136128 ps
CPU time 0.74 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206168 kb
Host smart-8a70acfc-44f6-4c1d-b479-b77121da8943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12154
8732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.121548732
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3629192103
Short name T1587
Test name
Test status
Simulation time 189282431 ps
CPU time 0.77 seconds
Started Jul 07 05:24:02 PM PDT 24
Finished Jul 07 05:24:03 PM PDT 24
Peak memory 206116 kb
Host smart-764daaed-38bf-4546-ab55-f53a4fb28ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36291
92103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3629192103
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1073706745
Short name T1615
Test name
Test status
Simulation time 178506052 ps
CPU time 0.84 seconds
Started Jul 07 05:24:03 PM PDT 24
Finished Jul 07 05:24:04 PM PDT 24
Peak memory 206184 kb
Host smart-a850f3ca-a95f-4740-95c0-d0dcb9f848a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10737
06745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1073706745
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.4289460895
Short name T2266
Test name
Test status
Simulation time 275390522 ps
CPU time 0.98 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206108 kb
Host smart-2e6661ba-f937-41ec-ba69-4979a3f4eb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42894
60895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.4289460895
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.970249369
Short name T1159
Test name
Test status
Simulation time 6557806714 ps
CPU time 185.35 seconds
Started Jul 07 05:24:08 PM PDT 24
Finished Jul 07 05:27:14 PM PDT 24
Peak memory 206492 kb
Host smart-cae78c7d-1dec-40c7-8aae-db95ab8127d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=970249369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.970249369
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1358876779
Short name T2645
Test name
Test status
Simulation time 191016862 ps
CPU time 0.91 seconds
Started Jul 07 05:24:06 PM PDT 24
Finished Jul 07 05:24:08 PM PDT 24
Peak memory 206200 kb
Host smart-72261b20-0d3a-408a-bbe9-7cd00b12c80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13588
76779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1358876779
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.504418995
Short name T1847
Test name
Test status
Simulation time 169210151 ps
CPU time 0.83 seconds
Started Jul 07 05:24:13 PM PDT 24
Finished Jul 07 05:24:14 PM PDT 24
Peak memory 206128 kb
Host smart-cb184b5f-389e-4e28-9fe3-b00aae01dd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50441
8995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.504418995
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.1544295159
Short name T2701
Test name
Test status
Simulation time 748878607 ps
CPU time 1.64 seconds
Started Jul 07 05:24:05 PM PDT 24
Finished Jul 07 05:24:07 PM PDT 24
Peak memory 206388 kb
Host smart-cf07ed09-859f-4e2c-b04d-763a933d9905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
95159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.1544295159
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2457924238
Short name T1642
Test name
Test status
Simulation time 3970642302 ps
CPU time 39.32 seconds
Started Jul 07 05:24:06 PM PDT 24
Finished Jul 07 05:24:46 PM PDT 24
Peak memory 206500 kb
Host smart-fc083dd1-9070-4fca-a614-b4d8ca02e599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24579
24238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2457924238
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1757233382
Short name T2631
Test name
Test status
Simulation time 113580118 ps
CPU time 0.8 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206260 kb
Host smart-e133a5fb-23f5-4975-8c0d-c01611506cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1757233382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1757233382
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3376708715
Short name T16
Test name
Test status
Simulation time 3493344039 ps
CPU time 4.67 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:19 PM PDT 24
Peak memory 206228 kb
Host smart-9199e68a-d395-4121-9528-102777ce196f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3376708715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3376708715
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.519991228
Short name T1677
Test name
Test status
Simulation time 13390624591 ps
CPU time 13.17 seconds
Started Jul 07 05:24:05 PM PDT 24
Finished Jul 07 05:24:18 PM PDT 24
Peak memory 206188 kb
Host smart-07ea8fa3-e1d5-4849-b497-8ecec5875673
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=519991228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.519991228
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.740059007
Short name T483
Test name
Test status
Simulation time 23373441213 ps
CPU time 31.06 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206144 kb
Host smart-86182e31-f294-4272-9dc7-ce8e02101b29
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=740059007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.740059007
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.219650602
Short name T85
Test name
Test status
Simulation time 169725154 ps
CPU time 0.89 seconds
Started Jul 07 05:24:06 PM PDT 24
Finished Jul 07 05:24:07 PM PDT 24
Peak memory 206196 kb
Host smart-3f3dd061-9e50-499a-9517-6852035122be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21965
0602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.219650602
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.4072662991
Short name T1431
Test name
Test status
Simulation time 175946165 ps
CPU time 0.82 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 206152 kb
Host smart-4351a25a-9690-4714-b932-f00bd322fcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40726
62991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.4072662991
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3179244102
Short name T2144
Test name
Test status
Simulation time 188775100 ps
CPU time 0.83 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206112 kb
Host smart-2f55c211-a287-4e5d-8926-d04ebdc9e309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31792
44102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3179244102
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1916043503
Short name T173
Test name
Test status
Simulation time 855178007 ps
CPU time 2.04 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:13 PM PDT 24
Peak memory 206304 kb
Host smart-327c114c-d1aa-476b-8136-be86c090867c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19160
43503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1916043503
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3287385940
Short name T2586
Test name
Test status
Simulation time 14535650684 ps
CPU time 29.37 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206368 kb
Host smart-3199fc3c-8f16-41fb-97a2-ee562ba16edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32873
85940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3287385940
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3026895618
Short name T1563
Test name
Test status
Simulation time 491737508 ps
CPU time 1.45 seconds
Started Jul 07 05:24:15 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206156 kb
Host smart-357b8e53-ade9-445b-a426-c89be89c31a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268
95618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3026895618
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3199443782
Short name T2108
Test name
Test status
Simulation time 149780134 ps
CPU time 0.77 seconds
Started Jul 07 05:24:06 PM PDT 24
Finished Jul 07 05:24:07 PM PDT 24
Peak memory 206200 kb
Host smart-7a6db270-8bbb-40e4-98ee-1f8218d7d247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994
43782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3199443782
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3696704830
Short name T1141
Test name
Test status
Simulation time 35344271 ps
CPU time 0.63 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206104 kb
Host smart-89ccd38e-5ac4-4aed-ac5b-2cc1a1a9b1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36967
04830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3696704830
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1903266453
Short name T871
Test name
Test status
Simulation time 982902653 ps
CPU time 2.31 seconds
Started Jul 07 05:24:18 PM PDT 24
Finished Jul 07 05:24:21 PM PDT 24
Peak memory 206296 kb
Host smart-09ad6d3e-1112-408e-9097-c7c733051555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19032
66453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1903266453
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1851820284
Short name T1103
Test name
Test status
Simulation time 179073935 ps
CPU time 2.14 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:14 PM PDT 24
Peak memory 206448 kb
Host smart-f50730cf-96b6-4d40-8135-a90ff2b66de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18518
20284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1851820284
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2033071429
Short name T2555
Test name
Test status
Simulation time 222853327 ps
CPU time 0.88 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 206180 kb
Host smart-7e1609d7-a3e1-4ca4-935a-f254fa030402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20330
71429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2033071429
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2385703339
Short name T817
Test name
Test status
Simulation time 146165282 ps
CPU time 0.76 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206128 kb
Host smart-a06a847f-b8d4-4750-aac7-b6f8a1c7c039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23857
03339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2385703339
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2354043139
Short name T887
Test name
Test status
Simulation time 215121963 ps
CPU time 0.87 seconds
Started Jul 07 05:24:08 PM PDT 24
Finished Jul 07 05:24:10 PM PDT 24
Peak memory 206164 kb
Host smart-ba503b82-aab1-4956-b45e-181a314760c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23540
43139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2354043139
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.2867041694
Short name T110
Test name
Test status
Simulation time 8454334631 ps
CPU time 78.62 seconds
Started Jul 07 05:24:20 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206448 kb
Host smart-46b9ea5e-822a-44fe-b64a-7b31fe3bb68b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2867041694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.2867041694
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2420397333
Short name T2663
Test name
Test status
Simulation time 205458436 ps
CPU time 0.94 seconds
Started Jul 07 05:24:07 PM PDT 24
Finished Jul 07 05:24:08 PM PDT 24
Peak memory 206192 kb
Host smart-97867df0-281e-4d59-a9e3-babcf63c1e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
97333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2420397333
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.372842081
Short name T1822
Test name
Test status
Simulation time 23428484192 ps
CPU time 27.63 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206272 kb
Host smart-604071b7-5368-41db-8cbe-a2560aad57e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37284
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.372842081
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3311554021
Short name T1420
Test name
Test status
Simulation time 3315439781 ps
CPU time 4.93 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:14 PM PDT 24
Peak memory 206264 kb
Host smart-334960e9-8993-4e80-9845-48dd6844adcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
54021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3311554021
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1108936865
Short name T1932
Test name
Test status
Simulation time 9875135657 ps
CPU time 73.35 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:25:28 PM PDT 24
Peak memory 206576 kb
Host smart-d91fcb13-9a57-4777-b37f-2aa2414f8cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
36865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1108936865
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.194463899
Short name T838
Test name
Test status
Simulation time 3578858374 ps
CPU time 31.73 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:43 PM PDT 24
Peak memory 206432 kb
Host smart-c14e086b-b258-4bad-b465-e3d0d5f4967a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=194463899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.194463899
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3556946484
Short name T163
Test name
Test status
Simulation time 275693407 ps
CPU time 0.94 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 206080 kb
Host smart-2c54f29b-c5a8-464a-8c68-f6b619cc19bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3556946484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3556946484
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2983841642
Short name T1164
Test name
Test status
Simulation time 203832633 ps
CPU time 0.91 seconds
Started Jul 07 05:24:26 PM PDT 24
Finished Jul 07 05:24:27 PM PDT 24
Peak memory 206188 kb
Host smart-94f40b53-604d-4309-b8df-b5d063110637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
41642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2983841642
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.349646251
Short name T1627
Test name
Test status
Simulation time 5469225973 ps
CPU time 54.28 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:25:04 PM PDT 24
Peak memory 206456 kb
Host smart-4f9282c4-3190-4496-b9a0-3e877258a45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34964
6251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.349646251
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3581615277
Short name T611
Test name
Test status
Simulation time 4190675781 ps
CPU time 39.49 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206400 kb
Host smart-ba235905-f778-4b4e-b78c-f52f87b61d04
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3581615277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3581615277
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1633736304
Short name T1689
Test name
Test status
Simulation time 159440172 ps
CPU time 0.81 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 206184 kb
Host smart-b4b15c94-edc8-4c8e-9bc8-a0382bc234d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1633736304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1633736304
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1764118219
Short name T488
Test name
Test status
Simulation time 152093978 ps
CPU time 0.84 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:10 PM PDT 24
Peak memory 206232 kb
Host smart-36d85743-236a-4872-b82e-d79f0dea5b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17641
18219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1764118219
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3954856682
Short name T133
Test name
Test status
Simulation time 211609267 ps
CPU time 0.82 seconds
Started Jul 07 05:24:15 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206188 kb
Host smart-eaa7b188-942e-4a66-b73e-0ac889742acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548
56682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3954856682
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3276521225
Short name T1907
Test name
Test status
Simulation time 229192062 ps
CPU time 0.93 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206096 kb
Host smart-52ec2621-7d0b-4aed-8bf2-0eda6575f8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32765
21225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3276521225
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1376098986
Short name T344
Test name
Test status
Simulation time 218257636 ps
CPU time 0.84 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206124 kb
Host smart-e916136f-6f2b-4f35-9636-63e2b433e997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
98986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1376098986
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2217811348
Short name T2703
Test name
Test status
Simulation time 210872098 ps
CPU time 0.87 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206116 kb
Host smart-f23d3cb2-41f2-4d45-9800-b67be28d0379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
11348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2217811348
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2011898093
Short name T2528
Test name
Test status
Simulation time 161635966 ps
CPU time 0.78 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:13 PM PDT 24
Peak memory 206120 kb
Host smart-08c1baf6-3d16-406a-aba6-3d1f920eef46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20118
98093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2011898093
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1695622491
Short name T2175
Test name
Test status
Simulation time 208274840 ps
CPU time 0.94 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206172 kb
Host smart-faee2987-82db-4f95-88ce-9f2c8a856dab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1695622491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1695622491
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1071801560
Short name T1194
Test name
Test status
Simulation time 158045545 ps
CPU time 0.77 seconds
Started Jul 07 05:24:11 PM PDT 24
Finished Jul 07 05:24:13 PM PDT 24
Peak memory 206116 kb
Host smart-10d70e11-2cf7-4c99-8f96-fb6e0663a235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10718
01560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1071801560
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.4210247824
Short name T2676
Test name
Test status
Simulation time 37599824 ps
CPU time 0.69 seconds
Started Jul 07 05:24:09 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206180 kb
Host smart-d2cedc09-6e94-42eb-bb09-cffc589fbe83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102
47824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.4210247824
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2981672726
Short name T309
Test name
Test status
Simulation time 21206181094 ps
CPU time 48.5 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206352 kb
Host smart-b2ca39bd-e850-47ff-9f54-3dc9ca78304b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29816
72726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2981672726
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3626827257
Short name T2152
Test name
Test status
Simulation time 169776383 ps
CPU time 0.83 seconds
Started Jul 07 05:24:15 PM PDT 24
Finished Jul 07 05:24:16 PM PDT 24
Peak memory 206204 kb
Host smart-4bcbf423-9775-4f81-b960-54eed4d2e93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36268
27257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3626827257
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.944043413
Short name T1086
Test name
Test status
Simulation time 171558291 ps
CPU time 0.83 seconds
Started Jul 07 05:24:12 PM PDT 24
Finished Jul 07 05:24:13 PM PDT 24
Peak memory 206124 kb
Host smart-aaa581cc-257e-434a-a214-1600d0e21969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94404
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.944043413
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.4058576475
Short name T2443
Test name
Test status
Simulation time 236131236 ps
CPU time 0.91 seconds
Started Jul 07 05:24:18 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206240 kb
Host smart-6ab8ac56-4f36-458e-8550-1e8eefd8976e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40585
76475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.4058576475
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2550250232
Short name T2409
Test name
Test status
Simulation time 190414896 ps
CPU time 0.86 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206188 kb
Host smart-c1e4912e-542b-402d-98ba-20df477c0712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25502
50232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2550250232
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.4049602003
Short name T1481
Test name
Test status
Simulation time 243366952 ps
CPU time 0.87 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:15 PM PDT 24
Peak memory 206036 kb
Host smart-ed24a023-8bd5-44ef-8151-56f3b0861d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40496
02003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.4049602003
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.4174323997
Short name T476
Test name
Test status
Simulation time 173417454 ps
CPU time 0.78 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:11 PM PDT 24
Peak memory 206176 kb
Host smart-10cfbca4-3a30-4f0d-acd9-f9e3b3834118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41743
23997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.4174323997
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.302725119
Short name T1767
Test name
Test status
Simulation time 205488204 ps
CPU time 0.9 seconds
Started Jul 07 05:24:20 PM PDT 24
Finished Jul 07 05:24:21 PM PDT 24
Peak memory 206196 kb
Host smart-86d4f34c-2f85-4f14-9f22-fe4b7351bb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30272
5119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.302725119
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2120937745
Short name T1017
Test name
Test status
Simulation time 191380641 ps
CPU time 0.86 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206100 kb
Host smart-7fc896a9-fdf2-4a42-9c94-b41e522d2b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21209
37745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2120937745
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3245780794
Short name T1890
Test name
Test status
Simulation time 5861468146 ps
CPU time 40 seconds
Started Jul 07 05:24:18 PM PDT 24
Finished Jul 07 05:24:58 PM PDT 24
Peak memory 206320 kb
Host smart-55c89615-42cb-4f43-a376-1a3a3ee2b643
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3245780794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3245780794
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.4134878091
Short name T1828
Test name
Test status
Simulation time 169063258 ps
CPU time 0.77 seconds
Started Jul 07 05:24:17 PM PDT 24
Finished Jul 07 05:24:18 PM PDT 24
Peak memory 206128 kb
Host smart-18c4223d-02d1-4935-8958-fe80d869c8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41348
78091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.4134878091
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.764289387
Short name T1437
Test name
Test status
Simulation time 151703067 ps
CPU time 0.75 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 206192 kb
Host smart-d7aca390-9804-43ce-96d3-61ce28ca5d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76428
9387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.764289387
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.2715392184
Short name T2215
Test name
Test status
Simulation time 508251322 ps
CPU time 1.44 seconds
Started Jul 07 05:24:15 PM PDT 24
Finished Jul 07 05:24:17 PM PDT 24
Peak memory 206204 kb
Host smart-1cd88bbd-2683-4af8-a4c9-3bbe4e109d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27153
92184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2715392184
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.694643627
Short name T1323
Test name
Test status
Simulation time 4365196458 ps
CPU time 125.84 seconds
Started Jul 07 05:24:12 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206528 kb
Host smart-da3cabf9-6a3a-4009-b182-78ceb5948bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69464
3627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.694643627
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.358494365
Short name T1166
Test name
Test status
Simulation time 46524061 ps
CPU time 0.71 seconds
Started Jul 07 05:24:21 PM PDT 24
Finished Jul 07 05:24:22 PM PDT 24
Peak memory 206228 kb
Host smart-c5fc8d3b-ba6d-4e1c-baa2-e3025fbb21e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=358494365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.358494365
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.333483001
Short name T10
Test name
Test status
Simulation time 3720092838 ps
CPU time 4.13 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206492 kb
Host smart-378601b7-b72c-4b5b-8371-e52cceadb1b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=333483001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.333483001
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3802199193
Short name T820
Test name
Test status
Simulation time 13387287452 ps
CPU time 12.33 seconds
Started Jul 07 05:24:10 PM PDT 24
Finished Jul 07 05:24:23 PM PDT 24
Peak memory 206420 kb
Host smart-eb690b19-3ea4-404a-aa0d-0d404d16b7db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3802199193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3802199193
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1194037445
Short name T218
Test name
Test status
Simulation time 23465781827 ps
CPU time 23.52 seconds
Started Jul 07 05:24:24 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206480 kb
Host smart-4b0c3f41-a970-48ae-b865-d1867654fa90
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1194037445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1194037445
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.959495293
Short name T1819
Test name
Test status
Simulation time 151587692 ps
CPU time 0.81 seconds
Started Jul 07 05:24:21 PM PDT 24
Finished Jul 07 05:24:23 PM PDT 24
Peak memory 206212 kb
Host smart-646ef2e8-133c-4fc8-a3b0-cc206004bb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95949
5293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.959495293
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1919896185
Short name T1130
Test name
Test status
Simulation time 145164845 ps
CPU time 0.79 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206188 kb
Host smart-2e09cac2-5127-4a1a-bbf1-73ff368f12f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
96185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1919896185
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2724389192
Short name T552
Test name
Test status
Simulation time 236590364 ps
CPU time 0.99 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206188 kb
Host smart-ad7bef03-b5e1-4370-be2e-f8f8e6ab7fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
89192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2724389192
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1390578501
Short name T1734
Test name
Test status
Simulation time 645609790 ps
CPU time 1.73 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:21 PM PDT 24
Peak memory 206184 kb
Host smart-ad5ee548-4f33-4c45-9493-1611ec7e09b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13905
78501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1390578501
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.162216159
Short name T2016
Test name
Test status
Simulation time 11975186942 ps
CPU time 23.02 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206456 kb
Host smart-ae0d5df7-e367-4305-9186-9667bf2f016b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16221
6159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.162216159
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1155355533
Short name T808
Test name
Test status
Simulation time 465360880 ps
CPU time 1.48 seconds
Started Jul 07 05:24:17 PM PDT 24
Finished Jul 07 05:24:19 PM PDT 24
Peak memory 206200 kb
Host smart-e575a972-6117-4c91-967c-dc79a1f8ee0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
55533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1155355533
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2076688222
Short name T1778
Test name
Test status
Simulation time 172754332 ps
CPU time 0.8 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206184 kb
Host smart-3e726279-801f-4c77-a4e0-09f868295a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20766
88222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2076688222
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.725557902
Short name T1478
Test name
Test status
Simulation time 80044796 ps
CPU time 0.76 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206200 kb
Host smart-28a11543-67e7-451f-9949-f83313b06e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72555
7902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.725557902
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2395978488
Short name T830
Test name
Test status
Simulation time 826874560 ps
CPU time 2.12 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:19 PM PDT 24
Peak memory 206404 kb
Host smart-93787930-5806-4631-9adb-253b5f62d35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
78488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2395978488
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1968525879
Short name T2038
Test name
Test status
Simulation time 188373824 ps
CPU time 2.23 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206404 kb
Host smart-ba1bafb3-6610-4ddf-96ef-4ee890c0830d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19685
25879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1968525879
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4275180147
Short name T1633
Test name
Test status
Simulation time 231881046 ps
CPU time 0.98 seconds
Started Jul 07 05:24:18 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206180 kb
Host smart-8190b2d2-a504-4c17-855e-0c7304e4f479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42751
80147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4275180147
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2509848262
Short name T1384
Test name
Test status
Simulation time 197122857 ps
CPU time 0.86 seconds
Started Jul 07 05:24:22 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206180 kb
Host smart-b7e5d33b-1d68-4885-b092-2d227bcc279a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25098
48262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2509848262
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3281090755
Short name T2256
Test name
Test status
Simulation time 221060044 ps
CPU time 0.92 seconds
Started Jul 07 05:24:20 PM PDT 24
Finished Jul 07 05:24:21 PM PDT 24
Peak memory 206196 kb
Host smart-118b614c-8dc3-4680-88f5-2a8b4edc0050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32810
90755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3281090755
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2491900743
Short name T1719
Test name
Test status
Simulation time 238979855 ps
CPU time 0.95 seconds
Started Jul 07 05:24:27 PM PDT 24
Finished Jul 07 05:24:29 PM PDT 24
Peak memory 206032 kb
Host smart-c9c1882a-5555-4bb8-98e9-7540aefc8f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24919
00743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2491900743
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1052227594
Short name T2396
Test name
Test status
Simulation time 23337221783 ps
CPU time 23.94 seconds
Started Jul 07 05:24:16 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206252 kb
Host smart-23f482a3-d346-4a32-9dc4-b58d7bdd4038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10522
27594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1052227594
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.127242613
Short name T739
Test name
Test status
Simulation time 3303437691 ps
CPU time 3.91 seconds
Started Jul 07 05:24:26 PM PDT 24
Finished Jul 07 05:24:30 PM PDT 24
Peak memory 206504 kb
Host smart-8c22aa05-0088-4b19-891e-6a61d2e07e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
2613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.127242613
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.4132447055
Short name T2053
Test name
Test status
Simulation time 9713600576 ps
CPU time 90.85 seconds
Started Jul 07 05:24:22 PM PDT 24
Finished Jul 07 05:25:54 PM PDT 24
Peak memory 206536 kb
Host smart-9ae037da-395a-43eb-a995-37f1b557295b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41324
47055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.4132447055
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2089445567
Short name T2469
Test name
Test status
Simulation time 5120908480 ps
CPU time 34.73 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:58 PM PDT 24
Peak memory 206532 kb
Host smart-4e9d667e-2e3e-496f-a9b7-a7455ac3f9c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2089445567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2089445567
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.4280315494
Short name T1803
Test name
Test status
Simulation time 287080832 ps
CPU time 0.95 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206172 kb
Host smart-3b720df6-a3bb-49ed-b5e9-bd06b23e7ab4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4280315494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.4280315494
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2132593945
Short name T365
Test name
Test status
Simulation time 231086853 ps
CPU time 0.92 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:24:34 PM PDT 24
Peak memory 206036 kb
Host smart-1e92e176-f032-4a77-bdb3-4a699ac553ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21325
93945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2132593945
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1228247530
Short name T1318
Test name
Test status
Simulation time 5094021213 ps
CPU time 36.41 seconds
Started Jul 07 05:24:14 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206312 kb
Host smart-a55b8a3e-e21a-4798-a7c1-016938212284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
47530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1228247530
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1871413755
Short name T2395
Test name
Test status
Simulation time 5830514580 ps
CPU time 160.4 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 206424 kb
Host smart-9d0e4322-f795-438a-9d4f-c1efcc72d202
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1871413755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1871413755
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3847815418
Short name T958
Test name
Test status
Simulation time 223107219 ps
CPU time 0.89 seconds
Started Jul 07 05:24:24 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206164 kb
Host smart-2f90288f-552b-42a0-a72c-170325373818
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3847815418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3847815418
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3834086624
Short name T729
Test name
Test status
Simulation time 149400142 ps
CPU time 0.77 seconds
Started Jul 07 05:24:17 PM PDT 24
Finished Jul 07 05:24:23 PM PDT 24
Peak memory 206188 kb
Host smart-60d6386e-0fee-4f04-afe7-f00c0fdc3520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
86624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3834086624
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3592898877
Short name T883
Test name
Test status
Simulation time 175791398 ps
CPU time 0.85 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206184 kb
Host smart-f67bd8ca-d770-47c8-bf1b-d265d0a125e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35928
98877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3592898877
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.576267708
Short name T1737
Test name
Test status
Simulation time 237234024 ps
CPU time 0.91 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206180 kb
Host smart-de3a1c73-b8c7-4f45-96f7-507f56881457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57626
7708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.576267708
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1781633657
Short name T2318
Test name
Test status
Simulation time 211110962 ps
CPU time 0.81 seconds
Started Jul 07 05:24:17 PM PDT 24
Finished Jul 07 05:24:19 PM PDT 24
Peak memory 206152 kb
Host smart-603c06e8-545b-44e7-b555-19b97f9a2350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17816
33657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1781633657
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1852748731
Short name T1679
Test name
Test status
Simulation time 155274299 ps
CPU time 0.82 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206228 kb
Host smart-0731cf1b-6871-417a-939b-93d6e057c10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18527
48731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1852748731
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1207723973
Short name T1860
Test name
Test status
Simulation time 172616847 ps
CPU time 0.85 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206188 kb
Host smart-eac1aa40-05b7-4813-bff4-82717a1ad97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
23973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1207723973
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3395922235
Short name T677
Test name
Test status
Simulation time 210630367 ps
CPU time 0.9 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206152 kb
Host smart-12424fd3-fdfe-4f4d-a938-ba044838340e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3395922235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3395922235
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.319610048
Short name T2224
Test name
Test status
Simulation time 144061707 ps
CPU time 0.84 seconds
Started Jul 07 05:24:42 PM PDT 24
Finished Jul 07 05:24:43 PM PDT 24
Peak memory 206196 kb
Host smart-83d9bfc9-df22-456e-beb7-4118ed2de31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
0048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.319610048
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3457663251
Short name T1675
Test name
Test status
Simulation time 36691913 ps
CPU time 0.62 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:20 PM PDT 24
Peak memory 206176 kb
Host smart-7ad53945-bf13-48e6-905d-826d5320660e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34576
63251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3457663251
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.632729337
Short name T268
Test name
Test status
Simulation time 8917940161 ps
CPU time 19.78 seconds
Started Jul 07 05:24:29 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206528 kb
Host smart-f4e6b32d-5168-4d8a-ad38-c78d823c1dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63272
9337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.632729337
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2226909547
Short name T81
Test name
Test status
Simulation time 181120206 ps
CPU time 0.85 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206120 kb
Host smart-5139ab2f-0910-4146-9325-308b415b68a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22269
09547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2226909547
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2727284342
Short name T992
Test name
Test status
Simulation time 227089879 ps
CPU time 0.95 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:31 PM PDT 24
Peak memory 206128 kb
Host smart-8a2eea20-9a41-4403-a1e9-998675a87f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27272
84342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2727284342
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2314829237
Short name T511
Test name
Test status
Simulation time 239982708 ps
CPU time 0.85 seconds
Started Jul 07 05:24:22 PM PDT 24
Finished Jul 07 05:24:23 PM PDT 24
Peak memory 206136 kb
Host smart-77fe7b03-7989-4e83-9dbe-d18b29fe59a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148
29237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2314829237
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2886623028
Short name T2447
Test name
Test status
Simulation time 255550538 ps
CPU time 0.92 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206144 kb
Host smart-082f9485-0e67-4019-96ee-4faf2277d161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28866
23028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2886623028
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.878890102
Short name T721
Test name
Test status
Simulation time 142749094 ps
CPU time 0.79 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206208 kb
Host smart-8e95fa55-e063-4b5f-ba31-3c132a64d24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87889
0102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.878890102
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.4077361874
Short name T634
Test name
Test status
Simulation time 153003892 ps
CPU time 0.77 seconds
Started Jul 07 05:24:20 PM PDT 24
Finished Jul 07 05:24:21 PM PDT 24
Peak memory 206424 kb
Host smart-55a62754-6c81-4a00-b924-c0f53d5d252f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
61874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.4077361874
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3197597854
Short name T1244
Test name
Test status
Simulation time 154475017 ps
CPU time 0.78 seconds
Started Jul 07 05:24:20 PM PDT 24
Finished Jul 07 05:24:21 PM PDT 24
Peak memory 206200 kb
Host smart-7aef2025-15ec-4637-8c17-862dd1426845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
97854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3197597854
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3623783665
Short name T2463
Test name
Test status
Simulation time 190742260 ps
CPU time 0.93 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206192 kb
Host smart-cb54ea89-f01e-4e60-983d-d260621d5430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
83665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3623783665
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3913682327
Short name T1030
Test name
Test status
Simulation time 4618505360 ps
CPU time 120.4 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:26:31 PM PDT 24
Peak memory 206724 kb
Host smart-bf3f3559-b961-4cff-9f33-9c4c026e9319
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3913682327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3913682327
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.398904062
Short name T1542
Test name
Test status
Simulation time 167847428 ps
CPU time 0.81 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206140 kb
Host smart-4e27b754-b56c-4b7a-a3c2-4be30baf401c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
4062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.398904062
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.881931808
Short name T2690
Test name
Test status
Simulation time 164105460 ps
CPU time 0.79 seconds
Started Jul 07 05:24:21 PM PDT 24
Finished Jul 07 05:24:22 PM PDT 24
Peak memory 206196 kb
Host smart-6a6ab0df-0f57-408a-b0cd-084b0177ff04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88193
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.881931808
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3197836854
Short name T1366
Test name
Test status
Simulation time 1276616654 ps
CPU time 2.83 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:27 PM PDT 24
Peak memory 206436 kb
Host smart-4a21a592-fdcd-4851-abc6-f017ecd5a82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978
36854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3197836854
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.852021192
Short name T733
Test name
Test status
Simulation time 4264181157 ps
CPU time 117.11 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206428 kb
Host smart-8042d4d5-3212-4819-b3c4-b11f1dad24e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85202
1192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.852021192
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.604744554
Short name T2353
Test name
Test status
Simulation time 54975714 ps
CPU time 0.71 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206220 kb
Host smart-2ddf7421-bb20-493d-b4d3-31fb2a4c1376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=604744554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.604744554
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.4207042633
Short name T2285
Test name
Test status
Simulation time 3676614099 ps
CPU time 4.56 seconds
Started Jul 07 05:24:22 PM PDT 24
Finished Jul 07 05:24:27 PM PDT 24
Peak memory 206136 kb
Host smart-fa3fdec1-9418-41ba-aa60-5e2f043e1017
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4207042633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.4207042633
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4189006626
Short name T2711
Test name
Test status
Simulation time 13298957843 ps
CPU time 13.96 seconds
Started Jul 07 05:24:21 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206208 kb
Host smart-4efa4dde-dcbf-4123-b9d5-3844637cfcf0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4189006626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4189006626
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3686187678
Short name T1389
Test name
Test status
Simulation time 23338140601 ps
CPU time 21.54 seconds
Started Jul 07 05:24:29 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206416 kb
Host smart-d339b43f-7480-43be-a9cc-88d7b0050fbd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3686187678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3686187678
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.90072147
Short name T1852
Test name
Test status
Simulation time 171614517 ps
CPU time 0.9 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:32 PM PDT 24
Peak memory 206120 kb
Host smart-11a11111-4814-4b45-a312-206ae73620f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90072
147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.90072147
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.310771150
Short name T667
Test name
Test status
Simulation time 199072394 ps
CPU time 0.87 seconds
Started Jul 07 05:24:28 PM PDT 24
Finished Jul 07 05:24:29 PM PDT 24
Peak memory 206196 kb
Host smart-7f5013c2-40bd-4a71-9a94-3f1de3e31dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31077
1150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.310771150
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3687079950
Short name T1713
Test name
Test status
Simulation time 367947133 ps
CPU time 1.25 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206212 kb
Host smart-fe8a9416-afad-4737-a2f5-30bacba26ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
79950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3687079950
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1823789565
Short name T2355
Test name
Test status
Simulation time 1190837974 ps
CPU time 2.8 seconds
Started Jul 07 05:24:19 PM PDT 24
Finished Jul 07 05:24:22 PM PDT 24
Peak memory 206344 kb
Host smart-b45f48da-0923-4b50-bc8b-984bce977a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18237
89565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1823789565
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3938976168
Short name T936
Test name
Test status
Simulation time 9542833954 ps
CPU time 17.68 seconds
Started Jul 07 05:24:28 PM PDT 24
Finished Jul 07 05:24:46 PM PDT 24
Peak memory 206444 kb
Host smart-c90c0d4c-1a57-4363-9b02-a684b44c6053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39389
76168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3938976168
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.481938713
Short name T1300
Test name
Test status
Simulation time 386718369 ps
CPU time 1.25 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:32 PM PDT 24
Peak memory 206120 kb
Host smart-e6f83f83-2506-4b07-9200-7b7db66d1872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48193
8713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.481938713
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1440952918
Short name T852
Test name
Test status
Simulation time 146345172 ps
CPU time 0.79 seconds
Started Jul 07 05:24:22 PM PDT 24
Finished Jul 07 05:24:23 PM PDT 24
Peak memory 206208 kb
Host smart-b12ca998-1e95-42cf-82b9-45eaad1c87ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14409
52918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1440952918
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1391076694
Short name T2471
Test name
Test status
Simulation time 56234718 ps
CPU time 0.68 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:25 PM PDT 24
Peak memory 206192 kb
Host smart-6ef90350-a4d8-46e5-828e-06a16a66f74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13910
76694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1391076694
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1441884953
Short name T165
Test name
Test status
Simulation time 859674313 ps
CPU time 2.33 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206376 kb
Host smart-02ff89d9-a34c-43dd-b50c-2a0b66e31ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14418
84953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1441884953
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3854086431
Short name T1714
Test name
Test status
Simulation time 162500779 ps
CPU time 1.22 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206332 kb
Host smart-0f5fb965-f006-4079-8cb3-63bb0fdb8f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38540
86431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3854086431
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3590153062
Short name T1958
Test name
Test status
Simulation time 213839921 ps
CPU time 0.89 seconds
Started Jul 07 05:24:25 PM PDT 24
Finished Jul 07 05:24:27 PM PDT 24
Peak memory 206184 kb
Host smart-b1048e04-8e70-4ad0-816b-7b867b6effa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35901
53062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3590153062
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1261164958
Short name T750
Test name
Test status
Simulation time 145011144 ps
CPU time 0.74 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:24:34 PM PDT 24
Peak memory 206188 kb
Host smart-4e2f4c7a-84c4-4db7-b308-b39c3cccb0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611
64958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1261164958
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3009185175
Short name T779
Test name
Test status
Simulation time 215576067 ps
CPU time 0.93 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206204 kb
Host smart-74ebce12-bc30-45cf-8d9b-0bb98c1e73a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
85175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3009185175
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2729722414
Short name T2620
Test name
Test status
Simulation time 241326774 ps
CPU time 0.89 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206032 kb
Host smart-1c0c9518-e2d2-4885-afa5-cbc75f522d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27297
22414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2729722414
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1232255107
Short name T610
Test name
Test status
Simulation time 23304872732 ps
CPU time 24.45 seconds
Started Jul 07 05:24:28 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206248 kb
Host smart-baf65394-b659-4e8b-bc05-794101177a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12322
55107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1232255107
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1036597603
Short name T254
Test name
Test status
Simulation time 3337353878 ps
CPU time 3.61 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206272 kb
Host smart-ac79a601-77b9-4e57-85f3-8f29ffe89383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10365
97603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1036597603
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.808091437
Short name T1495
Test name
Test status
Simulation time 6547324430 ps
CPU time 186.16 seconds
Started Jul 07 05:24:24 PM PDT 24
Finished Jul 07 05:27:31 PM PDT 24
Peak memory 206528 kb
Host smart-a4ffcfe7-e975-4b7e-a935-5c8998e67474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80809
1437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.808091437
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.4163831367
Short name T941
Test name
Test status
Simulation time 4551645488 ps
CPU time 128.26 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 206400 kb
Host smart-f68a60ea-84e4-49ca-8c9f-cb8fb4fd71fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4163831367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.4163831367
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.263285737
Short name T1937
Test name
Test status
Simulation time 284636431 ps
CPU time 1 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206144 kb
Host smart-9216909d-8aaf-4add-82e6-a08e5912d316
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=263285737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.263285737
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3452365852
Short name T539
Test name
Test status
Simulation time 189528675 ps
CPU time 0.88 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:24:42 PM PDT 24
Peak memory 206164 kb
Host smart-f97c7f08-d07b-4cd3-b34f-68ba78d1edd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34523
65852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3452365852
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1134527476
Short name T274
Test name
Test status
Simulation time 6165942160 ps
CPU time 56.86 seconds
Started Jul 07 05:24:22 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206460 kb
Host smart-37405d99-d5aa-44a5-8ce3-0001c515ffe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11345
27476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1134527476
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3888657075
Short name T2231
Test name
Test status
Simulation time 3522182264 ps
CPU time 92.6 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206484 kb
Host smart-1d1c387b-0d2f-4526-b37b-d4a1b3dfbaaf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3888657075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3888657075
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.455289192
Short name T1334
Test name
Test status
Simulation time 166169882 ps
CPU time 0.85 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206140 kb
Host smart-e6a18976-362d-4bf7-b892-7bd223fa001c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=455289192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.455289192
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1153160197
Short name T724
Test name
Test status
Simulation time 192892023 ps
CPU time 0.8 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206156 kb
Host smart-ce534411-c733-40a6-ac28-a6b124bc2422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11531
60197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1153160197
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1452788821
Short name T159
Test name
Test status
Simulation time 259061303 ps
CPU time 0.89 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206160 kb
Host smart-932f171a-a0fc-4ed8-8b57-4ec0c70909eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527
88821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1452788821
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3948726608
Short name T2693
Test name
Test status
Simulation time 189716830 ps
CPU time 0.86 seconds
Started Jul 07 05:24:36 PM PDT 24
Finished Jul 07 05:24:39 PM PDT 24
Peak memory 206148 kb
Host smart-c470b29e-0012-4f9a-802f-a3890c44ca56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
26608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3948726608
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3757734835
Short name T1127
Test name
Test status
Simulation time 170740591 ps
CPU time 0.81 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206184 kb
Host smart-f18af2f0-0fc4-4f81-a47a-ff3fc4825260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
34835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3757734835
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3815086306
Short name T439
Test name
Test status
Simulation time 192718729 ps
CPU time 0.95 seconds
Started Jul 07 05:24:26 PM PDT 24
Finished Jul 07 05:24:27 PM PDT 24
Peak memory 206100 kb
Host smart-6c110c42-41b4-46a5-b9b4-1bceaa599f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38150
86306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3815086306
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2813804624
Short name T951
Test name
Test status
Simulation time 195848687 ps
CPU time 0.82 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206168 kb
Host smart-d6c604ef-50bc-4cce-af80-ac258a74cbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28138
04624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2813804624
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3010101667
Short name T2250
Test name
Test status
Simulation time 242759289 ps
CPU time 1.01 seconds
Started Jul 07 05:24:24 PM PDT 24
Finished Jul 07 05:24:26 PM PDT 24
Peak memory 206152 kb
Host smart-5da09620-fb6b-4d20-aaba-b06f00ba6a5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3010101667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3010101667
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2666024101
Short name T2715
Test name
Test status
Simulation time 150018518 ps
CPU time 0.76 seconds
Started Jul 07 05:24:23 PM PDT 24
Finished Jul 07 05:24:24 PM PDT 24
Peak memory 206132 kb
Host smart-be932694-c031-4d8b-b295-88e829c24fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
24101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2666024101
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.984209533
Short name T90
Test name
Test status
Simulation time 23739458342 ps
CPU time 55.56 seconds
Started Jul 07 05:24:26 PM PDT 24
Finished Jul 07 05:25:22 PM PDT 24
Peak memory 206356 kb
Host smart-f59d710d-3607-48c0-852c-19c82d6bae40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98420
9533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.984209533
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.224974121
Short name T27
Test name
Test status
Simulation time 193448041 ps
CPU time 0.84 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:31 PM PDT 24
Peak memory 206188 kb
Host smart-c5bba514-1e5b-4b2e-9bca-1abde2a0fbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
4121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.224974121
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3865818632
Short name T846
Test name
Test status
Simulation time 236412601 ps
CPU time 0.87 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206160 kb
Host smart-eff9edba-c49a-46d1-81c3-f8b40e63ef47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38658
18632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3865818632
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2116550504
Short name T2522
Test name
Test status
Simulation time 214210680 ps
CPU time 0.88 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206192 kb
Host smart-81651453-afc1-4a50-9f1b-233461be08d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
50504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2116550504
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.480893887
Short name T2160
Test name
Test status
Simulation time 182965080 ps
CPU time 0.86 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:24:42 PM PDT 24
Peak memory 206192 kb
Host smart-db02e00c-5f53-4be0-9478-bf6617252020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48089
3887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.480893887
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.940275308
Short name T2014
Test name
Test status
Simulation time 165092914 ps
CPU time 0.78 seconds
Started Jul 07 05:24:38 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206200 kb
Host smart-dd82368d-205a-43aa-bc3e-1550fa695d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94027
5308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.940275308
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2250211341
Short name T120
Test name
Test status
Simulation time 158392204 ps
CPU time 0.78 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206116 kb
Host smart-47c71775-35b2-4d52-930b-4bb82a63fb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22502
11341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2250211341
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3147966152
Short name T103
Test name
Test status
Simulation time 170356575 ps
CPU time 0.79 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:31 PM PDT 24
Peak memory 206192 kb
Host smart-bae2be92-183a-452e-84cb-6fef8bb73dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31479
66152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3147966152
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.744401864
Short name T1378
Test name
Test status
Simulation time 255462338 ps
CPU time 0.95 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206116 kb
Host smart-2dfddea3-ef51-4a11-a7de-a7c856a1ac9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74440
1864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.744401864
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.22874672
Short name T1972
Test name
Test status
Simulation time 6304260833 ps
CPU time 164.13 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:27:17 PM PDT 24
Peak memory 206480 kb
Host smart-e234c287-010f-43b7-9f7e-1781756ac9c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=22874672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.22874672
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.175188467
Short name T1983
Test name
Test status
Simulation time 190130893 ps
CPU time 0.8 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206164 kb
Host smart-44d9175c-f0a6-4bd3-b77a-18da7b67f39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17518
8467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.175188467
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1051100
Short name T1455
Test name
Test status
Simulation time 168279992 ps
CPU time 0.84 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206152 kb
Host smart-7c0c1fa3-5562-413a-9748-fad2bc695d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
00 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1051100
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2967933186
Short name T2007
Test name
Test status
Simulation time 428375436 ps
CPU time 1.28 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:32 PM PDT 24
Peak memory 206184 kb
Host smart-af09098a-8d51-4d21-b2c5-54bd37c1d45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29679
33186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2967933186
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3922661502
Short name T1258
Test name
Test status
Simulation time 4003100521 ps
CPU time 39.25 seconds
Started Jul 07 05:24:29 PM PDT 24
Finished Jul 07 05:25:08 PM PDT 24
Peak memory 206484 kb
Host smart-87865042-8d29-492e-af24-d0076f5318a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
61502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3922661502
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.3966853401
Short name T2234
Test name
Test status
Simulation time 36372930 ps
CPU time 0.63 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206156 kb
Host smart-c61eff5c-b72a-4b8d-822d-ca8a67dd5a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3966853401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3966853401
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2738888572
Short name T2133
Test name
Test status
Simulation time 3844797719 ps
CPU time 4.37 seconds
Started Jul 07 05:24:29 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206268 kb
Host smart-ef490380-69c5-4df6-8778-98ffd8e8e32d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2738888572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2738888572
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.140978632
Short name T2603
Test name
Test status
Simulation time 13332598305 ps
CPU time 12.6 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206468 kb
Host smart-40395ae7-af14-4e5c-8b46-ce61cf7c1caf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=140978632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.140978632
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1643188029
Short name T14
Test name
Test status
Simulation time 23434666482 ps
CPU time 25.66 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 206436 kb
Host smart-5ae532ee-f15d-4007-8180-193a366f64da
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1643188029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1643188029
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2040214144
Short name T2419
Test name
Test status
Simulation time 194603828 ps
CPU time 0.83 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:31 PM PDT 24
Peak memory 206204 kb
Host smart-e5655632-43f6-425d-82de-e7cf209c6913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
14144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2040214144
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.4040948603
Short name T485
Test name
Test status
Simulation time 197693296 ps
CPU time 0.79 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206160 kb
Host smart-8d9a03b6-619e-4079-9482-c12b23418417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409
48603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.4040948603
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2420563146
Short name T2184
Test name
Test status
Simulation time 515630733 ps
CPU time 1.57 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:31 PM PDT 24
Peak memory 206468 kb
Host smart-63b56d43-c520-48f4-bbd7-f353ba1e0a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
63146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2420563146
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3690910854
Short name T945
Test name
Test status
Simulation time 786535784 ps
CPU time 1.88 seconds
Started Jul 07 05:24:28 PM PDT 24
Finished Jul 07 05:24:30 PM PDT 24
Peak memory 206380 kb
Host smart-970ce612-9fce-4440-bdb4-bf4df32402fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36909
10854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3690910854
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3000339567
Short name T978
Test name
Test status
Simulation time 5851320175 ps
CPU time 11.99 seconds
Started Jul 07 05:24:28 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206372 kb
Host smart-cfd19558-e3e3-4156-b156-9584186dde90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30003
39567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3000339567
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4204771005
Short name T791
Test name
Test status
Simulation time 419290938 ps
CPU time 1.28 seconds
Started Jul 07 05:24:30 PM PDT 24
Finished Jul 07 05:24:32 PM PDT 24
Peak memory 206112 kb
Host smart-ba3a921b-48a3-4e63-9c28-e81d05ee3ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42047
71005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4204771005
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2799371265
Short name T867
Test name
Test status
Simulation time 135114712 ps
CPU time 0.78 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206200 kb
Host smart-84b6f674-6f21-483d-bf51-eee0fa29484f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
71265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2799371265
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2418299769
Short name T396
Test name
Test status
Simulation time 52903110 ps
CPU time 0.68 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206144 kb
Host smart-6cf0f72a-b49a-4edf-81bc-91d91fb96f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24182
99769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2418299769
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1724888656
Short name T1233
Test name
Test status
Simulation time 822825315 ps
CPU time 1.97 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206104 kb
Host smart-9c0fa381-dccf-4837-9854-a1cf2e18e224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
88656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1724888656
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1308806382
Short name T931
Test name
Test status
Simulation time 305959234 ps
CPU time 2.11 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206332 kb
Host smart-b8271772-bf38-49a9-9029-558f16f8a64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
06382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1308806382
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2496044073
Short name T670
Test name
Test status
Simulation time 196174721 ps
CPU time 0.83 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:24:34 PM PDT 24
Peak memory 206192 kb
Host smart-4e0243af-4ff5-41b2-b6c1-0f1f2c90c64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
44073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2496044073
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.111340680
Short name T125
Test name
Test status
Simulation time 154445479 ps
CPU time 0.75 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206028 kb
Host smart-d332b86a-fa73-45ff-bfab-9612398db190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
0680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.111340680
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.652075240
Short name T1113
Test name
Test status
Simulation time 180391461 ps
CPU time 0.85 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206140 kb
Host smart-e6a28ffc-7446-4c5b-8563-2c648b15e235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65207
5240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.652075240
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3795345514
Short name T1698
Test name
Test status
Simulation time 9269917372 ps
CPU time 85.74 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206516 kb
Host smart-1b90df28-69bc-4f77-b77a-8781d29d1a33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3795345514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3795345514
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3283390420
Short name T1674
Test name
Test status
Simulation time 169324097 ps
CPU time 0.79 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206084 kb
Host smart-bdb02ffa-80b8-4fe2-8491-049924d39984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32833
90420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3283390420
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.4178870301
Short name T2454
Test name
Test status
Simulation time 23310676663 ps
CPU time 23.11 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 206200 kb
Host smart-001b3a06-2e37-49b0-a395-abc2fd3cacc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
70301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.4178870301
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.184163450
Short name T391
Test name
Test status
Simulation time 3271164885 ps
CPU time 3.62 seconds
Started Jul 07 05:24:44 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206152 kb
Host smart-ca4e03e3-1a27-4447-8ba6-fbc84cbdfe7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18416
3450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.184163450
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3419054031
Short name T2565
Test name
Test status
Simulation time 8975667854 ps
CPU time 250.48 seconds
Started Jul 07 05:24:43 PM PDT 24
Finished Jul 07 05:28:54 PM PDT 24
Peak memory 206436 kb
Host smart-d5d75a70-8133-4574-b40f-bf2da7dd174b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
54031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3419054031
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3817965040
Short name T2554
Test name
Test status
Simulation time 3908654803 ps
CPU time 106.86 seconds
Started Jul 07 05:24:36 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206484 kb
Host smart-190d8287-f1f4-40e4-a10d-b9d83c9a66f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3817965040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3817965040
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2167002617
Short name T2390
Test name
Test status
Simulation time 287384453 ps
CPU time 0.94 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206148 kb
Host smart-7aeb55a6-532e-4593-952f-9508cbf33a6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2167002617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2167002617
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3935524912
Short name T271
Test name
Test status
Simulation time 197784425 ps
CPU time 0.87 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206208 kb
Host smart-098333ae-888b-4b24-8e40-5aec4b874b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39355
24912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3935524912
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1975955963
Short name T1454
Test name
Test status
Simulation time 4640958299 ps
CPU time 131.02 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 206348 kb
Host smart-6da2d8b1-ece3-493c-ae3b-90350eeca7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
55963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1975955963
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3466638226
Short name T2662
Test name
Test status
Simulation time 5273138416 ps
CPU time 48.79 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206324 kb
Host smart-2eaadcd6-d077-49bb-bcff-bc876123620c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3466638226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3466638226
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3195852904
Short name T807
Test name
Test status
Simulation time 151638898 ps
CPU time 0.78 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206096 kb
Host smart-85fcc0bb-153a-4290-b418-a942797dd15d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3195852904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3195852904
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3464088782
Short name T1471
Test name
Test status
Simulation time 167128031 ps
CPU time 0.83 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206148 kb
Host smart-2d931a50-ade4-4da6-9618-c1a3826bd3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34640
88782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3464088782
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3543087411
Short name T150
Test name
Test status
Simulation time 241158067 ps
CPU time 0.96 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206040 kb
Host smart-4ff63361-7b57-4e44-bd07-47e243c093f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
87411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3543087411
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4179298391
Short name T737
Test name
Test status
Simulation time 171403204 ps
CPU time 0.81 seconds
Started Jul 07 05:24:32 PM PDT 24
Finished Jul 07 05:24:34 PM PDT 24
Peak memory 206232 kb
Host smart-f682a141-188a-4bd7-b364-7a3a7eb3e3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41792
98391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4179298391
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.758210417
Short name T2527
Test name
Test status
Simulation time 157159897 ps
CPU time 0.84 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206184 kb
Host smart-e456fa42-6180-4fed-98dd-e53e7558f4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75821
0417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.758210417
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1309643256
Short name T1667
Test name
Test status
Simulation time 171920801 ps
CPU time 0.81 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 206124 kb
Host smart-79819151-1eaa-46ca-9038-7060a9e6ea84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13096
43256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1309643256
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.106611868
Short name T2290
Test name
Test status
Simulation time 214286269 ps
CPU time 0.83 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206200 kb
Host smart-bf94aa09-5f94-4587-8e74-c753a17904c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10661
1868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.106611868
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2315385802
Short name T450
Test name
Test status
Simulation time 213220864 ps
CPU time 0.96 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:35 PM PDT 24
Peak memory 205864 kb
Host smart-149b656a-0504-4ced-bc86-fe152b9a922c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2315385802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2315385802
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.4209879046
Short name T1237
Test name
Test status
Simulation time 143745663 ps
CPU time 0.75 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206188 kb
Host smart-423f56f1-69ad-4350-b138-1765a9d1dc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
79046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.4209879046
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3827869805
Short name T1974
Test name
Test status
Simulation time 54139833 ps
CPU time 0.67 seconds
Started Jul 07 05:24:53 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206132 kb
Host smart-757478f8-41a1-408a-8908-594b4aa77943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38278
69805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3827869805
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.21870931
Short name T1328
Test name
Test status
Simulation time 13737873420 ps
CPU time 28.9 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:26:13 PM PDT 24
Peak memory 206216 kb
Host smart-5230e501-5fa8-4273-9873-46c9b7f7a87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21870
931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.21870931
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4246262209
Short name T662
Test name
Test status
Simulation time 175041094 ps
CPU time 0.9 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206192 kb
Host smart-8b122101-d78b-4c22-af86-b40c140c2c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
62209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4246262209
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3920530614
Short name T2284
Test name
Test status
Simulation time 186938457 ps
CPU time 0.86 seconds
Started Jul 07 05:24:41 PM PDT 24
Finished Jul 07 05:24:43 PM PDT 24
Peak memory 206188 kb
Host smart-815662b7-87fa-4c15-8ae9-139e02ac6119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39205
30614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3920530614
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1846360236
Short name T433
Test name
Test status
Simulation time 197941924 ps
CPU time 0.87 seconds
Started Jul 07 05:24:36 PM PDT 24
Finished Jul 07 05:24:39 PM PDT 24
Peak memory 206192 kb
Host smart-bca12058-82a4-4b9d-895c-1bd5d84363d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18463
60236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1846360236
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2233380025
Short name T1252
Test name
Test status
Simulation time 182801375 ps
CPU time 0.85 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206192 kb
Host smart-5dc83961-d068-4e54-8fb4-b3f633989d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22333
80025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2233380025
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3764269553
Short name T1658
Test name
Test status
Simulation time 179076950 ps
CPU time 0.77 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206084 kb
Host smart-fd233c9e-7a75-4d02-9cf0-98c79caf8d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642
69553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3764269553
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2177696861
Short name T1786
Test name
Test status
Simulation time 147603152 ps
CPU time 0.75 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:38 PM PDT 24
Peak memory 205916 kb
Host smart-7c302a31-3499-4566-ac31-18d82838962a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21776
96861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2177696861
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.903010023
Short name T776
Test name
Test status
Simulation time 165535188 ps
CPU time 0.82 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206192 kb
Host smart-c79cd8cf-2fce-4bd8-95e2-4c8589bf2473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90301
0023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.903010023
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3234861753
Short name T2673
Test name
Test status
Simulation time 280020991 ps
CPU time 1.01 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206084 kb
Host smart-e5220bdf-8918-4810-9dce-2f6ba4a1ac00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
61753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3234861753
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1062138267
Short name T588
Test name
Test status
Simulation time 4016918164 ps
CPU time 28.35 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:25:07 PM PDT 24
Peak memory 206420 kb
Host smart-32ede6b5-45cb-4621-963c-8a511e9870ee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1062138267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1062138267
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.828063908
Short name T2236
Test name
Test status
Simulation time 157337089 ps
CPU time 0.81 seconds
Started Jul 07 05:24:31 PM PDT 24
Finished Jul 07 05:24:33 PM PDT 24
Peak memory 206120 kb
Host smart-201c66de-9b9a-4e93-9d70-7b14498ef9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82806
3908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.828063908
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2968698389
Short name T2435
Test name
Test status
Simulation time 203888607 ps
CPU time 0.82 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206100 kb
Host smart-00348e8e-6f16-47ac-b9fc-7fec05425c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29686
98389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2968698389
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2940637013
Short name T784
Test name
Test status
Simulation time 1285807024 ps
CPU time 2.49 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 205624 kb
Host smart-f32d17e6-d307-4888-b172-6f14af9ce119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29406
37013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2940637013
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2843801653
Short name T1269
Test name
Test status
Simulation time 5121299705 ps
CPU time 42.4 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206180 kb
Host smart-cc8c6203-7c2c-412a-9907-48b172a722b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
01653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2843801653
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2813274667
Short name T811
Test name
Test status
Simulation time 50932395 ps
CPU time 0.69 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206152 kb
Host smart-93f787b5-adbf-4795-bae6-5fc9eb5df6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2813274667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2813274667
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1915281688
Short name T1838
Test name
Test status
Simulation time 4202269685 ps
CPU time 4.84 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206488 kb
Host smart-c1057fa2-930e-46e0-8cb0-c662e235de8b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1915281688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1915281688
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1747629870
Short name T2004
Test name
Test status
Simulation time 13400728285 ps
CPU time 14.99 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 205732 kb
Host smart-f0a1f3d4-1c38-49c5-8b0c-b56eba38cd0b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1747629870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1747629870
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2162602779
Short name T2111
Test name
Test status
Simulation time 23362885958 ps
CPU time 22.39 seconds
Started Jul 07 05:24:33 PM PDT 24
Finished Jul 07 05:24:56 PM PDT 24
Peak memory 206264 kb
Host smart-9942a19e-6545-4845-9404-5ff16292b28c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2162602779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2162602779
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2680859719
Short name T2135
Test name
Test status
Simulation time 200830587 ps
CPU time 0.86 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 206128 kb
Host smart-e33653b7-5012-4f25-aad4-a071615c3ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808
59719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2680859719
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1656061075
Short name T1397
Test name
Test status
Simulation time 188169324 ps
CPU time 0.8 seconds
Started Jul 07 05:24:52 PM PDT 24
Finished Jul 07 05:24:53 PM PDT 24
Peak memory 206120 kb
Host smart-334a707e-5abd-4ba2-a36b-7c35e1ca5171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
61075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1656061075
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3061745584
Short name T514
Test name
Test status
Simulation time 526892061 ps
CPU time 1.57 seconds
Started Jul 07 05:24:34 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206260 kb
Host smart-b96e9e31-8bad-4422-82d1-a0b35dad88d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30617
45584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3061745584
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3219532453
Short name T174
Test name
Test status
Simulation time 738084210 ps
CPU time 1.81 seconds
Started Jul 07 05:24:53 PM PDT 24
Finished Jul 07 05:24:55 PM PDT 24
Peak memory 206444 kb
Host smart-eaeb6625-fffd-4174-a47e-c54ab7b89ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
32453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3219532453
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2835640685
Short name T1229
Test name
Test status
Simulation time 12424194850 ps
CPU time 23.21 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206496 kb
Host smart-b5c88b5a-9a10-4cbe-8f60-ab56a4011e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28356
40685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2835640685
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2033715685
Short name T374
Test name
Test status
Simulation time 350909073 ps
CPU time 1.07 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206172 kb
Host smart-eaf2384d-4f33-420d-a371-e35fda03075a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
15685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2033715685
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2683004777
Short name T1940
Test name
Test status
Simulation time 148483172 ps
CPU time 0.77 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206160 kb
Host smart-40df725e-8b77-450b-85c8-c04f67be1f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830
04777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2683004777
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.802588884
Short name T2293
Test name
Test status
Simulation time 72068851 ps
CPU time 0.71 seconds
Started Jul 07 05:24:39 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206180 kb
Host smart-3de3549d-b6a7-4f1f-a4f1-d9bdf94a0381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80258
8884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.802588884
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.879659429
Short name T647
Test name
Test status
Simulation time 905216280 ps
CPU time 2.15 seconds
Started Jul 07 05:24:51 PM PDT 24
Finished Jul 07 05:24:53 PM PDT 24
Peak memory 206332 kb
Host smart-1247abf2-a034-46f6-8575-28b5cebf38fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87965
9429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.879659429
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1023437512
Short name T1129
Test name
Test status
Simulation time 180945088 ps
CPU time 2 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206396 kb
Host smart-ac3ca593-edd9-4458-a0ef-775c97bde0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
37512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1023437512
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4065787900
Short name T833
Test name
Test status
Simulation time 248964839 ps
CPU time 0.9 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:38 PM PDT 24
Peak memory 206140 kb
Host smart-54f5e2a7-5e31-49c5-a2f0-02fb80ab00e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40657
87900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4065787900
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2684046080
Short name T1235
Test name
Test status
Simulation time 138593680 ps
CPU time 0.75 seconds
Started Jul 07 05:24:36 PM PDT 24
Finished Jul 07 05:24:39 PM PDT 24
Peak memory 206180 kb
Host smart-cbbc0719-abf5-4ec9-9783-d0df8760a4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26840
46080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2684046080
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2058938412
Short name T2343
Test name
Test status
Simulation time 164849693 ps
CPU time 0.76 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206204 kb
Host smart-1b06b125-52e0-49c0-bede-4ef12d292e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20589
38412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2058938412
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.4145087741
Short name T1728
Test name
Test status
Simulation time 9264583179 ps
CPU time 265.87 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 206488 kb
Host smart-c4388e82-a97a-4cdb-bbd1-be575b6eee8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4145087741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4145087741
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1296323242
Short name T742
Test name
Test status
Simulation time 204947235 ps
CPU time 0.84 seconds
Started Jul 07 05:24:42 PM PDT 24
Finished Jul 07 05:24:44 PM PDT 24
Peak memory 206152 kb
Host smart-2344a05b-c57c-4389-9bc3-b4ec90a0922c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12963
23242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1296323242
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.4255205618
Short name T2241
Test name
Test status
Simulation time 23302668430 ps
CPU time 26.55 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:25:08 PM PDT 24
Peak memory 206248 kb
Host smart-37e7dea5-bcbc-4349-abca-a515920271e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42552
05618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.4255205618
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.4083329035
Short name T2707
Test name
Test status
Simulation time 3291085879 ps
CPU time 4.28 seconds
Started Jul 07 05:24:38 PM PDT 24
Finished Jul 07 05:24:44 PM PDT 24
Peak memory 206184 kb
Host smart-f6826001-be0c-44ff-b693-6476d9e7768b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40833
29035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.4083329035
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.42742573
Short name T1520
Test name
Test status
Simulation time 12758532373 ps
CPU time 91.99 seconds
Started Jul 07 05:24:38 PM PDT 24
Finished Jul 07 05:26:12 PM PDT 24
Peak memory 206508 kb
Host smart-fd59a412-174e-4cbd-bd53-d3926e9289cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.42742573
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.4035964430
Short name T1593
Test name
Test status
Simulation time 5195611714 ps
CPU time 150.13 seconds
Started Jul 07 05:24:39 PM PDT 24
Finished Jul 07 05:27:11 PM PDT 24
Peak memory 206424 kb
Host smart-01af6a35-e78c-47a2-834b-e8fb9613448a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4035964430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.4035964430
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2395782250
Short name T2345
Test name
Test status
Simulation time 272140965 ps
CPU time 0.97 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:24:42 PM PDT 24
Peak memory 206164 kb
Host smart-4bb41fd7-0698-4901-9760-4a1ccd143598
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2395782250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2395782250
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1090420488
Short name T435
Test name
Test status
Simulation time 228369177 ps
CPU time 0.92 seconds
Started Jul 07 05:24:35 PM PDT 24
Finished Jul 07 05:24:37 PM PDT 24
Peak memory 206200 kb
Host smart-57784a13-8afa-46a2-bdbe-8c5f55bbf4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
20488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1090420488
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2840301475
Short name T170
Test name
Test status
Simulation time 4932697443 ps
CPU time 37.79 seconds
Started Jul 07 05:24:36 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206448 kb
Host smart-8af333d5-01a3-4eb6-8504-104317e02c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403
01475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2840301475
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1193145140
Short name T1966
Test name
Test status
Simulation time 3835589818 ps
CPU time 103.24 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 206356 kb
Host smart-11a11a85-8751-4869-bd31-0407f4297756
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1193145140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1193145140
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2602229617
Short name T2534
Test name
Test status
Simulation time 153372984 ps
CPU time 0.79 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206012 kb
Host smart-8899a901-b847-4a4d-a199-068fafb3262a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2602229617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2602229617
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.599565912
Short name T1279
Test name
Test status
Simulation time 139990515 ps
CPU time 0.75 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206152 kb
Host smart-5819f3f1-b775-4dc7-a5c0-51f6af914aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59956
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.599565912
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2242307120
Short name T136
Test name
Test status
Simulation time 180258484 ps
CPU time 0.85 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206208 kb
Host smart-13d4f21d-fcdd-45fd-baa0-81b9bb486eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
07120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2242307120
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3260138932
Short name T2416
Test name
Test status
Simulation time 167444934 ps
CPU time 0.8 seconds
Started Jul 07 05:24:53 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206200 kb
Host smart-29d3aabb-6636-4813-b2a9-5d88436dda86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32601
38932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3260138932
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3128423468
Short name T68
Test name
Test status
Simulation time 219881502 ps
CPU time 0.82 seconds
Started Jul 07 05:24:44 PM PDT 24
Finished Jul 07 05:24:45 PM PDT 24
Peak memory 206116 kb
Host smart-d835c2ac-3f69-4acd-ad03-22a68b44c838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
23468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3128423468
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2744966479
Short name T1647
Test name
Test status
Simulation time 151119045 ps
CPU time 0.78 seconds
Started Jul 07 05:24:44 PM PDT 24
Finished Jul 07 05:24:45 PM PDT 24
Peak memory 206192 kb
Host smart-29705764-d140-45ac-b984-e50d756bb60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27449
66479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2744966479
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1669234292
Short name T1333
Test name
Test status
Simulation time 183943018 ps
CPU time 0.83 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206116 kb
Host smart-fe5286a3-c714-4fea-b982-8a5776e602ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16692
34292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1669234292
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3013214478
Short name T2403
Test name
Test status
Simulation time 210191386 ps
CPU time 0.9 seconds
Started Jul 07 05:24:38 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206172 kb
Host smart-4a359dcd-de6a-48f4-8461-a7c34b0bc861
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3013214478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3013214478
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1756769244
Short name T1190
Test name
Test status
Simulation time 149458795 ps
CPU time 0.78 seconds
Started Jul 07 05:24:38 PM PDT 24
Finished Jul 07 05:24:41 PM PDT 24
Peak memory 206120 kb
Host smart-e864797e-dd52-4df3-9b01-1c8b0540a870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17567
69244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1756769244
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1429567658
Short name T1150
Test name
Test status
Simulation time 37395724 ps
CPU time 0.68 seconds
Started Jul 07 05:24:43 PM PDT 24
Finished Jul 07 05:24:44 PM PDT 24
Peak memory 206156 kb
Host smart-7039e861-e765-435b-b54f-ec8d62a2437a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14295
67658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1429567658
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.4084623298
Short name T280
Test name
Test status
Simulation time 16066208263 ps
CPU time 34.31 seconds
Started Jul 07 05:24:43 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206412 kb
Host smart-1df584a8-3ef3-4c8d-986e-ec3d5282c52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40846
23298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.4084623298
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3598234932
Short name T501
Test name
Test status
Simulation time 188362172 ps
CPU time 0.83 seconds
Started Jul 07 05:24:41 PM PDT 24
Finished Jul 07 05:24:43 PM PDT 24
Peak memory 206204 kb
Host smart-ef35223d-d763-4fd2-9df1-adf0e5f72da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35982
34932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3598234932
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3481384305
Short name T622
Test name
Test status
Simulation time 217014909 ps
CPU time 0.9 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:24:42 PM PDT 24
Peak memory 206200 kb
Host smart-1946313c-4aa2-4a19-9fdb-89d8c5ac03b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34813
84305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3481384305
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.879676440
Short name T347
Test name
Test status
Simulation time 171725003 ps
CPU time 0.82 seconds
Started Jul 07 05:24:53 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206164 kb
Host smart-c87eca45-e141-4205-93a7-b80f2356f39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87967
6440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.879676440
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.123945750
Short name T372
Test name
Test status
Simulation time 175303222 ps
CPU time 0.9 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206168 kb
Host smart-a269562e-f66f-487c-bb14-facd103a4c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12394
5750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.123945750
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2657468287
Short name T2451
Test name
Test status
Simulation time 142728987 ps
CPU time 0.74 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206152 kb
Host smart-62d98d15-35a4-44f3-917f-49b24c46a977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26574
68287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2657468287
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3772374546
Short name T1120
Test name
Test status
Simulation time 199632255 ps
CPU time 0.82 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206108 kb
Host smart-45934533-6003-481b-9c94-b0cb47a35373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37723
74546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3772374546
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3237659611
Short name T863
Test name
Test status
Simulation time 157793522 ps
CPU time 0.79 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:46 PM PDT 24
Peak memory 206128 kb
Host smart-b4a10d88-1057-44c8-a900-040848c7fbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32376
59611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3237659611
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2956091846
Short name T1578
Test name
Test status
Simulation time 234090244 ps
CPU time 0.88 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:24:56 PM PDT 24
Peak memory 206132 kb
Host smart-101d44e0-04cf-4303-83e3-de13d9b4e9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
91846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2956091846
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1166123153
Short name T161
Test name
Test status
Simulation time 3469966838 ps
CPU time 94.73 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206316 kb
Host smart-90e0e425-d98a-421e-bc8e-e36258727012
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1166123153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1166123153
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1766986615
Short name T2309
Test name
Test status
Simulation time 206638136 ps
CPU time 0.81 seconds
Started Jul 07 05:24:43 PM PDT 24
Finished Jul 07 05:24:44 PM PDT 24
Peak memory 206204 kb
Host smart-022f4c5d-e2fd-47f9-8949-e8de5b9bca30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17669
86615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1766986615
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.937878033
Short name T641
Test name
Test status
Simulation time 173026281 ps
CPU time 0.83 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:24:42 PM PDT 24
Peak memory 205892 kb
Host smart-01dbcaba-bb0e-41a8-8015-c16dd4174b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93787
8033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.937878033
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3936731757
Short name T2376
Test name
Test status
Simulation time 783403212 ps
CPU time 1.82 seconds
Started Jul 07 05:24:41 PM PDT 24
Finished Jul 07 05:24:44 PM PDT 24
Peak memory 206280 kb
Host smart-fcbb425b-e355-4e88-84d3-b9cbe1e72b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39367
31757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3936731757
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1583454689
Short name T2180
Test name
Test status
Simulation time 4095066150 ps
CPU time 117.65 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 206508 kb
Host smart-c10f630e-851b-4bf6-8876-263c4ec59edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
54689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1583454689
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3783121248
Short name T664
Test name
Test status
Simulation time 38195924 ps
CPU time 0.67 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206144 kb
Host smart-c6ba9a08-36e9-45c1-9fa4-8096011577fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3783121248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3783121248
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.379595104
Short name T2316
Test name
Test status
Simulation time 3796913892 ps
CPU time 4.35 seconds
Started Jul 07 05:24:40 PM PDT 24
Finished Jul 07 05:24:46 PM PDT 24
Peak memory 206512 kb
Host smart-0e8c7581-e69c-4048-881d-75823f2aebfb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=379595104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.379595104
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3216553349
Short name T245
Test name
Test status
Simulation time 13444002196 ps
CPU time 11.87 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 206420 kb
Host smart-ceaf39a6-9f93-4289-b52e-ed626db1960c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3216553349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3216553349
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.973215009
Short name T1777
Test name
Test status
Simulation time 23368096225 ps
CPU time 22.76 seconds
Started Jul 07 05:24:41 PM PDT 24
Finished Jul 07 05:25:05 PM PDT 24
Peak memory 206180 kb
Host smart-b11f681f-7e0e-4da7-945d-6b8b6f672f0a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=973215009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.973215009
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1574720801
Short name T2580
Test name
Test status
Simulation time 152129770 ps
CPU time 0.77 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206124 kb
Host smart-421550dd-74c9-465f-bb7e-342371060dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15747
20801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1574720801
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1891649214
Short name T1682
Test name
Test status
Simulation time 150048703 ps
CPU time 0.78 seconds
Started Jul 07 05:24:52 PM PDT 24
Finished Jul 07 05:24:53 PM PDT 24
Peak memory 206188 kb
Host smart-7ff66f76-635b-43a3-b1fb-59c1ae86530b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
49214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1891649214
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1298730253
Short name T2278
Test name
Test status
Simulation time 429556386 ps
CPU time 1.3 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206192 kb
Host smart-f293e1e1-edb3-4867-8f53-8bfd5349e001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12987
30253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1298730253
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3966939356
Short name T189
Test name
Test status
Simulation time 897266429 ps
CPU time 2.19 seconds
Started Jul 07 05:24:38 PM PDT 24
Finished Jul 07 05:24:42 PM PDT 24
Peak memory 206364 kb
Host smart-cb18e5de-6a51-4c41-9c56-5f44591eca73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39669
39356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3966939356
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1348256794
Short name T2268
Test name
Test status
Simulation time 19480962224 ps
CPU time 35.77 seconds
Started Jul 07 05:24:41 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206444 kb
Host smart-97ec255b-5b07-44b6-b5ff-fba15ab8593a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13482
56794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1348256794
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2586687919
Short name T844
Test name
Test status
Simulation time 404426927 ps
CPU time 1.34 seconds
Started Jul 07 05:24:54 PM PDT 24
Finished Jul 07 05:24:56 PM PDT 24
Peak memory 206444 kb
Host smart-b3e2eab3-6833-4419-8bd3-c8e4abc59e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25866
87919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2586687919
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3547858460
Short name T695
Test name
Test status
Simulation time 145674409 ps
CPU time 0.79 seconds
Started Jul 07 05:24:44 PM PDT 24
Finished Jul 07 05:24:46 PM PDT 24
Peak memory 206044 kb
Host smart-de93594d-17c4-4e8d-9fba-d25aa40957ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478
58460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3547858460
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3394643778
Short name T261
Test name
Test status
Simulation time 47016377 ps
CPU time 0.67 seconds
Started Jul 07 05:24:37 PM PDT 24
Finished Jul 07 05:24:40 PM PDT 24
Peak memory 206176 kb
Host smart-c69c0562-de70-46b2-863f-91acc65f2d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33946
43778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3394643778
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2573177211
Short name T968
Test name
Test status
Simulation time 1034117421 ps
CPU time 2.41 seconds
Started Jul 07 05:24:43 PM PDT 24
Finished Jul 07 05:24:46 PM PDT 24
Peak memory 206384 kb
Host smart-762c18fa-5ad7-49d9-8498-64c2ce46953b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25731
77211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2573177211
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2789272781
Short name T570
Test name
Test status
Simulation time 389033426 ps
CPU time 2.27 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206440 kb
Host smart-9847b3ae-71aa-4ab7-bf81-8cfb2470f1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27892
72781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2789272781
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3810010207
Short name T954
Test name
Test status
Simulation time 206790401 ps
CPU time 0.91 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206196 kb
Host smart-287f24dd-ee55-4be8-9a90-51ae2767bdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
10207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3810010207
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1896210181
Short name T684
Test name
Test status
Simulation time 156573505 ps
CPU time 0.84 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206112 kb
Host smart-29075e4f-60de-498a-8871-aa464ece102b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18962
10181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1896210181
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.168261494
Short name T1327
Test name
Test status
Simulation time 189856660 ps
CPU time 0.83 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206036 kb
Host smart-d94c0488-07ea-4956-a45f-75f2b593e470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16826
1494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.168261494
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2324730001
Short name T1451
Test name
Test status
Simulation time 5577200125 ps
CPU time 151.49 seconds
Started Jul 07 05:24:52 PM PDT 24
Finished Jul 07 05:27:24 PM PDT 24
Peak memory 206480 kb
Host smart-c92f8e3a-2e33-462b-95bb-4ffab5cdd8c3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2324730001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2324730001
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2812501954
Short name T2346
Test name
Test status
Simulation time 211083235 ps
CPU time 0.86 seconds
Started Jul 07 05:24:53 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206188 kb
Host smart-a69a43f6-d32f-41cc-a34f-5e218629026f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
01954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2812501954
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.541695240
Short name T2019
Test name
Test status
Simulation time 23311195694 ps
CPU time 22.74 seconds
Started Jul 07 05:24:56 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206240 kb
Host smart-10afc3c1-23f1-4c94-9340-e80527f4f4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54169
5240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.541695240
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3036156074
Short name T1079
Test name
Test status
Simulation time 3298085378 ps
CPU time 4.01 seconds
Started Jul 07 05:24:43 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206260 kb
Host smart-8d669756-98a2-41c4-bf77-83184f33bcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
56074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3036156074
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.378096963
Short name T1419
Test name
Test status
Simulation time 13172226525 ps
CPU time 94.66 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206508 kb
Host smart-b10fab19-6f41-4fe2-9642-1ec675a171f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
6963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.378096963
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3055804147
Short name T1859
Test name
Test status
Simulation time 4482261064 ps
CPU time 125.14 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 206424 kb
Host smart-f0f5ebbf-58a4-47ee-b871-6a4cc1695a4b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3055804147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3055804147
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.4091255673
Short name T2085
Test name
Test status
Simulation time 248221413 ps
CPU time 0.89 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206176 kb
Host smart-10e8a6b6-6a84-4b1c-8ffe-63ed4fd1b12e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4091255673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.4091255673
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1729639912
Short name T1138
Test name
Test status
Simulation time 188837642 ps
CPU time 0.88 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206212 kb
Host smart-3864c0b7-416a-4d42-a318-e1e546e40b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17296
39912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1729639912
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1933455795
Short name T560
Test name
Test status
Simulation time 3143823160 ps
CPU time 87.97 seconds
Started Jul 07 05:24:52 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206416 kb
Host smart-3774c3c1-6864-48a5-80b0-9199b6e9c465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19334
55795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1933455795
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2329150477
Short name T1202
Test name
Test status
Simulation time 3854501978 ps
CPU time 109.97 seconds
Started Jul 07 05:24:42 PM PDT 24
Finished Jul 07 05:26:33 PM PDT 24
Peak memory 206696 kb
Host smart-88edf6c6-fc0f-4c7f-aa92-a1e1ea05944e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2329150477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2329150477
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.883392848
Short name T2612
Test name
Test status
Simulation time 173274119 ps
CPU time 0.83 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206172 kb
Host smart-8823e6df-5193-470b-a498-7e95fe7e960a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=883392848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.883392848
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1184867264
Short name T965
Test name
Test status
Simulation time 151080819 ps
CPU time 0.78 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:47 PM PDT 24
Peak memory 206208 kb
Host smart-df29d5e2-e0fe-4ce0-a218-ff86c00c5281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11848
67264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1184867264
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1911168173
Short name T2472
Test name
Test status
Simulation time 224799333 ps
CPU time 0.87 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206192 kb
Host smart-8b6d14be-d384-4480-8fc4-d25456d3b6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19111
68173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1911168173
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.654001269
Short name T601
Test name
Test status
Simulation time 174116901 ps
CPU time 0.81 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206188 kb
Host smart-27844f40-03d0-449e-bde2-6a1eedde3118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65400
1269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.654001269
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1015017662
Short name T2509
Test name
Test status
Simulation time 182092434 ps
CPU time 0.81 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 206192 kb
Host smart-8b218912-8527-4ea3-b4f1-43acb125b623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
17662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1015017662
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.889596318
Short name T2322
Test name
Test status
Simulation time 187577929 ps
CPU time 0.82 seconds
Started Jul 07 05:24:41 PM PDT 24
Finished Jul 07 05:24:43 PM PDT 24
Peak memory 206188 kb
Host smart-1be8c352-803e-46ca-b973-4df843f2c545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88959
6318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.889596318
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1049201848
Short name T2629
Test name
Test status
Simulation time 171605980 ps
CPU time 0.84 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206044 kb
Host smart-78c14212-2e7f-45e5-b040-bd6a98979751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10492
01848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1049201848
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.158939032
Short name T1356
Test name
Test status
Simulation time 217797749 ps
CPU time 0.91 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206172 kb
Host smart-88eca88f-2746-4ed0-bdee-268569e0a785
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=158939032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.158939032
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3639399147
Short name T828
Test name
Test status
Simulation time 154971222 ps
CPU time 0.84 seconds
Started Jul 07 05:24:46 PM PDT 24
Finished Jul 07 05:24:48 PM PDT 24
Peak memory 206228 kb
Host smart-60893698-c0fa-4d95-9bfb-ac1630edbe35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36393
99147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3639399147
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.4255038392
Short name T2691
Test name
Test status
Simulation time 59311341 ps
CPU time 0.67 seconds
Started Jul 07 05:24:51 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206144 kb
Host smart-3ca62700-c34a-4e58-a2bc-d68a54034940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550
38392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.4255038392
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3426119228
Short name T89
Test name
Test status
Simulation time 16351851440 ps
CPU time 38.94 seconds
Started Jul 07 05:24:54 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206500 kb
Host smart-9377aa3c-eb1d-4b0c-90a1-afa24797bdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34261
19228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3426119228
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1248394907
Short name T1962
Test name
Test status
Simulation time 146788250 ps
CPU time 0.8 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206204 kb
Host smart-6a39a233-59ea-46fd-9303-ca3744f9a842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
94907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1248394907
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1041278421
Short name T1814
Test name
Test status
Simulation time 182564953 ps
CPU time 0.8 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206108 kb
Host smart-bafe0918-4290-4f38-bc82-6a6e6ee809d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
78421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1041278421
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2594829136
Short name T1662
Test name
Test status
Simulation time 221820210 ps
CPU time 0.86 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206184 kb
Host smart-dd595237-f967-4727-a316-b3c4a5ddb67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948
29136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2594829136
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3718097128
Short name T2411
Test name
Test status
Simulation time 162809618 ps
CPU time 0.83 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206200 kb
Host smart-dd2dc643-b5ac-41ef-b20c-79206fffcee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37180
97128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3718097128
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3457503938
Short name T2561
Test name
Test status
Simulation time 175739798 ps
CPU time 0.83 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206188 kb
Host smart-05c49acd-daed-4eb0-ba02-ae227208ff97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575
03938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3457503938
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.688804414
Short name T1576
Test name
Test status
Simulation time 192595912 ps
CPU time 0.84 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206080 kb
Host smart-4c3eee1c-b5aa-4c3c-828b-fff3d67389f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68880
4414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.688804414
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.371937326
Short name T897
Test name
Test status
Simulation time 151213230 ps
CPU time 0.76 seconds
Started Jul 07 05:24:53 PM PDT 24
Finished Jul 07 05:24:54 PM PDT 24
Peak memory 206120 kb
Host smart-1ef73214-60a9-4324-baf3-63cd62462a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
7326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.371937326
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2533864477
Short name T2493
Test name
Test status
Simulation time 267356342 ps
CPU time 1.01 seconds
Started Jul 07 05:24:45 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206128 kb
Host smart-5ed6cf77-aa64-4609-a4d7-53e23477e965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25338
64477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2533864477
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1106289673
Short name T986
Test name
Test status
Simulation time 4617207447 ps
CPU time 44.63 seconds
Started Jul 07 05:24:47 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206484 kb
Host smart-2d536d73-329d-48ce-838a-9e4f144b6e0e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1106289673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1106289673
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.32415597
Short name T1221
Test name
Test status
Simulation time 202611409 ps
CPU time 0.88 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206184 kb
Host smart-4adc21a2-ab18-4904-baa7-559607f1cb7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.32415597
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.310613425
Short name T2699
Test name
Test status
Simulation time 189858007 ps
CPU time 0.88 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206156 kb
Host smart-f8bb1521-3d18-44dc-92cc-437465b44934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31061
3425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.310613425
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.865502234
Short name T1034
Test name
Test status
Simulation time 552493678 ps
CPU time 1.4 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 206140 kb
Host smart-fd39f334-31d5-46e6-951d-5850f15786c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86550
2234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.865502234
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1554604672
Short name T895
Test name
Test status
Simulation time 7235158651 ps
CPU time 64.72 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:25:55 PM PDT 24
Peak memory 206452 kb
Host smart-e692809d-3c25-4443-ae77-f62b0b3832d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15546
04672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1554604672
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.113701947
Short name T2324
Test name
Test status
Simulation time 35600621 ps
CPU time 0.68 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:17 PM PDT 24
Peak memory 206148 kb
Host smart-b859e004-6731-4c4b-b8bf-81c91b980b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=113701947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.113701947
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1971989800
Short name T2574
Test name
Test status
Simulation time 3908440053 ps
CPU time 5.33 seconds
Started Jul 07 05:24:49 PM PDT 24
Finished Jul 07 05:24:55 PM PDT 24
Peak memory 206348 kb
Host smart-cfaeb639-7a4f-4a75-b78f-7d39aa5519ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1971989800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1971989800
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.4184524764
Short name T1448
Test name
Test status
Simulation time 23389894982 ps
CPU time 23.65 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:25 PM PDT 24
Peak memory 206120 kb
Host smart-f5272cda-09c7-4b01-acf7-5c63addd4b1e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4184524764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.4184524764
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.161172411
Short name T2248
Test name
Test status
Simulation time 149089484 ps
CPU time 0.8 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:49 PM PDT 24
Peak memory 206196 kb
Host smart-77891ce3-a63b-4ead-90c9-59feba55017d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16117
2411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.161172411
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1555246295
Short name T1670
Test name
Test status
Simulation time 194135862 ps
CPU time 0.86 seconds
Started Jul 07 05:24:48 PM PDT 24
Finished Jul 07 05:24:50 PM PDT 24
Peak memory 206184 kb
Host smart-704c26ad-8d1d-41d7-a00e-f85cfffc814c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15552
46295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1555246295
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1830019122
Short name T648
Test name
Test status
Simulation time 575492198 ps
CPU time 1.66 seconds
Started Jul 07 05:24:52 PM PDT 24
Finished Jul 07 05:24:53 PM PDT 24
Peak memory 206432 kb
Host smart-337d8073-6d5a-4d76-a63c-a51b9840468a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18300
19122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1830019122
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2133522246
Short name T1307
Test name
Test status
Simulation time 391755162 ps
CPU time 1.21 seconds
Started Jul 07 05:24:55 PM PDT 24
Finished Jul 07 05:24:57 PM PDT 24
Peak memory 206224 kb
Host smart-d5319a75-caf4-4b67-8ec5-4a9ade447442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21335
22246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2133522246
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.4192674793
Short name T2609
Test name
Test status
Simulation time 19195741712 ps
CPU time 37.39 seconds
Started Jul 07 05:25:06 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 206432 kb
Host smart-1b9beaa8-4061-4b88-8886-fd3c2b0bcedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41926
74793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.4192674793
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1460382889
Short name T375
Test name
Test status
Simulation time 421227997 ps
CPU time 1.27 seconds
Started Jul 07 05:24:59 PM PDT 24
Finished Jul 07 05:25:00 PM PDT 24
Peak memory 206128 kb
Host smart-8f734e5a-3f50-4ff9-b34c-3877d17f52d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
82889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1460382889
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.218926359
Short name T2705
Test name
Test status
Simulation time 182027872 ps
CPU time 0.78 seconds
Started Jul 07 05:24:52 PM PDT 24
Finished Jul 07 05:24:53 PM PDT 24
Peak memory 206136 kb
Host smart-b55e1972-ac95-4ecc-b4be-79a1578f5ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
6359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.218926359
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1891803796
Short name T1014
Test name
Test status
Simulation time 40731256 ps
CPU time 0.71 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:06 PM PDT 24
Peak memory 206148 kb
Host smart-8106cbea-c227-408c-92f8-de7b227a7380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18918
03796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1891803796
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.4291929956
Short name T2117
Test name
Test status
Simulation time 891582215 ps
CPU time 2.11 seconds
Started Jul 07 05:24:59 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206352 kb
Host smart-2f70a2c9-2e73-47a4-802a-8d39b5be5713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42919
29956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.4291929956
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2878794211
Short name T2547
Test name
Test status
Simulation time 383962147 ps
CPU time 2.3 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206384 kb
Host smart-95237923-cdb2-42e2-98e0-1c697c52726e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28787
94211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2878794211
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2491332448
Short name T382
Test name
Test status
Simulation time 234159405 ps
CPU time 0.92 seconds
Started Jul 07 05:24:51 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206064 kb
Host smart-140c914a-0819-4b43-8bd5-dfab0c3b9a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24913
32448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2491332448
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3323813582
Short name T538
Test name
Test status
Simulation time 146133198 ps
CPU time 0.77 seconds
Started Jul 07 05:24:51 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206128 kb
Host smart-09a8f145-2644-43c2-96b8-f0f1016f83a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238
13582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3323813582
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1191235388
Short name T2398
Test name
Test status
Simulation time 238613837 ps
CPU time 0.97 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206100 kb
Host smart-cc80a651-8ae6-44c8-9332-601f9a9b5939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
35388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1191235388
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3032708415
Short name T2255
Test name
Test status
Simulation time 276141767 ps
CPU time 0.96 seconds
Started Jul 07 05:24:55 PM PDT 24
Finished Jul 07 05:24:56 PM PDT 24
Peak memory 206116 kb
Host smart-e73eaaf8-38aa-45fd-ade1-e682de8d939f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327
08415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3032708415
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1714234033
Short name T38
Test name
Test status
Simulation time 23301101185 ps
CPU time 25.85 seconds
Started Jul 07 05:24:56 PM PDT 24
Finished Jul 07 05:25:22 PM PDT 24
Peak memory 206280 kb
Host smart-62595256-4ee6-46e8-a4d1-88f459516610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
34033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1714234033
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1182184413
Short name T1498
Test name
Test status
Simulation time 3319430482 ps
CPU time 4.97 seconds
Started Jul 07 05:24:54 PM PDT 24
Finished Jul 07 05:24:59 PM PDT 24
Peak memory 206168 kb
Host smart-b4a0fb46-b23a-4d88-a957-08dfd45f95f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
84413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1182184413
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3909546590
Short name T1002
Test name
Test status
Simulation time 7300873213 ps
CPU time 198.99 seconds
Started Jul 07 05:24:54 PM PDT 24
Finished Jul 07 05:28:13 PM PDT 24
Peak memory 206392 kb
Host smart-10f20447-0e3e-48c5-8c1d-3458466ed9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39095
46590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3909546590
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3438050971
Short name T1671
Test name
Test status
Simulation time 3732966549 ps
CPU time 34.03 seconds
Started Jul 07 05:24:57 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206436 kb
Host smart-7532aa87-7be1-4cf2-99bf-378837980d51
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3438050971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3438050971
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3354420850
Short name T2653
Test name
Test status
Simulation time 245903799 ps
CPU time 0.89 seconds
Started Jul 07 05:24:55 PM PDT 24
Finished Jul 07 05:24:57 PM PDT 24
Peak memory 206064 kb
Host smart-c59261b3-0822-4098-9dc0-37a02233d9ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3354420850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3354420850
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2187763810
Short name T1765
Test name
Test status
Simulation time 188355914 ps
CPU time 0.87 seconds
Started Jul 07 05:24:50 PM PDT 24
Finished Jul 07 05:24:52 PM PDT 24
Peak memory 206120 kb
Host smart-88cccd57-80b6-4bce-bc4a-7c7e299223a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21877
63810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2187763810
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1729363351
Short name T1354
Test name
Test status
Simulation time 3403552029 ps
CPU time 33.98 seconds
Started Jul 07 05:24:55 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206448 kb
Host smart-09e795d9-6efe-4cc7-90c1-03d51ff53c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17293
63351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1729363351
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1752325443
Short name T1533
Test name
Test status
Simulation time 6337113027 ps
CPU time 171.76 seconds
Started Jul 07 05:25:07 PM PDT 24
Finished Jul 07 05:28:00 PM PDT 24
Peak memory 206476 kb
Host smart-8ef4ff82-c2e7-4501-af78-1dcde0e8b74e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1752325443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1752325443
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1098817414
Short name T1775
Test name
Test status
Simulation time 200167259 ps
CPU time 0.85 seconds
Started Jul 07 05:24:56 PM PDT 24
Finished Jul 07 05:24:57 PM PDT 24
Peak memory 206184 kb
Host smart-942480bb-c8a5-410c-9c84-b44fa7e4ec43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1098817414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1098817414
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1900131678
Short name T1390
Test name
Test status
Simulation time 149015197 ps
CPU time 0.76 seconds
Started Jul 07 05:25:10 PM PDT 24
Finished Jul 07 05:25:11 PM PDT 24
Peak memory 206208 kb
Host smart-e6d479ca-3008-4b39-b6bd-eb9c5d51d696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19001
31678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1900131678
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2411451638
Short name T155
Test name
Test status
Simulation time 193976221 ps
CPU time 0.9 seconds
Started Jul 07 05:24:59 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206184 kb
Host smart-b9149b61-a6da-4e6c-a0d0-520f9dfa513f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
51638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2411451638
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.296353567
Short name T1703
Test name
Test status
Simulation time 268574665 ps
CPU time 0.93 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:25:20 PM PDT 24
Peak memory 206180 kb
Host smart-0337c898-f8d9-471d-b918-1415009216b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29635
3567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.296353567
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2628904590
Short name T2599
Test name
Test status
Simulation time 184734967 ps
CPU time 0.83 seconds
Started Jul 07 05:24:56 PM PDT 24
Finished Jul 07 05:24:57 PM PDT 24
Peak memory 206196 kb
Host smart-4b67eeca-ab44-4ba3-bffb-a7d815e4da8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26289
04590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2628904590
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3917116199
Short name T2246
Test name
Test status
Simulation time 174721814 ps
CPU time 0.88 seconds
Started Jul 07 05:24:59 PM PDT 24
Finished Jul 07 05:25:00 PM PDT 24
Peak memory 206180 kb
Host smart-0717f66c-ee2d-46f3-b877-9099f66f2306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
16199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3917116199
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2090260766
Short name T179
Test name
Test status
Simulation time 176972294 ps
CPU time 0.88 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206208 kb
Host smart-49e31cea-ef8a-4404-955b-200d9565bfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20902
60766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2090260766
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2832864006
Short name T1550
Test name
Test status
Simulation time 197337767 ps
CPU time 0.83 seconds
Started Jul 07 05:25:04 PM PDT 24
Finished Jul 07 05:25:05 PM PDT 24
Peak memory 206136 kb
Host smart-09ccf441-eb2f-4b08-8e98-9c5103a55d56
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2832864006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2832864006
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1471566829
Short name T2359
Test name
Test status
Simulation time 150466500 ps
CPU time 0.79 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206184 kb
Host smart-516c6898-c4f4-4a8a-b5bf-3d1e7b243b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
66829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1471566829
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2657509789
Short name T2130
Test name
Test status
Simulation time 31612900 ps
CPU time 0.67 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 206108 kb
Host smart-7ffdc945-c3ad-403e-908f-9c06c7d4d3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26575
09789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2657509789
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1659819377
Short name T2422
Test name
Test status
Simulation time 16237799471 ps
CPU time 37.64 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:50 PM PDT 24
Peak memory 206536 kb
Host smart-6919effe-867a-424b-b1dd-1d70e608907c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16598
19377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1659819377
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.766704317
Short name T2277
Test name
Test status
Simulation time 262532764 ps
CPU time 0.93 seconds
Started Jul 07 05:24:57 PM PDT 24
Finished Jul 07 05:24:58 PM PDT 24
Peak memory 206136 kb
Host smart-44301799-67ee-4796-b973-26051e2b1dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76670
4317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.766704317
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.483819193
Short name T1957
Test name
Test status
Simulation time 174254963 ps
CPU time 0.84 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206196 kb
Host smart-b1145f8d-0699-4de2-8a85-d4a90ef31fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48381
9193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.483819193
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.761903049
Short name T1908
Test name
Test status
Simulation time 165547270 ps
CPU time 0.83 seconds
Started Jul 07 05:25:09 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 206120 kb
Host smart-525d8f78-2f4b-44bf-9af3-17821d245025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76190
3049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.761903049
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1641903665
Short name T1265
Test name
Test status
Simulation time 202424774 ps
CPU time 0.86 seconds
Started Jul 07 05:25:07 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206208 kb
Host smart-ddc9afbb-3117-474f-aa90-70ee9257995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16419
03665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1641903665
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3165413534
Short name T1117
Test name
Test status
Simulation time 178228999 ps
CPU time 0.85 seconds
Started Jul 07 05:24:56 PM PDT 24
Finished Jul 07 05:24:58 PM PDT 24
Peak memory 206108 kb
Host smart-057cffa4-c8b5-4af6-ba2d-97383ce0828d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31654
13534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3165413534
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3561442870
Short name T786
Test name
Test status
Simulation time 148745922 ps
CPU time 0.76 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206160 kb
Host smart-ccef1c70-2aed-48b2-b2ef-fa9b37cfc3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614
42870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3561442870
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3811815994
Short name T1429
Test name
Test status
Simulation time 151497775 ps
CPU time 0.76 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:25:20 PM PDT 24
Peak memory 206196 kb
Host smart-bdbe22fd-439e-496c-b363-0c5f2c9e1524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
15994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3811815994
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2453033084
Short name T419
Test name
Test status
Simulation time 238050167 ps
CPU time 0.95 seconds
Started Jul 07 05:24:57 PM PDT 24
Finished Jul 07 05:24:59 PM PDT 24
Peak memory 206140 kb
Host smart-eefc6f0f-a1dc-49a5-a240-7d43ead8287f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24530
33084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2453033084
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3337870572
Short name T2089
Test name
Test status
Simulation time 4618814744 ps
CPU time 32.57 seconds
Started Jul 07 05:25:06 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206388 kb
Host smart-a9f05a6f-2eba-4c0c-a735-a50c94fb6a5a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3337870572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3337870572
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3601158297
Short name T2017
Test name
Test status
Simulation time 193253472 ps
CPU time 0.85 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206112 kb
Host smart-19b50784-17ef-4cf1-98e0-80324c4086fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36011
58297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3601158297
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2404675966
Short name T1267
Test name
Test status
Simulation time 193574093 ps
CPU time 0.87 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206188 kb
Host smart-68886a06-31e1-4944-8ff6-ea3bda27bcb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24046
75966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2404675966
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3832889483
Short name T425
Test name
Test status
Simulation time 200298428 ps
CPU time 0.92 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206204 kb
Host smart-15d8294d-ca8f-4e5b-bf8b-e9685fbb7a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38328
89483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3832889483
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.733932164
Short name T2281
Test name
Test status
Simulation time 4602078908 ps
CPU time 125.26 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:27:25 PM PDT 24
Peak memory 206504 kb
Host smart-4477ef8d-f506-478b-927a-1cf503336e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73393
2164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.733932164
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.597474629
Short name T1637
Test name
Test status
Simulation time 37519952 ps
CPU time 0.69 seconds
Started Jul 07 05:25:26 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206232 kb
Host smart-0d8769d3-fd27-4630-9336-4c224415f9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=597474629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.597474629
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.4012615127
Short name T1824
Test name
Test status
Simulation time 13426992359 ps
CPU time 12.2 seconds
Started Jul 07 05:24:56 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206420 kb
Host smart-a7743a67-1957-41f2-b5f1-410cd1d983cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4012615127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.4012615127
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1165935460
Short name T2325
Test name
Test status
Simulation time 23330138383 ps
CPU time 21.31 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206484 kb
Host smart-3e43b85f-466c-4ca2-9155-9db355eb0508
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1165935460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1165935460
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.857760719
Short name T1048
Test name
Test status
Simulation time 175246231 ps
CPU time 0.82 seconds
Started Jul 07 05:25:00 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 206108 kb
Host smart-1565fbe6-6f17-4f4b-a41c-abd10d0a73a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85776
0719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.857760719
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2358768998
Short name T982
Test name
Test status
Simulation time 153337421 ps
CPU time 0.86 seconds
Started Jul 07 05:25:02 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206168 kb
Host smart-1f2f77f9-2e4f-4df9-ac0f-60135c46b4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23587
68998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2358768998
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3538595686
Short name T115
Test name
Test status
Simulation time 420368220 ps
CPU time 1.31 seconds
Started Jul 07 05:25:07 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206120 kb
Host smart-d7c9dfdb-274d-46e0-8008-01611ff26e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35385
95686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3538595686
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1510008488
Short name T1305
Test name
Test status
Simulation time 567710923 ps
CPU time 1.52 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206116 kb
Host smart-50df0558-99dd-4fe7-aecb-ea5bc9f7205b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15100
08488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1510008488
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3494159340
Short name T2601
Test name
Test status
Simulation time 19995435092 ps
CPU time 39.99 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:25:41 PM PDT 24
Peak memory 206464 kb
Host smart-9c14aef5-0623-404d-9996-9bfff03249e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
59340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3494159340
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3789662342
Short name T1528
Test name
Test status
Simulation time 323198804 ps
CPU time 1.17 seconds
Started Jul 07 05:24:58 PM PDT 24
Finished Jul 07 05:25:00 PM PDT 24
Peak memory 206200 kb
Host smart-ed6bf920-ad8c-4f07-82f4-7caf6166ed4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37896
62342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3789662342
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2997097375
Short name T1415
Test name
Test status
Simulation time 143820504 ps
CPU time 0.77 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206192 kb
Host smart-fccb8443-055f-4cc2-9b96-875bfc885535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29970
97375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2997097375
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.48108922
Short name T1238
Test name
Test status
Simulation time 49881057 ps
CPU time 0.69 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 206192 kb
Host smart-760274cc-319a-4755-9cf9-3f1f8a7e67cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48108
922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.48108922
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.975309390
Short name T2428
Test name
Test status
Simulation time 901955276 ps
CPU time 2.2 seconds
Started Jul 07 05:25:02 PM PDT 24
Finished Jul 07 05:25:04 PM PDT 24
Peak memory 206452 kb
Host smart-9b28c401-95c3-453e-a1fb-1635c9ab7805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97530
9390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.975309390
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3567650772
Short name T213
Test name
Test status
Simulation time 274539584 ps
CPU time 2.06 seconds
Started Jul 07 05:25:03 PM PDT 24
Finished Jul 07 05:25:05 PM PDT 24
Peak memory 206444 kb
Host smart-1d9ff0ad-93f8-493e-a3e5-d4939c447e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676
50772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3567650772
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2114877438
Short name T981
Test name
Test status
Simulation time 166272106 ps
CPU time 0.84 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:11 PM PDT 24
Peak memory 206196 kb
Host smart-28e7c743-dd5d-4cb8-96c7-f419644f5f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148
77438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2114877438
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1948724918
Short name T1825
Test name
Test status
Simulation time 170258944 ps
CPU time 0.77 seconds
Started Jul 07 05:25:03 PM PDT 24
Finished Jul 07 05:25:04 PM PDT 24
Peak memory 206184 kb
Host smart-39fdc1cc-b68f-43c2-8541-d45cd9d61e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19487
24918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1948724918
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2899633741
Short name T1656
Test name
Test status
Simulation time 176368881 ps
CPU time 0.81 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206188 kb
Host smart-f7456e03-bc3a-4b75-a407-d2ee737e5177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28996
33741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2899633741
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.4057307145
Short name T2462
Test name
Test status
Simulation time 6902712401 ps
CPU time 55.1 seconds
Started Jul 07 05:25:10 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206480 kb
Host smart-9c99ae50-49e3-4585-8380-0d8996830623
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4057307145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.4057307145
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1046872217
Short name T29
Test name
Test status
Simulation time 239377969 ps
CPU time 0.96 seconds
Started Jul 07 05:25:02 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206184 kb
Host smart-b5fe8cb6-7d57-47f2-8951-d72994126489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10468
72217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1046872217
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1987935039
Short name T919
Test name
Test status
Simulation time 23317364416 ps
CPU time 24.64 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206176 kb
Host smart-f58bf985-44b3-433b-9c48-a78413e79d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879
35039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1987935039
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1708676263
Short name T2621
Test name
Test status
Simulation time 3334335345 ps
CPU time 4.72 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:25:06 PM PDT 24
Peak memory 206252 kb
Host smart-5c8e7892-f069-48e6-9b69-36d645762a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
76263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1708676263
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.3756837386
Short name T1816
Test name
Test status
Simulation time 13453193646 ps
CPU time 127.76 seconds
Started Jul 07 05:25:33 PM PDT 24
Finished Jul 07 05:27:41 PM PDT 24
Peak memory 206508 kb
Host smart-1d6df11d-b6e0-43c9-931c-38d089e9ad42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37568
37386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.3756837386
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.968574084
Short name T853
Test name
Test status
Simulation time 3599722407 ps
CPU time 98.2 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 206456 kb
Host smart-0e28bfa9-6904-4c8b-99a0-b02417ac24c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=968574084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.968574084
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.467338822
Short name T1320
Test name
Test status
Simulation time 273637881 ps
CPU time 0.95 seconds
Started Jul 07 05:25:04 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 206184 kb
Host smart-c37b263b-3824-4dec-b87a-3d1771c401ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=467338822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.467338822
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1038915950
Short name T2605
Test name
Test status
Simulation time 214308486 ps
CPU time 0.87 seconds
Started Jul 07 05:25:02 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206188 kb
Host smart-09dc7c57-a24b-4285-a3a8-a0d26d6cb14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10389
15950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1038915950
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.297832002
Short name T1302
Test name
Test status
Simulation time 5359616533 ps
CPU time 150.56 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 206460 kb
Host smart-80f01f2e-732e-4304-b0c0-addeecb42511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29783
2002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.297832002
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1543922756
Short name T1556
Test name
Test status
Simulation time 6263300321 ps
CPU time 46.48 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 206432 kb
Host smart-7a032848-5fc6-4df5-9a4c-ce7794713ac7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1543922756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1543922756
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2978490187
Short name T736
Test name
Test status
Simulation time 199373078 ps
CPU time 0.81 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 206164 kb
Host smart-cd7f0931-2512-48f3-8bc6-da24791529a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2978490187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2978490187
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2313838692
Short name T1750
Test name
Test status
Simulation time 217945516 ps
CPU time 0.84 seconds
Started Jul 07 05:25:11 PM PDT 24
Finished Jul 07 05:25:12 PM PDT 24
Peak memory 206188 kb
Host smart-6a4201d4-a09d-4184-b54e-189dd267e2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23138
38692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2313838692
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2895069536
Short name T142
Test name
Test status
Simulation time 235926641 ps
CPU time 0.98 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206184 kb
Host smart-bef9ea6e-a61d-4344-8bda-31f0dd02fe55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
69536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2895069536
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2499672479
Short name T2383
Test name
Test status
Simulation time 169688553 ps
CPU time 0.82 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 206108 kb
Host smart-59356b46-1f47-4e73-af4e-948e91012668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24996
72479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2499672479
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4279108660
Short name T2593
Test name
Test status
Simulation time 187543051 ps
CPU time 0.81 seconds
Started Jul 07 05:25:02 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206108 kb
Host smart-c10f2895-db54-4cd6-8da1-13a4198d4ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
08660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4279108660
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.530139827
Short name T1038
Test name
Test status
Simulation time 210240303 ps
CPU time 0.92 seconds
Started Jul 07 05:25:01 PM PDT 24
Finished Jul 07 05:25:02 PM PDT 24
Peak memory 206188 kb
Host smart-ca6b0b06-0ce6-43cb-ac2b-f289469d4ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53013
9827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.530139827
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3502461819
Short name T1253
Test name
Test status
Simulation time 162772860 ps
CPU time 0.8 seconds
Started Jul 07 05:25:06 PM PDT 24
Finished Jul 07 05:25:07 PM PDT 24
Peak memory 206188 kb
Host smart-a6612453-cffd-47cb-af04-d63c2f4de0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35024
61819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3502461819
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3512428064
Short name T2544
Test name
Test status
Simulation time 257940970 ps
CPU time 0.93 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206160 kb
Host smart-11cfd4b7-fdf5-4d33-8787-0bbb1c280877
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3512428064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3512428064
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.4098643377
Short name T2366
Test name
Test status
Simulation time 141408022 ps
CPU time 0.76 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206240 kb
Host smart-67d91fe9-ae8b-4f69-92cf-ed32e8f761e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40986
43377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.4098643377
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.494460300
Short name T25
Test name
Test status
Simulation time 92366223 ps
CPU time 0.82 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206028 kb
Host smart-be014801-9699-435e-8815-4f8f8b9d7f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49446
0300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.494460300
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1386957259
Short name T2187
Test name
Test status
Simulation time 12480329092 ps
CPU time 28.06 seconds
Started Jul 07 05:25:07 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206480 kb
Host smart-94f5992a-8f6a-4bba-b836-38ee8f930c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13869
57259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1386957259
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1710743419
Short name T723
Test name
Test status
Simulation time 216462657 ps
CPU time 0.85 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206188 kb
Host smart-246fbad3-d9d2-4d99-8297-1a1528f9450b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17107
43419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1710743419
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.549720909
Short name T547
Test name
Test status
Simulation time 272815660 ps
CPU time 0.99 seconds
Started Jul 07 05:25:10 PM PDT 24
Finished Jul 07 05:25:11 PM PDT 24
Peak memory 206112 kb
Host smart-cfddf1de-323d-4b2f-8866-d1147ff215dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54972
0909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.549720909
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3725499042
Short name T1395
Test name
Test status
Simulation time 221014644 ps
CPU time 0.85 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206116 kb
Host smart-700a9b72-f648-43df-90be-4e701efc0ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37254
99042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3725499042
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2883005406
Short name T475
Test name
Test status
Simulation time 158000473 ps
CPU time 0.81 seconds
Started Jul 07 05:25:06 PM PDT 24
Finished Jul 07 05:25:07 PM PDT 24
Peak memory 205900 kb
Host smart-64fe5a59-022a-4339-aece-67c86a8f18a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
05406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2883005406
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3745510370
Short name T1570
Test name
Test status
Simulation time 227625825 ps
CPU time 0.89 seconds
Started Jul 07 05:25:06 PM PDT 24
Finished Jul 07 05:25:08 PM PDT 24
Peak memory 206208 kb
Host smart-6f597a15-6624-425e-91fe-6e67783cf32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37455
10370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3745510370
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2547136591
Short name T413
Test name
Test status
Simulation time 153432545 ps
CPU time 0.79 seconds
Started Jul 07 05:25:02 PM PDT 24
Finished Jul 07 05:25:03 PM PDT 24
Peak memory 206184 kb
Host smart-7fee69b9-b652-4e11-b206-cc1ae2ebb6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25471
36591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2547136591
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.183012817
Short name T2134
Test name
Test status
Simulation time 198830013 ps
CPU time 0.82 seconds
Started Jul 07 05:25:07 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206136 kb
Host smart-97087d9d-e37f-4e8b-bcfc-7b7034144419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18301
2817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.183012817
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1352492725
Short name T1379
Test name
Test status
Simulation time 252893744 ps
CPU time 0.97 seconds
Started Jul 07 05:25:05 PM PDT 24
Finished Jul 07 05:25:07 PM PDT 24
Peak memory 206184 kb
Host smart-e0165501-b415-4184-b218-91bd31b2fba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13524
92725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1352492725
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2219948673
Short name T1963
Test name
Test status
Simulation time 3948312054 ps
CPU time 28.82 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206416 kb
Host smart-b43dbbce-b763-4dca-87d9-1c0af449b1e1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2219948673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2219948673
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1530562158
Short name T953
Test name
Test status
Simulation time 162365046 ps
CPU time 0.78 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206036 kb
Host smart-9147f501-fef0-48d0-adbd-d2480aee0094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15305
62158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1530562158
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2078345272
Short name T1993
Test name
Test status
Simulation time 204037086 ps
CPU time 0.89 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206184 kb
Host smart-7608c0af-310f-40e8-af61-15b6c1a75859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783
45272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2078345272
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3874133285
Short name T574
Test name
Test status
Simulation time 859207742 ps
CPU time 1.8 seconds
Started Jul 07 05:25:08 PM PDT 24
Finished Jul 07 05:25:10 PM PDT 24
Peak memory 206312 kb
Host smart-bb3628e8-7d97-450f-9e40-25f9e9f51a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38741
33285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3874133285
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1412666553
Short name T1873
Test name
Test status
Simulation time 3983925434 ps
CPU time 37.42 seconds
Started Jul 07 05:25:08 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206392 kb
Host smart-7bbb81a8-de40-466d-a75f-aadfcca99941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14126
66553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1412666553
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2036914693
Short name T468
Test name
Test status
Simulation time 44811048 ps
CPU time 0.69 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:20:07 PM PDT 24
Peak memory 206156 kb
Host smart-2e9c7331-4ed9-4e41-8421-1a71f998a08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2036914693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2036914693
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1841388105
Short name T12
Test name
Test status
Simulation time 3674896497 ps
CPU time 4.43 seconds
Started Jul 07 05:19:50 PM PDT 24
Finished Jul 07 05:19:55 PM PDT 24
Peak memory 206408 kb
Host smart-a927d3a0-6a30-4b08-b7dd-eb4b94a25eea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1841388105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1841388105
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2397168462
Short name T2660
Test name
Test status
Simulation time 13380409146 ps
CPU time 12.57 seconds
Started Jul 07 05:19:54 PM PDT 24
Finished Jul 07 05:20:07 PM PDT 24
Peak memory 206228 kb
Host smart-53377b24-9eed-41be-84de-9abf0317ada8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2397168462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2397168462
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.182248996
Short name T1772
Test name
Test status
Simulation time 23283581251 ps
CPU time 27.74 seconds
Started Jul 07 05:19:52 PM PDT 24
Finished Jul 07 05:20:20 PM PDT 24
Peak memory 206296 kb
Host smart-8da2cdda-1077-4658-bc7c-d7e56babe175
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=182248996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.182248996
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2272152592
Short name T831
Test name
Test status
Simulation time 179945692 ps
CPU time 0.83 seconds
Started Jul 07 05:19:52 PM PDT 24
Finished Jul 07 05:19:53 PM PDT 24
Peak memory 206208 kb
Host smart-380aff42-a488-4991-ac77-cc851e28b3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
52592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2272152592
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.247672173
Short name T48
Test name
Test status
Simulation time 213117116 ps
CPU time 0.81 seconds
Started Jul 07 05:19:57 PM PDT 24
Finished Jul 07 05:19:58 PM PDT 24
Peak memory 206180 kb
Host smart-3cdc699d-fbdc-486c-9370-3eedadc1c83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24767
2173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.247672173
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2581293153
Short name T87
Test name
Test status
Simulation time 145343473 ps
CPU time 0.81 seconds
Started Jul 07 05:19:51 PM PDT 24
Finished Jul 07 05:19:52 PM PDT 24
Peak memory 206148 kb
Host smart-395b6899-92e2-47c6-99ae-4f684ed39736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25812
93153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2581293153
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.872295393
Short name T1168
Test name
Test status
Simulation time 151277579 ps
CPU time 0.75 seconds
Started Jul 07 05:19:49 PM PDT 24
Finished Jul 07 05:19:50 PM PDT 24
Peak memory 206108 kb
Host smart-364aefc5-2002-44d4-9f4c-40725924b490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87229
5393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.872295393
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2259942250
Short name T208
Test name
Test status
Simulation time 428226599 ps
CPU time 1.28 seconds
Started Jul 07 05:19:50 PM PDT 24
Finished Jul 07 05:19:51 PM PDT 24
Peak memory 206184 kb
Host smart-a0a41b7d-98d4-4967-9c65-cdf87e6c6fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22599
42250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2259942250
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3270377978
Short name T1561
Test name
Test status
Simulation time 1067521667 ps
CPU time 2.4 seconds
Started Jul 07 05:19:54 PM PDT 24
Finished Jul 07 05:19:57 PM PDT 24
Peak memory 206328 kb
Host smart-8f91741c-c22a-4bb6-be64-950f8fbc89f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
77978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3270377978
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1755284675
Short name T1025
Test name
Test status
Simulation time 7996925705 ps
CPU time 14.48 seconds
Started Jul 07 05:19:50 PM PDT 24
Finished Jul 07 05:20:05 PM PDT 24
Peak memory 206512 kb
Host smart-4b9b14d7-7233-4e76-b0a2-ff38b628da37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17552
84675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1755284675
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1971561883
Short name T1989
Test name
Test status
Simulation time 342549524 ps
CPU time 1.13 seconds
Started Jul 07 05:19:58 PM PDT 24
Finished Jul 07 05:20:00 PM PDT 24
Peak memory 206188 kb
Host smart-9ac3dd10-9d1b-48b8-a93a-479b8aa86b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
61883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1971561883
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1420267124
Short name T933
Test name
Test status
Simulation time 187826187 ps
CPU time 0.79 seconds
Started Jul 07 05:19:53 PM PDT 24
Finished Jul 07 05:19:54 PM PDT 24
Peak memory 206160 kb
Host smart-6e6c6bad-2468-4695-9b67-8fd67bbdb524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14202
67124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1420267124
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.966545656
Short name T2402
Test name
Test status
Simulation time 50870690 ps
CPU time 0.68 seconds
Started Jul 07 05:19:55 PM PDT 24
Finished Jul 07 05:19:56 PM PDT 24
Peak memory 206176 kb
Host smart-d12672bb-80ee-4c25-808e-d52ad76a5166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96654
5656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.966545656
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.418539340
Short name T364
Test name
Test status
Simulation time 1013296557 ps
CPU time 2.33 seconds
Started Jul 07 05:19:53 PM PDT 24
Finished Jul 07 05:19:56 PM PDT 24
Peak memory 206440 kb
Host smart-0f3153f5-0aed-481a-8bcb-04b58db2eff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
9340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.418539340
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.171062768
Short name T1264
Test name
Test status
Simulation time 154646986 ps
CPU time 1.28 seconds
Started Jul 07 05:19:57 PM PDT 24
Finished Jul 07 05:19:59 PM PDT 24
Peak memory 206424 kb
Host smart-8a22916f-9542-4f9b-b744-1a48f9804a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
2768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.171062768
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.228183989
Short name T2094
Test name
Test status
Simulation time 111252704684 ps
CPU time 166.56 seconds
Started Jul 07 05:19:55 PM PDT 24
Finished Jul 07 05:22:42 PM PDT 24
Peak memory 206472 kb
Host smart-9822e1a0-14c0-4174-b4db-6aa977438a15
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=228183989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.228183989
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2219848971
Short name T1830
Test name
Test status
Simulation time 87238936360 ps
CPU time 119.36 seconds
Started Jul 07 05:19:53 PM PDT 24
Finished Jul 07 05:21:53 PM PDT 24
Peak memory 206412 kb
Host smart-68b25399-cea9-4f92-9060-bf127bfe8919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219848971 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2219848971
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1061029361
Short name T714
Test name
Test status
Simulation time 105093954360 ps
CPU time 146.69 seconds
Started Jul 07 05:19:55 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206432 kb
Host smart-782ff77b-a431-422c-a84c-1a35632a900d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1061029361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1061029361
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.3628150794
Short name T2157
Test name
Test status
Simulation time 101037000323 ps
CPU time 137.91 seconds
Started Jul 07 05:19:58 PM PDT 24
Finished Jul 07 05:22:17 PM PDT 24
Peak memory 206444 kb
Host smart-07e2450a-6f66-401d-8c8f-069af00e8717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628150794 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3628150794
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.193216806
Short name T2142
Test name
Test status
Simulation time 107184618295 ps
CPU time 142.69 seconds
Started Jul 07 05:19:56 PM PDT 24
Finished Jul 07 05:22:19 PM PDT 24
Peak memory 206456 kb
Host smart-25914099-10c2-40b5-9569-ef3ef86c21d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19321
6806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.193216806
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2620198105
Short name T1744
Test name
Test status
Simulation time 226007064 ps
CPU time 0.9 seconds
Started Jul 07 05:19:53 PM PDT 24
Finished Jul 07 05:19:55 PM PDT 24
Peak memory 206436 kb
Host smart-47538b9c-be8c-44e6-aa7b-dc740af6a690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26201
98105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2620198105
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.826022111
Short name T1070
Test name
Test status
Simulation time 133302397 ps
CPU time 0.75 seconds
Started Jul 07 05:19:53 PM PDT 24
Finished Jul 07 05:19:54 PM PDT 24
Peak memory 206184 kb
Host smart-3a941eb1-c74d-43fb-a80b-a8b50a46e4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82602
2111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.826022111
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2098981202
Short name T2476
Test name
Test status
Simulation time 217629451 ps
CPU time 0.95 seconds
Started Jul 07 05:19:58 PM PDT 24
Finished Jul 07 05:19:59 PM PDT 24
Peak memory 206184 kb
Host smart-a8ccadb8-db00-451d-842d-10fa0100f912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20989
81202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2098981202
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.2173968380
Short name T2600
Test name
Test status
Simulation time 7959782352 ps
CPU time 54.94 seconds
Started Jul 07 05:19:54 PM PDT 24
Finished Jul 07 05:20:49 PM PDT 24
Peak memory 206496 kb
Host smart-5ae4a4c8-71c2-4089-8252-7f7b5d0f173c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2173968380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.2173968380
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1191249944
Short name T678
Test name
Test status
Simulation time 232214038 ps
CPU time 0.88 seconds
Started Jul 07 05:19:54 PM PDT 24
Finished Jul 07 05:19:55 PM PDT 24
Peak memory 206112 kb
Host smart-9e6729f9-120f-4df8-8d20-8cb63525179d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
49944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1191249944
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.990960672
Short name T35
Test name
Test status
Simulation time 23321456376 ps
CPU time 24.81 seconds
Started Jul 07 05:19:58 PM PDT 24
Finished Jul 07 05:20:23 PM PDT 24
Peak memory 206252 kb
Host smart-b3b4732a-2130-45da-828e-3c229c736b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99096
0672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.990960672
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.4004308104
Short name T371
Test name
Test status
Simulation time 3330703314 ps
CPU time 3.98 seconds
Started Jul 07 05:20:00 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206256 kb
Host smart-52a1f61f-5943-4efa-9026-f2e120778fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
08104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.4004308104
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.725033599
Short name T681
Test name
Test status
Simulation time 8619096637 ps
CPU time 227.54 seconds
Started Jul 07 05:19:56 PM PDT 24
Finished Jul 07 05:23:44 PM PDT 24
Peak memory 206516 kb
Host smart-99a605d6-26ca-4853-b1e2-9117a23c130d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72503
3599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.725033599
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.93025328
Short name T1902
Test name
Test status
Simulation time 4199762821 ps
CPU time 31.36 seconds
Started Jul 07 05:19:59 PM PDT 24
Finished Jul 07 05:20:31 PM PDT 24
Peak memory 206428 kb
Host smart-23653ed9-4520-48a6-918b-bf82fd336849
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=93025328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.93025328
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.50395171
Short name T658
Test name
Test status
Simulation time 239852758 ps
CPU time 0.91 seconds
Started Jul 07 05:20:02 PM PDT 24
Finished Jul 07 05:20:03 PM PDT 24
Peak memory 206164 kb
Host smart-f4f40f41-ecc8-4b76-a5fa-93244fcf4018
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=50395171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.50395171
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.209044691
Short name T2658
Test name
Test status
Simulation time 186951756 ps
CPU time 0.87 seconds
Started Jul 07 05:19:59 PM PDT 24
Finished Jul 07 05:20:01 PM PDT 24
Peak memory 206188 kb
Host smart-3db5819c-3d69-40f0-b49c-fcd5677853a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
4691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.209044691
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.1969208273
Short name T1809
Test name
Test status
Simulation time 5187444277 ps
CPU time 39.26 seconds
Started Jul 07 05:20:00 PM PDT 24
Finished Jul 07 05:20:39 PM PDT 24
Peak memory 206304 kb
Host smart-f1e2c714-e467-452e-aedc-d32ccf0d647c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19692
08273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.1969208273
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1360358729
Short name T1901
Test name
Test status
Simulation time 2660612483 ps
CPU time 25.78 seconds
Started Jul 07 05:19:56 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206404 kb
Host smart-a48f0325-ae3f-4af1-9779-7162857b6956
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1360358729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1360358729
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1939735406
Short name T626
Test name
Test status
Simulation time 163275231 ps
CPU time 0.79 seconds
Started Jul 07 05:19:57 PM PDT 24
Finished Jul 07 05:19:59 PM PDT 24
Peak memory 206104 kb
Host smart-78569111-7141-4deb-b0dd-5a0c631f8e03
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1939735406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1939735406
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.329638644
Short name T1364
Test name
Test status
Simulation time 180031570 ps
CPU time 0.79 seconds
Started Jul 07 05:19:57 PM PDT 24
Finished Jul 07 05:19:58 PM PDT 24
Peak memory 206212 kb
Host smart-106628d1-6edd-42d8-96ca-71104b3271f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32963
8644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.329638644
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2840270725
Short name T131
Test name
Test status
Simulation time 207160371 ps
CPU time 0.94 seconds
Started Jul 07 05:20:01 PM PDT 24
Finished Jul 07 05:20:02 PM PDT 24
Peak memory 206188 kb
Host smart-6b103b85-a818-4008-9380-72d6b64ab57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28402
70725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2840270725
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2980222361
Short name T566
Test name
Test status
Simulation time 181610457 ps
CPU time 0.8 seconds
Started Jul 07 05:19:57 PM PDT 24
Finished Jul 07 05:19:58 PM PDT 24
Peak memory 206152 kb
Host smart-5aa8d727-9775-4d14-9ed2-8c36e497dbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29802
22361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2980222361
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2707837630
Short name T1519
Test name
Test status
Simulation time 193485121 ps
CPU time 0.93 seconds
Started Jul 07 05:20:02 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206188 kb
Host smart-3af58da2-9ee7-4ff6-a542-4e5db0bb6095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27078
37630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2707837630
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1917399328
Short name T2483
Test name
Test status
Simulation time 177572080 ps
CPU time 0.84 seconds
Started Jul 07 05:19:58 PM PDT 24
Finished Jul 07 05:20:00 PM PDT 24
Peak memory 206120 kb
Host smart-9b29398d-e757-43c3-b48d-41eb445f8a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173
99328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1917399328
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.4184906231
Short name T191
Test name
Test status
Simulation time 153083140 ps
CPU time 0.8 seconds
Started Jul 07 05:20:00 PM PDT 24
Finished Jul 07 05:20:01 PM PDT 24
Peak memory 206132 kb
Host smart-ac92ef02-bb9c-4cd2-9167-ecc0f9057ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41849
06231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.4184906231
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2708396083
Short name T2002
Test name
Test status
Simulation time 208792074 ps
CPU time 1.02 seconds
Started Jul 07 05:20:03 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206220 kb
Host smart-473eb55a-8a97-4dc9-80ec-b7ad4c9ec4e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2708396083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2708396083
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3563524661
Short name T228
Test name
Test status
Simulation time 215736152 ps
CPU time 0.97 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:20:05 PM PDT 24
Peak memory 206192 kb
Host smart-403debe1-d883-4a22-a3d8-5f6cf8847a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35635
24661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3563524661
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1896416787
Short name T1321
Test name
Test status
Simulation time 201472536 ps
CPU time 0.87 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 206180 kb
Host smart-6719468a-7bb7-48f1-8a5e-644739a76a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18964
16787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1896416787
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.155981388
Short name T2043
Test name
Test status
Simulation time 39824618 ps
CPU time 0.62 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:20:07 PM PDT 24
Peak memory 205468 kb
Host smart-5aae9a0e-1f68-456f-805d-77a9015aceab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
1388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.155981388
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1020482282
Short name T1309
Test name
Test status
Simulation time 11004384757 ps
CPU time 24.22 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:20:29 PM PDT 24
Peak memory 206476 kb
Host smart-e177b4c2-4e79-40bf-8ac3-1223ac79e9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
82282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1020482282
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3341040141
Short name T1230
Test name
Test status
Simulation time 183134668 ps
CPU time 0.9 seconds
Started Jul 07 05:20:02 PM PDT 24
Finished Jul 07 05:20:03 PM PDT 24
Peak memory 206064 kb
Host smart-c81533fc-13e3-4014-8c98-205f7c1678d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33410
40141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3341040141
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2884587441
Short name T2059
Test name
Test status
Simulation time 165557693 ps
CPU time 0.84 seconds
Started Jul 07 05:20:02 PM PDT 24
Finished Jul 07 05:20:03 PM PDT 24
Peak memory 206152 kb
Host smart-18c29caa-143d-4ab5-adbe-0e6dab15357f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28845
87441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2884587441
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1864003359
Short name T926
Test name
Test status
Simulation time 3603101967 ps
CPU time 88.27 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 205800 kb
Host smart-9a9d0bbe-1ecd-4a72-8d91-955f87321f64
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1864003359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1864003359
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1263957901
Short name T1500
Test name
Test status
Simulation time 11017214091 ps
CPU time 71 seconds
Started Jul 07 05:20:00 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 206396 kb
Host smart-f5fc1632-99db-4496-b901-1362d3917d6a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1263957901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1263957901
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2870678100
Short name T2590
Test name
Test status
Simulation time 207396520 ps
CPU time 0.86 seconds
Started Jul 07 05:20:08 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 206036 kb
Host smart-c9f9bef3-43a8-4e18-a115-0f7820af072c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28706
78100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2870678100
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3159912797
Short name T902
Test name
Test status
Simulation time 252452685 ps
CPU time 0.89 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 206184 kb
Host smart-7d26319c-b306-4faa-b123-16b6289f3fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31599
12797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3159912797
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4237548625
Short name T2526
Test name
Test status
Simulation time 183183388 ps
CPU time 0.9 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:20:05 PM PDT 24
Peak memory 206200 kb
Host smart-ae29f0a7-2294-42ec-8695-a99d8680fb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
48625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4237548625
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.455087701
Short name T2446
Test name
Test status
Simulation time 212310880 ps
CPU time 0.84 seconds
Started Jul 07 05:20:00 PM PDT 24
Finished Jul 07 05:20:02 PM PDT 24
Peak memory 206120 kb
Host smart-5d92c212-cd78-4c90-afc6-1031c9954218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45508
7701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.455087701
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.545519046
Short name T223
Test name
Test status
Simulation time 556241056 ps
CPU time 1.41 seconds
Started Jul 07 05:20:05 PM PDT 24
Finished Jul 07 05:20:07 PM PDT 24
Peak memory 225052 kb
Host smart-79418440-c1d5-4b2e-84e8-39ff8ea4611f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=545519046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.545519046
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2320263897
Short name T2545
Test name
Test status
Simulation time 418415953 ps
CPU time 1.28 seconds
Started Jul 07 05:20:03 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206184 kb
Host smart-4cfa0a16-b19b-4609-ab38-e841237657b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
63897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2320263897
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1994428214
Short name T823
Test name
Test status
Simulation time 226270686 ps
CPU time 0.88 seconds
Started Jul 07 05:20:03 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206104 kb
Host smart-d147c857-dc15-4dc6-a92a-e94173a6d505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
28214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1994428214
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1427599982
Short name T1095
Test name
Test status
Simulation time 147033151 ps
CPU time 0.78 seconds
Started Jul 07 05:19:59 PM PDT 24
Finished Jul 07 05:20:00 PM PDT 24
Peak memory 206108 kb
Host smart-8aa21f1e-1610-4980-b718-0c82269f1dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14275
99982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1427599982
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2957000823
Short name T104
Test name
Test status
Simulation time 155045010 ps
CPU time 0.8 seconds
Started Jul 07 05:20:03 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206188 kb
Host smart-93f204a8-dd46-4748-bdbd-97a9fbdc7058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570
00823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2957000823
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1756903212
Short name T1170
Test name
Test status
Simulation time 226874984 ps
CPU time 0.99 seconds
Started Jul 07 05:20:01 PM PDT 24
Finished Jul 07 05:20:02 PM PDT 24
Peak memory 206152 kb
Host smart-0ad10f74-43be-4f28-859f-b6f831891f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17569
03212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1756903212
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2629411030
Short name T1871
Test name
Test status
Simulation time 6670012646 ps
CPU time 189.45 seconds
Started Jul 07 05:20:05 PM PDT 24
Finished Jul 07 05:23:15 PM PDT 24
Peak memory 206316 kb
Host smart-9f2ddd5d-03ea-4bd5-8c7b-c95fb878c8c0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2629411030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2629411030
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.857322777
Short name T997
Test name
Test status
Simulation time 188365216 ps
CPU time 0.83 seconds
Started Jul 07 05:20:05 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 206116 kb
Host smart-61656cb7-2616-4aa3-a6c9-b54ffa969842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85732
2777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.857322777
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.497272591
Short name T2034
Test name
Test status
Simulation time 156411978 ps
CPU time 0.8 seconds
Started Jul 07 05:20:05 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 205900 kb
Host smart-2c9a2685-7eb6-405f-8b55-aecd179e69bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49727
2591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.497272591
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1280775927
Short name T1035
Test name
Test status
Simulation time 1134239256 ps
CPU time 2.53 seconds
Started Jul 07 05:20:07 PM PDT 24
Finished Jul 07 05:20:10 PM PDT 24
Peak memory 206428 kb
Host smart-9fcb6ae2-d702-44c7-b91b-e3096ec396b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12807
75927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1280775927
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.284564966
Short name T1810
Test name
Test status
Simulation time 4343456544 ps
CPU time 31.63 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:20:38 PM PDT 24
Peak memory 206356 kb
Host smart-11785191-909d-4f37-bc32-dc1003ad1bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
4966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.284564966
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.521373915
Short name T466
Test name
Test status
Simulation time 35750956 ps
CPU time 0.69 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:17 PM PDT 24
Peak memory 206140 kb
Host smart-95a3952a-967e-40d1-8614-908fbc10410f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=521373915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.521373915
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3454036383
Short name T1926
Test name
Test status
Simulation time 4396158265 ps
CPU time 5.59 seconds
Started Jul 07 05:25:09 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 206228 kb
Host smart-abb1ebe5-77fa-4203-ba88-a740edae6a36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3454036383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3454036383
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3944365291
Short name T1749
Test name
Test status
Simulation time 13387048876 ps
CPU time 15.69 seconds
Started Jul 07 05:25:11 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206420 kb
Host smart-d05a2ef0-43df-42d6-addb-6dff7d5aa050
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3944365291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3944365291
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3730809548
Short name T1092
Test name
Test status
Simulation time 23375766064 ps
CPU time 24.05 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206268 kb
Host smart-b19b23e7-8031-422b-8019-2e3bd1cd4e37
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3730809548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3730809548
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.836378883
Short name T573
Test name
Test status
Simulation time 207434803 ps
CPU time 0.87 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206080 kb
Host smart-37b0f8dd-a896-4e77-afc9-9803beb6fdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83637
8883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.836378883
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4104806518
Short name T1148
Test name
Test status
Simulation time 160532311 ps
CPU time 0.81 seconds
Started Jul 07 05:25:07 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206172 kb
Host smart-181d99d9-117d-4ad2-9f47-13a8e6659414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41048
06518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4104806518
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3234061452
Short name T1995
Test name
Test status
Simulation time 248910420 ps
CPU time 1.05 seconds
Started Jul 07 05:25:09 PM PDT 24
Finished Jul 07 05:25:11 PM PDT 24
Peak memory 206204 kb
Host smart-38eedab7-ec48-40c5-8c41-051705dfe7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32340
61452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3234061452
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2041537215
Short name T2458
Test name
Test status
Simulation time 620732954 ps
CPU time 1.69 seconds
Started Jul 07 05:25:21 PM PDT 24
Finished Jul 07 05:25:23 PM PDT 24
Peak memory 206192 kb
Host smart-e2f8d4f0-47f6-4fab-875e-02487e6b520e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20415
37215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2041537215
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2492201538
Short name T102
Test name
Test status
Simulation time 17640369175 ps
CPU time 31.31 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:26:12 PM PDT 24
Peak memory 206428 kb
Host smart-d0ee54bb-de1d-4a28-876c-c97e06585eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24922
01538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2492201538
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2276473437
Short name T83
Test name
Test status
Simulation time 389272270 ps
CPU time 1.22 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:25:20 PM PDT 24
Peak memory 206444 kb
Host smart-326c8f94-08b9-4ceb-802c-0c4f0986256d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22764
73437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2276473437
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3311659793
Short name T441
Test name
Test status
Simulation time 148024729 ps
CPU time 0.76 seconds
Started Jul 07 05:25:10 PM PDT 24
Finished Jul 07 05:25:11 PM PDT 24
Peak memory 206188 kb
Host smart-a0e8bfc4-3b8e-4485-8d42-b675bc3f0d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33116
59793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3311659793
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2514107580
Short name T2650
Test name
Test status
Simulation time 42063080 ps
CPU time 0.7 seconds
Started Jul 07 05:25:11 PM PDT 24
Finished Jul 07 05:25:12 PM PDT 24
Peak memory 206180 kb
Host smart-e7cf2a9b-0170-4a21-8ea7-9019d469351f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25141
07580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2514107580
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.234943820
Short name T1021
Test name
Test status
Simulation time 936358817 ps
CPU time 2.19 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:25:25 PM PDT 24
Peak memory 206364 kb
Host smart-b2b1b253-4ffe-421a-95e8-fad261a46aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
3820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.234943820
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2669286922
Short name T467
Test name
Test status
Simulation time 279313540 ps
CPU time 2.04 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 206384 kb
Host smart-4d5feedb-99a9-412c-b973-b96c2b0a3721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26692
86922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2669286922
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.43407548
Short name T555
Test name
Test status
Simulation time 162375029 ps
CPU time 0.85 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206112 kb
Host smart-24fd0fef-362d-44c0-a3ca-6a3b20ac3450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43407
548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.43407548
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3051249956
Short name T1245
Test name
Test status
Simulation time 146333686 ps
CPU time 0.81 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206136 kb
Host smart-87c4a6af-a88d-4841-aaeb-6fe7cafa5573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30512
49956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3051249956
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1186876350
Short name T1770
Test name
Test status
Simulation time 250605765 ps
CPU time 0.94 seconds
Started Jul 07 05:25:11 PM PDT 24
Finished Jul 07 05:25:12 PM PDT 24
Peak memory 206100 kb
Host smart-fbaec2ef-87a6-45ed-9461-539fbc3ddf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11868
76350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1186876350
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.4020379302
Short name T1660
Test name
Test status
Simulation time 243511151 ps
CPU time 0.9 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:24 PM PDT 24
Peak memory 206152 kb
Host smart-53c2c3eb-acb1-44e6-8c76-53c69f04ca60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
79302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.4020379302
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2961643844
Short name T428
Test name
Test status
Simulation time 23307835756 ps
CPU time 25.35 seconds
Started Jul 07 05:25:08 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206248 kb
Host smart-6e890f33-fc95-4105-a6f8-6a6aa417dfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29616
43844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2961643844
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3714001309
Short name T1295
Test name
Test status
Simulation time 3335653508 ps
CPU time 3.96 seconds
Started Jul 07 05:25:11 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 206264 kb
Host smart-7d39cd79-8a92-466d-a8cb-6aef835ac55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37140
01309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3714001309
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.663574055
Short name T2202
Test name
Test status
Simulation time 9798710632 ps
CPU time 272.17 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:29:51 PM PDT 24
Peak memory 206516 kb
Host smart-f1f37150-948a-4972-b2b3-8611d48199c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66357
4055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.663574055
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.4118947752
Short name T1291
Test name
Test status
Simulation time 7050325939 ps
CPU time 186.79 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:28:35 PM PDT 24
Peak memory 206356 kb
Host smart-96e51f2b-166b-46bc-8aa4-3638342f08a9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4118947752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.4118947752
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.611602701
Short name T21
Test name
Test status
Simulation time 244156042 ps
CPU time 0.93 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206168 kb
Host smart-676aa691-e863-4696-abb4-5ee72716e50d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=611602701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.611602701
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2015625197
Short name T974
Test name
Test status
Simulation time 190180559 ps
CPU time 0.82 seconds
Started Jul 07 05:25:26 PM PDT 24
Finished Jul 07 05:25:28 PM PDT 24
Peak memory 206104 kb
Host smart-ee97083d-ef88-45f0-9af7-dffea43b7d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20156
25197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2015625197
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1082980427
Short name T2523
Test name
Test status
Simulation time 5654220744 ps
CPU time 165.09 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:28:16 PM PDT 24
Peak memory 206456 kb
Host smart-4ce4f620-f878-4d38-8fcd-bfaa151ddacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10829
80427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1082980427
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1534384607
Short name T1023
Test name
Test status
Simulation time 5760241936 ps
CPU time 53.78 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:26:22 PM PDT 24
Peak memory 206320 kb
Host smart-ca5555a8-b773-443f-89ee-f4a26d451e70
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1534384607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1534384607
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3575167817
Short name T1801
Test name
Test status
Simulation time 145352207 ps
CPU time 0.78 seconds
Started Jul 07 05:25:34 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206172 kb
Host smart-dfc5d002-4647-49c5-b4c7-5ceb47c926e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3575167817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3575167817
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.571430182
Short name T1600
Test name
Test status
Simulation time 143116606 ps
CPU time 0.8 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206196 kb
Host smart-c1e867b9-08f4-4fbc-9f74-f308d73a0cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57143
0182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.571430182
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3419534475
Short name T157
Test name
Test status
Simulation time 236777864 ps
CPU time 0.91 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206184 kb
Host smart-223d1a6c-fbf2-4bf6-bceb-1af480b3f9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34195
34475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3419534475
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.979296387
Short name T874
Test name
Test status
Simulation time 155634759 ps
CPU time 0.82 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 206188 kb
Host smart-18d397ca-8453-4c9e-9947-2f6e676077cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97929
6387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.979296387
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1050792270
Short name T1939
Test name
Test status
Simulation time 189793122 ps
CPU time 0.85 seconds
Started Jul 07 05:25:14 PM PDT 24
Finished Jul 07 05:25:15 PM PDT 24
Peak memory 206204 kb
Host smart-7839bd8f-312e-4da9-8a1f-2b27aaeaaf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507
92270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1050792270
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1997829087
Short name T2468
Test name
Test status
Simulation time 198690327 ps
CPU time 0.84 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206428 kb
Host smart-1aec3d8c-a947-4984-baf3-f174693b8dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
29087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1997829087
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3123662713
Short name T1187
Test name
Test status
Simulation time 221696986 ps
CPU time 0.87 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206112 kb
Host smart-3acb33d5-9dda-4fcd-8f67-d3a921ec0eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
62713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3123662713
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1203298462
Short name T877
Test name
Test status
Simulation time 241708576 ps
CPU time 1.04 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 206164 kb
Host smart-fa50c41c-17ce-4f54-bda4-287a4909733b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1203298462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1203298462
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2191355375
Short name T1797
Test name
Test status
Simulation time 142584581 ps
CPU time 0.79 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206160 kb
Host smart-87f03f7d-1b57-4fea-8c5a-cb25c0567963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21913
55375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2191355375
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1226547982
Short name T1609
Test name
Test status
Simulation time 39452882 ps
CPU time 0.68 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206180 kb
Host smart-245dbfe0-c1d2-4962-b279-053b53278a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12265
47982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1226547982
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.596670001
Short name T1161
Test name
Test status
Simulation time 13502350034 ps
CPU time 28.84 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 205680 kb
Host smart-19ed7eac-6cbe-4690-bb2f-8a9292badfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59667
0001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.596670001
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2553824965
Short name T1659
Test name
Test status
Simulation time 162004607 ps
CPU time 0.79 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:25:13 PM PDT 24
Peak memory 206172 kb
Host smart-28bcb541-6b1c-4efc-83cc-1d760ead43c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25538
24965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2553824965
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.4151791562
Short name T1968
Test name
Test status
Simulation time 165393257 ps
CPU time 0.83 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:28 PM PDT 24
Peak memory 206192 kb
Host smart-72cd343a-f427-4e41-978f-a903bc8f700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
91562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4151791562
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1437428734
Short name T489
Test name
Test status
Simulation time 163250929 ps
CPU time 0.76 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206152 kb
Host smart-13a58a87-93e9-4618-8a7c-aad3ac9ab48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14374
28734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1437428734
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.7485393
Short name T360
Test name
Test status
Simulation time 181992339 ps
CPU time 0.86 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206188 kb
Host smart-5367b850-e033-44eb-802c-2ffda001a559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74853
93 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.7485393
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2233086588
Short name T1997
Test name
Test status
Simulation time 207368257 ps
CPU time 0.86 seconds
Started Jul 07 05:25:24 PM PDT 24
Finished Jul 07 05:25:25 PM PDT 24
Peak memory 206120 kb
Host smart-725da347-c1a9-42dd-b97f-d825ad1b1f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
86588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2233086588
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1843855211
Short name T916
Test name
Test status
Simulation time 165181304 ps
CPU time 0.78 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:25:24 PM PDT 24
Peak memory 206116 kb
Host smart-5da89763-56a4-4fe7-8417-71492abc39e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18438
55211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1843855211
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.245762997
Short name T1393
Test name
Test status
Simulation time 148200082 ps
CPU time 0.82 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206216 kb
Host smart-3c01de09-c4aa-4bd7-b650-076147190988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24576
2997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.245762997
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1913465424
Short name T2326
Test name
Test status
Simulation time 212043515 ps
CPU time 0.98 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206428 kb
Host smart-d64ec3fa-5eb1-4eb1-9594-9ecb1255b5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19134
65424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1913465424
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3957073390
Short name T2641
Test name
Test status
Simulation time 6277066244 ps
CPU time 56.78 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 206420 kb
Host smart-9e200f73-1828-4906-87f1-4bae02ba4218
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3957073390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3957073390
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1279430570
Short name T67
Test name
Test status
Simulation time 162196302 ps
CPU time 0.79 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206160 kb
Host smart-c37f49a3-06a9-4d88-a7bd-e23317be1339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
30570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1279430570
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1575908166
Short name T2438
Test name
Test status
Simulation time 155123515 ps
CPU time 0.76 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 205448 kb
Host smart-f2f1b958-c8f7-4f37-9dc5-01ecbe401161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15759
08166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1575908166
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.1903124043
Short name T675
Test name
Test status
Simulation time 390530601 ps
CPU time 1.23 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206196 kb
Host smart-6b45f606-c637-4a29-886d-9c145296bcac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19031
24043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.1903124043
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2215697380
Short name T2628
Test name
Test status
Simulation time 7350459738 ps
CPU time 55.69 seconds
Started Jul 07 05:25:12 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206156 kb
Host smart-e36c2657-518d-47c9-a944-08d6a4119750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156
97380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2215697380
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3926028732
Short name T215
Test name
Test status
Simulation time 45375037 ps
CPU time 0.66 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:25:24 PM PDT 24
Peak memory 206184 kb
Host smart-029e0a85-e982-4660-b926-981069cd095a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3926028732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3926028732
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.339258627
Short name T1628
Test name
Test status
Simulation time 3726775350 ps
CPU time 4.78 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206360 kb
Host smart-c7b0faec-8670-42dc-9512-f6d7c13a08df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=339258627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.339258627
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1855403206
Short name T2120
Test name
Test status
Simulation time 13347965154 ps
CPU time 15.53 seconds
Started Jul 07 05:25:13 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206236 kb
Host smart-b210c89d-1ee7-4747-8b82-a221134c8214
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1855403206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1855403206
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3682696923
Short name T1216
Test name
Test status
Simulation time 23327093865 ps
CPU time 22.89 seconds
Started Jul 07 05:25:24 PM PDT 24
Finished Jul 07 05:25:47 PM PDT 24
Peak memory 206224 kb
Host smart-a82a0e93-c916-40e4-9796-c88e9bd3d8bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3682696923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3682696923
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3235697439
Short name T2052
Test name
Test status
Simulation time 152021673 ps
CPU time 0.82 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206216 kb
Host smart-e98122b4-a77f-4d00-8122-6b7bb10b63e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
97439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3235697439
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2759709429
Short name T568
Test name
Test status
Simulation time 164735308 ps
CPU time 0.78 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:23 PM PDT 24
Peak memory 206032 kb
Host smart-8c1d1848-836c-49b7-814a-05bde057d692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
09429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2759709429
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2117863504
Short name T2171
Test name
Test status
Simulation time 473022452 ps
CPU time 1.47 seconds
Started Jul 07 05:25:14 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206200 kb
Host smart-d4950b6f-9d76-4f25-beef-29d67c23005c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
63504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2117863504
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3001469756
Short name T116
Test name
Test status
Simulation time 1142594975 ps
CPU time 2.77 seconds
Started Jul 07 05:25:33 PM PDT 24
Finished Jul 07 05:25:36 PM PDT 24
Peak memory 206388 kb
Host smart-4fe87e80-55ce-48fe-9e2f-1de03eb5fd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30014
69756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3001469756
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3415148372
Short name T2217
Test name
Test status
Simulation time 19355285837 ps
CPU time 34.21 seconds
Started Jul 07 05:25:33 PM PDT 24
Finished Jul 07 05:26:08 PM PDT 24
Peak memory 206480 kb
Host smart-238d6429-2c72-4134-a2a4-6bc19269720d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34151
48372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3415148372
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.253789173
Short name T956
Test name
Test status
Simulation time 400504599 ps
CPU time 1.31 seconds
Started Jul 07 05:25:26 PM PDT 24
Finished Jul 07 05:25:28 PM PDT 24
Peak memory 206036 kb
Host smart-02beb371-7452-4b4a-b0fd-8a7348a6d330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
9173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.253789173
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3584215479
Short name T1979
Test name
Test status
Simulation time 138935717 ps
CPU time 0.81 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:16 PM PDT 24
Peak memory 206200 kb
Host smart-674edfbc-6dd2-4cfa-be10-375a3eb5479d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
15479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3584215479
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3534899360
Short name T2682
Test name
Test status
Simulation time 37025167 ps
CPU time 0.69 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206112 kb
Host smart-0071e92a-afb8-44d7-8496-0996e2a01d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35348
99360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3534899360
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2717162154
Short name T571
Test name
Test status
Simulation time 963725885 ps
CPU time 2.24 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206416 kb
Host smart-d31879c5-420c-4eac-999b-aa65eb6a1a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171
62154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2717162154
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3867585086
Short name T1773
Test name
Test status
Simulation time 170247027 ps
CPU time 1.68 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206344 kb
Host smart-0c248595-742a-4f7b-a817-271b8117db53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
85086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3867585086
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.890211780
Short name T2704
Test name
Test status
Simulation time 268422878 ps
CPU time 0.93 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:17 PM PDT 24
Peak memory 206184 kb
Host smart-ef37d50b-13bb-439a-b1f7-46125fedce94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89021
1780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.890211780
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3187024581
Short name T2530
Test name
Test status
Simulation time 140608871 ps
CPU time 0.78 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206120 kb
Host smart-c5cd67a5-7d71-4074-864e-f8c2a8c6b740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31870
24581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3187024581
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.876802697
Short name T2048
Test name
Test status
Simulation time 316357524 ps
CPU time 1.07 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:17 PM PDT 24
Peak memory 206180 kb
Host smart-9dc737c1-b850-4399-8920-55bed66c4464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87680
2697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.876802697
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2291841835
Short name T432
Test name
Test status
Simulation time 218046474 ps
CPU time 0.9 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206208 kb
Host smart-00f3aa63-dc08-4aa2-9b0c-b1fec93fe50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22918
41835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2291841835
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.277745957
Short name T1151
Test name
Test status
Simulation time 23293928289 ps
CPU time 22.3 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206248 kb
Host smart-2c5a46d7-c947-4427-8da4-9a4d6808365d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27774
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.277745957
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1976810229
Short name T2393
Test name
Test status
Simulation time 3264385659 ps
CPU time 3.37 seconds
Started Jul 07 05:25:31 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206272 kb
Host smart-3c528adc-7b23-45c7-bd9f-19a30e5f00ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19768
10229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1976810229
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3079903045
Short name T843
Test name
Test status
Simulation time 12305558742 ps
CPU time 120.77 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:27:29 PM PDT 24
Peak memory 206452 kb
Host smart-bd6735cb-6994-417a-bd97-97e741cb1b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30799
03045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3079903045
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1149806007
Short name T1083
Test name
Test status
Simulation time 4942777609 ps
CPU time 134.7 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 206684 kb
Host smart-32b87b45-1ae2-45a9-b61a-2b8810d378ad
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1149806007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1149806007
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3595166497
Short name T1646
Test name
Test status
Simulation time 281845106 ps
CPU time 0.96 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:17 PM PDT 24
Peak memory 206164 kb
Host smart-f49f9a1a-52eb-4ae0-ad17-a86ba3f40032
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3595166497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3595166497
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.678127010
Short name T563
Test name
Test status
Simulation time 200789688 ps
CPU time 0.93 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206444 kb
Host smart-a8833cf6-d26b-415b-b980-7d37ea8fe03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67812
7010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.678127010
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3523675656
Short name T722
Test name
Test status
Simulation time 4032823441 ps
CPU time 114.68 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 206356 kb
Host smart-1fde2b5b-61a2-4ad3-b415-f5e5978266b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35236
75656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3523675656
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1994195343
Short name T743
Test name
Test status
Simulation time 5367741941 ps
CPU time 37.62 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206432 kb
Host smart-a3145be0-4efb-4ffd-b49a-19d4f2c9ea93
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1994195343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1994195343
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.72870568
Short name T1292
Test name
Test status
Simulation time 209785397 ps
CPU time 0.85 seconds
Started Jul 07 05:25:15 PM PDT 24
Finished Jul 07 05:25:17 PM PDT 24
Peak memory 206160 kb
Host smart-2036e995-e9d3-4b4c-b66b-7b091c4c7a47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=72870568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.72870568
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2442818302
Short name T2425
Test name
Test status
Simulation time 157754737 ps
CPU time 0.79 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 206436 kb
Host smart-3ba45793-421d-4129-8796-3f2a1d3d1163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24428
18302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2442818302
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3227761046
Short name T1766
Test name
Test status
Simulation time 214348814 ps
CPU time 0.85 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206168 kb
Host smart-4c15c97e-30bf-4a8b-b2d7-aa5600e23235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277
61046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3227761046
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.801250882
Short name T2313
Test name
Test status
Simulation time 156641799 ps
CPU time 0.81 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206180 kb
Host smart-5e1239ca-68ee-4a8f-9453-eec04ec9796d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80125
0882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.801250882
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.755299870
Short name T886
Test name
Test status
Simulation time 194636371 ps
CPU time 0.91 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:25:20 PM PDT 24
Peak memory 206036 kb
Host smart-c46073db-738e-45fb-8fa9-ebbfe6dcfbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75529
9870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.755299870
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2845005055
Short name T1248
Test name
Test status
Simulation time 163877503 ps
CPU time 0.82 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206160 kb
Host smart-130ee8c0-92f1-4655-bc71-709bf72a6e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28450
05055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2845005055
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3220297502
Short name T199
Test name
Test status
Simulation time 151612355 ps
CPU time 0.75 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206196 kb
Host smart-aa9e4126-1bda-409f-bd05-4b7b16367acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32202
97502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3220297502
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.621760656
Short name T2635
Test name
Test status
Simulation time 192232312 ps
CPU time 0.89 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206144 kb
Host smart-0d1fe59a-757e-4e8e-9cd0-8a2ee1467fdd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=621760656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.621760656
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.295519804
Short name T1875
Test name
Test status
Simulation time 148093735 ps
CPU time 0.76 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206204 kb
Host smart-8a96b618-707f-4da5-a550-f411ca7b6cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29551
9804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.295519804
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1833816261
Short name T2162
Test name
Test status
Simulation time 81135083 ps
CPU time 0.72 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:25:20 PM PDT 24
Peak memory 206176 kb
Host smart-cc71fbca-5a8a-4563-ab9b-ae9f0dc5f5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18338
16261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1833816261
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.4294137258
Short name T281
Test name
Test status
Simulation time 17421178924 ps
CPU time 39.75 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206488 kb
Host smart-50711c16-db0d-48d8-86b1-acb3bc6616e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42941
37258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.4294137258
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1068195078
Short name T1624
Test name
Test status
Simulation time 151422443 ps
CPU time 0.84 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206120 kb
Host smart-ca92963d-b854-4dbb-a564-60a08ef7b289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10681
95078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1068195078
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2033834757
Short name T682
Test name
Test status
Simulation time 174158828 ps
CPU time 0.81 seconds
Started Jul 07 05:25:33 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206188 kb
Host smart-933bf9c8-4182-429c-b025-7a2c0b5f6656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338
34757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2033834757
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1639200630
Short name T1815
Test name
Test status
Simulation time 198257493 ps
CPU time 0.86 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206068 kb
Host smart-13470b9d-c14e-4505-8ebb-2a6523651289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16392
00630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1639200630
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.4082722093
Short name T1863
Test name
Test status
Simulation time 178771001 ps
CPU time 0.84 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:23 PM PDT 24
Peak memory 206120 kb
Host smart-70670a86-d1af-440a-94a9-69e453ecc740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827
22093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.4082722093
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2822061972
Short name T1509
Test name
Test status
Simulation time 192551460 ps
CPU time 0.83 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206200 kb
Host smart-bbecb357-644d-4a7c-abf4-7405c472d3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220
61972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2822061972
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3841673867
Short name T2247
Test name
Test status
Simulation time 174499267 ps
CPU time 0.8 seconds
Started Jul 07 05:25:33 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206152 kb
Host smart-bd4281ee-afdc-447c-9545-5e5cc172e947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38416
73867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3841673867
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3335363215
Short name T1965
Test name
Test status
Simulation time 152343908 ps
CPU time 0.78 seconds
Started Jul 07 05:25:34 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206204 kb
Host smart-faecca3b-05d6-4d4a-8dac-8ae61000408d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33353
63215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3335363215
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1580228116
Short name T1930
Test name
Test status
Simulation time 205402568 ps
CPU time 0.89 seconds
Started Jul 07 05:25:34 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206184 kb
Host smart-05c3440a-3ef3-4b64-bee0-04f53417eec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15802
28116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1580228116
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.95933832
Short name T2056
Test name
Test status
Simulation time 5920327732 ps
CPU time 156.89 seconds
Started Jul 07 05:25:17 PM PDT 24
Finished Jul 07 05:27:55 PM PDT 24
Peak memory 206436 kb
Host smart-216c658a-652f-4e6b-b0ae-552976256e41
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=95933832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.95933832
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.291059881
Short name T2051
Test name
Test status
Simulation time 158422401 ps
CPU time 0.85 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206184 kb
Host smart-a7a59248-a8c7-4f73-ab89-19bef0392caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29105
9881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.291059881
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4185737262
Short name T2391
Test name
Test status
Simulation time 199559072 ps
CPU time 0.84 seconds
Started Jul 07 05:25:16 PM PDT 24
Finished Jul 07 05:25:18 PM PDT 24
Peak memory 206196 kb
Host smart-e2cf8155-db03-4b5a-a698-6822b4660bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41857
37262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4185737262
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.3143407758
Short name T1447
Test name
Test status
Simulation time 474330611 ps
CPU time 1.28 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:23 PM PDT 24
Peak memory 206184 kb
Host smart-18ec76a9-6d32-4114-a108-56bc3acd2ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31434
07758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3143407758
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2765883986
Short name T1263
Test name
Test status
Simulation time 4330302471 ps
CPU time 113.77 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:27:38 PM PDT 24
Peak memory 206504 kb
Host smart-db2f50bf-3c48-4e68-8ecc-b54b73ee4e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
83986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2765883986
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2544783399
Short name T2320
Test name
Test status
Simulation time 31607931 ps
CPU time 0.71 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:45 PM PDT 24
Peak memory 206148 kb
Host smart-870246f7-8f6f-40ae-92c3-77037971be55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2544783399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2544783399
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3552766491
Short name T1917
Test name
Test status
Simulation time 3796153470 ps
CPU time 4.78 seconds
Started Jul 07 05:25:24 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206184 kb
Host smart-def44545-710a-40bc-9acd-91a5614647d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3552766491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3552766491
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3571665611
Short name T770
Test name
Test status
Simulation time 13411374806 ps
CPU time 14.93 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206200 kb
Host smart-78cfb8d5-655c-461e-8ab6-655ee4b804f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3571665611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3571665611
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.561871070
Short name T1091
Test name
Test status
Simulation time 23348934195 ps
CPU time 22.88 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:25:47 PM PDT 24
Peak memory 206500 kb
Host smart-7b00d81d-acfa-44da-9172-9171de0e9b6b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=561871070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.561871070
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1048015824
Short name T1101
Test name
Test status
Simulation time 157006110 ps
CPU time 0.84 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206148 kb
Host smart-6f053df0-ef57-4fd9-b9ad-736634c04c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480
15824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1048015824
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.4169220238
Short name T932
Test name
Test status
Simulation time 193757167 ps
CPU time 0.84 seconds
Started Jul 07 05:25:31 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206208 kb
Host smart-d35fc62a-128b-451d-b615-88463042278d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41692
20238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.4169220238
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3287941110
Short name T1026
Test name
Test status
Simulation time 428091760 ps
CPU time 1.42 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206432 kb
Host smart-949c3f63-e221-42be-a20c-a3fa9b51d161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32879
41110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3287941110
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1242071216
Short name T1274
Test name
Test status
Simulation time 429770641 ps
CPU time 1.29 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206132 kb
Host smart-d68af2f9-163f-4ff2-adab-4883d42693b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420
71216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1242071216
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2783455667
Short name T201
Test name
Test status
Simulation time 15596816206 ps
CPU time 28.74 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 206516 kb
Host smart-24829c23-a659-4e25-a53f-df11302107a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27834
55667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2783455667
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2443258555
Short name T872
Test name
Test status
Simulation time 451649350 ps
CPU time 1.33 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206132 kb
Host smart-76f28de5-7f9d-43bb-ba88-70d744ef98bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24432
58555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2443258555
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.4260253718
Short name T876
Test name
Test status
Simulation time 142586581 ps
CPU time 0.75 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206192 kb
Host smart-ded3d622-5970-42af-9e70-ab814f907a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42602
53718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.4260253718
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2499293775
Short name T780
Test name
Test status
Simulation time 57400528 ps
CPU time 0.68 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206024 kb
Host smart-e3b9b330-54c9-4588-9ea7-a5c5cf96e761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24992
93775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2499293775
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.4249932142
Short name T1490
Test name
Test status
Simulation time 831837821 ps
CPU time 2.01 seconds
Started Jul 07 05:25:18 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206352 kb
Host smart-1614167d-6db6-4743-9aa9-5ab8b4700b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
32142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.4249932142
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.623931395
Short name T1406
Test name
Test status
Simulation time 203501100 ps
CPU time 2.01 seconds
Started Jul 07 05:25:19 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206348 kb
Host smart-8c3d5070-6c44-4eca-8ee3-d2a2e7a8e6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62393
1395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.623931395
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1083713939
Short name T124
Test name
Test status
Simulation time 213832579 ps
CPU time 0.88 seconds
Started Jul 07 05:25:34 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206128 kb
Host smart-9773a593-7337-440f-8fb8-07d5b6492c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10837
13939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1083713939
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3122412314
Short name T2141
Test name
Test status
Simulation time 144884378 ps
CPU time 0.79 seconds
Started Jul 07 05:25:21 PM PDT 24
Finished Jul 07 05:25:22 PM PDT 24
Peak memory 205892 kb
Host smart-38aa9870-9af2-4517-a7a7-3436bbf02884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
12314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3122412314
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3647731978
Short name T1853
Test name
Test status
Simulation time 221336564 ps
CPU time 0.87 seconds
Started Jul 07 05:25:33 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206188 kb
Host smart-78490d1f-68f5-450e-a063-67c5c3661bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477
31978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3647731978
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2136533269
Short name T973
Test name
Test status
Simulation time 178553123 ps
CPU time 0.84 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206100 kb
Host smart-6879bf90-af13-456e-8f54-3b22fd4b4660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21365
33269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2136533269
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1259363997
Short name T1557
Test name
Test status
Simulation time 23350682383 ps
CPU time 23.11 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206256 kb
Host smart-7b4ac2ab-7017-4af2-a45f-7eebaf1b26ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12593
63997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1259363997
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.538981370
Short name T1990
Test name
Test status
Simulation time 3338695653 ps
CPU time 3.88 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206204 kb
Host smart-dd409a2d-25a9-48fb-86c5-fe804acadc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53898
1370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.538981370
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3372837423
Short name T1555
Test name
Test status
Simulation time 10039852939 ps
CPU time 71.15 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 206440 kb
Host smart-fd4b08db-3d24-44e8-998d-4b14e8ae5c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33728
37423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3372837423
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.4046400049
Short name T1818
Test name
Test status
Simulation time 5231022422 ps
CPU time 148.3 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:27:51 PM PDT 24
Peak memory 206424 kb
Host smart-1529523e-e4a5-48c3-b7bc-032890306206
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4046400049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.4046400049
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.224174630
Short name T1947
Test name
Test status
Simulation time 238508328 ps
CPU time 0.87 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206184 kb
Host smart-e3106ec1-7cfc-46ee-9998-ae2f95600947
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=224174630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.224174630
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1685971627
Short name T1485
Test name
Test status
Simulation time 183055889 ps
CPU time 0.89 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:23 PM PDT 24
Peak memory 206120 kb
Host smart-10ac2cf9-5d8f-4c5d-9e08-585160fbfb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16859
71627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1685971627
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3223855438
Short name T1884
Test name
Test status
Simulation time 6347702514 ps
CPU time 58.97 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 206448 kb
Host smart-356c842f-7255-415c-b372-ef480ec80e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
55438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3223855438
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.146723833
Short name T1169
Test name
Test status
Simulation time 2778395942 ps
CPU time 74.53 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 206480 kb
Host smart-948fe59e-ab5d-4f3b-b250-4d8284e8c1eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=146723833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.146723833
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.149092118
Short name T1222
Test name
Test status
Simulation time 181811094 ps
CPU time 0.88 seconds
Started Jul 07 05:25:20 PM PDT 24
Finished Jul 07 05:25:21 PM PDT 24
Peak memory 206164 kb
Host smart-2d1cdef5-99fa-48d8-ae9b-1e327bfef085
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=149092118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.149092118
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4123247407
Short name T2221
Test name
Test status
Simulation time 145586530 ps
CPU time 0.81 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:25:25 PM PDT 24
Peak memory 206188 kb
Host smart-aecc5912-5c66-4547-ae22-7e3e399c19dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41232
47407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4123247407
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1107963312
Short name T130
Test name
Test status
Simulation time 181431000 ps
CPU time 0.81 seconds
Started Jul 07 05:25:23 PM PDT 24
Finished Jul 07 05:25:24 PM PDT 24
Peak memory 206204 kb
Host smart-58160537-9063-4f3a-836c-9d9c723b8e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
63312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1107963312
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.62797464
Short name T492
Test name
Test status
Simulation time 218736062 ps
CPU time 0.88 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206204 kb
Host smart-9e2fc04b-cac2-4e39-88a3-b21434d216eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62797
464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.62797464
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.696513662
Short name T1289
Test name
Test status
Simulation time 244481864 ps
CPU time 0.94 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206164 kb
Host smart-e882ed09-30f6-49a7-955d-4ac102772562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69651
3662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.696513662
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1558702707
Short name T448
Test name
Test status
Simulation time 165139190 ps
CPU time 0.79 seconds
Started Jul 07 05:25:24 PM PDT 24
Finished Jul 07 05:25:25 PM PDT 24
Peak memory 206188 kb
Host smart-bba9e284-0403-4133-950d-880a753d1938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15587
02707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1558702707
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.437267145
Short name T746
Test name
Test status
Simulation time 159277989 ps
CPU time 0.79 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206200 kb
Host smart-bcf5e4c3-d00f-4898-aca3-9e0545058c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43726
7145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.437267145
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.4203927263
Short name T652
Test name
Test status
Simulation time 235389916 ps
CPU time 0.93 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:41 PM PDT 24
Peak memory 206052 kb
Host smart-5c8915ed-df8d-4054-aed3-18717b00692f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4203927263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.4203927263
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2281399808
Short name T1422
Test name
Test status
Simulation time 153952288 ps
CPU time 0.8 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206032 kb
Host smart-9871cc54-2001-4eff-ba3d-5216f663ce42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813
99808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2281399808
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2481950720
Short name T2240
Test name
Test status
Simulation time 40064888 ps
CPU time 0.66 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:28 PM PDT 24
Peak memory 206096 kb
Host smart-46424dd4-7703-40d2-b2b0-48a6cab794b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24819
50720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2481950720
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2669637652
Short name T277
Test name
Test status
Simulation time 16423308588 ps
CPU time 36.3 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 214588 kb
Host smart-d3af8467-4943-4797-af76-43cd1359d7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
37652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2669637652
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2461349528
Short name T1776
Test name
Test status
Simulation time 172905273 ps
CPU time 0.82 seconds
Started Jul 07 05:25:26 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206200 kb
Host smart-e578cb32-6bcf-4226-a6e7-759baa6e6a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24613
49528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2461349528
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2803915362
Short name T47
Test name
Test status
Simulation time 229787030 ps
CPU time 0.84 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206196 kb
Host smart-603beaae-f2d5-4eb6-9f55-3b7dd1f22b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
15362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2803915362
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.908199898
Short name T482
Test name
Test status
Simulation time 203117080 ps
CPU time 0.82 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:27 PM PDT 24
Peak memory 206188 kb
Host smart-9ff25e88-4c60-44c7-a42a-227d0a09e4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90819
9898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.908199898
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3292804595
Short name T2307
Test name
Test status
Simulation time 166490238 ps
CPU time 0.87 seconds
Started Jul 07 05:25:22 PM PDT 24
Finished Jul 07 05:25:24 PM PDT 24
Peak memory 206188 kb
Host smart-0798a060-9c2f-4b44-b74a-09ce07c3107e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32928
04595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3292804595
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3636409850
Short name T1811
Test name
Test status
Simulation time 188265621 ps
CPU time 0.82 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:41 PM PDT 24
Peak memory 206148 kb
Host smart-c805f760-c460-4660-8d56-e917e29f5430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36364
09850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3636409850
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1882210303
Short name T1981
Test name
Test status
Simulation time 161376699 ps
CPU time 0.79 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206184 kb
Host smart-cb13b6af-a918-44fe-9b75-cd724e7b54d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822
10303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1882210303
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2703220156
Short name T2257
Test name
Test status
Simulation time 170133789 ps
CPU time 0.79 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206140 kb
Host smart-171c3d45-86d8-424c-a663-49a68aa0a4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27032
20156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2703220156
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1271907413
Short name T621
Test name
Test status
Simulation time 211222869 ps
CPU time 1.01 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206116 kb
Host smart-3385f458-a063-4e9f-a7c3-1370a7d5b982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719
07413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1271907413
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3188022959
Short name T2678
Test name
Test status
Simulation time 5962172254 ps
CPU time 53.87 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 206444 kb
Host smart-bf4a33b6-5b95-493c-a1b0-52b3123a38b6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3188022959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3188022959
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1885926961
Short name T1246
Test name
Test status
Simulation time 177466275 ps
CPU time 0.87 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206088 kb
Host smart-346ecf15-9b51-4f17-bf24-3c9b475d1a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18859
26961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1885926961
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.4208098902
Short name T478
Test name
Test status
Simulation time 200350189 ps
CPU time 0.84 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206140 kb
Host smart-38fead15-537a-4f5d-8c36-b619e45ee27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
98902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.4208098902
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.290437097
Short name T2233
Test name
Test status
Simulation time 711350456 ps
CPU time 1.67 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206156 kb
Host smart-5775ca3e-80cc-4ce9-be2d-137beb903506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
7097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.290437097
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3018811568
Short name T1914
Test name
Test status
Simulation time 5051223165 ps
CPU time 49.9 seconds
Started Jul 07 05:25:24 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 206520 kb
Host smart-7391a61a-ad74-404a-9211-52c0e8b6de0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30188
11568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3018811568
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1056247202
Short name T999
Test name
Test status
Simulation time 62581482 ps
CPU time 0.7 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 204912 kb
Host smart-c932458a-6fe1-43a3-9ba5-30186e51ecd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1056247202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1056247202
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3685510867
Short name T244
Test name
Test status
Simulation time 4360350575 ps
CPU time 5.01 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206416 kb
Host smart-32b41799-d783-4f94-9110-0c0a01361e8a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3685510867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3685510867
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.648001449
Short name T866
Test name
Test status
Simulation time 13356606833 ps
CPU time 15.77 seconds
Started Jul 07 05:25:25 PM PDT 24
Finished Jul 07 05:25:41 PM PDT 24
Peak memory 206492 kb
Host smart-19e2ef2c-4fc9-4eec-a6c9-1eb06d4a90c3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=648001449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.648001449
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1969277128
Short name T1678
Test name
Test status
Simulation time 23356091155 ps
CPU time 28.89 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:26:00 PM PDT 24
Peak memory 206076 kb
Host smart-614688b9-fb6d-424a-8daa-6a0c6d3ad4b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1969277128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1969277128
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.4183398757
Short name T1304
Test name
Test status
Simulation time 182238464 ps
CPU time 0.85 seconds
Started Jul 07 05:25:34 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206152 kb
Host smart-8e06c3fb-e834-4063-9844-59f302a35b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
98757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.4183398757
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1116253580
Short name T2149
Test name
Test status
Simulation time 185168544 ps
CPU time 0.83 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206188 kb
Host smart-bbacfd1e-12ac-460f-ad88-d643b626806a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11162
53580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1116253580
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2931359908
Short name T194
Test name
Test status
Simulation time 492746692 ps
CPU time 1.61 seconds
Started Jul 07 05:25:26 PM PDT 24
Finished Jul 07 05:25:28 PM PDT 24
Peak memory 206448 kb
Host smart-aa57a3b6-cbda-457d-86cd-54ffb1f8aa4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29313
59908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2931359908
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3003003132
Short name T1723
Test name
Test status
Simulation time 562894876 ps
CPU time 1.4 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:45 PM PDT 24
Peak memory 206112 kb
Host smart-9e54edc5-e305-4dc3-8ab6-825c2dfb0ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30030
03132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3003003132
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1940161663
Short name T2399
Test name
Test status
Simulation time 12498757703 ps
CPU time 24.82 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206452 kb
Host smart-77a0531b-e781-44d3-b777-a7890695d6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19401
61663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1940161663
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.16649470
Short name T966
Test name
Test status
Simulation time 398007069 ps
CPU time 1.23 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206112 kb
Host smart-82509523-528b-4349-832b-71789be7ec36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16649
470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.16649470
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1324406703
Short name T41
Test name
Test status
Simulation time 143348828 ps
CPU time 0.74 seconds
Started Jul 07 05:25:31 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206192 kb
Host smart-2e939a52-c433-4c17-b5a5-3185eae7e91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13244
06703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1324406703
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2363193466
Short name T730
Test name
Test status
Simulation time 36517285 ps
CPU time 0.72 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206176 kb
Host smart-ff13fa43-ade7-4202-b6af-b8cca4912b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
93466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2363193466
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1840198281
Short name T1661
Test name
Test status
Simulation time 925386153 ps
CPU time 2.17 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206384 kb
Host smart-ae91d206-b031-4469-9386-8cf5fa2b3201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18401
98281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1840198281
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4191368508
Short name T2317
Test name
Test status
Simulation time 225905991 ps
CPU time 1.56 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 206328 kb
Host smart-a69be113-b56d-4b77-9992-e5b1d93e9eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41913
68508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4191368508
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2137027281
Short name T1835
Test name
Test status
Simulation time 186718348 ps
CPU time 0.81 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206216 kb
Host smart-754dfd53-2826-4297-a942-2072e870a34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21370
27281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2137027281
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3853855410
Short name T465
Test name
Test status
Simulation time 186604605 ps
CPU time 0.78 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206180 kb
Host smart-9ee16402-3bbb-4960-9d58-e465a7a65f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538
55410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3853855410
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3187414396
Short name T2223
Test name
Test status
Simulation time 208781915 ps
CPU time 0.88 seconds
Started Jul 07 05:25:27 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 206196 kb
Host smart-d32d9f32-3d6f-47f1-b873-4ae7cc0ee430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31874
14396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3187414396
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.128882404
Short name T2382
Test name
Test status
Simulation time 7443588797 ps
CPU time 51.34 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206432 kb
Host smart-9b5ee247-1df7-498a-8800-88074a587006
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=128882404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.128882404
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.4291071022
Short name T1249
Test name
Test status
Simulation time 235556540 ps
CPU time 0.96 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206184 kb
Host smart-601654ba-961f-41e6-aed6-ebc6421cc816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42910
71022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.4291071022
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2844785798
Short name T444
Test name
Test status
Simulation time 23351463107 ps
CPU time 24.25 seconds
Started Jul 07 05:25:31 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206096 kb
Host smart-7c33306b-4043-49e0-a813-c538ba85b270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
85798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2844785798
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1207249490
Short name T2216
Test name
Test status
Simulation time 3281606439 ps
CPU time 3.81 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206060 kb
Host smart-5a530ced-6171-4cd6-99bc-1cf038852420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12072
49490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1207249490
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.4215739147
Short name T913
Test name
Test status
Simulation time 10859047475 ps
CPU time 103.6 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:27:13 PM PDT 24
Peak memory 206520 kb
Host smart-04bf07ce-06b0-48ab-8429-ae88788a8185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42157
39147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.4215739147
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.291416648
Short name T2127
Test name
Test status
Simulation time 5582757752 ps
CPU time 156.97 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:28:15 PM PDT 24
Peak memory 206432 kb
Host smart-d352a917-5291-4c86-bada-cceb76637c5c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=291416648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.291416648
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3587936061
Short name T2203
Test name
Test status
Simulation time 244836034 ps
CPU time 1.07 seconds
Started Jul 07 05:25:31 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206020 kb
Host smart-0bd61bbf-4f38-4184-a514-0bd219671d70
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3587936061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3587936061
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2281943081
Short name T1996
Test name
Test status
Simulation time 192926677 ps
CPU time 0.84 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 206120 kb
Host smart-40d51f23-9194-45ab-a6ef-df54c7f08125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22819
43081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2281943081
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3708696991
Short name T2068
Test name
Test status
Simulation time 6705630587 ps
CPU time 60.26 seconds
Started Jul 07 05:25:30 PM PDT 24
Finished Jul 07 05:26:31 PM PDT 24
Peak memory 206512 kb
Host smart-7d74b54c-ae3a-46d8-ad21-56a1d54a70bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37086
96991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3708696991
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3201180988
Short name T1377
Test name
Test status
Simulation time 7502320712 ps
CPU time 199.44 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 206436 kb
Host smart-df5fe125-e4f2-4c5e-98f4-14a16233187c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3201180988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3201180988
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2352584438
Short name T2679
Test name
Test status
Simulation time 153101922 ps
CPU time 0.81 seconds
Started Jul 07 05:25:29 PM PDT 24
Finished Jul 07 05:25:31 PM PDT 24
Peak memory 206188 kb
Host smart-43d30843-ab86-411f-8ada-30c56365bbcc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2352584438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2352584438
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3996587571
Short name T1011
Test name
Test status
Simulation time 234782579 ps
CPU time 0.87 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206068 kb
Host smart-882872f4-bd95-42aa-bf4b-63a5a2cabc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39965
87571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3996587571
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.437810090
Short name T140
Test name
Test status
Simulation time 180679761 ps
CPU time 0.88 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:45 PM PDT 24
Peak memory 206112 kb
Host smart-fc1501b0-e1ec-445e-8981-ca6a244ae099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43781
0090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.437810090
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2188881596
Short name T1928
Test name
Test status
Simulation time 184505553 ps
CPU time 0.87 seconds
Started Jul 07 05:25:28 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 206176 kb
Host smart-aa9b19fc-857e-4f72-ad2d-8c52f635d1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21888
81596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2188881596
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.967105752
Short name T702
Test name
Test status
Simulation time 189805255 ps
CPU time 0.86 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:41 PM PDT 24
Peak memory 206192 kb
Host smart-a42cec34-ca2a-4cd8-aec6-085e2510ecee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96710
5752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.967105752
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.557891497
Short name T2481
Test name
Test status
Simulation time 169110981 ps
CPU time 0.8 seconds
Started Jul 07 05:25:39 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206188 kb
Host smart-74f2aad1-604a-4817-b93d-d98e8c8664ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55789
1497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.557891497
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2951062807
Short name T2685
Test name
Test status
Simulation time 156440327 ps
CPU time 0.79 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206192 kb
Host smart-2054cfcf-e61c-4752-abf7-d9767e3d8c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
62807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2951062807
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.4224906686
Short name T1306
Test name
Test status
Simulation time 198505898 ps
CPU time 0.95 seconds
Started Jul 07 05:25:49 PM PDT 24
Finished Jul 07 05:25:50 PM PDT 24
Peak memory 206084 kb
Host smart-62ceb3c8-deec-4a05-8bd5-944490704d27
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4224906686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.4224906686
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.500051384
Short name T1684
Test name
Test status
Simulation time 169710614 ps
CPU time 0.84 seconds
Started Jul 07 05:25:31 PM PDT 24
Finished Jul 07 05:25:32 PM PDT 24
Peak memory 206108 kb
Host smart-d6f07d8f-782a-46bf-a8e8-f7f36d9103f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50005
1384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.500051384
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1192874965
Short name T2286
Test name
Test status
Simulation time 37888782 ps
CPU time 0.69 seconds
Started Jul 07 05:25:34 PM PDT 24
Finished Jul 07 05:25:35 PM PDT 24
Peak memory 206176 kb
Host smart-99cc0286-a365-45bf-b833-999dc817219e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
74965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1192874965
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3642159850
Short name T2424
Test name
Test status
Simulation time 12730292465 ps
CPU time 28.38 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 214680 kb
Host smart-f4fbb7b5-c0ba-4fd9-ac31-bd633d6ac745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36421
59850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3642159850
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3760969999
Short name T358
Test name
Test status
Simulation time 169571059 ps
CPU time 0.84 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:41 PM PDT 24
Peak memory 206188 kb
Host smart-52413b33-2895-4139-843d-5fa300620167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
69999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3760969999
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2224652115
Short name T2712
Test name
Test status
Simulation time 231179244 ps
CPU time 0.9 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 206188 kb
Host smart-e850c62a-0ede-4cb4-9038-9c19c975a0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246
52115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2224652115
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2764984577
Short name T1639
Test name
Test status
Simulation time 166937444 ps
CPU time 0.82 seconds
Started Jul 07 05:25:32 PM PDT 24
Finished Jul 07 05:25:34 PM PDT 24
Peak memory 206432 kb
Host smart-c682f97d-09c4-4786-a1f7-2042a26ac2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27649
84577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2764984577
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.524214262
Short name T709
Test name
Test status
Simulation time 189122787 ps
CPU time 0.9 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:38 PM PDT 24
Peak memory 206156 kb
Host smart-3c33093d-22af-4619-8a77-10f50d88e7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52421
4262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.524214262
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1465180246
Short name T1345
Test name
Test status
Simulation time 176043536 ps
CPU time 0.78 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206184 kb
Host smart-e1df84e9-986a-4811-ad41-111135b47e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
80246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1465180246
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4117756327
Short name T2626
Test name
Test status
Simulation time 146817660 ps
CPU time 0.81 seconds
Started Jul 07 05:25:39 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206104 kb
Host smart-5712fa3b-086d-4e2a-b8dd-c6f0f27f7d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41177
56327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4117756327
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3534185995
Short name T582
Test name
Test status
Simulation time 164730448 ps
CPU time 0.8 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206188 kb
Host smart-c4c7c9ab-50f7-4b99-8f46-98da4f6bb8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35341
85995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3534185995
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.4147391912
Short name T841
Test name
Test status
Simulation time 239334662 ps
CPU time 0.91 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206108 kb
Host smart-760fd5c4-fb2c-4ab2-81d1-cbad09cf659c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41473
91912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.4147391912
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3254827533
Short name T1087
Test name
Test status
Simulation time 182767744 ps
CPU time 0.85 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206188 kb
Host smart-5feeb102-1a17-4726-8f5d-fbde892772fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32548
27533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3254827533
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.180295028
Short name T1224
Test name
Test status
Simulation time 193817154 ps
CPU time 0.84 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206152 kb
Host smart-d8d42592-6d43-4ed8-af9c-d866531290e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029
5028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.180295028
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2196419189
Short name T491
Test name
Test status
Simulation time 701148553 ps
CPU time 1.67 seconds
Started Jul 07 05:25:52 PM PDT 24
Finished Jul 07 05:25:54 PM PDT 24
Peak memory 206128 kb
Host smart-991fbfb3-59d9-4f9a-b0de-3771f3164b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21964
19189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2196419189
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1246972619
Short name T1715
Test name
Test status
Simulation time 7084560593 ps
CPU time 51.41 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 206372 kb
Host smart-175e6274-32a6-434f-b74a-2abb0b4b9c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12469
72619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1246972619
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.514047894
Short name T1430
Test name
Test status
Simulation time 41607153 ps
CPU time 0.66 seconds
Started Jul 07 05:26:06 PM PDT 24
Finished Jul 07 05:26:08 PM PDT 24
Peak memory 206216 kb
Host smart-51b81377-c3f8-45b9-b9b0-b14fd30af372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=514047894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.514047894
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2501033606
Short name T1774
Test name
Test status
Simulation time 4124412889 ps
CPU time 5.79 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206664 kb
Host smart-28354d5a-ef0b-4fd9-b4b2-08b5035c7177
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2501033606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2501033606
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.746664012
Short name T2238
Test name
Test status
Simulation time 13364423463 ps
CPU time 13.22 seconds
Started Jul 07 05:25:50 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206164 kb
Host smart-2e1a5955-895d-40ca-961d-c0df6c8e814a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=746664012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.746664012
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2333792924
Short name T2360
Test name
Test status
Simulation time 23405719492 ps
CPU time 27.05 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:26:11 PM PDT 24
Peak memory 206316 kb
Host smart-0be6b49f-5b54-4836-9835-f8d0a66d1dd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2333792924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2333792924
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.394357792
Short name T459
Test name
Test status
Simulation time 198134923 ps
CPU time 0.85 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 206184 kb
Host smart-d77b1431-fc57-4a57-9b56-a21c345a9479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39435
7792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.394357792
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2255459148
Short name T1071
Test name
Test status
Simulation time 145916377 ps
CPU time 0.78 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206120 kb
Host smart-cbcff23f-a5c7-44eb-8186-e105f4fcea97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22554
59148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2255459148
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.788801170
Short name T2027
Test name
Test status
Simulation time 227783919 ps
CPU time 1.03 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 206196 kb
Host smart-d87b01f6-06a5-441c-9368-0a6dd1d03063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78880
1170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.788801170
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.940643134
Short name T1145
Test name
Test status
Simulation time 1306516060 ps
CPU time 2.8 seconds
Started Jul 07 05:25:50 PM PDT 24
Finished Jul 07 05:25:53 PM PDT 24
Peak memory 206368 kb
Host smart-50243c2a-ed8f-4723-99b3-f38bac033279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94064
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.940643134
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3428353763
Short name T2292
Test name
Test status
Simulation time 6406065717 ps
CPU time 13.04 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:16 PM PDT 24
Peak memory 206468 kb
Host smart-7bd8b9a0-0118-4c67-b4b9-5c043b6fb9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34283
53763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3428353763
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.531267947
Short name T2465
Test name
Test status
Simulation time 460499357 ps
CPU time 1.45 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:47 PM PDT 24
Peak memory 206032 kb
Host smart-bcf742f1-359b-4bc1-b16a-c6cf567cfbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53126
7947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.531267947
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3080981305
Short name T2709
Test name
Test status
Simulation time 232258256 ps
CPU time 0.82 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:38 PM PDT 24
Peak memory 206188 kb
Host smart-9d556b92-676a-4267-a2de-9822c2d14649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30809
81305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3080981305
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3588191934
Short name T1126
Test name
Test status
Simulation time 37677486 ps
CPU time 0.66 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206136 kb
Host smart-a4e07a37-830a-45a0-a27d-3f9ce8e1c062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35881
91934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3588191934
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.212471316
Short name T2100
Test name
Test status
Simulation time 904556046 ps
CPU time 2.21 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:43 PM PDT 24
Peak memory 206320 kb
Host smart-4c48c6ed-011a-4ca8-bda1-69574c586a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
1316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.212471316
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4252673753
Short name T1069
Test name
Test status
Simulation time 314302087 ps
CPU time 2.3 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 206292 kb
Host smart-ae29687d-5fab-4410-b6e7-6035b1caf915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42526
73753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4252673753
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3232877023
Short name T1648
Test name
Test status
Simulation time 244576811 ps
CPU time 1.02 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:25:38 PM PDT 24
Peak memory 206184 kb
Host smart-bfdab6ea-0f5d-4156-b73f-ae9c917b14b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32328
77023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3232877023
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3666578334
Short name T1361
Test name
Test status
Simulation time 140762615 ps
CPU time 0.72 seconds
Started Jul 07 05:25:46 PM PDT 24
Finished Jul 07 05:25:47 PM PDT 24
Peak memory 206200 kb
Host smart-e1b009dd-4954-4df2-b529-e360e8b7e149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36665
78334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3666578334
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.4126135017
Short name T1453
Test name
Test status
Simulation time 206635813 ps
CPU time 0.89 seconds
Started Jul 07 05:25:46 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206188 kb
Host smart-2ce63d28-8d0e-4dc1-a0ad-04597d83fe78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41261
35017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.4126135017
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.4140448708
Short name T1664
Test name
Test status
Simulation time 9309758768 ps
CPU time 258.8 seconds
Started Jul 07 05:25:52 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 206412 kb
Host smart-c51cb18a-2f41-484c-b3e5-fd98cbe87347
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4140448708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.4140448708
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2667842218
Short name T423
Test name
Test status
Simulation time 191078735 ps
CPU time 0.83 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 204848 kb
Host smart-1ef028bf-fe43-4493-8015-38cd6dd459fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26678
42218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2667842218
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.830019909
Short name T454
Test name
Test status
Simulation time 23295297314 ps
CPU time 24.31 seconds
Started Jul 07 05:25:36 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206268 kb
Host smart-d2ee6c40-c38e-4cf9-87f0-9dc0f6993c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83001
9909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.830019909
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3877670053
Short name T2503
Test name
Test status
Simulation time 3286183691 ps
CPU time 4.68 seconds
Started Jul 07 05:25:46 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 206248 kb
Host smart-9d03ca14-670b-41ca-8a14-2b740d20f698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38776
70053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3877670053
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.330947143
Short name T2177
Test name
Test status
Simulation time 8993163676 ps
CPU time 250.78 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 206560 kb
Host smart-8c0fbdd8-2c74-416b-ac90-2dd3c54b3b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33094
7143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.330947143
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1191181867
Short name T2374
Test name
Test status
Simulation time 6304387687 ps
CPU time 43.99 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 206432 kb
Host smart-c5a0870d-b78a-4e6c-8876-139a03a5b93f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1191181867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1191181867
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.217933123
Short name T2035
Test name
Test status
Simulation time 233459063 ps
CPU time 0.96 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 206064 kb
Host smart-20bff401-d80c-47c7-ad35-37be6f9c5bf4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=217933123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.217933123
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4074467645
Short name T1623
Test name
Test status
Simulation time 224652849 ps
CPU time 1 seconds
Started Jul 07 05:25:40 PM PDT 24
Finished Jul 07 05:25:47 PM PDT 24
Peak memory 206136 kb
Host smart-90b546c9-689f-4271-a856-a97516bc23e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744
67645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4074467645
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.578361362
Short name T2672
Test name
Test status
Simulation time 3609929395 ps
CPU time 105.44 seconds
Started Jul 07 05:25:45 PM PDT 24
Finished Jul 07 05:27:32 PM PDT 24
Peak memory 206412 kb
Host smart-013cde9f-7bc1-440c-b9db-59c0fc7d74c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57836
1362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.578361362
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.2055730783
Short name T2657
Test name
Test status
Simulation time 6736577189 ps
CPU time 63.27 seconds
Started Jul 07 05:25:51 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 206444 kb
Host smart-979c23f8-8397-4ed7-8be8-e7653899a269
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2055730783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.2055730783
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1647942641
Short name T2695
Test name
Test status
Simulation time 153432362 ps
CPU time 0.83 seconds
Started Jul 07 05:25:37 PM PDT 24
Finished Jul 07 05:25:39 PM PDT 24
Peak memory 206176 kb
Host smart-10f62b59-9f2e-4edc-870e-0070d67a32e6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1647942641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1647942641
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.349323968
Short name T1832
Test name
Test status
Simulation time 145697831 ps
CPU time 0.81 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 206112 kb
Host smart-4a1ed46b-1cf4-463c-97d9-b841b2f30e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34932
3968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.349323968
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.586022670
Short name T139
Test name
Test status
Simulation time 192115145 ps
CPU time 0.89 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:25:42 PM PDT 24
Peak memory 206184 kb
Host smart-65cdb99a-e4ca-4926-b573-99653ae6772f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58602
2670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.586022670
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2893710452
Short name T1450
Test name
Test status
Simulation time 247962873 ps
CPU time 0.88 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 206148 kb
Host smart-c2e45ada-68b2-4744-9d76-67082f74c798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28937
10452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2893710452
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.363559536
Short name T2562
Test name
Test status
Simulation time 168846928 ps
CPU time 0.83 seconds
Started Jul 07 05:25:52 PM PDT 24
Finished Jul 07 05:25:53 PM PDT 24
Peak memory 206100 kb
Host smart-14e66649-9f46-445a-8484-ebada4963775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
9536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.363559536
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.484253532
Short name T1739
Test name
Test status
Simulation time 193300046 ps
CPU time 0.82 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:25:43 PM PDT 24
Peak memory 206216 kb
Host smart-52e5d7b6-1348-42d9-8b47-8aa342565f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48425
3532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.484253532
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1045600430
Short name T674
Test name
Test status
Simulation time 170087496 ps
CPU time 0.88 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:00 PM PDT 24
Peak memory 206136 kb
Host smart-657cdaea-759c-458c-9afc-c0ebe6e58cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10456
00430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1045600430
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.408437293
Short name T814
Test name
Test status
Simulation time 270510580 ps
CPU time 1.04 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206188 kb
Host smart-d7ac7a2d-6f46-4349-8fb6-9041f9994bac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=408437293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.408437293
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2724437053
Short name T809
Test name
Test status
Simulation time 164070871 ps
CPU time 0.82 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:46 PM PDT 24
Peak memory 206184 kb
Host smart-22c02418-4a75-44fc-afbe-ecf5c093ddc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
37053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2724437053
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.452511926
Short name T1426
Test name
Test status
Simulation time 39472165 ps
CPU time 0.67 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 206096 kb
Host smart-255ce3f1-7c23-4212-b324-5addbe4e15d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45251
1926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.452511926
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3422060708
Short name T263
Test name
Test status
Simulation time 15857862717 ps
CPU time 34.45 seconds
Started Jul 07 05:25:41 PM PDT 24
Finished Jul 07 05:26:15 PM PDT 24
Peak memory 206540 kb
Host smart-6d162f6d-c166-47da-8df5-dab06f853307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34220
60708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3422060708
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3189660715
Short name T2102
Test name
Test status
Simulation time 261948011 ps
CPU time 0.94 seconds
Started Jul 07 05:25:39 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206200 kb
Host smart-e102dbce-b926-4065-997a-4c7867f2bcf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
60715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3189660715
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3872570422
Short name T2227
Test name
Test status
Simulation time 275498297 ps
CPU time 1 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206224 kb
Host smart-5a36b0f6-4b82-4ded-ac29-0458daa6e93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38725
70422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3872570422
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3130554571
Short name T2516
Test name
Test status
Simulation time 176830038 ps
CPU time 0.88 seconds
Started Jul 07 05:25:49 PM PDT 24
Finished Jul 07 05:25:50 PM PDT 24
Peak memory 206188 kb
Host smart-e27916ab-3496-4411-a447-80ba38518f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31305
54571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3130554571
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1994492748
Short name T689
Test name
Test status
Simulation time 189724061 ps
CPU time 0.87 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 206132 kb
Host smart-b4c8e1ed-1c6d-44ad-bc35-1e80e5f411b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
92748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1994492748
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3760191754
Short name T596
Test name
Test status
Simulation time 190681684 ps
CPU time 0.8 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:25:43 PM PDT 24
Peak memory 206192 kb
Host smart-7ebb3c36-a353-4a05-b6ac-1b81017be7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37601
91754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3760191754
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2587377734
Short name T2021
Test name
Test status
Simulation time 158565046 ps
CPU time 0.79 seconds
Started Jul 07 05:25:54 PM PDT 24
Finished Jul 07 05:25:55 PM PDT 24
Peak memory 206136 kb
Host smart-6e7b32f2-56da-417d-bfb1-6ba45289a669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873
77734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2587377734
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2800451698
Short name T1473
Test name
Test status
Simulation time 150633504 ps
CPU time 0.8 seconds
Started Jul 07 05:25:52 PM PDT 24
Finished Jul 07 05:25:53 PM PDT 24
Peak memory 206144 kb
Host smart-a85d815c-324c-4dc7-a11f-9c11266d6fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28004
51698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2800451698
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.451360540
Short name T1176
Test name
Test status
Simulation time 210042984 ps
CPU time 0.9 seconds
Started Jul 07 05:25:42 PM PDT 24
Finished Jul 07 05:25:43 PM PDT 24
Peak memory 206132 kb
Host smart-4974d3c6-419e-40f7-a831-73fcdd99135b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45136
0540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.451360540
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3148862316
Short name T422
Test name
Test status
Simulation time 4300168898 ps
CPU time 32.25 seconds
Started Jul 07 05:25:43 PM PDT 24
Finished Jul 07 05:26:16 PM PDT 24
Peak memory 206416 kb
Host smart-63ea1dfb-af5e-41ed-9201-211baff50112
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3148862316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3148862316
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.765138410
Short name T1299
Test name
Test status
Simulation time 159818607 ps
CPU time 0.85 seconds
Started Jul 07 05:25:38 PM PDT 24
Finished Jul 07 05:25:40 PM PDT 24
Peak memory 206064 kb
Host smart-fb0a6137-f29c-43d5-91ae-7528a2aa7dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76513
8410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.765138410
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.384862802
Short name T1290
Test name
Test status
Simulation time 183801655 ps
CPU time 0.82 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206200 kb
Host smart-cd903d8e-1ac5-41f4-a00f-44654cca9b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
2802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.384862802
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2659715459
Short name T503
Test name
Test status
Simulation time 343513845 ps
CPU time 1.11 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:02 PM PDT 24
Peak memory 206196 kb
Host smart-2e0808bb-c228-452f-8890-c6c6589a14fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26597
15459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2659715459
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1596966058
Short name T1108
Test name
Test status
Simulation time 6199953400 ps
CPU time 175.33 seconds
Started Jul 07 05:25:46 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 206208 kb
Host smart-f8b993fc-d60d-43ca-8707-28733036f584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969
66058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1596966058
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2998561879
Short name T627
Test name
Test status
Simulation time 56942038 ps
CPU time 0.73 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206224 kb
Host smart-ba8f9966-705c-4194-a19b-30de9a54d485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2998561879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2998561879
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3719835298
Short name T2327
Test name
Test status
Simulation time 4426828744 ps
CPU time 4.96 seconds
Started Jul 07 05:25:46 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 205940 kb
Host smart-3e0333d4-0b36-4b52-a49b-f5b43da34267
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3719835298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3719835298
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2013468583
Short name T989
Test name
Test status
Simulation time 13507635704 ps
CPU time 13.52 seconds
Started Jul 07 05:25:45 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 206444 kb
Host smart-84aa577a-bd6b-4038-bc2e-2bd4aad3aa85
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2013468583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2013468583
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1482481878
Short name T2254
Test name
Test status
Simulation time 23385056495 ps
CPU time 23.25 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:26:08 PM PDT 24
Peak memory 206144 kb
Host smart-9344087c-74b4-46f0-996a-9e304462b1f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1482481878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1482481878
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1319974854
Short name T854
Test name
Test status
Simulation time 166281634 ps
CPU time 0.81 seconds
Started Jul 07 05:25:47 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206204 kb
Host smart-50ea1304-e43f-4b3d-9826-0a4fe536a4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199
74854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1319974854
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3471784590
Short name T1262
Test name
Test status
Simulation time 146804174 ps
CPU time 0.73 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:45 PM PDT 24
Peak memory 206184 kb
Host smart-e727d853-7bac-4482-bcfb-db25e264a706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
84590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3471784590
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2327468945
Short name T686
Test name
Test status
Simulation time 328883306 ps
CPU time 1.14 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206088 kb
Host smart-17a1382d-f0b6-4dd2-a2cc-2601c4fd6ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23274
68945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2327468945
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1619123634
Short name T826
Test name
Test status
Simulation time 1418224034 ps
CPU time 2.89 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206392 kb
Host smart-211006ae-2b29-4ae5-b265-a8fc06ea2f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16191
23634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1619123634
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3092911293
Short name T993
Test name
Test status
Simulation time 14116459545 ps
CPU time 27.74 seconds
Started Jul 07 05:25:54 PM PDT 24
Finished Jul 07 05:26:22 PM PDT 24
Peak memory 206444 kb
Host smart-b5bd835f-6828-4445-8348-76bc5d9ab30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
11293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3092911293
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2409137967
Short name T2125
Test name
Test status
Simulation time 364742627 ps
CPU time 1.16 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206200 kb
Host smart-568c1b8b-6046-4b21-b06a-eca9103b52f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24091
37967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2409137967
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1860799662
Short name T2461
Test name
Test status
Simulation time 191722386 ps
CPU time 0.8 seconds
Started Jul 07 05:25:54 PM PDT 24
Finished Jul 07 05:25:55 PM PDT 24
Peak memory 206200 kb
Host smart-0c890ca2-11db-48da-b021-fb99f2b2a628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
99662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1860799662
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.640863940
Short name T1867
Test name
Test status
Simulation time 53082049 ps
CPU time 0.67 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206192 kb
Host smart-855bf9c5-4715-4419-8284-adb58917ff1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64086
3940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.640863940
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1715872083
Short name T2265
Test name
Test status
Simulation time 1012474534 ps
CPU time 2.31 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206696 kb
Host smart-3e85f5a5-1eac-408a-bdb9-3e6669181199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
72083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1715872083
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1568772025
Short name T577
Test name
Test status
Simulation time 296716890 ps
CPU time 1.7 seconds
Started Jul 07 05:25:44 PM PDT 24
Finished Jul 07 05:25:47 PM PDT 24
Peak memory 206372 kb
Host smart-bcfb95c3-4c2f-4d8f-8cc9-dfee9696c7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15687
72025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1568772025
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1970551812
Short name T2304
Test name
Test status
Simulation time 245226234 ps
CPU time 0.91 seconds
Started Jul 07 05:25:58 PM PDT 24
Finished Jul 07 05:26:00 PM PDT 24
Peak memory 206084 kb
Host smart-f063c00a-d992-44a6-814e-08820f08c948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19705
51812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1970551812
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1042571123
Short name T2295
Test name
Test status
Simulation time 150963887 ps
CPU time 0.77 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:02 PM PDT 24
Peak memory 206148 kb
Host smart-19ff0e09-6668-44a4-90b8-2ebd326a80b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10425
71123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1042571123
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1904274489
Short name T367
Test name
Test status
Simulation time 197181450 ps
CPU time 0.89 seconds
Started Jul 07 05:25:46 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206188 kb
Host smart-5db2aa4b-a561-4ebe-bea3-4589ba3f1c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19042
74489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1904274489
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.18594949
Short name T690
Test name
Test status
Simulation time 6270025170 ps
CPU time 43.55 seconds
Started Jul 07 05:25:45 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 206276 kb
Host smart-ed5fdd47-a613-4e6c-9853-d9ade5a3af9d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=18594949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.18594949
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.544205621
Short name T2315
Test name
Test status
Simulation time 237165298 ps
CPU time 0.95 seconds
Started Jul 07 05:25:49 PM PDT 24
Finished Jul 07 05:25:50 PM PDT 24
Peak memory 206164 kb
Host smart-69581d02-11d6-461a-af40-82fabc7a5bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54420
5621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.544205621
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1157207546
Short name T1149
Test name
Test status
Simulation time 23371012272 ps
CPU time 26.48 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 206256 kb
Host smart-358ce62a-3a29-4aab-845b-ebfb7c5b9148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11572
07546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1157207546
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.138767188
Short name T2344
Test name
Test status
Simulation time 3314246956 ps
CPU time 4.52 seconds
Started Jul 07 05:25:48 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 206272 kb
Host smart-d9d0dd1c-19ac-4edb-aa23-3e3fc7c427ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13876
7188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.138767188
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.269563860
Short name T1160
Test name
Test status
Simulation time 8252741188 ps
CPU time 59.07 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 206444 kb
Host smart-f4d86b77-6ad0-4339-8630-ca996ec27e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26956
3860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.269563860
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.205958480
Short name T2633
Test name
Test status
Simulation time 6596044242 ps
CPU time 187.59 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:29:11 PM PDT 24
Peak memory 206484 kb
Host smart-352c0a46-5722-4abf-8636-33cff9413991
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=205958480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.205958480
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3489323125
Short name T1135
Test name
Test status
Simulation time 241887997 ps
CPU time 0.9 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 206120 kb
Host smart-59bb0ae5-15f8-4e68-be4c-b2070e81e1b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3489323125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3489323125
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3368471508
Short name T1717
Test name
Test status
Simulation time 188674115 ps
CPU time 0.91 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206104 kb
Host smart-e7147cdc-a7d4-4a7b-b081-af242f0e3171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33684
71508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3368471508
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2933176766
Short name T649
Test name
Test status
Simulation time 3929416929 ps
CPU time 113.13 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:27:56 PM PDT 24
Peak memory 206696 kb
Host smart-93ec432a-6634-4b5a-9f1a-5638d560284c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29331
76766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2933176766
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3992066118
Short name T878
Test name
Test status
Simulation time 5148331555 ps
CPU time 150.55 seconds
Started Jul 07 05:25:50 PM PDT 24
Finished Jul 07 05:28:20 PM PDT 24
Peak memory 206404 kb
Host smart-d7c12086-d419-4622-9141-980bcf5755dd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3992066118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3992066118
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3309445295
Short name T1893
Test name
Test status
Simulation time 158883452 ps
CPU time 0.79 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206096 kb
Host smart-688f9584-5a04-4532-9602-e60aad1b89a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3309445295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3309445295
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.167404458
Short name T2351
Test name
Test status
Simulation time 153324789 ps
CPU time 0.77 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206128 kb
Host smart-d8263ad6-6fdd-4239-b600-eceede03618f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
4458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.167404458
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2370714690
Short name T149
Test name
Test status
Simulation time 193960551 ps
CPU time 0.83 seconds
Started Jul 07 05:25:51 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 206100 kb
Host smart-183f57d5-d313-46dd-a51c-7087c637c1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23707
14690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2370714690
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1248090886
Short name T1854
Test name
Test status
Simulation time 165140171 ps
CPU time 0.79 seconds
Started Jul 07 05:25:48 PM PDT 24
Finished Jul 07 05:25:50 PM PDT 24
Peak memory 206176 kb
Host smart-6e313fbf-3f37-4546-9b12-a5df2f0ff84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12480
90886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1248090886
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3331829104
Short name T2543
Test name
Test status
Simulation time 158605945 ps
CPU time 0.73 seconds
Started Jul 07 05:26:06 PM PDT 24
Finished Jul 07 05:26:08 PM PDT 24
Peak memory 205936 kb
Host smart-b81a914d-ac40-4a8f-ac0f-4f0ba1df7d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
29104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3331829104
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.4004851304
Short name T2074
Test name
Test status
Simulation time 183946087 ps
CPU time 0.87 seconds
Started Jul 07 05:25:49 PM PDT 24
Finished Jul 07 05:25:50 PM PDT 24
Peak memory 206184 kb
Host smart-314a7b27-3fcd-462f-8ed8-0d7c25c3a39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40048
51304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.4004851304
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4103764011
Short name T2200
Test name
Test status
Simulation time 147643458 ps
CPU time 0.83 seconds
Started Jul 07 05:25:53 PM PDT 24
Finished Jul 07 05:25:54 PM PDT 24
Peak memory 206200 kb
Host smart-71f71c6f-f2b7-4618-8b79-ab4acec92c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41037
64011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4103764011
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1845006825
Short name T896
Test name
Test status
Simulation time 215306036 ps
CPU time 0.98 seconds
Started Jul 07 05:25:51 PM PDT 24
Finished Jul 07 05:25:52 PM PDT 24
Peak memory 206152 kb
Host smart-27de52cd-f515-4d3a-9496-278c7ce4c866
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1845006825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1845006825
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.169940496
Short name T2700
Test name
Test status
Simulation time 150085003 ps
CPU time 0.81 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 206192 kb
Host smart-56056ad4-5c80-41a3-97d0-5ca0a26c08ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16994
0496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.169940496
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.920088329
Short name T1680
Test name
Test status
Simulation time 45811404 ps
CPU time 0.67 seconds
Started Jul 07 05:25:57 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206164 kb
Host smart-de06d963-6740-4273-9b73-06e7fa984a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92008
8329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.920088329
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3574572317
Short name T1530
Test name
Test status
Simulation time 21101092472 ps
CPU time 51.29 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 206492 kb
Host smart-7431ff39-d464-4433-aa8e-67d13f49f031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35745
72317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3574572317
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1484050839
Short name T1918
Test name
Test status
Simulation time 154869273 ps
CPU time 0.79 seconds
Started Jul 07 05:25:50 PM PDT 24
Finished Jul 07 05:25:51 PM PDT 24
Peak memory 206196 kb
Host smart-81ceff13-0b59-452d-b859-b043125a5f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14840
50839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1484050839
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.290291062
Short name T1388
Test name
Test status
Simulation time 243325579 ps
CPU time 0.95 seconds
Started Jul 07 05:25:54 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206144 kb
Host smart-8d5bae6b-1d94-4bc8-8f6d-4f9178d57c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029
1062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.290291062
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1222662646
Short name T1638
Test name
Test status
Simulation time 172208716 ps
CPU time 0.82 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206156 kb
Host smart-97cecf0b-2e6a-41f3-8d7e-d2a51c4b7483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226
62646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1222662646
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2963619916
Short name T1602
Test name
Test status
Simulation time 173265571 ps
CPU time 0.84 seconds
Started Jul 07 05:26:07 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206120 kb
Host smart-1f2a1a3d-3580-48c7-aa64-9a924e0856b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29636
19916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2963619916
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.85368315
Short name T1044
Test name
Test status
Simulation time 169825200 ps
CPU time 0.8 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206116 kb
Host smart-db87ee45-48d9-4af0-88a3-a3796ffccf0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85368
315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.85368315
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2044493830
Short name T2114
Test name
Test status
Simulation time 156187838 ps
CPU time 0.77 seconds
Started Jul 07 05:25:47 PM PDT 24
Finished Jul 07 05:25:48 PM PDT 24
Peak memory 206164 kb
Host smart-b3371eb6-cd76-4d98-9eae-adf73f39ecae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
93830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2044493830
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3084188293
Short name T885
Test name
Test status
Simulation time 146795149 ps
CPU time 0.78 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206192 kb
Host smart-352ec781-497c-4fae-b25d-08526e506683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30841
88293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3084188293
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2533014581
Short name T959
Test name
Test status
Simulation time 234237355 ps
CPU time 1 seconds
Started Jul 07 05:25:53 PM PDT 24
Finished Jul 07 05:25:55 PM PDT 24
Peak memory 206196 kb
Host smart-11b569f0-bf86-4c6c-8153-4cfa858c42ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25330
14581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2533014581
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3730468607
Short name T1375
Test name
Test status
Simulation time 6609241937 ps
CPU time 51.34 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 206360 kb
Host smart-760a2043-0d90-4cab-9812-38c41f0bf6c6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3730468607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3730468607
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.349752543
Short name T1868
Test name
Test status
Simulation time 159180149 ps
CPU time 0.78 seconds
Started Jul 07 05:25:48 PM PDT 24
Finished Jul 07 05:25:49 PM PDT 24
Peak memory 206168 kb
Host smart-5c2ff80a-5306-4f4c-a335-a7ba1077df85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34975
2543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.349752543
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1728795019
Short name T1212
Test name
Test status
Simulation time 204261060 ps
CPU time 0.86 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206180 kb
Host smart-a9bb4c14-7ce2-4d18-8859-996d5dea57a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
95019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1728795019
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.4177293490
Short name T28
Test name
Test status
Simulation time 1026249765 ps
CPU time 2.33 seconds
Started Jul 07 05:25:51 PM PDT 24
Finished Jul 07 05:25:53 PM PDT 24
Peak memory 206364 kb
Host smart-5ff78c24-75b5-4a75-b0d1-3f3dcb4d08fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41772
93490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.4177293490
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1417891490
Short name T2417
Test name
Test status
Simulation time 7140468692 ps
CPU time 199.81 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 206496 kb
Host smart-3a35ff74-9c9e-4d56-bc23-0a0695c26953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
91490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1417891490
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.3336117245
Short name T216
Test name
Test status
Simulation time 57056242 ps
CPU time 0.71 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206220 kb
Host smart-b66ec4f8-ce7c-41c5-9152-49347cd53285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3336117245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3336117245
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.900341490
Short name T2167
Test name
Test status
Simulation time 4255156526 ps
CPU time 5.06 seconds
Started Jul 07 05:25:54 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 206228 kb
Host smart-d42ea67c-4d8a-4d64-9ea8-3a39662316fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=900341490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.900341490
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3080208785
Short name T1944
Test name
Test status
Simulation time 13357343881 ps
CPU time 15.19 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:17 PM PDT 24
Peak memory 206232 kb
Host smart-26af6e22-ba69-4ae6-b0e9-e7d692312f00
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3080208785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3080208785
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.958912271
Short name T2479
Test name
Test status
Simulation time 23461199260 ps
CPU time 23.78 seconds
Started Jul 07 05:25:54 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206496 kb
Host smart-32ba8fb2-4ed1-470b-a3cc-4fe41203fb83
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=958912271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.958912271
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3213063888
Short name T1037
Test name
Test status
Simulation time 181044519 ps
CPU time 0.8 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:00 PM PDT 24
Peak memory 206108 kb
Host smart-997a16f9-8a81-4fb9-be75-ebb805d4f5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32130
63888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3213063888
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.4277027038
Short name T2107
Test name
Test status
Simulation time 169085584 ps
CPU time 0.81 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206036 kb
Host smart-3fb503fc-58f1-48ff-8e1c-ec98eaa64d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
27038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.4277027038
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.4219259725
Short name T184
Test name
Test status
Simulation time 333001262 ps
CPU time 1.16 seconds
Started Jul 07 05:25:57 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 205780 kb
Host smart-dde8b05d-9cba-4f87-be26-ff186b9e1977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42192
59725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.4219259725
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2511871104
Short name T2504
Test name
Test status
Simulation time 1269431410 ps
CPU time 2.84 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206280 kb
Host smart-088a8a59-86a2-4881-a0b4-9d257c4d0dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25118
71104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2511871104
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2806058690
Short name T1946
Test name
Test status
Simulation time 12038424486 ps
CPU time 23.5 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206432 kb
Host smart-e8951fb8-942b-421c-8cea-d812ed985f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28060
58690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2806058690
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.880517413
Short name T1572
Test name
Test status
Simulation time 337184463 ps
CPU time 1.23 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206188 kb
Host smart-834fe01d-d8d9-4217-b87e-83db45469614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88051
7413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.880517413
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.230428477
Short name T1015
Test name
Test status
Simulation time 173062521 ps
CPU time 0.78 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:00 PM PDT 24
Peak memory 206108 kb
Host smart-eca34515-1ed9-407e-b1c4-df5a5dfc65ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23042
8477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.230428477
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.4194880585
Short name T1360
Test name
Test status
Simulation time 61319725 ps
CPU time 0.69 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:00 PM PDT 24
Peak memory 206180 kb
Host smart-aa6251b5-f62d-4a8b-bfc2-30ba3fd14579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948
80585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.4194880585
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.500821114
Short name T2199
Test name
Test status
Simulation time 724877056 ps
CPU time 2 seconds
Started Jul 07 05:25:58 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206392 kb
Host smart-09ea9395-b53a-46b8-9cee-97983929232a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50082
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.500821114
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2552046871
Short name T2558
Test name
Test status
Simulation time 171470112 ps
CPU time 1.71 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:02 PM PDT 24
Peak memory 206676 kb
Host smart-8b393ad2-a6d5-4922-ae10-5dfd51dbb8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
46871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2552046871
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2691023032
Short name T273
Test name
Test status
Simulation time 242767588 ps
CPU time 0.95 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206184 kb
Host smart-43b93ce6-d55c-4e43-8f78-ccbb26224323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26910
23032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2691023032
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.285204035
Short name T1013
Test name
Test status
Simulation time 200039297 ps
CPU time 0.79 seconds
Started Jul 07 05:25:57 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206188 kb
Host smart-1b054dba-4322-48c3-8ee3-fead86fbd6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28520
4035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.285204035
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.4288245512
Short name T1589
Test name
Test status
Simulation time 185117991 ps
CPU time 0.87 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206100 kb
Host smart-e3a8c23c-1041-47f1-a400-38766057f9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42882
45512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.4288245512
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.4133909807
Short name T2212
Test name
Test status
Simulation time 10477915506 ps
CPU time 74.76 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 206344 kb
Host smart-20b961fe-56a0-4dd3-8a27-85b76ceef652
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4133909807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.4133909807
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2953324495
Short name T499
Test name
Test status
Simulation time 270914225 ps
CPU time 0.94 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:02 PM PDT 24
Peak memory 206184 kb
Host smart-1b51e007-e26c-4e5b-aa1e-24a0e94700b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29533
24495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2953324495
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3933322581
Short name T2334
Test name
Test status
Simulation time 23283959352 ps
CPU time 21.63 seconds
Started Jul 07 05:25:58 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206252 kb
Host smart-baf2407f-eb62-4fd3-9213-c686d8853b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39333
22581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3933322581
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.898984563
Short name T1759
Test name
Test status
Simulation time 3331689137 ps
CPU time 3.8 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206244 kb
Host smart-e47517d2-91ac-4347-839c-dfb461e016fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89898
4563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.898984563
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.4205016638
Short name T2537
Test name
Test status
Simulation time 7433860357 ps
CPU time 201.12 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:29:20 PM PDT 24
Peak memory 206548 kb
Host smart-af2e279f-eb16-4e91-a791-761466084f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
16638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.4205016638
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2703568385
Short name T592
Test name
Test status
Simulation time 7678670906 ps
CPU time 208.74 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 206332 kb
Host smart-391a86cb-0ae7-48b5-bf11-784950475908
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2703568385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2703568385
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3460241314
Short name T1128
Test name
Test status
Simulation time 234829668 ps
CPU time 0.91 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:26:19 PM PDT 24
Peak memory 206092 kb
Host smart-52216d62-48c9-45c3-ad3f-f6356f8e347f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3460241314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3460241314
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2181443913
Short name T1143
Test name
Test status
Simulation time 213580535 ps
CPU time 0.91 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206188 kb
Host smart-dc5609f2-1631-44f9-b614-f88f1c676819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21814
43913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2181443913
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1754689287
Short name T537
Test name
Test status
Simulation time 4393319717 ps
CPU time 35.23 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:35 PM PDT 24
Peak memory 206464 kb
Host smart-50f8b3d4-8632-412b-9661-0887e0e4c6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
89287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1754689287
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.4034305035
Short name T818
Test name
Test status
Simulation time 4561491117 ps
CPU time 35.19 seconds
Started Jul 07 05:25:53 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 206420 kb
Host smart-c695eab3-fddc-4023-9f92-834b7941c56b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4034305035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.4034305035
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1432133056
Short name T1372
Test name
Test status
Simulation time 189431806 ps
CPU time 0.85 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206092 kb
Host smart-f411fb2c-bb6c-49b3-8991-d9b479a62dbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1432133056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1432133056
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1508946040
Short name T562
Test name
Test status
Simulation time 149888138 ps
CPU time 0.77 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206112 kb
Host smart-becc704d-4090-47cb-9611-97e97c1881c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15089
46040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1508946040
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.146699901
Short name T2379
Test name
Test status
Simulation time 201025714 ps
CPU time 0.83 seconds
Started Jul 07 05:26:12 PM PDT 24
Finished Jul 07 05:26:13 PM PDT 24
Peak memory 206116 kb
Host smart-66c023a7-e37d-44b8-8d66-02428ff902d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669
9901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.146699901
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2707401182
Short name T2340
Test name
Test status
Simulation time 204741124 ps
CPU time 0.81 seconds
Started Jul 07 05:25:58 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 205956 kb
Host smart-8f6b9b36-3503-4732-859c-42cb8e7f9a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27074
01182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2707401182
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.172408466
Short name T2625
Test name
Test status
Simulation time 222005409 ps
CPU time 0.86 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206192 kb
Host smart-6b401912-5564-4045-99ea-d8444bbbbec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240
8466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.172408466
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1000292229
Short name T1984
Test name
Test status
Simulation time 156614249 ps
CPU time 0.85 seconds
Started Jul 07 05:25:56 PM PDT 24
Finished Jul 07 05:25:57 PM PDT 24
Peak memory 206188 kb
Host smart-7e80e7e2-17f8-4351-b728-bbb07ae4dfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10002
92229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1000292229
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.4206339040
Short name T845
Test name
Test status
Simulation time 193486502 ps
CPU time 0.88 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206196 kb
Host smart-1ba35d40-224b-45ed-ad42-09635a0b1da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42063
39040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.4206339040
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2179824967
Short name T1856
Test name
Test status
Simulation time 240727514 ps
CPU time 0.95 seconds
Started Jul 07 05:25:57 PM PDT 24
Finished Jul 07 05:25:58 PM PDT 24
Peak memory 206008 kb
Host smart-7b301488-a8f1-4747-a7fd-4d3082ba8e2f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2179824967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2179824967
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.600264861
Short name T1922
Test name
Test status
Simulation time 145713026 ps
CPU time 0.79 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206184 kb
Host smart-57b71de9-1253-437e-8848-6da6f26808ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60026
4861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.600264861
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2011337503
Short name T850
Test name
Test status
Simulation time 50090345 ps
CPU time 0.65 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206200 kb
Host smart-4217aba3-e28c-4f1a-8e25-e0fbbeacbaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20113
37503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2011337503
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.689325608
Short name T264
Test name
Test status
Simulation time 13334525653 ps
CPU time 33.19 seconds
Started Jul 07 05:25:57 PM PDT 24
Finished Jul 07 05:26:31 PM PDT 24
Peak memory 206084 kb
Host smart-8c8a3076-d569-4335-a564-5435a1bea7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68932
5608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.689325608
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.4014542238
Short name T1612
Test name
Test status
Simulation time 187092012 ps
CPU time 0.85 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206184 kb
Host smart-3cca2a1c-2b67-41d9-b15d-19e3a0dc8d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40145
42238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4014542238
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3381134911
Short name T1139
Test name
Test status
Simulation time 157831121 ps
CPU time 0.8 seconds
Started Jul 07 05:25:55 PM PDT 24
Finished Jul 07 05:25:56 PM PDT 24
Peak memory 206192 kb
Host smart-fb9d41a1-a769-423f-b769-bb70a20f0c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33811
34911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3381134911
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3419194627
Short name T2287
Test name
Test status
Simulation time 230991926 ps
CPU time 0.95 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206432 kb
Host smart-22293e31-9b80-4e73-b11d-47372f71e165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34191
94627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3419194627
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.4180908328
Short name T1060
Test name
Test status
Simulation time 158337526 ps
CPU time 0.77 seconds
Started Jul 07 05:26:14 PM PDT 24
Finished Jul 07 05:26:15 PM PDT 24
Peak memory 206116 kb
Host smart-f861889f-a45b-44af-8773-e45030068033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
08328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.4180908328
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3128963454
Short name T821
Test name
Test status
Simulation time 144770283 ps
CPU time 0.76 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206180 kb
Host smart-41962e58-57fb-49e8-9931-6c2edf7258f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31289
63454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3128963454
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1493467344
Short name T1712
Test name
Test status
Simulation time 161792644 ps
CPU time 0.82 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206208 kb
Host smart-2c4ed42b-992e-4c3a-8762-427abf5d30b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934
67344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1493467344
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2203935996
Short name T1799
Test name
Test status
Simulation time 157251938 ps
CPU time 0.83 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206428 kb
Host smart-474b8235-3fd9-4aa5-8da1-f9bf23ec887f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22039
35996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2203935996
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3634037926
Short name T1191
Test name
Test status
Simulation time 217423460 ps
CPU time 0.94 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206204 kb
Host smart-a5f8919c-db57-4be6-9c92-064830bccffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36340
37926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3634037926
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1622571623
Short name T1732
Test name
Test status
Simulation time 4474590637 ps
CPU time 29.55 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 206192 kb
Host smart-54470a86-e4f8-4951-acd7-cabea3743f80
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1622571623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1622571623
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.585205610
Short name T2182
Test name
Test status
Simulation time 177967740 ps
CPU time 0.86 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206232 kb
Host smart-3839777a-c9b7-4951-8ea3-35424529ee3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58520
5610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.585205610
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3756694315
Short name T237
Test name
Test status
Simulation time 233152896 ps
CPU time 0.94 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206200 kb
Host smart-9d069d5c-b6d9-47c8-a3c2-31d4406a4272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37566
94315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3756694315
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1962545077
Short name T2197
Test name
Test status
Simulation time 1083836697 ps
CPU time 2.38 seconds
Started Jul 07 05:26:05 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206432 kb
Host smart-d4f2f1e2-99b2-41ad-9481-58064d89add2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
45077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1962545077
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2194500679
Short name T1504
Test name
Test status
Simulation time 3277101784 ps
CPU time 21.84 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206412 kb
Host smart-0603fd6c-f9d4-4b30-b4a3-cf94912a358d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21945
00679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2194500679
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.631901145
Short name T628
Test name
Test status
Simulation time 84748534 ps
CPU time 0.72 seconds
Started Jul 07 05:26:05 PM PDT 24
Finished Jul 07 05:26:08 PM PDT 24
Peak memory 206152 kb
Host smart-40e4d9e2-e7c4-4220-b266-5055a91a9388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=631901145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.631901145
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3351096098
Short name T2109
Test name
Test status
Simulation time 4060356963 ps
CPU time 4.45 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206472 kb
Host smart-4422039c-6093-41ca-8445-1ec1358748cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3351096098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3351096098
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.338896923
Short name T1459
Test name
Test status
Simulation time 13357286819 ps
CPU time 13.44 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206432 kb
Host smart-167bf915-6cec-4dc9-8428-171712b99ce1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=338896923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.338896923
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1854388047
Short name T1987
Test name
Test status
Simulation time 23398538709 ps
CPU time 26.86 seconds
Started Jul 07 05:26:05 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 205988 kb
Host smart-14bb0871-8a80-4f6a-919c-2b7996458b73
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1854388047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1854388047
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2275053613
Short name T2556
Test name
Test status
Simulation time 156766373 ps
CPU time 0.84 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206184 kb
Host smart-d0a4f2a6-da20-428c-95c1-77399cd6b5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22750
53613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2275053613
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.4168797486
Short name T1551
Test name
Test status
Simulation time 195180491 ps
CPU time 0.82 seconds
Started Jul 07 05:25:58 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 206120 kb
Host smart-44ac4bc8-484b-41a8-9994-d0f3af35b1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
97486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.4168797486
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.177284231
Short name T585
Test name
Test status
Simulation time 456176944 ps
CPU time 1.57 seconds
Started Jul 07 05:26:00 PM PDT 24
Finished Jul 07 05:26:02 PM PDT 24
Peak memory 206200 kb
Host smart-a844f819-0b83-44a5-a14e-8830c77dd106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728
4231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.177284231
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3911252723
Short name T1497
Test name
Test status
Simulation time 890565230 ps
CPU time 2.04 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206640 kb
Host smart-c3578b60-0e17-48a1-995f-2aa98e77ac16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39112
52723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3911252723
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3774360468
Short name T197
Test name
Test status
Simulation time 9993687844 ps
CPU time 20.02 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:26 PM PDT 24
Peak memory 206536 kb
Host smart-ec031a0f-c238-4301-aebc-6171141506a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37743
60468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3774360468
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3162682320
Short name T1009
Test name
Test status
Simulation time 389640096 ps
CPU time 1.29 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206188 kb
Host smart-39ec55a7-06c1-441a-802d-be59f9d856ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626
82320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3162682320
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.241380384
Short name T1250
Test name
Test status
Simulation time 141515176 ps
CPU time 0.76 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206136 kb
Host smart-a12121e3-5557-4fc9-9ddb-b0deaa68abac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
0384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.241380384
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.68729613
Short name T1432
Test name
Test status
Simulation time 59055667 ps
CPU time 0.68 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206212 kb
Host smart-6a3e87df-2a9b-4ef2-9160-36b8bbf6b6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68729
613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.68729613
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1126023356
Short name T1785
Test name
Test status
Simulation time 783452827 ps
CPU time 2.03 seconds
Started Jul 07 05:26:06 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206372 kb
Host smart-15ec9363-8910-4b07-b978-80d9290096e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11260
23356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1126023356
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1647432457
Short name T1040
Test name
Test status
Simulation time 189360306 ps
CPU time 1.95 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206376 kb
Host smart-0169c4da-14b2-49b8-b7eb-9cf9a0ec829a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474
32457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1647432457
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.258545452
Short name T1007
Test name
Test status
Simulation time 236823975 ps
CPU time 0.85 seconds
Started Jul 07 05:25:58 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 206176 kb
Host smart-795c1563-0bf3-4784-b991-88d56364dc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
5452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.258545452
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3481445631
Short name T401
Test name
Test status
Simulation time 145555162 ps
CPU time 0.82 seconds
Started Jul 07 05:26:07 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206180 kb
Host smart-6e06de50-d6c6-4237-b7e5-8b804679b796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
45631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3481445631
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2796944683
Short name T2649
Test name
Test status
Simulation time 193548379 ps
CPU time 0.86 seconds
Started Jul 07 05:25:57 PM PDT 24
Finished Jul 07 05:25:59 PM PDT 24
Peak memory 206168 kb
Host smart-bbcb643f-4765-47a4-94f9-17a96c6ebdee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
44683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2796944683
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.172466224
Short name T813
Test name
Test status
Simulation time 195288191 ps
CPU time 0.85 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206040 kb
Host smart-6b4bc3e6-1110-411e-8764-d550ec1204c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17246
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.172466224
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2293245630
Short name T1486
Test name
Test status
Simulation time 23326178557 ps
CPU time 23.69 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 206180 kb
Host smart-2459d493-30fc-4e73-b7f6-e45607e8c89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22932
45630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2293245630
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.899707870
Short name T673
Test name
Test status
Simulation time 3321886579 ps
CPU time 4.17 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206252 kb
Host smart-bb2764b2-3312-4450-b6a3-fe438c6e8029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89970
7870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.899707870
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.487972497
Short name T1254
Test name
Test status
Simulation time 9071013616 ps
CPU time 247.73 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:30:11 PM PDT 24
Peak memory 206220 kb
Host smart-5f905ca4-1918-49f5-95d4-1e93b0947915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48797
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.487972497
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2019608280
Short name T2047
Test name
Test status
Simulation time 4665214923 ps
CPU time 35.59 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 206480 kb
Host smart-1471df62-bde3-4930-a610-78078a7ca2f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2019608280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2019608280
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.969027528
Short name T1690
Test name
Test status
Simulation time 244551259 ps
CPU time 0.87 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206088 kb
Host smart-8a99c308-89ee-4498-916a-1307e35df974
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=969027528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.969027528
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2255176935
Short name T2235
Test name
Test status
Simulation time 188301961 ps
CPU time 0.85 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206188 kb
Host smart-7f683396-5f23-4f27-934f-75f63b18c6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22551
76935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2255176935
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2578855560
Short name T2105
Test name
Test status
Simulation time 6377482955 ps
CPU time 45 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 206448 kb
Host smart-f881cfa2-44f6-42df-987d-95d517c9c3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
55560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2578855560
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3513579028
Short name T1861
Test name
Test status
Simulation time 7605422964 ps
CPU time 53.12 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 206476 kb
Host smart-bba6cfd1-b818-4cdc-b504-320cebbfb299
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3513579028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3513579028
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3521407194
Short name T2637
Test name
Test status
Simulation time 162017591 ps
CPU time 0.84 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206172 kb
Host smart-ece8de45-c9a8-4f83-ac98-4d098d0fbf3a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3521407194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3521407194
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3042592556
Short name T569
Test name
Test status
Simulation time 185450580 ps
CPU time 0.85 seconds
Started Jul 07 05:26:01 PM PDT 24
Finished Jul 07 05:26:03 PM PDT 24
Peak memory 206188 kb
Host smart-14933ad3-c81a-49ff-8d7c-afa22a4a7546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
92556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3042592556
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3465532241
Short name T147
Test name
Test status
Simulation time 182862611 ps
CPU time 0.86 seconds
Started Jul 07 05:26:05 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206108 kb
Host smart-475d6681-dede-475a-9bbf-429830f3b113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
32241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3465532241
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3289856894
Short name T477
Test name
Test status
Simulation time 158244687 ps
CPU time 0.77 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206196 kb
Host smart-26e55501-7654-4f9b-b25a-ee38ead300e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
56894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3289856894
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.968353281
Short name T881
Test name
Test status
Simulation time 174161543 ps
CPU time 0.81 seconds
Started Jul 07 05:26:11 PM PDT 24
Finished Jul 07 05:26:13 PM PDT 24
Peak memory 206132 kb
Host smart-31e8311d-4210-440e-b22e-3fa9b2e8c15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96835
3281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.968353281
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1648469957
Short name T1165
Test name
Test status
Simulation time 174243664 ps
CPU time 0.85 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206188 kb
Host smart-876fd5b6-dd24-4113-be98-e3433b5c0ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16484
69957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1648469957
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2209709590
Short name T1953
Test name
Test status
Simulation time 157363574 ps
CPU time 0.81 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:04 PM PDT 24
Peak memory 206156 kb
Host smart-d68faf52-0a7c-4bd9-97bd-f10d8c395eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22097
09590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2209709590
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3457648867
Short name T550
Test name
Test status
Simulation time 261778285 ps
CPU time 0.98 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206124 kb
Host smart-31ed5599-bba2-4db4-a6b4-5b9b299a1170
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3457648867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3457648867
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.667938805
Short name T1317
Test name
Test status
Simulation time 158469694 ps
CPU time 0.83 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:06 PM PDT 24
Peak memory 206192 kb
Host smart-1b198afd-1278-4c28-880e-110fbd478101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66793
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.667938805
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.66632714
Short name T33
Test name
Test status
Simulation time 29465175 ps
CPU time 0.68 seconds
Started Jul 07 05:26:12 PM PDT 24
Finished Jul 07 05:26:13 PM PDT 24
Peak memory 206188 kb
Host smart-851c1ba9-1440-4cd6-82e0-3676a33aa1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66632
714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.66632714
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2627367908
Short name T2116
Test name
Test status
Simulation time 20201604201 ps
CPU time 44.21 seconds
Started Jul 07 05:26:03 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 206528 kb
Host smart-d2925ebf-6402-4e75-babc-923c1ec0ccb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26273
67908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2627367908
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.676127329
Short name T1562
Test name
Test status
Simulation time 171057169 ps
CPU time 0.84 seconds
Started Jul 07 05:26:02 PM PDT 24
Finished Jul 07 05:26:05 PM PDT 24
Peak memory 206168 kb
Host smart-8f801b0e-c061-48ba-a56c-07a7665e2ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67612
7329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.676127329
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.963832319
Short name T2009
Test name
Test status
Simulation time 234565390 ps
CPU time 0.92 seconds
Started Jul 07 05:25:59 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206056 kb
Host smart-fbb7e71c-5938-4b64-849f-85daa318c838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96383
2319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.963832319
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1789056669
Short name T698
Test name
Test status
Simulation time 303554115 ps
CPU time 0.99 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:11 PM PDT 24
Peak memory 206124 kb
Host smart-3cfffabd-929e-48ef-9c11-15ae89159b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17890
56669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1789056669
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1382765753
Short name T1467
Test name
Test status
Simulation time 185463960 ps
CPU time 0.81 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:15 PM PDT 24
Peak memory 206188 kb
Host smart-67886515-61f1-4b76-a3bf-627929f4314d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13827
65753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1382765753
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3960910955
Short name T985
Test name
Test status
Simulation time 135142389 ps
CPU time 0.78 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206108 kb
Host smart-bfc3defe-169b-47cf-a5e4-7d7b77685e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39609
10955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3960910955
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1576532098
Short name T2230
Test name
Test status
Simulation time 217205319 ps
CPU time 0.81 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:16 PM PDT 24
Peak memory 206112 kb
Host smart-09ebf6c8-f46d-4300-9411-cfaab84d0bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15765
32098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1576532098
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2360030171
Short name T361
Test name
Test status
Simulation time 156639275 ps
CPU time 0.76 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 205924 kb
Host smart-145505ef-79ac-4967-908f-480ed8ff5939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23600
30171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2360030171
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.239875751
Short name T2330
Test name
Test status
Simulation time 202206600 ps
CPU time 0.89 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:11 PM PDT 24
Peak memory 206208 kb
Host smart-211d0b14-7ed8-4a9e-99b0-b4cbd4b10a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23987
5751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.239875751
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3932463115
Short name T1640
Test name
Test status
Simulation time 3633050542 ps
CPU time 34.16 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 206484 kb
Host smart-03c3715c-3c71-4aaa-8860-4664eeafd8ad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3932463115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3932463115
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1620392450
Short name T1894
Test name
Test status
Simulation time 208065915 ps
CPU time 0.83 seconds
Started Jul 07 05:26:10 PM PDT 24
Finished Jul 07 05:26:11 PM PDT 24
Peak memory 206196 kb
Host smart-4096c803-c183-490e-882b-4729817b8ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16203
92450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1620392450
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1886601421
Short name T1967
Test name
Test status
Simulation time 189643289 ps
CPU time 0.77 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 206184 kb
Host smart-9ffcf7d7-cea2-48e3-84ea-d17168d1d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18866
01421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1886601421
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3452569316
Short name T2300
Test name
Test status
Simulation time 770276964 ps
CPU time 1.92 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206288 kb
Host smart-afc65a5c-f3b3-440f-b8fb-8bfb23dfe639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
69316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3452569316
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3098969379
Short name T1352
Test name
Test status
Simulation time 3484730131 ps
CPU time 32.04 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 206496 kb
Host smart-37a2d179-1b60-406b-a9d7-8f6df9c71425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30989
69379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3098969379
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2441477338
Short name T1312
Test name
Test status
Simulation time 37748934 ps
CPU time 0.67 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:26:19 PM PDT 24
Peak memory 206264 kb
Host smart-fb3ebd68-5add-4551-98c1-9f86a897d5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2441477338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2441477338
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.4052493847
Short name T2186
Test name
Test status
Simulation time 3586802840 ps
CPU time 4.32 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206476 kb
Host smart-0ecd92e6-dac7-4274-9aa2-95aeefa17727
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4052493847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.4052493847
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2458151489
Short name T1198
Test name
Test status
Simulation time 13362684730 ps
CPU time 14.84 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:33 PM PDT 24
Peak memory 206232 kb
Host smart-df107d09-2ffc-49f0-a322-70906b46344a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2458151489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2458151489
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3741296502
Short name T1402
Test name
Test status
Simulation time 23413738978 ps
CPU time 24.6 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 206332 kb
Host smart-288e51d2-85e5-4430-a5b3-5f70eef8a822
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3741296502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3741296502
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1568951888
Short name T545
Test name
Test status
Simulation time 202564879 ps
CPU time 0.84 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 206100 kb
Host smart-14b90f3e-a113-4472-981b-a3ebcece8197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15689
51888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1568951888
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4184407912
Short name T2646
Test name
Test status
Simulation time 159979839 ps
CPU time 0.85 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:17 PM PDT 24
Peak memory 206116 kb
Host smart-cc743efe-99b3-45e6-a11a-648384aff0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41844
07912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4184407912
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.232072275
Short name T525
Test name
Test status
Simulation time 318281959 ps
CPU time 1.21 seconds
Started Jul 07 05:26:20 PM PDT 24
Finished Jul 07 05:26:22 PM PDT 24
Peak memory 206196 kb
Host smart-f1411abd-f06e-4c7c-ac6b-fe7b8d5d15bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23207
2275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.232072275
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.400299682
Short name T2594
Test name
Test status
Simulation time 1205921595 ps
CPU time 3.03 seconds
Started Jul 07 05:26:06 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206448 kb
Host smart-1146054a-1e98-49f7-9eb1-5436e5e68df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
9682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.400299682
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.698741617
Short name T907
Test name
Test status
Simulation time 17770845775 ps
CPU time 32.02 seconds
Started Jul 07 05:26:12 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 206524 kb
Host smart-57fc7ad9-ee77-4e9d-b87b-b865f0a52d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69874
1617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.698741617
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2023402626
Short name T1544
Test name
Test status
Simulation time 507358275 ps
CPU time 1.5 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206128 kb
Host smart-5093984d-8527-46c3-b625-039d2c5c805e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20234
02626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2023402626
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3571738480
Short name T741
Test name
Test status
Simulation time 147260413 ps
CPU time 0.74 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 206188 kb
Host smart-69599d26-892d-4b09-8aad-fa0f80a9651b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
38480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3571738480
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1144135166
Short name T556
Test name
Test status
Simulation time 35276700 ps
CPU time 0.73 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 206144 kb
Host smart-644f7074-b012-445d-87a2-f3641596720c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11441
35166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1144135166
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3892941502
Short name T1225
Test name
Test status
Simulation time 813798193 ps
CPU time 2.15 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206352 kb
Host smart-0736966e-3714-4aee-b795-3547d685920a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38929
41502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3892941502
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1388173337
Short name T1534
Test name
Test status
Simulation time 178723561 ps
CPU time 1.94 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:12 PM PDT 24
Peak memory 206368 kb
Host smart-05ecf22d-8971-4bc2-8e77-bd9db6da17b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13881
73337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1388173337
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3215798409
Short name T1851
Test name
Test status
Simulation time 243968416 ps
CPU time 0.96 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:15 PM PDT 24
Peak memory 206184 kb
Host smart-78676388-b0c7-4e17-bd3c-0ece43bd3879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32157
98409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3215798409
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.675999671
Short name T1603
Test name
Test status
Simulation time 134437686 ps
CPU time 0.79 seconds
Started Jul 07 05:26:14 PM PDT 24
Finished Jul 07 05:26:15 PM PDT 24
Peak memory 206140 kb
Host smart-30b36984-2b40-4b0c-8a3f-761153502552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67599
9671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.675999671
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2128997124
Short name T1539
Test name
Test status
Simulation time 184612506 ps
CPU time 0.89 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:19 PM PDT 24
Peak memory 206184 kb
Host smart-cd07da18-c63c-44a2-934c-a8385210433a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21289
97124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2128997124
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3817242366
Short name T2280
Test name
Test status
Simulation time 228574375 ps
CPU time 0.86 seconds
Started Jul 07 05:26:04 PM PDT 24
Finished Jul 07 05:26:07 PM PDT 24
Peak memory 206200 kb
Host smart-7419101d-3ad3-4cfb-b01d-8589cccd6a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38172
42366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3817242366
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2422164430
Short name T2363
Test name
Test status
Simulation time 23355270881 ps
CPU time 25.3 seconds
Started Jul 07 05:26:05 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 206196 kb
Host smart-30e96e15-71dc-453e-90b2-6b9ebdbba2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24221
64430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2422164430
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1500918743
Short name T412
Test name
Test status
Simulation time 3376250448 ps
CPU time 3.93 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:17 PM PDT 24
Peak memory 206244 kb
Host smart-21c91cde-f5ad-4789-ba49-2068a0734252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009
18743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1500918743
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3169375015
Short name T95
Test name
Test status
Simulation time 10556583819 ps
CPU time 98.2 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:27:59 PM PDT 24
Peak memory 206468 kb
Host smart-2d1465cb-ca5d-4aba-991c-6541f6c09fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
75015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3169375015
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.599717996
Short name T1910
Test name
Test status
Simulation time 3712866827 ps
CPU time 27.73 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 206492 kb
Host smart-ae726dfc-9176-439c-adeb-80afe7aa69e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=599717996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.599717996
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.529562852
Short name T2464
Test name
Test status
Simulation time 248105655 ps
CPU time 0.97 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206096 kb
Host smart-e4cf06e9-8c9a-4249-83ec-1a7724e025ee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=529562852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.529562852
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3603176107
Short name T2434
Test name
Test status
Simulation time 245908077 ps
CPU time 0.94 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:17 PM PDT 24
Peak memory 206204 kb
Host smart-fa1bc367-1a41-46a3-a70f-1efbfb50b66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36031
76107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3603176107
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2966252442
Short name T1196
Test name
Test status
Simulation time 4907526988 ps
CPU time 46.2 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:27:00 PM PDT 24
Peak memory 206428 kb
Host smart-3ec45e67-3bed-4b08-850a-97f76905eb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
52442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2966252442
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.1829380290
Short name T1924
Test name
Test status
Simulation time 5175409455 ps
CPU time 47.99 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:27:05 PM PDT 24
Peak memory 206488 kb
Host smart-ac1d1e06-d1d6-4dc8-8b0a-b732888d472b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1829380290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.1829380290
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.3565401308
Short name T1842
Test name
Test status
Simulation time 165787455 ps
CPU time 0.83 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:17 PM PDT 24
Peak memory 206144 kb
Host smart-f1d91361-f247-4b1c-aa04-df013022c154
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3565401308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.3565401308
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2679557043
Short name T1742
Test name
Test status
Simulation time 149187074 ps
CPU time 0.81 seconds
Started Jul 07 05:26:14 PM PDT 24
Finished Jul 07 05:26:15 PM PDT 24
Peak memory 206200 kb
Host smart-9227fa01-5521-4ff2-ac18-28270499a67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26795
57043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2679557043
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2870733225
Short name T127
Test name
Test status
Simulation time 226160970 ps
CPU time 0.88 seconds
Started Jul 07 05:26:13 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 206184 kb
Host smart-1a554582-d229-4add-b713-66e03a9ebe1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28707
33225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2870733225
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1964983169
Short name T633
Test name
Test status
Simulation time 183354648 ps
CPU time 0.88 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206156 kb
Host smart-08bcb7e6-9c06-4fa3-81bf-205c253f3c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
83169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1964983169
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2716795651
Short name T847
Test name
Test status
Simulation time 181849087 ps
CPU time 0.84 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:16 PM PDT 24
Peak memory 206192 kb
Host smart-c7b71e0f-fa34-4880-8ffd-2d640581233f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
95651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2716795651
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1035773331
Short name T1668
Test name
Test status
Simulation time 180366977 ps
CPU time 0.85 seconds
Started Jul 07 05:26:06 PM PDT 24
Finished Jul 07 05:26:08 PM PDT 24
Peak memory 206184 kb
Host smart-10f524d5-c81e-47fc-aa13-ed1950987977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10357
73331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1035773331
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2761999329
Short name T923
Test name
Test status
Simulation time 151998730 ps
CPU time 0.79 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:22 PM PDT 24
Peak memory 206088 kb
Host smart-53756610-06c5-401f-b344-a77da5decbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619
99329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2761999329
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3580038555
Short name T995
Test name
Test status
Simulation time 240862737 ps
CPU time 0.92 seconds
Started Jul 07 05:26:09 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 206176 kb
Host smart-4c7e32cc-9705-4e9f-aaca-33241391cfae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3580038555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3580038555
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1584577237
Short name T546
Test name
Test status
Simulation time 146045108 ps
CPU time 0.74 seconds
Started Jul 07 05:26:08 PM PDT 24
Finished Jul 07 05:26:09 PM PDT 24
Peak memory 206104 kb
Host smart-48c9d002-f91b-447a-b59e-ea3b831ad1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
77237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1584577237
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2999022500
Short name T1407
Test name
Test status
Simulation time 70687585 ps
CPU time 0.72 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206148 kb
Host smart-b7461d34-b9d3-4d37-a2dd-6174d5f9af63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
22500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2999022500
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.4052666655
Short name T2436
Test name
Test status
Simulation time 7819966802 ps
CPU time 20.37 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 206500 kb
Host smart-7a21ab3b-78f5-4394-bed3-5122b8ff0e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40526
66655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.4052666655
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3750337546
Short name T971
Test name
Test status
Simulation time 187919744 ps
CPU time 0.85 seconds
Started Jul 07 05:26:14 PM PDT 24
Finished Jul 07 05:26:16 PM PDT 24
Peak memory 206184 kb
Host smart-9abfc846-bdb2-46ea-a823-6337df2500cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37503
37546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3750337546
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2202824445
Short name T665
Test name
Test status
Simulation time 219887528 ps
CPU time 0.92 seconds
Started Jul 07 05:26:31 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 206196 kb
Host smart-456ce586-408b-4e4c-a755-549a4f8a5dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
24445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2202824445
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2203794227
Short name T2036
Test name
Test status
Simulation time 232122093 ps
CPU time 0.89 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206036 kb
Host smart-ee55a994-c9d1-4081-bd47-07e206635c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037
94227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2203794227
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.261664931
Short name T924
Test name
Test status
Simulation time 200016539 ps
CPU time 0.86 seconds
Started Jul 07 05:26:22 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206192 kb
Host smart-6563c2ea-b58b-4f1e-8260-8e632a9cc568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26166
4931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.261664931
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.4051563940
Short name T1090
Test name
Test status
Simulation time 173716375 ps
CPU time 0.83 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206204 kb
Host smart-f26ef823-6d9e-4ce2-8222-904cf690542a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40515
63940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.4051563940
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1620820994
Short name T1889
Test name
Test status
Simulation time 163921256 ps
CPU time 0.8 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:17 PM PDT 24
Peak memory 206188 kb
Host smart-63d2cd6d-b28f-482a-8235-0d676dfc44e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208
20994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1620820994
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3525169549
Short name T2088
Test name
Test status
Simulation time 149640425 ps
CPU time 0.78 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206180 kb
Host smart-52083dee-2a2c-4354-b5f9-f5dbe3c18deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35251
69549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3525169549
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3011087207
Short name T783
Test name
Test status
Simulation time 220255749 ps
CPU time 0.94 seconds
Started Jul 07 05:26:27 PM PDT 24
Finished Jul 07 05:26:28 PM PDT 24
Peak memory 205776 kb
Host smart-7e24c8f3-d5fa-4b29-9581-dc8da3097ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
87207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3011087207
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1293780836
Short name T1276
Test name
Test status
Simulation time 5196245504 ps
CPU time 47.62 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:27:07 PM PDT 24
Peak memory 206184 kb
Host smart-5b37b0fc-7926-4754-9bf3-b2bec46d1576
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1293780836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1293780836
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1017157718
Short name T676
Test name
Test status
Simulation time 165932041 ps
CPU time 0.86 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 206432 kb
Host smart-fa229feb-f433-4e40-b7e9-bf19ccd9366e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10171
57718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1017157718
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3405747184
Short name T1386
Test name
Test status
Simulation time 202076925 ps
CPU time 0.81 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:19 PM PDT 24
Peak memory 206108 kb
Host smart-b2a7a58f-525d-4c83-ae16-e3b8f8af0320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
47184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3405747184
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3860323830
Short name T2643
Test name
Test status
Simulation time 1114733491 ps
CPU time 2.41 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:37 PM PDT 24
Peak memory 206364 kb
Host smart-7b1bae36-574f-4a16-8242-03de989b6eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
23830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3860323830
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3055276606
Short name T668
Test name
Test status
Simulation time 4207630962 ps
CPU time 31.77 seconds
Started Jul 07 05:26:29 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 206440 kb
Host smart-fc655871-d932-4079-aea8-25aa1b848346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30552
76606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3055276606
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1545782504
Short name T1503
Test name
Test status
Simulation time 51046529 ps
CPU time 0.73 seconds
Started Jul 07 05:26:26 PM PDT 24
Finished Jul 07 05:26:27 PM PDT 24
Peak memory 206232 kb
Host smart-416ba1d9-9424-4504-8995-7f321f31ffb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1545782504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1545782504
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.55836055
Short name T1912
Test name
Test status
Simulation time 3945777927 ps
CPU time 4.7 seconds
Started Jul 07 05:26:23 PM PDT 24
Finished Jul 07 05:26:28 PM PDT 24
Peak memory 206396 kb
Host smart-41723b54-e190-4e6b-8cd5-59f0c1dbbc36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=55836055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.55836055
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.4151704237
Short name T1733
Test name
Test status
Simulation time 13375841500 ps
CPU time 13.04 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:33 PM PDT 24
Peak memory 206160 kb
Host smart-94088473-4b01-4fbf-92c2-80fb0fb51c22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4151704237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.4151704237
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3634113721
Short name T1178
Test name
Test status
Simulation time 23374485052 ps
CPU time 22.58 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 206656 kb
Host smart-31045b9d-9b9f-4c20-977b-3bed1ee3bbd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3634113721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3634113721
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1347558223
Short name T774
Test name
Test status
Simulation time 169200568 ps
CPU time 0.84 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206188 kb
Host smart-791e5f7d-235c-4b04-ad35-47d2a2343562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13475
58223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1347558223
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1241731930
Short name T1805
Test name
Test status
Simulation time 140879760 ps
CPU time 0.78 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206212 kb
Host smart-24b50ba6-d34c-4e47-8d25-95b2f7248a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
31930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1241731930
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1201803080
Short name T740
Test name
Test status
Simulation time 386609845 ps
CPU time 1.36 seconds
Started Jul 07 05:26:29 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 206184 kb
Host smart-17ff2ca0-9536-44f5-93cd-f166d5251d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12018
03080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1201803080
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.7979314
Short name T2101
Test name
Test status
Simulation time 1360190382 ps
CPU time 2.78 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206420 kb
Host smart-1a65b7d7-b5c5-4c57-b202-92c0bdf0751a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79793
14 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.7979314
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1549007819
Short name T2706
Test name
Test status
Simulation time 16823140606 ps
CPU time 32.5 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:52 PM PDT 24
Peak memory 206348 kb
Host smart-d490973a-ee87-4eb4-b365-6ba35a726cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490
07819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1549007819
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1849046117
Short name T2687
Test name
Test status
Simulation time 437503361 ps
CPU time 1.25 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 206192 kb
Host smart-dd6c5adb-c77d-49ed-99d1-d60e11390d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18490
46117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1849046117
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1903104689
Short name T725
Test name
Test status
Simulation time 171830371 ps
CPU time 0.78 seconds
Started Jul 07 05:26:12 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 206188 kb
Host smart-111eadab-586d-481e-875f-ead962da6a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19031
04689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1903104689
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3059100588
Short name T1236
Test name
Test status
Simulation time 33187480 ps
CPU time 0.66 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206120 kb
Host smart-fdd11677-20d8-42ce-8471-0e9a1ea460f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30591
00588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3059100588
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1634894844
Short name T1789
Test name
Test status
Simulation time 837763694 ps
CPU time 1.98 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 206316 kb
Host smart-c0dc6dcb-c81c-4898-b1fc-b92bb9306e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348
94844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1634894844
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3259564372
Short name T2261
Test name
Test status
Simulation time 268344819 ps
CPU time 1.47 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:26 PM PDT 24
Peak memory 206376 kb
Host smart-67e77a3a-7e0f-4c0f-a72b-199d2a821119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32595
64372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3259564372
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.134034377
Short name T751
Test name
Test status
Simulation time 186226983 ps
CPU time 0.89 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 206032 kb
Host smart-98c4e56e-9ef4-4757-bb91-195b3d7808fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13403
4377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.134034377
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2080247044
Short name T2618
Test name
Test status
Simulation time 162015514 ps
CPU time 0.75 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:19 PM PDT 24
Peak memory 206184 kb
Host smart-4d4be385-7c62-4c65-9877-6d40f1b9d329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20802
47044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2080247044
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3181958734
Short name T766
Test name
Test status
Simulation time 244815158 ps
CPU time 0.93 seconds
Started Jul 07 05:26:27 PM PDT 24
Finished Jul 07 05:26:28 PM PDT 24
Peak memory 205848 kb
Host smart-bf08584e-e383-41fd-8782-2a2350281823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819
58734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3181958734
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1008397044
Short name T1886
Test name
Test status
Simulation time 10230619852 ps
CPU time 101.9 seconds
Started Jul 07 05:26:22 PM PDT 24
Finished Jul 07 05:28:04 PM PDT 24
Peak memory 206500 kb
Host smart-34e27efb-1200-4e0c-9402-5060afba9ac2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1008397044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1008397044
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.161001158
Short name T1175
Test name
Test status
Simulation time 257491910 ps
CPU time 0.98 seconds
Started Jul 07 05:26:22 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206112 kb
Host smart-aa97ffc2-cac3-4ba4-836c-b1667b4f4370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16100
1158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.161001158
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.4127696022
Short name T349
Test name
Test status
Simulation time 23313492546 ps
CPU time 24.27 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 206248 kb
Host smart-de2e5f30-6193-4c33-899d-45b016d7d4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41276
96022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.4127696022
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1289695708
Short name T1706
Test name
Test status
Simulation time 3353693604 ps
CPU time 3.63 seconds
Started Jul 07 05:26:20 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206256 kb
Host smart-ec965db5-6ffe-405c-adef-ed6746eaf992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12896
95708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1289695708
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.357981143
Short name T1336
Test name
Test status
Simulation time 14130734085 ps
CPU time 404.01 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:33:01 PM PDT 24
Peak memory 206388 kb
Host smart-0d2bf31c-e474-4fcd-9398-6c9e07a58cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35798
1143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.357981143
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1979787254
Short name T359
Test name
Test status
Simulation time 4666102229 ps
CPU time 35.47 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 206392 kb
Host smart-d799988f-a220-44f5-9e26-8da5a9f2cf58
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1979787254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1979787254
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.522610285
Short name T453
Test name
Test status
Simulation time 239085264 ps
CPU time 0.94 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:26:19 PM PDT 24
Peak memory 206044 kb
Host smart-45ac8d9c-681d-4306-bd63-a6e18cafc460
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=522610285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.522610285
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3380058612
Short name T1206
Test name
Test status
Simulation time 234448995 ps
CPU time 0.92 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 206200 kb
Host smart-d780c58d-2277-4ced-97df-8b6ca6ec7a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
58612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3380058612
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3933651724
Short name T2155
Test name
Test status
Simulation time 4628474020 ps
CPU time 128.93 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 206468 kb
Host smart-04a0578b-2e8e-4707-9b76-97f1c5c0a48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39336
51724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3933651724
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1353756182
Short name T1075
Test name
Test status
Simulation time 6848834482 ps
CPU time 50.61 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:27:12 PM PDT 24
Peak memory 206484 kb
Host smart-0ee5ea31-5ed3-4f31-8984-80c517a98c03
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1353756182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1353756182
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2545447096
Short name T2151
Test name
Test status
Simulation time 149702826 ps
CPU time 0.79 seconds
Started Jul 07 05:26:23 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206080 kb
Host smart-96d923c3-1577-4ee1-af70-386b31b3cbd7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2545447096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2545447096
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1257027673
Short name T1880
Test name
Test status
Simulation time 136025370 ps
CPU time 0.75 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206196 kb
Host smart-c2325d04-5de0-42fb-bf40-f36232a3fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12570
27673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1257027673
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.36523894
Short name T1492
Test name
Test status
Simulation time 200032916 ps
CPU time 0.84 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:26 PM PDT 24
Peak memory 206180 kb
Host smart-1a48e042-8c80-4825-b46e-89547961dc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36523
894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.36523894
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1982882969
Short name T1152
Test name
Test status
Simulation time 184261562 ps
CPU time 0.82 seconds
Started Jul 07 05:26:22 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206148 kb
Host smart-12c0d615-202e-451a-8988-81072566a51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
82969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1982882969
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1437002355
Short name T2448
Test name
Test status
Simulation time 196851872 ps
CPU time 0.81 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206196 kb
Host smart-ad503b67-7cc7-4947-b0b6-bb9bbcb5db5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14370
02355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1437002355
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3289619005
Short name T922
Test name
Test status
Simulation time 163720376 ps
CPU time 0.79 seconds
Started Jul 07 05:26:20 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206216 kb
Host smart-97dc5cec-614f-421f-afed-a23d1a663bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32896
19005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3289619005
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.4068782265
Short name T183
Test name
Test status
Simulation time 194959679 ps
CPU time 0.84 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 206112 kb
Host smart-0e4b1cce-0ba5-497f-b4ab-d80e8cc858d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
82265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.4068782265
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.994085586
Short name T2362
Test name
Test status
Simulation time 217927803 ps
CPU time 0.9 seconds
Started Jul 07 05:26:20 PM PDT 24
Finished Jul 07 05:26:22 PM PDT 24
Peak memory 206168 kb
Host smart-1e5af353-1f30-43fb-a6ed-027e770e339d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=994085586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.994085586
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.125127919
Short name T2619
Test name
Test status
Simulation time 185185630 ps
CPU time 0.82 seconds
Started Jul 07 05:26:18 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206200 kb
Host smart-e9632b32-65b8-4fe8-b3e5-b4566b2389fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
7919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.125127919
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2485505795
Short name T769
Test name
Test status
Simulation time 48319247 ps
CPU time 0.69 seconds
Started Jul 07 05:26:22 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206080 kb
Host smart-1111c05c-aabc-466f-a31e-932b882d33de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
05795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2485505795
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3471729001
Short name T88
Test name
Test status
Simulation time 6137900098 ps
CPU time 15.91 seconds
Started Jul 07 05:26:17 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 206408 kb
Host smart-da9778e5-cf87-42a8-af9f-10e8a3e2e9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
29001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3471729001
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3071256507
Short name T1866
Test name
Test status
Simulation time 175236565 ps
CPU time 0.85 seconds
Started Jul 07 05:26:16 PM PDT 24
Finished Jul 07 05:26:18 PM PDT 24
Peak memory 206212 kb
Host smart-32f06b1a-af41-4097-8fad-b75086caa3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712
56507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3071256507
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1508325168
Short name T164
Test name
Test status
Simulation time 205660004 ps
CPU time 0.84 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:20 PM PDT 24
Peak memory 206184 kb
Host smart-3130a7a7-7a16-42ea-bd08-170cc1f30c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15083
25168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1508325168
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1449419527
Short name T679
Test name
Test status
Simulation time 228347978 ps
CPU time 0.9 seconds
Started Jul 07 05:26:23 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206132 kb
Host smart-0a57335e-77bf-4583-8f11-dda3ee95da95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14494
19527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1449419527
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1129139386
Short name T2456
Test name
Test status
Simulation time 184077233 ps
CPU time 0.92 seconds
Started Jul 07 05:26:20 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206152 kb
Host smart-9b5cf97e-7085-410a-a1a3-2784aa455bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11291
39386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1129139386
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2751248204
Short name T1241
Test name
Test status
Simulation time 154298961 ps
CPU time 0.75 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206108 kb
Host smart-df6017ac-c215-47da-8801-13d549cc8a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27512
48204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2751248204
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2376448719
Short name T2642
Test name
Test status
Simulation time 149294581 ps
CPU time 0.78 seconds
Started Jul 07 05:26:23 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206104 kb
Host smart-482e8d72-2b9b-484d-a5d2-2c2bbbb21280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
48719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2376448719
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3227544463
Short name T1518
Test name
Test status
Simulation time 153915103 ps
CPU time 0.77 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:25 PM PDT 24
Peak memory 206184 kb
Host smart-68477db8-750e-4c9e-a2dc-76019f9f1808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32275
44463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3227544463
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2267015001
Short name T890
Test name
Test status
Simulation time 215021764 ps
CPU time 0.93 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:23 PM PDT 24
Peak memory 206192 kb
Host smart-eccdff39-4b7c-4a75-a48b-1e19f89f2765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
15001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2267015001
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3643659551
Short name T531
Test name
Test status
Simulation time 4255645109 ps
CPU time 40.46 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 206496 kb
Host smart-f3b073f2-3c77-43e5-9c2b-c6e70b3487a8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3643659551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3643659551
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3438336839
Short name T2228
Test name
Test status
Simulation time 169738769 ps
CPU time 0.83 seconds
Started Jul 07 05:26:23 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 206068 kb
Host smart-58d7e48f-4398-4872-8f4e-996a54cebd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34383
36839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3438336839
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3091692463
Short name T1142
Test name
Test status
Simulation time 150277056 ps
CPU time 0.79 seconds
Started Jul 07 05:26:15 PM PDT 24
Finished Jul 07 05:26:16 PM PDT 24
Peak memory 206156 kb
Host smart-69e1a049-4714-44a2-a70d-531861125396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30916
92463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3091692463
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3214738566
Short name T424
Test name
Test status
Simulation time 210344915 ps
CPU time 0.9 seconds
Started Jul 07 05:26:19 PM PDT 24
Finished Jul 07 05:26:21 PM PDT 24
Peak memory 206200 kb
Host smart-a0c18c5d-5b54-45de-91e2-b1353392597b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
38566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3214738566
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.4075848877
Short name T1078
Test name
Test status
Simulation time 6592477132 ps
CPU time 61.79 seconds
Started Jul 07 05:26:23 PM PDT 24
Finished Jul 07 05:27:26 PM PDT 24
Peak memory 206444 kb
Host smart-56daea80-44ec-43db-954a-1cb95dc35a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40758
48877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.4075848877
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1677857003
Short name T892
Test name
Test status
Simulation time 55676033 ps
CPU time 0.7 seconds
Started Jul 07 05:20:21 PM PDT 24
Finished Jul 07 05:20:23 PM PDT 24
Peak memory 206192 kb
Host smart-0ba93506-c4b1-4f27-8213-84b766211c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1677857003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1677857003
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.725448472
Short name T1950
Test name
Test status
Simulation time 3863595457 ps
CPU time 5.1 seconds
Started Jul 07 05:20:08 PM PDT 24
Finished Jul 07 05:20:13 PM PDT 24
Peak memory 206484 kb
Host smart-bec549c5-22b0-4583-9f2d-b48a24b27e9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=725448472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.725448472
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.129611722
Short name T2090
Test name
Test status
Simulation time 13380531172 ps
CPU time 13.49 seconds
Started Jul 07 05:20:03 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206492 kb
Host smart-db5687c0-dc75-4b03-8c47-0a3a93adce68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=129611722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.129611722
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1118319973
Short name T792
Test name
Test status
Simulation time 23342740640 ps
CPU time 21.82 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:20:29 PM PDT 24
Peak memory 206432 kb
Host smart-78b33ba1-4824-4a30-8d23-3747c6321fc5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1118319973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.1118319973
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2158884234
Short name T2168
Test name
Test status
Simulation time 160338938 ps
CPU time 0.81 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:20:07 PM PDT 24
Peak memory 206180 kb
Host smart-b0029c2d-4156-4e9a-934f-e5aa01c2bd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
84234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2158884234
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2629517649
Short name T2319
Test name
Test status
Simulation time 181526662 ps
CPU time 0.85 seconds
Started Jul 07 05:20:03 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 206068 kb
Host smart-be4f8414-8fa5-44e6-8ee0-6039fb026086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26295
17649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2629517649
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2783616355
Short name T787
Test name
Test status
Simulation time 305074988 ps
CPU time 1.08 seconds
Started Jul 07 05:20:14 PM PDT 24
Finished Jul 07 05:20:15 PM PDT 24
Peak memory 206152 kb
Host smart-abcf2501-2428-4101-89c1-b26b28baaf91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27836
16355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2783616355
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2270780308
Short name T781
Test name
Test status
Simulation time 389144239 ps
CPU time 1.06 seconds
Started Jul 07 05:20:08 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 206192 kb
Host smart-b20b7f59-fcea-4d3a-bcec-a53b5c0eb0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707
80308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2270780308
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3744482417
Short name T558
Test name
Test status
Simulation time 16265005167 ps
CPU time 30.52 seconds
Started Jul 07 05:20:06 PM PDT 24
Finished Jul 07 05:20:37 PM PDT 24
Peak memory 206444 kb
Host smart-24375c32-053f-4bd4-8197-bd70d7c3421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37444
82417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3744482417
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1176238857
Short name T1285
Test name
Test status
Simulation time 370002373 ps
CPU time 1.18 seconds
Started Jul 07 05:20:04 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 206196 kb
Host smart-f629cd27-76a7-4571-bd75-ad65ba2d7f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11762
38857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1176238857
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3424594416
Short name T37
Test name
Test status
Simulation time 162821004 ps
CPU time 0.78 seconds
Started Jul 07 05:20:08 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 206104 kb
Host smart-53038312-53e3-4dca-a1ba-802f63ec0898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34245
94416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3424594416
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2333473017
Short name T595
Test name
Test status
Simulation time 76526242 ps
CPU time 0.68 seconds
Started Jul 07 05:20:16 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206192 kb
Host smart-1aef9c11-7790-4ce7-8791-d0aa9284bca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23334
73017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2333473017
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2210345298
Short name T2060
Test name
Test status
Simulation time 1009492340 ps
CPU time 2.41 seconds
Started Jul 07 05:20:10 PM PDT 24
Finished Jul 07 05:20:12 PM PDT 24
Peak memory 206476 kb
Host smart-fafe3bfa-d4d9-458a-b5fc-f9708d1b27af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
45298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2210345298
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2513601672
Short name T795
Test name
Test status
Simulation time 199127836 ps
CPU time 2.23 seconds
Started Jul 07 05:20:07 PM PDT 24
Finished Jul 07 05:20:10 PM PDT 24
Peak memory 206360 kb
Host smart-561d6b1a-0ec9-4792-a3b3-f5c945e282da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25136
01672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2513601672
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.206356411
Short name T1056
Test name
Test status
Simulation time 194046852 ps
CPU time 0.8 seconds
Started Jul 07 05:20:16 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206192 kb
Host smart-1d7e6b9e-f412-4aab-bb9c-995f41c0d61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
6411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.206356411
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.381769564
Short name T1358
Test name
Test status
Simulation time 149501370 ps
CPU time 0.79 seconds
Started Jul 07 05:20:10 PM PDT 24
Finished Jul 07 05:20:11 PM PDT 24
Peak memory 206124 kb
Host smart-323c3c39-67b1-420a-8874-8a861a0fddfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
9564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.381769564
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3701337058
Short name T1748
Test name
Test status
Simulation time 241416867 ps
CPU time 0.86 seconds
Started Jul 07 05:20:09 PM PDT 24
Finished Jul 07 05:20:10 PM PDT 24
Peak memory 206208 kb
Host smart-d724358c-479a-423a-b7b9-9ce1344132ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
37058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3701337058
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3080101984
Short name T239
Test name
Test status
Simulation time 8827251743 ps
CPU time 259.78 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:24:39 PM PDT 24
Peak memory 206516 kb
Host smart-e996861a-5b15-4d92-975e-1635944144cd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3080101984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3080101984
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1869769260
Short name T519
Test name
Test status
Simulation time 186293326 ps
CPU time 0.84 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206184 kb
Host smart-866437d7-6146-4565-9486-02e9c9cca5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
69260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1869769260
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2783108859
Short name T1278
Test name
Test status
Simulation time 23286924049 ps
CPU time 25.6 seconds
Started Jul 07 05:20:14 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206176 kb
Host smart-0de3c3d9-1daf-4050-97fc-7e35cef73cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27831
08859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2783108859
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1073867092
Short name T1813
Test name
Test status
Simulation time 3311358865 ps
CPU time 3.95 seconds
Started Jul 07 05:20:08 PM PDT 24
Finished Jul 07 05:20:12 PM PDT 24
Peak memory 206496 kb
Host smart-e2ea7302-4a31-4f55-9907-d0025b144444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
67092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1073867092
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1357223515
Short name T1631
Test name
Test status
Simulation time 8015737894 ps
CPU time 57.23 seconds
Started Jul 07 05:20:14 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 206524 kb
Host smart-6a580617-9673-44ea-8c56-2a3994e7d689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
23515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1357223515
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1191086792
Short name T944
Test name
Test status
Simulation time 4625089603 ps
CPU time 35.06 seconds
Started Jul 07 05:20:17 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206372 kb
Host smart-9bbc8582-01e1-4c8d-9661-5d4fc55e90b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1191086792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1191086792
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2985839551
Short name T436
Test name
Test status
Simulation time 252614521 ps
CPU time 0.93 seconds
Started Jul 07 05:20:16 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206172 kb
Host smart-a914097e-60dd-4683-8f63-b1ae6633e1e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2985839551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2985839551
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1669960049
Short name T1711
Test name
Test status
Simulation time 187994096 ps
CPU time 0.91 seconds
Started Jul 07 05:20:16 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206164 kb
Host smart-bf1f9827-0a68-4060-9a71-6e993fd6dbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
60049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1669960049
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3367228093
Short name T810
Test name
Test status
Simulation time 4013291903 ps
CPU time 112.15 seconds
Started Jul 07 05:20:14 PM PDT 24
Finished Jul 07 05:22:06 PM PDT 24
Peak memory 206364 kb
Host smart-8ed922b0-4078-45d1-889e-bb3c85ed5285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33672
28093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3367228093
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.4176762760
Short name T2535
Test name
Test status
Simulation time 6456870415 ps
CPU time 61.31 seconds
Started Jul 07 05:20:14 PM PDT 24
Finished Jul 07 05:21:15 PM PDT 24
Peak memory 206436 kb
Host smart-11dca808-1dcf-4eeb-8d35-460d3dae457e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4176762760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.4176762760
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3560342862
Short name T806
Test name
Test status
Simulation time 220319016 ps
CPU time 0.87 seconds
Started Jul 07 05:20:15 PM PDT 24
Finished Jul 07 05:20:16 PM PDT 24
Peak memory 206164 kb
Host smart-e792c3d5-34a2-413e-977b-f48832bf9437
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3560342862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3560342862
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.4107771131
Short name T1583
Test name
Test status
Simulation time 203743054 ps
CPU time 0.8 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:20:19 PM PDT 24
Peak memory 206188 kb
Host smart-57fbec71-f643-4f22-9359-15d07d3592a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41077
71131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4107771131
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.436304143
Short name T1883
Test name
Test status
Simulation time 220207977 ps
CPU time 0.89 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206180 kb
Host smart-f7b38a0f-992b-4f2b-bad1-a352a8e3d0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43630
4143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.436304143
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3852651660
Short name T1259
Test name
Test status
Simulation time 208020828 ps
CPU time 0.86 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:20:19 PM PDT 24
Peak memory 206196 kb
Host smart-1ba7bcae-871d-47fc-8616-1a4de4d8009e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38526
51660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3852651660
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3415288757
Short name T2077
Test name
Test status
Simulation time 204982065 ps
CPU time 0.88 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206188 kb
Host smart-9d1bd416-7b52-446e-b7de-869dc457f8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152
88757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3415288757
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.957482048
Short name T2342
Test name
Test status
Simulation time 168915121 ps
CPU time 0.78 seconds
Started Jul 07 05:20:16 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206160 kb
Host smart-271c4809-f8e4-42cb-9399-e1debcf09aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95748
2048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.957482048
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.347130148
Short name T2323
Test name
Test status
Simulation time 155560091 ps
CPU time 0.81 seconds
Started Jul 07 05:20:21 PM PDT 24
Finished Jul 07 05:20:23 PM PDT 24
Peak memory 206188 kb
Host smart-45538afe-0306-433a-8b0f-f4d8639944c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.347130148
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1813639458
Short name T23
Test name
Test status
Simulation time 227141376 ps
CPU time 0.93 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206204 kb
Host smart-0b3900b6-ca27-48c6-9255-14d46a372668
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1813639458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1813639458
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2946760813
Short name T1396
Test name
Test status
Simulation time 153006301 ps
CPU time 0.76 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206116 kb
Host smart-d3b534fe-3006-406f-87cc-8aec94d1ad3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29467
60813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2946760813
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2499210005
Short name T1296
Test name
Test status
Simulation time 34405439 ps
CPU time 0.63 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206108 kb
Host smart-6e281605-c64c-4248-b2fe-5097698a37bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24992
10005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2499210005
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.25493141
Short name T279
Test name
Test status
Simulation time 7076794152 ps
CPU time 16.64 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:20:35 PM PDT 24
Peak memory 206476 kb
Host smart-833abbd3-0888-4bd6-a0b3-70bf815ea311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25493
141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.25493141
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2045218507
Short name T1812
Test name
Test status
Simulation time 199563752 ps
CPU time 0.85 seconds
Started Jul 07 05:20:21 PM PDT 24
Finished Jul 07 05:20:23 PM PDT 24
Peak memory 206136 kb
Host smart-2a905b44-753e-45d3-b578-88b68961604b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20452
18507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2045218507
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3092690979
Short name T1619
Test name
Test status
Simulation time 300564977 ps
CPU time 0.96 seconds
Started Jul 07 05:20:16 PM PDT 24
Finished Jul 07 05:20:17 PM PDT 24
Peak memory 206164 kb
Host smart-5ac4f8ce-c65f-4dbd-99eb-ae14154e50f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30926
90979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3092690979
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3167667567
Short name T2143
Test name
Test status
Simulation time 7068484258 ps
CPU time 172.36 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 206472 kb
Host smart-ed2650b4-cc57-41f6-a09c-88956a339bd2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3167667567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3167667567
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2864938380
Short name T185
Test name
Test status
Simulation time 5749147862 ps
CPU time 139.53 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:22:38 PM PDT 24
Peak memory 206508 kb
Host smart-4c9ec555-b403-4a11-94ee-ac60ab4d847b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2864938380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2864938380
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1444361340
Short name T1303
Test name
Test status
Simulation time 18925083045 ps
CPU time 107.75 seconds
Started Jul 07 05:20:17 PM PDT 24
Finished Jul 07 05:22:05 PM PDT 24
Peak memory 206504 kb
Host smart-9a9afe0d-ff17-472e-95cf-895729086023
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1444361340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1444361340
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3480579982
Short name T1005
Test name
Test status
Simulation time 206953781 ps
CPU time 0.81 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206188 kb
Host smart-0ced7a88-0139-4390-9757-c627f22ec1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34805
79982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3480579982
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.858725173
Short name T2576
Test name
Test status
Simulation time 165646403 ps
CPU time 0.85 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:20:20 PM PDT 24
Peak memory 206184 kb
Host smart-5f6fddea-02a5-4bf2-a34d-a6458a34517f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85872
5173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.858725173
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.206954626
Short name T1796
Test name
Test status
Simulation time 162238758 ps
CPU time 0.8 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206184 kb
Host smart-078376b2-4e89-45db-a069-cf336278abde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20695
4626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.206954626
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3325959315
Short name T718
Test name
Test status
Simulation time 151981434 ps
CPU time 0.83 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:20 PM PDT 24
Peak memory 206188 kb
Host smart-a5bb053f-361a-4367-89a0-9b741fd0b1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
59315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3325959315
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.845876878
Short name T824
Test name
Test status
Simulation time 150056070 ps
CPU time 0.74 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206440 kb
Host smart-f3359c36-f599-41ab-a096-692d2bb4d320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84587
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.845876878
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3582743586
Short name T962
Test name
Test status
Simulation time 224081034 ps
CPU time 0.91 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206116 kb
Host smart-53446e31-7726-4551-a8b7-8f64ce690b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827
43586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3582743586
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3421717691
Short name T602
Test name
Test status
Simulation time 4735107466 ps
CPU time 34.07 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:55 PM PDT 24
Peak memory 206416 kb
Host smart-25e21e50-5de2-44ff-a362-0d6a34f69501
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3421717691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3421717691
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.4094647111
Short name T2444
Test name
Test status
Simulation time 147555814 ps
CPU time 0.78 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206116 kb
Host smart-aa900543-e0d0-4e9a-a7df-7163c8860235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40946
47111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.4094647111
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2014080886
Short name T1943
Test name
Test status
Simulation time 177195789 ps
CPU time 0.81 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206192 kb
Host smart-e2d84801-7441-4583-b982-491d2beb118f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20140
80886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2014080886
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1971993237
Short name T2126
Test name
Test status
Simulation time 902582597 ps
CPU time 2.28 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:23 PM PDT 24
Peak memory 206364 kb
Host smart-20b730aa-4251-4591-a1f9-fb76dbd84755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19719
93237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1971993237
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.920126381
Short name T2501
Test name
Test status
Simulation time 4574476114 ps
CPU time 32.35 seconds
Started Jul 07 05:20:21 PM PDT 24
Finished Jul 07 05:20:54 PM PDT 24
Peak memory 206464 kb
Host smart-11ce05b5-b248-4e0b-ac35-dc883eed4aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92012
6381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.920126381
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.2035114534
Short name T474
Test name
Test status
Simulation time 57201217 ps
CPU time 0.68 seconds
Started Jul 07 05:20:33 PM PDT 24
Finished Jul 07 05:20:34 PM PDT 24
Peak memory 206216 kb
Host smart-87df73a6-c75c-4adf-abe9-9639c0be253c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2035114534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2035114534
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1439232815
Short name T1596
Test name
Test status
Simulation time 3864495545 ps
CPU time 4.44 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:25 PM PDT 24
Peak memory 206152 kb
Host smart-9722c840-b11c-4924-b354-7d335800d6fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1439232815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1439232815
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3812157934
Short name T862
Test name
Test status
Simulation time 13399562517 ps
CPU time 13.22 seconds
Started Jul 07 05:20:18 PM PDT 24
Finished Jul 07 05:20:32 PM PDT 24
Peak memory 206196 kb
Host smart-e3f1f69c-0f95-4b21-a67c-0b5fef3441d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3812157934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3812157934
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2252362677
Short name T2388
Test name
Test status
Simulation time 23394004385 ps
CPU time 23.5 seconds
Started Jul 07 05:20:27 PM PDT 24
Finished Jul 07 05:20:51 PM PDT 24
Peak memory 206236 kb
Host smart-08d7ec77-f0ac-485e-bd22-e0124d4aa1fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2252362677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2252362677
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.325026010
Short name T398
Test name
Test status
Simulation time 142507302 ps
CPU time 0.75 seconds
Started Jul 07 05:20:23 PM PDT 24
Finished Jul 07 05:20:24 PM PDT 24
Peak memory 205712 kb
Host smart-aba2132c-8727-4ad8-af5a-f80d42b8fe15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32502
6010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.325026010
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1100823146
Short name T2517
Test name
Test status
Simulation time 176782268 ps
CPU time 0.84 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206204 kb
Host smart-74bc9037-7c13-46b0-8a41-b07f5242e44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11008
23146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1100823146
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.306080133
Short name T1848
Test name
Test status
Simulation time 356438327 ps
CPU time 1.25 seconds
Started Jul 07 05:20:21 PM PDT 24
Finished Jul 07 05:20:23 PM PDT 24
Peak memory 206116 kb
Host smart-9f834a5b-7980-478d-a8e1-71815e548311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608
0133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.306080133
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.935608193
Short name T636
Test name
Test status
Simulation time 446785967 ps
CPU time 1.27 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206192 kb
Host smart-e5090b30-7fd5-4d83-845e-be73428d78a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93560
8193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.935608193
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3929087763
Short name T1747
Test name
Test status
Simulation time 16033416439 ps
CPU time 28.53 seconds
Started Jul 07 05:20:23 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 205688 kb
Host smart-a6f5704d-1663-4087-b03e-ff9816a1c272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39290
87763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3929087763
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2251820563
Short name T2018
Test name
Test status
Simulation time 459157903 ps
CPU time 1.32 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:22 PM PDT 24
Peak memory 206236 kb
Host smart-616050bb-216e-460a-8eaa-2ecebd687733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22518
20563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2251820563
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1180299002
Short name T1970
Test name
Test status
Simulation time 193376614 ps
CPU time 0.82 seconds
Started Jul 07 05:20:27 PM PDT 24
Finished Jul 07 05:20:28 PM PDT 24
Peak memory 206200 kb
Host smart-3d04eee3-04ba-428b-8bd1-13baaaf2f1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11802
99002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1180299002
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3915623988
Short name T2575
Test name
Test status
Simulation time 41641790 ps
CPU time 0.65 seconds
Started Jul 07 05:20:20 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206212 kb
Host smart-637b3479-6493-43a1-8cfd-c405cd98b2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
23988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3915623988
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1790513850
Short name T1427
Test name
Test status
Simulation time 967964732 ps
CPU time 2.13 seconds
Started Jul 07 05:20:26 PM PDT 24
Finished Jul 07 05:20:29 PM PDT 24
Peak memory 206432 kb
Host smart-908f7604-afaf-47da-aeaa-e1f21260e58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17905
13850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1790513850
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.857183858
Short name T2470
Test name
Test status
Simulation time 173777886 ps
CPU time 1.72 seconds
Started Jul 07 05:20:19 PM PDT 24
Finished Jul 07 05:20:21 PM PDT 24
Peak memory 206436 kb
Host smart-9d2e2a14-e52b-46b7-b9ec-40ab83666ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85718
3858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.857183858
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1364687441
Short name T1192
Test name
Test status
Simulation time 182343123 ps
CPU time 0.81 seconds
Started Jul 07 05:20:26 PM PDT 24
Finished Jul 07 05:20:27 PM PDT 24
Peak memory 206196 kb
Host smart-af754098-4203-4720-aba4-4732e01b3b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13646
87441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1364687441
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3945376477
Short name T2568
Test name
Test status
Simulation time 172733365 ps
CPU time 0.78 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:25 PM PDT 24
Peak memory 206108 kb
Host smart-db219543-42da-4245-ab2f-feb6d87e3ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
76477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3945376477
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.2162414797
Short name T111
Test name
Test status
Simulation time 6374171266 ps
CPU time 59.29 seconds
Started Jul 07 05:20:26 PM PDT 24
Finished Jul 07 05:21:26 PM PDT 24
Peak memory 206496 kb
Host smart-8283917a-76c4-4095-90a6-9962f051a4d9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2162414797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.2162414797
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1829793273
Short name T1700
Test name
Test status
Simulation time 212270173 ps
CPU time 0.85 seconds
Started Jul 07 05:20:25 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206204 kb
Host smart-743f25aa-44ef-4f00-a949-8d7c3af31d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18297
93273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1829793273
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1736296952
Short name T370
Test name
Test status
Simulation time 23334732516 ps
CPU time 30.13 seconds
Started Jul 07 05:20:25 PM PDT 24
Finished Jul 07 05:20:56 PM PDT 24
Peak memory 206252 kb
Host smart-5f4eee4d-c853-487c-a7b5-fcfbdf914ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17362
96952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1736296952
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.918875400
Short name T1102
Test name
Test status
Simulation time 3256419272 ps
CPU time 3.95 seconds
Started Jul 07 05:20:27 PM PDT 24
Finished Jul 07 05:20:31 PM PDT 24
Peak memory 206280 kb
Host smart-85031bea-5704-4383-8cf5-35ccc8a4a16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91887
5400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.918875400
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2918664804
Short name T2474
Test name
Test status
Simulation time 7222386675 ps
CPU time 64.61 seconds
Started Jul 07 05:20:25 PM PDT 24
Finished Jul 07 05:21:31 PM PDT 24
Peak memory 206496 kb
Host smart-c2fe8d64-df89-449d-ae1a-e2352a0dfbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29186
64804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2918664804
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.8334402
Short name T796
Test name
Test status
Simulation time 7784179809 ps
CPU time 55.23 seconds
Started Jul 07 05:20:26 PM PDT 24
Finished Jul 07 05:21:22 PM PDT 24
Peak memory 206488 kb
Host smart-f32fa29d-c3b6-44b5-84dc-d39b214b8dbd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=8334402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.8334402
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.898096318
Short name T837
Test name
Test status
Simulation time 282859867 ps
CPU time 0.93 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206144 kb
Host smart-917b075a-6960-4dc6-aca2-d161f4bd8631
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=898096318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.898096318
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.698988862
Short name T394
Test name
Test status
Simulation time 208823886 ps
CPU time 0.92 seconds
Started Jul 07 05:20:23 PM PDT 24
Finished Jul 07 05:20:25 PM PDT 24
Peak memory 206088 kb
Host smart-64c73c5e-e44d-4c71-b8c9-ee9ebdfe5bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69898
8862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.698988862
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.328341798
Short name T1440
Test name
Test status
Simulation time 5298641211 ps
CPU time 50.05 seconds
Started Jul 07 05:20:27 PM PDT 24
Finished Jul 07 05:21:17 PM PDT 24
Peak memory 206364 kb
Host smart-477db394-56a5-43dd-a387-f3b6d4955ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
1798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.328341798
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1998950436
Short name T40
Test name
Test status
Simulation time 6537832476 ps
CPU time 61.91 seconds
Started Jul 07 05:20:28 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206428 kb
Host smart-afc4e942-e6e4-4a17-91cd-274c2a28ab54
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1998950436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1998950436
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4291344892
Short name T2410
Test name
Test status
Simulation time 155614115 ps
CPU time 0.77 seconds
Started Jul 07 05:20:23 PM PDT 24
Finished Jul 07 05:20:24 PM PDT 24
Peak memory 206092 kb
Host smart-ddeb0810-711a-48b5-a25b-da14e007db7e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4291344892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4291344892
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2896580621
Short name T1163
Test name
Test status
Simulation time 148174084 ps
CPU time 0.79 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206116 kb
Host smart-88f7878d-3cd1-4a5e-be48-268563dadc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28965
80621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2896580621
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1242761706
Short name T152
Test name
Test status
Simulation time 203537890 ps
CPU time 0.86 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206192 kb
Host smart-3b4da33e-10f1-4d36-a56f-4db0a0979d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427
61706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1242761706
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1881240630
Short name T882
Test name
Test status
Simulation time 178230205 ps
CPU time 0.86 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206196 kb
Host smart-5e059f6e-6ed1-46db-83b9-b2185865e405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18812
40630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1881240630
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1127669461
Short name T644
Test name
Test status
Simulation time 157791621 ps
CPU time 0.77 seconds
Started Jul 07 05:20:23 PM PDT 24
Finished Jul 07 05:20:25 PM PDT 24
Peak memory 206156 kb
Host smart-80024197-b523-42ba-8d20-ea2b77c4f592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11276
69461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1127669461
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4077544872
Short name T1157
Test name
Test status
Simulation time 159388047 ps
CPU time 0.84 seconds
Started Jul 07 05:20:26 PM PDT 24
Finished Jul 07 05:20:28 PM PDT 24
Peak memory 206156 kb
Host smart-ef0e4b53-08c9-4afa-821b-27df154cc384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775
44872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4077544872
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3688242945
Short name T1272
Test name
Test status
Simulation time 165600627 ps
CPU time 0.81 seconds
Started Jul 07 05:20:24 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 206120 kb
Host smart-889e9802-57a4-4674-a702-bf7b49b1dc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36882
42945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3688242945
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1558109920
Short name T1326
Test name
Test status
Simulation time 234419047 ps
CPU time 0.95 seconds
Started Jul 07 05:20:25 PM PDT 24
Finished Jul 07 05:20:27 PM PDT 24
Peak memory 206140 kb
Host smart-bf9e9433-b027-4497-a448-cacc77101d66
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1558109920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1558109920
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3109967993
Short name T2375
Test name
Test status
Simulation time 142384500 ps
CPU time 0.78 seconds
Started Jul 07 05:20:30 PM PDT 24
Finished Jul 07 05:20:31 PM PDT 24
Peak memory 206152 kb
Host smart-d15e6c07-729e-433f-b30b-7f97f12f3a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31099
67993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3109967993
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4134523475
Short name T893
Test name
Test status
Simulation time 32696414 ps
CPU time 0.66 seconds
Started Jul 07 05:20:29 PM PDT 24
Finished Jul 07 05:20:30 PM PDT 24
Peak memory 206196 kb
Host smart-1add16f5-88ff-4899-b3e0-b870b2c7678d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41345
23475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4134523475
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3220250632
Short name T1858
Test name
Test status
Simulation time 15992084101 ps
CPU time 32.8 seconds
Started Jul 07 05:20:32 PM PDT 24
Finished Jul 07 05:21:05 PM PDT 24
Peak memory 206472 kb
Host smart-6acf2c0b-335f-4586-b6d2-f8826674a759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32202
50632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3220250632
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3317772815
Short name T1687
Test name
Test status
Simulation time 187513683 ps
CPU time 0.88 seconds
Started Jul 07 05:20:29 PM PDT 24
Finished Jul 07 05:20:30 PM PDT 24
Peak memory 206160 kb
Host smart-761c50e3-cbba-4e5d-b2bf-2357b44a6dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33177
72815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3317772815
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3952645852
Short name T2024
Test name
Test status
Simulation time 193062033 ps
CPU time 0.87 seconds
Started Jul 07 05:20:30 PM PDT 24
Finished Jul 07 05:20:32 PM PDT 24
Peak memory 206124 kb
Host smart-fd02305a-ce19-435a-ac1b-5486f28b19ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
45852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3952645852
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2071297597
Short name T168
Test name
Test status
Simulation time 7016153523 ps
CPU time 30.01 seconds
Started Jul 07 05:20:34 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206432 kb
Host smart-e2b3ffae-0171-4f8b-b8b5-733216788e9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2071297597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2071297597
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.516079391
Short name T2500
Test name
Test status
Simulation time 13790131614 ps
CPU time 278.55 seconds
Started Jul 07 05:20:30 PM PDT 24
Finished Jul 07 05:25:09 PM PDT 24
Peak memory 206480 kb
Host smart-3e153b3a-26d2-4c3d-9ef8-f30aa6b87d1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=516079391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.516079391
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1804086148
Short name T2647
Test name
Test status
Simulation time 7861257066 ps
CPU time 41.87 seconds
Started Jul 07 05:20:31 PM PDT 24
Finished Jul 07 05:21:13 PM PDT 24
Peak memory 206412 kb
Host smart-7b77d2d2-3f38-4934-8232-6db8683e1dcc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1804086148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1804086148
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1512366272
Short name T1978
Test name
Test status
Simulation time 221396703 ps
CPU time 0.94 seconds
Started Jul 07 05:20:29 PM PDT 24
Finished Jul 07 05:20:30 PM PDT 24
Peak memory 206188 kb
Host smart-e8e0a747-4305-4139-9565-9ec90c678134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
66272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1512366272
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.4105806568
Short name T1704
Test name
Test status
Simulation time 171058864 ps
CPU time 0.83 seconds
Started Jul 07 05:20:30 PM PDT 24
Finished Jul 07 05:20:31 PM PDT 24
Peak memory 206208 kb
Host smart-a9bb19dd-5b87-4a76-8cdb-39b6215cde7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41058
06568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.4105806568
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2128576749
Short name T92
Test name
Test status
Simulation time 162552011 ps
CPU time 0.84 seconds
Started Jul 07 05:20:29 PM PDT 24
Finished Jul 07 05:20:30 PM PDT 24
Peak memory 206440 kb
Host smart-a38898c5-25e8-4e01-a8ae-2bf8c6d0ef7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
76749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2128576749
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1619668398
Short name T457
Test name
Test status
Simulation time 157996523 ps
CPU time 0.79 seconds
Started Jul 07 05:20:28 PM PDT 24
Finished Jul 07 05:20:29 PM PDT 24
Peak memory 206060 kb
Host smart-278ee00c-1ecd-4ccd-a1d4-3e7c6b065cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16196
68398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1619668398
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1337681090
Short name T2617
Test name
Test status
Simulation time 158181228 ps
CPU time 0.88 seconds
Started Jul 07 05:20:28 PM PDT 24
Finished Jul 07 05:20:29 PM PDT 24
Peak memory 206192 kb
Host smart-4396431c-1165-4b90-aa40-51dccaf1298a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
81090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1337681090
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2336329244
Short name T1376
Test name
Test status
Simulation time 191278455 ps
CPU time 0.9 seconds
Started Jul 07 05:20:36 PM PDT 24
Finished Jul 07 05:20:37 PM PDT 24
Peak memory 206188 kb
Host smart-40fc5639-02bb-4e76-b670-ad2dc234c4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23363
29244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2336329244
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3306457068
Short name T516
Test name
Test status
Simulation time 4960761122 ps
CPU time 48.3 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 206396 kb
Host smart-3b4451dd-c2c9-4c59-a88f-0b79583943ff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3306457068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3306457068
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1959391745
Short name T1599
Test name
Test status
Simulation time 151655625 ps
CPU time 0.76 seconds
Started Jul 07 05:20:34 PM PDT 24
Finished Jul 07 05:20:35 PM PDT 24
Peak memory 206132 kb
Host smart-53e23d8d-ad80-4e7e-90d1-294e0226256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19593
91745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1959391745
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1288398554
Short name T1998
Test name
Test status
Simulation time 161637415 ps
CPU time 0.77 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:20:38 PM PDT 24
Peak memory 206184 kb
Host smart-801530a2-7740-4827-bef7-c36bc3c6bd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
98554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1288398554
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.934990003
Short name T2674
Test name
Test status
Simulation time 271659998 ps
CPU time 0.99 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:20:39 PM PDT 24
Peak memory 206188 kb
Host smart-97da9fed-1570-4b82-b941-971b6f162dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93499
0003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.934990003
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.290219741
Short name T524
Test name
Test status
Simulation time 5734822992 ps
CPU time 55.29 seconds
Started Jul 07 05:20:34 PM PDT 24
Finished Jul 07 05:21:30 PM PDT 24
Peak memory 206512 kb
Host smart-b96b0083-8a35-4ecc-8834-a4be7f133100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
9741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.290219741
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2741806320
Short name T2338
Test name
Test status
Simulation time 25292504 ps
CPU time 0.7 seconds
Started Jul 07 05:20:40 PM PDT 24
Finished Jul 07 05:20:41 PM PDT 24
Peak memory 206196 kb
Host smart-ff9545f9-c239-43e1-b05f-0b4417202045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2741806320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2741806320
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1605032369
Short name T1514
Test name
Test status
Simulation time 4166254347 ps
CPU time 4.92 seconds
Started Jul 07 05:20:36 PM PDT 24
Finished Jul 07 05:20:41 PM PDT 24
Peak memory 206240 kb
Host smart-a592aca5-bc4b-428c-8309-41fd9620e4f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1605032369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1605032369
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2942966881
Short name T1403
Test name
Test status
Simulation time 13383638446 ps
CPU time 13.02 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:20:50 PM PDT 24
Peak memory 206164 kb
Host smart-457a58d0-361b-4196-bb6b-6f9ccfde4b2b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2942966881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2942966881
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1331367846
Short name T1268
Test name
Test status
Simulation time 23404359820 ps
CPU time 24.58 seconds
Started Jul 07 05:20:32 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206244 kb
Host smart-477f1ff8-52aa-460a-8742-2efa4637d05d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1331367846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1331367846
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3827486949
Short name T1546
Test name
Test status
Simulation time 164652657 ps
CPU time 0.85 seconds
Started Jul 07 05:20:33 PM PDT 24
Finished Jul 07 05:20:34 PM PDT 24
Peak memory 206196 kb
Host smart-2f824b99-6797-4f35-9299-92174b45395e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38274
86949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3827486949
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.715505332
Short name T777
Test name
Test status
Simulation time 168584778 ps
CPU time 0.79 seconds
Started Jul 07 05:20:35 PM PDT 24
Finished Jul 07 05:20:36 PM PDT 24
Peak memory 206184 kb
Host smart-c69c823b-9e28-434d-93c0-1c9a768238a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71550
5332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.715505332
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.4089620682
Short name T1348
Test name
Test status
Simulation time 217078340 ps
CPU time 0.93 seconds
Started Jul 07 05:20:36 PM PDT 24
Finished Jul 07 05:20:37 PM PDT 24
Peak memory 206132 kb
Host smart-2e5c9e74-326c-4c91-951c-e2a16a0944a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
20682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.4089620682
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.884415687
Short name T2103
Test name
Test status
Simulation time 720539328 ps
CPU time 1.75 seconds
Started Jul 07 05:20:32 PM PDT 24
Finished Jul 07 05:20:34 PM PDT 24
Peak memory 206364 kb
Host smart-f02fd895-ab3c-483a-9756-000c9ba2eeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88441
5687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.884415687
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.927111910
Short name T939
Test name
Test status
Simulation time 6388926753 ps
CPU time 12.68 seconds
Started Jul 07 05:20:34 PM PDT 24
Finished Jul 07 05:20:47 PM PDT 24
Peak memory 206488 kb
Host smart-d6e08cf0-8025-4266-9fe1-624f4a49eb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92711
1910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.927111910
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2023755177
Short name T1575
Test name
Test status
Simulation time 454301546 ps
CPU time 1.38 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:20:38 PM PDT 24
Peak memory 206136 kb
Host smart-56aa89cc-c8cb-4470-9c9e-ed7e5d937ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
55177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2023755177
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3822735928
Short name T1731
Test name
Test status
Simulation time 149267776 ps
CPU time 0.84 seconds
Started Jul 07 05:20:36 PM PDT 24
Finished Jul 07 05:20:37 PM PDT 24
Peak memory 206208 kb
Host smart-3bd54a36-c7a8-463f-84fe-adb61839b8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
35928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3822735928
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2062784848
Short name T2553
Test name
Test status
Simulation time 102355737 ps
CPU time 0.75 seconds
Started Jul 07 05:20:34 PM PDT 24
Finished Jul 07 05:20:35 PM PDT 24
Peak memory 206148 kb
Host smart-6756a5b5-ea1f-4f84-bad9-7bea325268c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627
84848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2062784848
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2637246630
Short name T1004
Test name
Test status
Simulation time 911102919 ps
CPU time 2.13 seconds
Started Jul 07 05:20:33 PM PDT 24
Finished Jul 07 05:20:35 PM PDT 24
Peak memory 206328 kb
Host smart-e868d3eb-45ae-43c8-8cae-aa8a820790cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
46630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2637246630
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1043487410
Short name T864
Test name
Test status
Simulation time 357509289 ps
CPU time 1.97 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:20:45 PM PDT 24
Peak memory 206416 kb
Host smart-19e5c65c-eed9-4488-8883-b2a84945a9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10434
87410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1043487410
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3610941615
Short name T123
Test name
Test status
Simulation time 222799642 ps
CPU time 0.88 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206040 kb
Host smart-f563ad8d-c95f-41fb-9521-078508792620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
41615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3610941615
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1580331407
Short name T1119
Test name
Test status
Simulation time 149854155 ps
CPU time 0.76 seconds
Started Jul 07 05:20:38 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206204 kb
Host smart-b36b4235-e6cf-4c17-b136-c7f2f3192145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15803
31407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1580331407
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.871612240
Short name T2201
Test name
Test status
Simulation time 211008239 ps
CPU time 0.91 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206180 kb
Host smart-eefb6a6e-61a5-4b45-ac44-f31ffcce4fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87161
2240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.871612240
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3915416759
Short name T78
Test name
Test status
Simulation time 7027344410 ps
CPU time 199.08 seconds
Started Jul 07 05:20:38 PM PDT 24
Finished Jul 07 05:23:58 PM PDT 24
Peak memory 206424 kb
Host smart-7d55b2f4-5ca9-4bb6-88ec-2b17e7ea371f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3915416759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3915416759
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1363055352
Short name T356
Test name
Test status
Simulation time 184868252 ps
CPU time 0.87 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206116 kb
Host smart-e5c3ec34-cb69-4218-9405-b3b8bf672f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
55352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1363055352
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1649971335
Short name T353
Test name
Test status
Simulation time 23318621883 ps
CPU time 25.1 seconds
Started Jul 07 05:20:38 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206232 kb
Host smart-0e18fab8-b2ee-4cf7-84de-13598495f73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16499
71335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1649971335
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2869536696
Short name T1394
Test name
Test status
Simulation time 3301514778 ps
CPU time 4.02 seconds
Started Jul 07 05:20:36 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206152 kb
Host smart-5bd1bca5-95ea-4c3a-affe-9e5e256da83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28695
36696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2869536696
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.618087062
Short name T540
Test name
Test status
Simulation time 11195367310 ps
CPU time 322.99 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:26:01 PM PDT 24
Peak memory 206416 kb
Host smart-a9b673bc-bff5-4e14-852c-716ee6f723fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61808
7062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.618087062
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.257076580
Short name T403
Test name
Test status
Simulation time 5522223342 ps
CPU time 50.54 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:21:32 PM PDT 24
Peak memory 206404 kb
Host smart-52f69c43-477e-46b8-b643-51580bde6e9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=257076580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.257076580
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2550081803
Short name T1209
Test name
Test status
Simulation time 239648647 ps
CPU time 0.91 seconds
Started Jul 07 05:20:38 PM PDT 24
Finished Jul 07 05:20:39 PM PDT 24
Peak memory 206104 kb
Host smart-7257d254-98e9-4d52-88c5-8c1f21ef85a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2550081803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2550081803
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1010761854
Short name T861
Test name
Test status
Simulation time 188925011 ps
CPU time 0.87 seconds
Started Jul 07 05:20:38 PM PDT 24
Finished Jul 07 05:20:39 PM PDT 24
Peak memory 206172 kb
Host smart-0dfa370b-3c52-46ae-9fd1-eac72a063cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10107
61854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1010761854
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1800584264
Short name T707
Test name
Test status
Simulation time 4009024995 ps
CPU time 28.77 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:21:08 PM PDT 24
Peak memory 206380 kb
Host smart-51ce13eb-0189-4789-a512-569ef9c7f1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
84264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1800584264
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.872079938
Short name T2702
Test name
Test status
Simulation time 5325362555 ps
CPU time 140.19 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:23:03 PM PDT 24
Peak memory 206404 kb
Host smart-3a50e6f9-ce54-403a-b450-68bc59a324c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=872079938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.872079938
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1970234241
Short name T1651
Test name
Test status
Simulation time 160189389 ps
CPU time 0.83 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:20:39 PM PDT 24
Peak memory 206012 kb
Host smart-98528698-9a63-45b4-8be5-22cf8edadbe6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1970234241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1970234241
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.770466285
Short name T1598
Test name
Test status
Simulation time 138971255 ps
CPU time 0.8 seconds
Started Jul 07 05:20:38 PM PDT 24
Finished Jul 07 05:20:39 PM PDT 24
Peak memory 206200 kb
Host smart-a2c4d3ad-49ad-453e-9637-f7bb32a41519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77046
6285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.770466285
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3673782263
Short name T112
Test name
Test status
Simulation time 199737560 ps
CPU time 0.86 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:20:42 PM PDT 24
Peak memory 206188 kb
Host smart-571e3be4-2a0a-43d1-bbff-cd76da69d19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36737
82263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3673782263
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1102412347
Short name T2669
Test name
Test status
Simulation time 212405980 ps
CPU time 0.88 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206116 kb
Host smart-1ab25fae-bd1b-48bd-b03b-ce3561befa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11024
12347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1102412347
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4092442554
Short name T352
Test name
Test status
Simulation time 173651093 ps
CPU time 0.81 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:20:43 PM PDT 24
Peak memory 206192 kb
Host smart-cc433800-3652-4ae4-8a70-d6712a465a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
42554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4092442554
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.339120426
Short name T526
Test name
Test status
Simulation time 185770746 ps
CPU time 0.84 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:44 PM PDT 24
Peak memory 206188 kb
Host smart-c926a234-7c61-4b56-bc9d-34a7065c803a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33912
0426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.339120426
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3615132460
Short name T1586
Test name
Test status
Simulation time 160455019 ps
CPU time 0.86 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:43 PM PDT 24
Peak memory 206168 kb
Host smart-52d3c1e8-0024-489b-ac80-772ac2fbdf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
32460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3615132460
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.787378024
Short name T20
Test name
Test status
Simulation time 230839090 ps
CPU time 0.95 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206164 kb
Host smart-9922ec0b-94ce-40f3-8171-fb5442d55230
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=787378024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.787378024
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1840947607
Short name T2644
Test name
Test status
Simulation time 181713252 ps
CPU time 0.76 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:43 PM PDT 24
Peak memory 206184 kb
Host smart-9b86bf08-d4b3-4b97-a0b4-b468433af12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
47607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1840947607
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2765237471
Short name T2208
Test name
Test status
Simulation time 49599518 ps
CPU time 0.68 seconds
Started Jul 07 05:20:37 PM PDT 24
Finished Jul 07 05:20:38 PM PDT 24
Peak memory 206152 kb
Host smart-14c88826-3922-4aa7-b51f-7f22cddc023b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27652
37471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2765237471
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.786661403
Short name T2071
Test name
Test status
Simulation time 6371879826 ps
CPU time 15.32 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206480 kb
Host smart-fd3dde9e-57d5-427f-9f92-19bf7023e0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78666
1403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.786661403
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.182644338
Short name T1057
Test name
Test status
Simulation time 146756987 ps
CPU time 0.84 seconds
Started Jul 07 05:20:46 PM PDT 24
Finished Jul 07 05:20:47 PM PDT 24
Peak memory 206184 kb
Host smart-e4162bed-a574-4c2d-a1b6-d1a0f878de95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18264
4338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.182644338
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2543811327
Short name T1764
Test name
Test status
Simulation time 181920977 ps
CPU time 0.84 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:20:42 PM PDT 24
Peak memory 206204 kb
Host smart-cd34321c-2188-483f-975c-4d0094f26fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
11327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2543811327
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1912030893
Short name T196
Test name
Test status
Simulation time 9325067706 ps
CPU time 60.3 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 206384 kb
Host smart-c572d446-c746-43ab-8ff8-b7406cb057b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1912030893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1912030893
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1173476529
Short name T461
Test name
Test status
Simulation time 9794892238 ps
CPU time 171.86 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:23:33 PM PDT 24
Peak memory 206508 kb
Host smart-2d4f94cd-eaa3-43db-bd69-98af364dc8a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1173476529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1173476529
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1056994051
Short name T1817
Test name
Test status
Simulation time 11897578471 ps
CPU time 77.54 seconds
Started Jul 07 05:20:44 PM PDT 24
Finished Jul 07 05:22:02 PM PDT 24
Peak memory 206512 kb
Host smart-bc9e64de-6e80-4f30-a6cd-d8212b1b6b65
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1056994051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1056994051
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.134238685
Short name T805
Test name
Test status
Simulation time 186100927 ps
CPU time 0.83 seconds
Started Jul 07 05:20:40 PM PDT 24
Finished Jul 07 05:20:41 PM PDT 24
Peak memory 206032 kb
Host smart-c44e93d8-6cb2-4253-9b55-9d2213e584f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
8685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.134238685
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1205490244
Short name T1506
Test name
Test status
Simulation time 169904663 ps
CPU time 0.85 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:20:42 PM PDT 24
Peak memory 206192 kb
Host smart-44c7842e-ffd5-484d-8cf3-5e053637ad90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054
90244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1205490244
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1747230499
Short name T583
Test name
Test status
Simulation time 142851998 ps
CPU time 0.77 seconds
Started Jul 07 05:20:39 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 206200 kb
Host smart-73a7915b-9aae-4f71-bd3e-4147a90d888c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
30499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1747230499
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.96053179
Short name T1820
Test name
Test status
Simulation time 158809451 ps
CPU time 0.79 seconds
Started Jul 07 05:20:41 PM PDT 24
Finished Jul 07 05:20:42 PM PDT 24
Peak memory 206188 kb
Host smart-0b554684-d002-4870-82ed-a9e53b5e1dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96053
179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.96053179
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.387121416
Short name T701
Test name
Test status
Simulation time 169235640 ps
CPU time 0.81 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:43 PM PDT 24
Peak memory 206196 kb
Host smart-e00e6b2f-ce65-433c-9f3e-e04ee373c011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
1416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.387121416
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2619152027
Short name T1468
Test name
Test status
Simulation time 210810569 ps
CPU time 0.95 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:20:44 PM PDT 24
Peak memory 205896 kb
Host smart-a4996f5c-5c4a-4341-8122-e96b331d2521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
52027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2619152027
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3488326186
Short name T1043
Test name
Test status
Simulation time 4540894995 ps
CPU time 34.1 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:21:18 PM PDT 24
Peak memory 206532 kb
Host smart-ce11febd-0e9e-44e0-b837-7c6e3cc5fcba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3488326186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3488326186
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3355767489
Short name T1994
Test name
Test status
Simulation time 226554183 ps
CPU time 0.86 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:44 PM PDT 24
Peak memory 206200 kb
Host smart-0e6019ee-84a4-4996-9a2d-e669df03f1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33557
67489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3355767489
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.287426569
Short name T1964
Test name
Test status
Simulation time 167516813 ps
CPU time 0.8 seconds
Started Jul 07 05:20:40 PM PDT 24
Finished Jul 07 05:20:41 PM PDT 24
Peak memory 206196 kb
Host smart-37881904-a599-420e-b8d8-5319dee40797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
6569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.287426569
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.447693823
Short name T1218
Test name
Test status
Simulation time 1038500523 ps
CPU time 2.27 seconds
Started Jul 07 05:20:42 PM PDT 24
Finished Jul 07 05:20:44 PM PDT 24
Peak memory 206456 kb
Host smart-b3400032-3c49-44ef-bc03-a3ef28184ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44769
3823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.447693823
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2548911434
Short name T1297
Test name
Test status
Simulation time 6165824043 ps
CPU time 43.7 seconds
Started Jul 07 05:20:40 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 206416 kb
Host smart-72e8d469-eaec-490f-a02b-01b3783174ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25489
11434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2548911434
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1640050491
Short name T1948
Test name
Test status
Simulation time 54899795 ps
CPU time 0.67 seconds
Started Jul 07 05:21:00 PM PDT 24
Finished Jul 07 05:21:01 PM PDT 24
Peak memory 206224 kb
Host smart-556d2738-8892-4e4d-a7c3-96283f869d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1640050491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1640050491
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3536913799
Short name T2467
Test name
Test status
Simulation time 4203917346 ps
CPU time 4.85 seconds
Started Jul 07 05:20:44 PM PDT 24
Finished Jul 07 05:20:49 PM PDT 24
Peak memory 206160 kb
Host smart-bb0a74a2-574a-454b-bb94-3df608c2bf95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3536913799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3536913799
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2396814226
Short name T859
Test name
Test status
Simulation time 13311239999 ps
CPU time 12.64 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:20:56 PM PDT 24
Peak memory 206160 kb
Host smart-ecf23304-3abd-4d1a-8831-ac44e1e78ae7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2396814226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2396814226
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1614672963
Short name T1496
Test name
Test status
Simulation time 23413164186 ps
CPU time 23.95 seconds
Started Jul 07 05:20:46 PM PDT 24
Finished Jul 07 05:21:11 PM PDT 24
Peak memory 206140 kb
Host smart-45af7ae4-3be9-4122-aee6-df587b96023c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1614672963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.1614672963
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.892952703
Short name T2050
Test name
Test status
Simulation time 142665087 ps
CPU time 0.77 seconds
Started Jul 07 05:20:48 PM PDT 24
Finished Jul 07 05:20:49 PM PDT 24
Peak memory 206188 kb
Host smart-ca98a951-238e-447d-a5a4-022b1c61ed81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89295
2703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.892952703
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1649792795
Short name T1538
Test name
Test status
Simulation time 253142110 ps
CPU time 0.9 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:20:45 PM PDT 24
Peak memory 206196 kb
Host smart-3e8e76bf-17fa-4c26-9e4c-56fa78e57864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16497
92795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1649792795
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2728587094
Short name T727
Test name
Test status
Simulation time 298575074 ps
CPU time 1.15 seconds
Started Jul 07 05:20:47 PM PDT 24
Finished Jul 07 05:20:48 PM PDT 24
Peak memory 206192 kb
Host smart-aa7e5d6c-f74c-472b-ae3c-ff9e7ffbdfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
87094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2728587094
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3415654062
Short name T2583
Test name
Test status
Simulation time 1145997826 ps
CPU time 2.43 seconds
Started Jul 07 05:20:43 PM PDT 24
Finished Jul 07 05:20:46 PM PDT 24
Peak memory 206416 kb
Host smart-a062fa1d-8d62-4fec-b894-baf63d82fdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34156
54062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3415654062
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2480288066
Short name T1655
Test name
Test status
Simulation time 22692599601 ps
CPU time 42.37 seconds
Started Jul 07 05:20:45 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 206504 kb
Host smart-52d087f7-9c06-488c-9c4b-befc128a5d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
88066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2480288066
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2785003712
Short name T1549
Test name
Test status
Simulation time 311490106 ps
CPU time 1.07 seconds
Started Jul 07 05:20:46 PM PDT 24
Finished Jul 07 05:20:47 PM PDT 24
Peak memory 206128 kb
Host smart-1b3b4cc1-5af8-49b9-8d79-e5c08640168f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27850
03712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2785003712
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.428843615
Short name T1614
Test name
Test status
Simulation time 176916844 ps
CPU time 0.76 seconds
Started Jul 07 05:20:49 PM PDT 24
Finished Jul 07 05:20:50 PM PDT 24
Peak memory 206032 kb
Host smart-dfcbb786-d2f9-4e86-98dd-6f785e450f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
3615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.428843615
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.411942397
Short name T2129
Test name
Test status
Simulation time 118827264 ps
CPU time 0.72 seconds
Started Jul 07 05:20:50 PM PDT 24
Finished Jul 07 05:20:51 PM PDT 24
Peak memory 206204 kb
Host smart-add79ab3-817f-466b-a3ba-2b8555105509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41194
2397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.411942397
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2460098019
Short name T1896
Test name
Test status
Simulation time 954561545 ps
CPU time 2.22 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206440 kb
Host smart-f2e77816-c78a-464d-9310-41e7b312f989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600
98019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2460098019
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.112899619
Short name T2624
Test name
Test status
Simulation time 229836797 ps
CPU time 1.52 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 206372 kb
Host smart-9500599f-ea10-4c17-badb-13c6e1dbd874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
9619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.112899619
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2206078979
Short name T1054
Test name
Test status
Simulation time 214369172 ps
CPU time 0.89 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 206116 kb
Host smart-3565a058-d2d5-414b-8532-e8d61f07303e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
78979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2206078979
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.560520851
Short name T1018
Test name
Test status
Simulation time 197824934 ps
CPU time 0.79 seconds
Started Jul 07 05:20:48 PM PDT 24
Finished Jul 07 05:20:49 PM PDT 24
Peak memory 206420 kb
Host smart-93a92a37-749d-4492-943b-0cb8416a9762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56052
0851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.560520851
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3132067431
Short name T2491
Test name
Test status
Simulation time 227576403 ps
CPU time 0.92 seconds
Started Jul 07 05:20:49 PM PDT 24
Finished Jul 07 05:20:50 PM PDT 24
Peak memory 206152 kb
Host smart-df399253-6130-4ffa-8b5e-f93ef17c7b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31320
67431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3132067431
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2229985849
Short name T2670
Test name
Test status
Simulation time 9576740600 ps
CPU time 93.27 seconds
Started Jul 07 05:20:49 PM PDT 24
Finished Jul 07 05:22:22 PM PDT 24
Peak memory 206428 kb
Host smart-5cf6539b-7428-4dca-acaa-47c63c7e1f92
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2229985849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2229985849
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3334920872
Short name T377
Test name
Test status
Simulation time 231764420 ps
CPU time 0.99 seconds
Started Jul 07 05:20:52 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206216 kb
Host smart-3a68ee03-1abf-4deb-9540-e87c84d9dc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33349
20872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3334920872
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2936985966
Short name T760
Test name
Test status
Simulation time 23343106192 ps
CPU time 27.76 seconds
Started Jul 07 05:20:47 PM PDT 24
Finished Jul 07 05:21:15 PM PDT 24
Peak memory 206232 kb
Host smart-8cf2338d-9342-4bb6-831c-d0d1bb6a3493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29369
85966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2936985966
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1760234602
Short name T1077
Test name
Test status
Simulation time 3313716636 ps
CPU time 3.65 seconds
Started Jul 07 05:20:49 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206224 kb
Host smart-7c992634-c971-457a-b668-3480053c9ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
34602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1760234602
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.1515797462
Short name T2511
Test name
Test status
Simulation time 6172943690 ps
CPU time 42.87 seconds
Started Jul 07 05:20:52 PM PDT 24
Finished Jul 07 05:21:35 PM PDT 24
Peak memory 206512 kb
Host smart-d5bfd906-5db1-4c81-9e12-1919162c6013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15157
97462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1515797462
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.3030817626
Short name T346
Test name
Test status
Simulation time 4546830345 ps
CPU time 126.63 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:22:58 PM PDT 24
Peak memory 206372 kb
Host smart-85301e6a-ec6a-4062-9d42-b983cc9a05b9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3030817626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.3030817626
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2106037823
Short name T1605
Test name
Test status
Simulation time 306621177 ps
CPU time 0.93 seconds
Started Jul 07 05:20:50 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 206164 kb
Host smart-3c02a590-e0b0-40d3-ba18-0de41cb632c8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2106037823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2106037823
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3441936694
Short name T409
Test name
Test status
Simulation time 196033531 ps
CPU time 0.91 seconds
Started Jul 07 05:20:53 PM PDT 24
Finished Jul 07 05:20:55 PM PDT 24
Peak memory 206204 kb
Host smart-c357904c-f9da-4bf3-a554-1a7109b1848f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
36694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3441936694
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2665088244
Short name T2506
Test name
Test status
Simulation time 5066030476 ps
CPU time 47.91 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:21:40 PM PDT 24
Peak memory 206424 kb
Host smart-5dac78e1-cb71-40cb-b5c4-530503492165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26650
88244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2665088244
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2295649012
Short name T2066
Test name
Test status
Simulation time 5212077367 ps
CPU time 37.81 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:21:29 PM PDT 24
Peak memory 206420 kb
Host smart-9f216fb9-d803-469e-a4af-4bb45d15ad8c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2295649012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2295649012
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2331630046
Short name T1592
Test name
Test status
Simulation time 181614518 ps
CPU time 0.81 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 206160 kb
Host smart-3b72ca0c-b5ca-4283-b09b-232c7f1aa5c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2331630046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2331630046
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1029115808
Short name T1465
Test name
Test status
Simulation time 145094902 ps
CPU time 0.75 seconds
Started Jul 07 05:20:52 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206188 kb
Host smart-5810eb2a-6fb8-4ded-bbc3-33efd7d84212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10291
15808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1029115808
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1140127936
Short name T1951
Test name
Test status
Simulation time 230168895 ps
CPU time 0.98 seconds
Started Jul 07 05:20:51 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 206156 kb
Host smart-85573605-10e9-488c-8852-4c419dc53799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11401
27936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1140127936
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3144161641
Short name T942
Test name
Test status
Simulation time 169219246 ps
CPU time 0.82 seconds
Started Jul 07 05:20:52 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206192 kb
Host smart-ff67cdd6-6ba8-47a3-bc2f-b66d95ba0014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31441
61641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3144161641
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2940263333
Short name T2597
Test name
Test status
Simulation time 167637687 ps
CPU time 0.8 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206184 kb
Host smart-1b28b620-dccc-4bec-a21b-bc131499a253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402
63333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2940263333
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1942357797
Short name T1652
Test name
Test status
Simulation time 179781755 ps
CPU time 0.81 seconds
Started Jul 07 05:20:53 PM PDT 24
Finished Jul 07 05:20:54 PM PDT 24
Peak memory 206184 kb
Host smart-2d9c6d87-72fa-4a65-b8b2-504efcb73626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
57797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1942357797
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1472704883
Short name T2616
Test name
Test status
Simulation time 161392701 ps
CPU time 0.83 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206088 kb
Host smart-2227b8bf-90e5-4db6-ad65-98467721df60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14727
04883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1472704883
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3957304710
Short name T712
Test name
Test status
Simulation time 280882313 ps
CPU time 1.03 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 206160 kb
Host smart-73ab58d7-9980-494c-b58e-bbd55c6f19f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3957304710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3957304710
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3372861971
Short name T2078
Test name
Test status
Simulation time 155208324 ps
CPU time 0.77 seconds
Started Jul 07 05:20:55 PM PDT 24
Finished Jul 07 05:20:56 PM PDT 24
Peak memory 206232 kb
Host smart-0a1c03b8-ac70-40e9-a85d-bbd49f44d78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33728
61971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3372861971
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.4253441449
Short name T34
Test name
Test status
Simulation time 42324822 ps
CPU time 0.64 seconds
Started Jul 07 05:20:52 PM PDT 24
Finished Jul 07 05:20:53 PM PDT 24
Peak memory 206192 kb
Host smart-5643df32-c291-4929-8d62-2c6abb34f933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
41449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.4253441449
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.904385906
Short name T1608
Test name
Test status
Simulation time 9231265692 ps
CPU time 20.26 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:21:19 PM PDT 24
Peak memory 206512 kb
Host smart-abaa0868-9e3d-43fb-939d-ae3a3e9f7a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90438
5906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.904385906
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1419539140
Short name T2569
Test name
Test status
Simulation time 167895877 ps
CPU time 0.8 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206220 kb
Host smart-fffa364a-26a9-43b9-b2c7-bb2cbdc9fedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14195
39140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1419539140
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.478752155
Short name T961
Test name
Test status
Simulation time 225747916 ps
CPU time 0.96 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206060 kb
Host smart-70b1ac7a-1c88-487c-91f1-a4d6f669f07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47875
2155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.478752155
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1547193900
Short name T1286
Test name
Test status
Simulation time 7953017291 ps
CPU time 127.26 seconds
Started Jul 07 05:20:55 PM PDT 24
Finished Jul 07 05:23:02 PM PDT 24
Peak memory 206492 kb
Host smart-cd282efd-7d41-436f-8b32-1eb3f1c3a0c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1547193900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1547193900
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.4170425269
Short name T1123
Test name
Test status
Simulation time 11387743280 ps
CPU time 55.6 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:21:51 PM PDT 24
Peak memory 206476 kb
Host smart-907449e9-e309-47c0-8a0c-a439476956c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4170425269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.4170425269
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2566200696
Short name T1826
Test name
Test status
Simulation time 280974845 ps
CPU time 0.96 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206164 kb
Host smart-90512065-5cb8-4ddd-bf0d-bec7fb96561c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25662
00696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2566200696
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3326675537
Short name T969
Test name
Test status
Simulation time 162835847 ps
CPU time 0.91 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206036 kb
Host smart-525f81f8-9cb4-4fb7-a299-08503145d41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266
75537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3326675537
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1241721400
Short name T608
Test name
Test status
Simulation time 160605414 ps
CPU time 0.79 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206204 kb
Host smart-3a02e014-f78c-42ab-935c-31c044a25f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
21400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1241721400
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3216088702
Short name T660
Test name
Test status
Simulation time 178677065 ps
CPU time 0.77 seconds
Started Jul 07 05:20:53 PM PDT 24
Finished Jul 07 05:20:54 PM PDT 24
Peak memory 206160 kb
Host smart-99ab00fd-4bf4-435d-bef4-87ea77489024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32160
88702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3216088702
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.87238132
Short name T651
Test name
Test status
Simulation time 155696802 ps
CPU time 0.82 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206116 kb
Host smart-21c33010-343f-4526-8586-6b9fc659182c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87238
132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.87238132
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3597860239
Short name T1762
Test name
Test status
Simulation time 250596609 ps
CPU time 1.01 seconds
Started Jul 07 05:21:01 PM PDT 24
Finished Jul 07 05:21:02 PM PDT 24
Peak memory 206112 kb
Host smart-e107bfb3-aef1-48eb-ae27-16d324ecbb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978
60239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3597860239
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1458947135
Short name T369
Test name
Test status
Simulation time 4349910267 ps
CPU time 122.11 seconds
Started Jul 07 05:20:53 PM PDT 24
Finished Jul 07 05:22:56 PM PDT 24
Peak memory 206448 kb
Host smart-7e512d46-caf0-49da-9d9d-a1cc4b78fb23
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1458947135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1458947135
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3402060710
Short name T1725
Test name
Test status
Simulation time 203305311 ps
CPU time 0.82 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206188 kb
Host smart-37d62129-534f-469f-b7eb-b991f446e764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
60710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3402060710
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.863117167
Short name T2548
Test name
Test status
Simulation time 193927194 ps
CPU time 0.8 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206200 kb
Host smart-147e349c-898d-49fc-9336-fb4a068dccc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86311
7167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.863117167
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3721428462
Short name T1288
Test name
Test status
Simulation time 426215002 ps
CPU time 1.19 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206184 kb
Host smart-2e9b97e7-f88a-4323-a428-30876f0adefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37214
28462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3721428462
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2324761082
Short name T400
Test name
Test status
Simulation time 7898863009 ps
CPU time 230.25 seconds
Started Jul 07 05:21:00 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 206496 kb
Host smart-4cf93069-7910-49a0-96c7-02c96a786ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247
61082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2324761082
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2064635801
Short name T612
Test name
Test status
Simulation time 76066079 ps
CPU time 0.7 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 206172 kb
Host smart-26dc1071-9393-48b5-93b8-8c916f9b6170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2064635801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2064635801
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3232422687
Short name T1039
Test name
Test status
Simulation time 3536946341 ps
CPU time 5.3 seconds
Started Jul 07 05:20:59 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206268 kb
Host smart-74abe8cb-d2f0-433e-bc8e-c8f2923c69a5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3232422687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3232422687
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.4187890800
Short name T2335
Test name
Test status
Simulation time 13408319453 ps
CPU time 13.6 seconds
Started Jul 07 05:20:55 PM PDT 24
Finished Jul 07 05:21:09 PM PDT 24
Peak memory 206508 kb
Host smart-8f3bb407-bda5-4393-bac0-21905d91de7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4187890800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.4187890800
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.705752200
Short name T15
Test name
Test status
Simulation time 23469659268 ps
CPU time 24.64 seconds
Started Jul 07 05:20:59 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 206528 kb
Host smart-bd7e4f1b-d3c2-4e2d-bddd-54e84b75f2db
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=705752200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.705752200
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2554512323
Short name T2192
Test name
Test status
Simulation time 157690511 ps
CPU time 0.78 seconds
Started Jul 07 05:20:55 PM PDT 24
Finished Jul 07 05:20:56 PM PDT 24
Peak memory 206136 kb
Host smart-e7ea9e9b-436b-4d38-8a72-abb293b90301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25545
12323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2554512323
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.4272000103
Short name T711
Test name
Test status
Simulation time 160442935 ps
CPU time 0.74 seconds
Started Jul 07 05:20:55 PM PDT 24
Finished Jul 07 05:20:56 PM PDT 24
Peak memory 206196 kb
Host smart-636d341d-614f-4df7-bb0b-8c1e3a911a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42720
00103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.4272000103
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3290517982
Short name T1653
Test name
Test status
Simulation time 297083268 ps
CPU time 0.99 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:20:58 PM PDT 24
Peak memory 206032 kb
Host smart-d75ae141-d1a8-4e27-8b2d-d250035b730d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32905
17982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3290517982
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.4292148811
Short name T2518
Test name
Test status
Simulation time 504316624 ps
CPU time 1.5 seconds
Started Jul 07 05:20:57 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206204 kb
Host smart-13ae801d-76dc-46d6-804b-e7b2f43ef264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
48811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.4292148811
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1782299234
Short name T99
Test name
Test status
Simulation time 18504137331 ps
CPU time 40.34 seconds
Started Jul 07 05:20:57 PM PDT 24
Finished Jul 07 05:21:38 PM PDT 24
Peak memory 206360 kb
Host smart-000775ec-93de-4513-bcdf-e3e607a0669e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
99234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1782299234
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2256384822
Short name T1275
Test name
Test status
Simulation time 399065323 ps
CPU time 1.24 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206192 kb
Host smart-1323fb57-b9d0-42e0-b1ed-449d33ea69cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22563
84822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2256384822
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3043879157
Short name T1569
Test name
Test status
Simulation time 137183968 ps
CPU time 0.75 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:20:59 PM PDT 24
Peak memory 206044 kb
Host smart-938149ee-b3bf-4fd0-83e9-205422ad1f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438
79157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3043879157
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2806690183
Short name T1381
Test name
Test status
Simulation time 30784756 ps
CPU time 0.66 seconds
Started Jul 07 05:20:56 PM PDT 24
Finished Jul 07 05:20:57 PM PDT 24
Peak memory 206108 kb
Host smart-149bf433-fbf4-420d-9e91-9f1011c9d159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28066
90183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2806690183
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2188211527
Short name T1720
Test name
Test status
Simulation time 969014553 ps
CPU time 2.18 seconds
Started Jul 07 05:20:57 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 206440 kb
Host smart-50cdf6bf-fa64-49e7-a529-10b2f483404a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
11527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2188211527
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.4092257925
Short name T2579
Test name
Test status
Simulation time 252138112 ps
CPU time 1.53 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206304 kb
Host smart-ec2a4b74-cf61-426a-87c7-10a9f620e9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
57925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.4092257925
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.4004876943
Short name T1535
Test name
Test status
Simulation time 205180429 ps
CPU time 0.92 seconds
Started Jul 07 05:21:01 PM PDT 24
Finished Jul 07 05:21:02 PM PDT 24
Peak memory 206192 kb
Host smart-8331a641-c65c-42fc-8518-3aaeb324e727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40048
76943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.4004876943
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1887016563
Short name T1240
Test name
Test status
Simulation time 219147625 ps
CPU time 0.78 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206212 kb
Host smart-55519b49-e34d-4610-8130-80086a32dc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18870
16563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1887016563
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2082009581
Short name T875
Test name
Test status
Simulation time 218718976 ps
CPU time 0.92 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206116 kb
Host smart-f8abe7e5-83d8-4668-b747-3eda835c2b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20820
09581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2082009581
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.4020546667
Short name T1559
Test name
Test status
Simulation time 5562477754 ps
CPU time 42.17 seconds
Started Jul 07 05:21:08 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 206480 kb
Host smart-4c26c249-ebd0-451e-a98e-fea6e5e29d05
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4020546667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.4020546667
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1470789375
Short name T1100
Test name
Test status
Simulation time 204757162 ps
CPU time 0.91 seconds
Started Jul 07 05:21:01 PM PDT 24
Finished Jul 07 05:21:02 PM PDT 24
Peak memory 206196 kb
Host smart-ad6f97b0-2976-4e36-b005-d75aa669dd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
89375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1470789375
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1033869055
Short name T2541
Test name
Test status
Simulation time 23312023358 ps
CPU time 20.9 seconds
Started Jul 07 05:21:03 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 206204 kb
Host smart-12efb3c9-4f1c-41e3-8849-2abc3a70927f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
69055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1033869055
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2396573713
Short name T734
Test name
Test status
Simulation time 3321215278 ps
CPU time 4.77 seconds
Started Jul 07 05:21:01 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206248 kb
Host smart-e007f235-3d77-4b62-8253-5df7a88db657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
73713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2396573713
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1454558824
Short name T1433
Test name
Test status
Simulation time 8628328697 ps
CPU time 60.14 seconds
Started Jul 07 05:21:03 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 206480 kb
Host smart-c9c2ecf8-4955-44d7-b7d0-729b8c714011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14545
58824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1454558824
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3054871478
Short name T752
Test name
Test status
Simulation time 4616907021 ps
CPU time 33.17 seconds
Started Jul 07 05:21:01 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 206424 kb
Host smart-7bac8605-463f-4c97-85b1-a1ae54771bdb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3054871478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3054871478
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2353950813
Short name T408
Test name
Test status
Simulation time 252127070 ps
CPU time 1.01 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 206096 kb
Host smart-6549fe41-9098-48f5-8dd2-3ebb73b05eaa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2353950813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2353950813
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.4229867693
Short name T1024
Test name
Test status
Simulation time 250318299 ps
CPU time 0.88 seconds
Started Jul 07 05:20:58 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 206120 kb
Host smart-ab8ffd9e-5b82-430d-bf47-07e533c3fbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42298
67693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.4229867693
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2979578243
Short name T411
Test name
Test status
Simulation time 4522975616 ps
CPU time 35.48 seconds
Started Jul 07 05:21:00 PM PDT 24
Finished Jul 07 05:21:36 PM PDT 24
Peak memory 206320 kb
Host smart-d0b02f4b-606f-4e95-bf93-b332d0ff88a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
78243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2979578243
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.690861335
Short name T64
Test name
Test status
Simulation time 5132788886 ps
CPU time 138.72 seconds
Started Jul 07 05:21:06 PM PDT 24
Finished Jul 07 05:23:25 PM PDT 24
Peak memory 206412 kb
Host smart-32589003-1717-41e4-b12a-c189aebd4349
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=690861335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.690861335
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2309595752
Short name T2496
Test name
Test status
Simulation time 208261777 ps
CPU time 0.83 seconds
Started Jul 07 05:21:00 PM PDT 24
Finished Jul 07 05:21:01 PM PDT 24
Peak memory 206096 kb
Host smart-68fb84e6-3dd6-46b2-9486-95a965376fed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2309595752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2309595752
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1656081794
Short name T2185
Test name
Test status
Simulation time 152040632 ps
CPU time 0.77 seconds
Started Jul 07 05:21:03 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206188 kb
Host smart-662aef7d-f2bd-4b21-9776-3823ba87854a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
81794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1656081794
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.4081400386
Short name T134
Test name
Test status
Simulation time 244600138 ps
CPU time 0.91 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206120 kb
Host smart-62c8c0c6-55d0-475b-a332-fba2e56c4e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40814
00386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.4081400386
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2853728969
Short name T1226
Test name
Test status
Simulation time 237109629 ps
CPU time 0.92 seconds
Started Jul 07 05:21:03 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206184 kb
Host smart-c48b41fe-4f48-40ec-9dfc-67669c386cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28537
28969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2853728969
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2377902730
Short name T2525
Test name
Test status
Simulation time 178128082 ps
CPU time 0.82 seconds
Started Jul 07 05:21:02 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206188 kb
Host smart-c909ecc9-d341-481d-8087-5f2b54f9e2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
02730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2377902730
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2067484915
Short name T870
Test name
Test status
Simulation time 178858263 ps
CPU time 0.81 seconds
Started Jul 07 05:21:06 PM PDT 24
Finished Jul 07 05:21:07 PM PDT 24
Peak memory 206168 kb
Host smart-ee01eb70-59af-4ef9-995f-27cfa3d40388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20674
84915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2067484915
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.223461114
Short name T192
Test name
Test status
Simulation time 155614123 ps
CPU time 0.81 seconds
Started Jul 07 05:21:01 PM PDT 24
Finished Jul 07 05:21:02 PM PDT 24
Peak memory 206088 kb
Host smart-0a179ecc-7e45-4e1a-a686-f037bc2ccf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22346
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.223461114
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.209845218
Short name T851
Test name
Test status
Simulation time 228925602 ps
CPU time 0.98 seconds
Started Jul 07 05:21:00 PM PDT 24
Finished Jul 07 05:21:01 PM PDT 24
Peak memory 206420 kb
Host smart-e1df78c3-9fd7-4c27-a30f-314847277703
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=209845218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.209845218
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1582135548
Short name T222
Test name
Test status
Simulation time 145701446 ps
CPU time 0.82 seconds
Started Jul 07 05:21:00 PM PDT 24
Finished Jul 07 05:21:01 PM PDT 24
Peak memory 206120 kb
Host smart-cbaca606-ecce-4842-b5c8-eb76319a6e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15821
35548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1582135548
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3984142961
Short name T31
Test name
Test status
Simulation time 40790001 ps
CPU time 0.73 seconds
Started Jul 07 05:21:03 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 206148 kb
Host smart-3aecb36b-45b9-43ee-b1d1-4cf133410ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
42961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3984142961
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.234556990
Short name T2549
Test name
Test status
Simulation time 9231804190 ps
CPU time 20.36 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 206456 kb
Host smart-fd9eb265-05f9-4e15-a4bc-24ea2a46fb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23455
6990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.234556990
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1020142973
Short name T443
Test name
Test status
Simulation time 199645563 ps
CPU time 0.86 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206116 kb
Host smart-032f9f72-b19b-416a-924d-cde803af3893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10201
42973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1020142973
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3050947762
Short name T1425
Test name
Test status
Simulation time 263879396 ps
CPU time 0.88 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206156 kb
Host smart-d3187612-db68-4e2b-a70a-2521d55f84dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30509
47762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3050947762
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1534307051
Short name T2418
Test name
Test status
Simulation time 11116083722 ps
CPU time 194.55 seconds
Started Jul 07 05:21:03 PM PDT 24
Finished Jul 07 05:24:18 PM PDT 24
Peak memory 206484 kb
Host smart-4d2370b9-b43e-45c2-bbcb-8a23d33290ee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1534307051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1534307051
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3563186194
Short name T182
Test name
Test status
Simulation time 10146728663 ps
CPU time 266.2 seconds
Started Jul 07 05:21:06 PM PDT 24
Finished Jul 07 05:25:33 PM PDT 24
Peak memory 206472 kb
Host smart-af3e9f2c-85a9-4858-8ab7-2a800a08536e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3563186194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3563186194
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4074874355
Short name T1058
Test name
Test status
Simulation time 12747952750 ps
CPU time 88.38 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:22:34 PM PDT 24
Peak memory 206428 kb
Host smart-4b5f0377-0e8c-4d76-8d9b-eb0c6f28a85f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4074874355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4074874355
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.658118315
Short name T1109
Test name
Test status
Simulation time 172137305 ps
CPU time 0.81 seconds
Started Jul 07 05:21:06 PM PDT 24
Finished Jul 07 05:21:07 PM PDT 24
Peak memory 206116 kb
Host smart-94379157-e289-417a-ac2b-64e2963870e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65811
8315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.658118315
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.679915384
Short name T417
Test name
Test status
Simulation time 193480660 ps
CPU time 0.89 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206164 kb
Host smart-8d1664d7-9e4b-4483-aaf0-7a43bca038f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67991
5384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.679915384
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4037485614
Short name T46
Test name
Test status
Simulation time 196434471 ps
CPU time 0.9 seconds
Started Jul 07 05:21:06 PM PDT 24
Finished Jul 07 05:21:07 PM PDT 24
Peak memory 206120 kb
Host smart-66b03836-6eba-4a4a-b796-ae20cbcd3a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40374
85614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4037485614
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2412206666
Short name T1489
Test name
Test status
Simulation time 165142556 ps
CPU time 0.81 seconds
Started Jul 07 05:21:05 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 206192 kb
Host smart-a4aa10b6-7741-464d-8284-011cde6009a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24122
06666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2412206666
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3912613316
Short name T446
Test name
Test status
Simulation time 164730990 ps
CPU time 0.84 seconds
Started Jul 07 05:21:04 PM PDT 24
Finished Jul 07 05:21:05 PM PDT 24
Peak memory 206204 kb
Host smart-b6c8b8b8-3e6c-4362-8a45-f32f8b2ea12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39126
13316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3912613316
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.4053900037
Short name T2492
Test name
Test status
Simulation time 249205854 ps
CPU time 1.03 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:09 PM PDT 24
Peak memory 206148 kb
Host smart-3a3608e1-01e8-4b04-9f2c-847c8e374c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40539
00037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.4053900037
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2543807798
Short name T950
Test name
Test status
Simulation time 5005169630 ps
CPU time 141.26 seconds
Started Jul 07 05:21:04 PM PDT 24
Finished Jul 07 05:23:26 PM PDT 24
Peak memory 206472 kb
Host smart-2abd1271-7ca1-4795-97d2-7232e23bbb52
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2543807798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2543807798
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3137019601
Short name T2352
Test name
Test status
Simulation time 226084242 ps
CPU time 0.87 seconds
Started Jul 07 05:21:08 PM PDT 24
Finished Jul 07 05:21:09 PM PDT 24
Peak memory 206444 kb
Host smart-c85c125a-2974-46ac-87ab-ced6ac72c6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31370
19601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3137019601
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2389400058
Short name T2156
Test name
Test status
Simulation time 180736902 ps
CPU time 0.87 seconds
Started Jul 07 05:21:07 PM PDT 24
Finished Jul 07 05:21:08 PM PDT 24
Peak memory 206148 kb
Host smart-9a0e1260-3c07-4b2c-848d-bc53c47d91fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23894
00058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2389400058
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3965505162
Short name T671
Test name
Test status
Simulation time 1215434962 ps
CPU time 2.35 seconds
Started Jul 07 05:21:10 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 206368 kb
Host smart-d23cb31d-5881-4216-aa58-9245ce19f19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39655
05162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3965505162
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3008037214
Short name T1688
Test name
Test status
Simulation time 8141180932 ps
CPU time 58.77 seconds
Started Jul 07 05:21:12 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 206508 kb
Host smart-b56a527f-5dcc-4c5e-b305-0ff56c6be1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30080
37214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3008037214
Directory /workspace/9.usbdev_streaming_out/latest
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