Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90506	1		T1	2		T2	2		T3	2
all_values[1]	90506	1		T1	2		T2	2		T3	2
all_values[2]	90506	1		T1	2		T2	2		T3	2
all_values[3]	90506	1		T1	2		T2	2		T3	2
all_values[4]	90506	1		T1	2		T2	2		T3	2
all_values[5]	90506	1		T1	2		T2	2		T3	2
all_values[6]	90506	1		T1	2		T2	2		T3	2
all_values[7]	90506	1		T1	2		T2	2		T3	2
all_values[8]	90506	1		T1	2		T2	2		T3	2
all_values[9]	90506	1		T1	2		T2	2		T3	2
all_values[10]	90506	1		T1	2		T2	2		T3	2
all_values[11]	90506	1		T1	2		T2	2		T3	2
all_values[12]	90506	1		T1	2		T2	2		T3	2
all_values[13]	90506	1		T1	2		T2	2		T3	2
all_values[14]	90506	1		T1	2		T2	2		T3	2
all_values[15]	90506	1		T1	2		T2	2		T3	2
all_values[16]	90506	1		T1	2		T2	2		T3	2
all_values[17]	90506	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1622048	1		T1	36		T2	36		T3	34
auto[1]	7060	1		T3	2		T28	2		T31	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1623769	1		T1	36		T2	36		T3	36
auto[1]	5339	1		T203	129		T204	118		T205	124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	89511	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	155	1		T203	6		T204	4		T205	2
all_values[0]	auto[1]	auto[0]	688	1		T33	3		T35	3		T48	3
all_values[0]	auto[1]	auto[1]	152	1		T203	2		T204	2		T205	6
all_values[1]	auto[0]	auto[0]	88682	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	148	1		T203	5		T204	5		T205	1
all_values[1]	auto[1]	auto[0]	1527	1		T28	2		T31	14		T34	3
all_values[1]	auto[1]	auto[1]	149	1		T203	3		T204	1		T205	5
all_values[2]	auto[0]	auto[0]	90078	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	140	1		T203	1		T204	3		T205	5
all_values[2]	auto[1]	auto[0]	133	1		T18	2		T44	2		T45	2
all_values[2]	auto[1]	auto[1]	155	1		T203	3		T204	5		T205	3
all_values[3]	auto[0]	auto[0]	88753	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	168	1		T203	5		T204	2		T205	1
all_values[3]	auto[1]	auto[0]	1451	1		T65	1429		T204	1		T205	1
all_values[3]	auto[1]	auto[1]	134	1		T203	3		T204	5		T205	6
all_values[4]	auto[0]	auto[0]	90183	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	120	1		T203	2		T204	2		T206	2
all_values[4]	auto[1]	auto[0]	28	1		T66	2		T204	1		T205	2
all_values[4]	auto[1]	auto[1]	175	1		T203	6		T204	4		T205	6
all_values[5]	auto[0]	auto[0]	90179	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	154	1		T203	1		T204	6		T205	4
all_values[5]	auto[1]	auto[0]	34	1		T206	1		T282	1		T283	7
all_values[5]	auto[1]	auto[1]	139	1		T203	7		T204	2		T205	4
all_values[6]	auto[0]	auto[0]	90187	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	128	1		T204	5		T206	6		T280	1
all_values[6]	auto[1]	auto[0]	32	1		T203	2		T204	2		T284	3
all_values[6]	auto[1]	auto[1]	159	1		T203	4		T204	1		T205	6
all_values[7]	auto[0]	auto[0]	90173	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	139	1		T203	5		T204	1		T205	1
all_values[7]	auto[1]	auto[0]	37	1		T49	2		T204	4		T280	1
all_values[7]	auto[1]	auto[1]	157	1		T203	3		T204	3		T205	7
all_values[8]	auto[0]	auto[0]	90180	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	161	1		T203	2		T204	5		T205	4
all_values[8]	auto[1]	auto[0]	43	1		T53	11		T203	1		T204	1
all_values[8]	auto[1]	auto[1]	122	1		T203	5		T204	1		T205	2
all_values[9]	auto[0]	auto[0]	90166	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	159	1		T204	5		T205	5		T206	3
all_values[9]	auto[1]	auto[0]	53	1		T62	5		T63	5		T64	5
all_values[9]	auto[1]	auto[1]	128	1		T203	7		T205	3		T206	4
all_values[10]	auto[0]	auto[0]	90182	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	143	1		T203	3		T204	4		T205	1
all_values[10]	auto[1]	auto[0]	31	1		T204	1		T282	1		T284	3
all_values[10]	auto[1]	auto[1]	150	1		T203	4		T204	2		T205	7
all_values[11]	auto[0]	auto[0]	90078	1		T1	2		T2	2		T4	2
all_values[11]	auto[0]	auto[1]	136	1		T204	1		T205	1		T206	1
all_values[11]	auto[1]	auto[0]	128	1		T3	2		T70	2		T71	2
all_values[11]	auto[1]	auto[1]	164	1		T203	8		T204	6		T205	3
all_values[12]	auto[0]	auto[0]	90165	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	137	1		T203	3		T204	3		T206	6
all_values[12]	auto[1]	auto[0]	43	1		T73	3		T74	3		T75	3
all_values[12]	auto[1]	auto[1]	161	1		T203	5		T204	5		T205	4
all_values[13]	auto[0]	auto[0]	90181	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	151	1		T203	1		T204	5		T205	3
all_values[13]	auto[1]	auto[0]	17	1		T203	1		T206	1		T280	1
all_values[13]	auto[1]	auto[1]	157	1		T203	6		T204	3		T205	5
all_values[14]	auto[0]	auto[0]	90185	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	154	1		T203	6		T204	4		T205	1
all_values[14]	auto[1]	auto[0]	31	1		T203	1		T206	2		T280	2
all_values[14]	auto[1]	auto[1]	136	1		T203	1		T204	2		T205	7
all_values[15]	auto[0]	auto[0]	90187	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	140	1		T203	2		T204	5		T206	4
all_values[15]	auto[1]	auto[0]	27	1		T203	1		T205	1		T284	1
all_values[15]	auto[1]	auto[1]	152	1		T203	4		T204	2		T205	6
all_values[16]	auto[0]	auto[0]	90163	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	164	1		T203	7		T204	1		T205	4
all_values[16]	auto[1]	auto[0]	48	1		T67	8		T68	8		T69	8
all_values[16]	auto[1]	auto[1]	131	1		T203	1		T204	5		T205	3
all_values[17]	auto[0]	auto[0]	90162	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	156	1		T203	7		T204	5		T205	4
all_values[17]	auto[1]	auto[0]	23	1		T54	2		T55	2		T56	2
all_values[17]	auto[1]	auto[1]	165	1		T203	1		T204	3		T205	4