Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90506	1		T1	2		T2	2		T3	2
all_pins[1]	90506	1		T1	2		T2	2		T3	2
all_pins[2]	90506	1		T1	2		T2	2		T3	2
all_pins[3]	90506	1		T1	2		T2	2		T3	2
all_pins[4]	90506	1		T1	2		T2	2		T3	2
all_pins[5]	90506	1		T1	2		T2	2		T3	2
all_pins[6]	90506	1		T1	2		T2	2		T3	2
all_pins[7]	90506	1		T1	2		T2	2		T3	2
all_pins[8]	90506	1		T1	2		T2	2		T3	2
all_pins[9]	90506	1		T1	2		T2	2		T3	2
all_pins[10]	90506	1		T1	2		T2	2		T3	2
all_pins[11]	90506	1		T1	2		T2	2		T3	2
all_pins[12]	90506	1		T1	2		T2	2		T3	2
all_pins[13]	90506	1		T1	2		T2	2		T3	2
all_pins[14]	90506	1		T1	2		T2	2		T3	2
all_pins[15]	90506	1		T1	2		T2	2		T3	2
all_pins[16]	90506	1		T1	2		T2	2		T3	2
all_pins[17]	90506	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1626722	1		T1	36		T2	36		T3	35
values[0x1]	2386	1		T3	1		T28	1		T31	12
transitions[0x0=>0x1]	2046	1		T3	1		T28	1		T31	12
transitions[0x1=>0x0]	2063	1		T3	1		T28	1		T31	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90386	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	120	1		T285	1		T286	1		T287	1
all_pins[0]	transitions[0x0=>0x1]	103	1		T285	1		T286	1		T287	1
all_pins[0]	transitions[0x1=>0x0]	991	1		T28	1		T31	12		T34	1
all_pins[1]	values[0x0]	89498	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1008	1		T28	1		T31	12		T34	1
all_pins[1]	transitions[0x0=>0x1]	994	1		T28	1		T31	12		T34	1
all_pins[1]	transitions[0x1=>0x0]	118	1		T18	1		T44	1		T45	1
all_pins[2]	values[0x0]	90374	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	132	1		T18	1		T44	1		T45	1
all_pins[2]	transitions[0x0=>0x1]	112	1		T18	1		T44	1		T45	1
all_pins[2]	transitions[0x1=>0x0]	47	1		T65	1		T203	2		T204	2
all_pins[3]	values[0x0]	90439	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	67	1		T65	1		T203	2		T204	4
all_pins[3]	transitions[0x0=>0x1]	49	1		T65	1		T203	2		T204	4
all_pins[3]	transitions[0x1=>0x0]	74	1		T66	1		T203	3		T206	2
all_pins[4]	values[0x0]	90414	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	92	1		T66	1		T203	3		T205	1
all_pins[4]	transitions[0x0=>0x1]	68	1		T66	1		T205	1		T206	2
all_pins[4]	transitions[0x1=>0x0]	41	1		T203	1		T204	1		T206	1
all_pins[5]	values[0x0]	90441	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	65	1		T203	4		T204	1		T206	1
all_pins[5]	transitions[0x0=>0x1]	48	1		T203	2		T204	1		T206	1
all_pins[5]	transitions[0x1=>0x0]	65	1		T203	1		T205	4		T206	2
all_pins[6]	values[0x0]	90424	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	82	1		T203	3		T205	4		T206	2
all_pins[6]	transitions[0x0=>0x1]	61	1		T203	3		T205	2		T280	1
all_pins[6]	transitions[0x1=>0x0]	44	1		T49	1		T203	2		T204	1
all_pins[7]	values[0x0]	90441	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	65	1		T49	1		T203	2		T204	1
all_pins[7]	transitions[0x0=>0x1]	50	1		T49	1		T203	1		T204	1
all_pins[7]	transitions[0x1=>0x0]	39	1		T53	1		T204	1		T205	1
all_pins[8]	values[0x0]	90452	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	54	1		T53	1		T203	1		T204	1
all_pins[8]	transitions[0x0=>0x1]	38	1		T53	1		T204	1		T205	2
all_pins[8]	transitions[0x1=>0x0]	60	1		T62	2		T63	2		T64	2
all_pins[9]	values[0x0]	90430	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	76	1		T62	2		T63	2		T64	2
all_pins[9]	transitions[0x0=>0x1]	64	1		T62	2		T63	2		T64	2
all_pins[9]	transitions[0x1=>0x0]	45	1		T204	2		T205	4		T206	2
all_pins[10]	values[0x0]	90449	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	57	1		T204	2		T205	5		T206	3
all_pins[10]	transitions[0x0=>0x1]	41	1		T204	1		T205	3		T288	1
all_pins[10]	transitions[0x1=>0x0]	116	1		T3	1		T70	1		T71	1
all_pins[11]	values[0x0]	90374	1		T1	2		T2	2		T3	1
all_pins[11]	values[0x1]	132	1		T3	1		T70	1		T71	1
all_pins[11]	transitions[0x0=>0x1]	100	1		T3	1		T70	1		T71	1
all_pins[11]	transitions[0x1=>0x0]	50	1		T73	1		T74	1		T75	1
all_pins[12]	values[0x0]	90424	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	82	1		T73	1		T74	1		T75	1
all_pins[12]	transitions[0x0=>0x1]	61	1		T73	1		T74	1		T75	1
all_pins[12]	transitions[0x1=>0x0]	54	1		T203	2		T205	1		T280	1
all_pins[13]	values[0x0]	90431	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	75	1		T203	5		T205	3		T280	3
all_pins[13]	transitions[0x0=>0x1]	63	1		T203	5		T205	1		T280	1
all_pins[13]	transitions[0x1=>0x0]	47	1		T203	1		T204	1		T205	2
all_pins[14]	values[0x0]	90447	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	59	1		T203	1		T204	1		T205	4
all_pins[14]	transitions[0x0=>0x1]	42	1		T204	1		T280	2		T288	1
all_pins[14]	transitions[0x1=>0x0]	57	1		T203	2		T206	3		T288	2
all_pins[15]	values[0x0]	90432	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	74	1		T203	3		T205	4		T206	3
all_pins[15]	transitions[0x0=>0x1]	53	1		T203	3		T205	4		T206	2
all_pins[15]	transitions[0x1=>0x0]	58	1		T67	4		T68	4		T69	4
all_pins[16]	values[0x0]	90427	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	79	1		T67	4		T68	4		T69	4
all_pins[16]	transitions[0x0=>0x1]	63	1		T67	4		T68	4		T69	4
all_pins[16]	transitions[0x1=>0x0]	51	1		T54	1		T55	1		T56	1
all_pins[17]	values[0x0]	90439	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	67	1		T54	1		T55	1		T56	1
all_pins[17]	transitions[0x0=>0x1]	36	1		T54	1		T55	1		T56	1
all_pins[17]	transitions[0x1=>0x0]	106	1		T285	1		T286	1		T287	1