Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	299	1		T203	7		T204	7		T205	7
all_values[1]	299	1		T203	7		T204	7		T205	7
all_values[2]	299	1		T203	7		T204	7		T205	7
all_values[3]	299	1		T203	7		T204	7		T205	7
all_values[4]	299	1		T203	7		T204	7		T205	7
all_values[5]	299	1		T203	7		T204	7		T205	7
all_values[6]	299	1		T203	7		T204	7		T205	7
all_values[7]	299	1		T203	7		T204	7		T205	7
all_values[8]	299	1		T203	7		T204	7		T205	7
all_values[9]	299	1		T203	7		T204	7		T205	7
all_values[10]	299	1		T203	7		T204	7		T205	7
all_values[11]	299	1		T203	7		T204	7		T205	7
all_values[12]	299	1		T203	7		T204	7		T205	7
all_values[13]	299	1		T203	7		T204	7		T205	7
all_values[14]	299	1		T203	7		T204	7		T205	7
all_values[15]	299	1		T203	7		T204	7		T205	7
all_values[16]	299	1		T203	7		T204	7		T205	7
all_values[17]	299	1		T203	7		T204	7		T205	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2921	1		T203	63		T204	75		T205	56
auto[1]	2461	1		T203	63		T204	51		T205	70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	896	1		T203	15		T204	26		T205	20
auto[1]	4486	1		T203	111		T204	100		T205	106

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3122	1		T203	61		T204	77		T205	67
auto[1]	2260	1		T203	65		T204	49		T205	59

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1		T204	1		T289	1		T283	1
all_values[0]	auto[0]	auto[0]	auto[1]	65	1		T203	2		T204	1		T205	1
all_values[0]	auto[0]	auto[1]	auto[0]	12	1		T204	1		T283	1		T290	1
all_values[0]	auto[0]	auto[1]	auto[1]	55	1		T203	2		T204	1		T205	3
all_values[0]	auto[1]	auto[0]	auto[1]	78	1		T203	2		T204	2		T205	2
all_values[0]	auto[1]	auto[1]	auto[1]	59	1		T203	1		T204	1		T205	1
all_values[1]	auto[0]	auto[0]	auto[0]	28	1		T204	1		T205	1		T283	1
all_values[1]	auto[0]	auto[0]	auto[1]	62	1		T203	2		T204	2		T206	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1		T204	1		T205	1		T282	1
all_values[1]	auto[0]	auto[1]	auto[1]	60	1		T204	1		T205	2		T206	3
all_values[1]	auto[1]	auto[0]	auto[1]	77	1		T203	3		T204	1		T280	2
all_values[1]	auto[1]	auto[1]	auto[1]	51	1		T203	2		T204	1		T205	3
all_values[2]	auto[0]	auto[0]	auto[0]	29	1		T203	4		T206	1		T288	1
all_values[2]	auto[0]	auto[0]	auto[1]	60	1		T204	2		T205	4		T206	1
all_values[2]	auto[0]	auto[1]	auto[0]	24	1		T288	1		T284	2		T281	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1		T203	1		T204	1		T206	2
all_values[2]	auto[1]	auto[0]	auto[1]	65	1		T204	3		T205	1		T206	2
all_values[2]	auto[1]	auto[1]	auto[1]	59	1		T203	2		T204	1		T205	2
all_values[3]	auto[0]	auto[0]	auto[0]	26	1		T204	1		T205	1		T280	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1		T203	1		T205	1		T206	3
all_values[3]	auto[0]	auto[1]	auto[0]	19	1		T206	1		T282	2		T291	1
all_values[3]	auto[0]	auto[1]	auto[1]	58	1		T203	1		T204	2		T205	2
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T203	3		T206	1		T280	1
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T203	2		T204	4		T205	3
all_values[4]	auto[0]	auto[0]	auto[0]	35	1		T204	2		T205	1		T288	1
all_values[4]	auto[0]	auto[0]	auto[1]	50	1		T204	1		T206	1		T288	1
all_values[4]	auto[0]	auto[1]	auto[0]	16	1		T205	1		T283	1		T292	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1		T203	3		T204	3		T205	4
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T203	1		T204	1		T280	1
all_values[4]	auto[1]	auto[1]	auto[1]	63	1		T203	3		T205	1		T206	2
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T206	1		T282	2		T284	2
all_values[5]	auto[0]	auto[0]	auto[1]	65	1		T203	1		T204	2		T205	2
all_values[5]	auto[0]	auto[1]	auto[0]	23	1		T206	1		T282	2		T283	4
all_values[5]	auto[0]	auto[1]	auto[1]	61	1		T203	2		T204	3		T205	2
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T203	1		T204	1		T205	3
all_values[5]	auto[1]	auto[1]	auto[1]	64	1		T203	3		T204	1		T206	1
all_values[6]	auto[0]	auto[0]	auto[0]	37	1		T203	1		T204	1		T205	2
all_values[6]	auto[0]	auto[0]	auto[1]	51	1		T204	2		T206	1		T280	1
all_values[6]	auto[0]	auto[1]	auto[0]	21	1		T203	3		T204	1		T284	3
all_values[6]	auto[0]	auto[1]	auto[1]	63	1		T203	1		T205	3		T206	1
all_values[6]	auto[1]	auto[0]	auto[1]	71	1		T203	1		T204	3		T205	1
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T203	1		T205	1		T206	2
all_values[7]	auto[0]	auto[0]	auto[0]	26	1		T204	1		T280	1		T288	4
all_values[7]	auto[0]	auto[0]	auto[1]	56	1		T203	2		T206	2		T280	1
all_values[7]	auto[0]	auto[1]	auto[0]	24	1		T204	3		T282	2		T290	2
all_values[7]	auto[0]	auto[1]	auto[1]	61	1		T203	2		T204	1		T205	4
all_values[7]	auto[1]	auto[0]	auto[1]	74	1		T203	2		T204	2		T205	1
all_values[7]	auto[1]	auto[1]	auto[1]	58	1		T203	1		T205	2		T206	2
all_values[8]	auto[0]	auto[0]	auto[0]	41	1		T203	1		T204	2		T205	2
all_values[8]	auto[0]	auto[0]	auto[1]	68	1		T203	1		T204	3		T205	2
all_values[8]	auto[0]	auto[1]	auto[0]	21	1		T280	1		T281	3		T290	3
all_values[8]	auto[0]	auto[1]	auto[1]	48	1		T203	2		T204	1		T206	1
all_values[8]	auto[1]	auto[0]	auto[1]	68	1		T203	1		T205	2		T206	4
all_values[8]	auto[1]	auto[1]	auto[1]	53	1		T203	2		T204	1		T205	1
all_values[9]	auto[0]	auto[0]	auto[0]	41	1		T203	1		T204	2		T206	1
all_values[9]	auto[0]	auto[0]	auto[1]	65	1		T204	1		T205	2		T288	1
all_values[9]	auto[0]	auto[1]	auto[0]	18	1		T204	1		T290	2		T293	1
all_values[9]	auto[0]	auto[1]	auto[1]	52	1		T203	2		T205	1		T206	1
all_values[9]	auto[1]	auto[0]	auto[1]	71	1		T204	2		T205	2		T206	2
all_values[9]	auto[1]	auto[1]	auto[1]	52	1		T203	4		T204	1		T205	2
all_values[10]	auto[0]	auto[0]	auto[0]	27	1		T203	1		T204	2		T289	5
all_values[10]	auto[0]	auto[0]	auto[1]	60	1		T203	1		T204	1		T206	1
all_values[10]	auto[0]	auto[1]	auto[0]	25	1		T282	1		T284	3		T289	2
all_values[10]	auto[0]	auto[1]	auto[1]	69	1		T203	2		T204	2		T205	1
all_values[10]	auto[1]	auto[0]	auto[1]	71	1		T203	2		T205	2		T206	2
all_values[10]	auto[1]	auto[1]	auto[1]	47	1		T203	1		T204	2		T205	4
all_values[11]	auto[0]	auto[0]	auto[0]	28	1		T204	1		T205	2		T280	2
all_values[11]	auto[0]	auto[0]	auto[1]	51	1		T204	1		T206	1		T288	3
all_values[11]	auto[0]	auto[1]	auto[0]	20	1		T205	2		T281	1		T293	1
all_values[11]	auto[0]	auto[1]	auto[1]	71	1		T203	1		T204	1		T205	1
all_values[11]	auto[1]	auto[0]	auto[1]	56	1		T203	1		T204	2		T205	1
all_values[11]	auto[1]	auto[1]	auto[1]	73	1		T203	5		T204	2		T205	1
all_values[12]	auto[0]	auto[0]	auto[0]	29	1		T205	2		T280	1		T289	2
all_values[12]	auto[0]	auto[0]	auto[1]	56	1		T203	1		T204	1		T206	3
all_values[12]	auto[0]	auto[1]	auto[0]	21	1		T205	2		T206	1		T280	1
all_values[12]	auto[0]	auto[1]	auto[1]	68	1		T203	1		T204	1		T205	1
all_values[12]	auto[1]	auto[0]	auto[1]	66	1		T203	3		T204	1		T206	2
all_values[12]	auto[1]	auto[1]	auto[1]	59	1		T203	2		T204	4		T205	2
all_values[13]	auto[0]	auto[0]	auto[0]	27	1		T203	1		T206	3		T280	1
all_values[13]	auto[0]	auto[0]	auto[1]	77	1		T204	4		T205	2		T206	1
all_values[13]	auto[0]	auto[1]	auto[0]	12	1		T206	1		T294	1		T295	1
all_values[13]	auto[0]	auto[1]	auto[1]	61	1		T203	2		T204	1		T205	1
all_values[13]	auto[1]	auto[0]	auto[1]	73	1		T203	1		T204	2		T205	3
all_values[13]	auto[1]	auto[1]	auto[1]	49	1		T203	3		T205	1		T280	2
all_values[14]	auto[0]	auto[0]	auto[0]	32	1		T203	1		T204	2		T280	1
all_values[14]	auto[0]	auto[0]	auto[1]	61	1		T203	3		T204	2		T288	1
all_values[14]	auto[0]	auto[1]	auto[0]	23	1		T206	2		T280	1		T293	1
all_values[14]	auto[0]	auto[1]	auto[1]	63	1		T203	1		T205	1		T206	3
all_values[14]	auto[1]	auto[0]	auto[1]	74	1		T203	1		T204	1		T205	1
all_values[14]	auto[1]	auto[1]	auto[1]	46	1		T203	1		T204	2		T205	5
all_values[15]	auto[0]	auto[0]	auto[0]	35	1		T203	1		T204	1		T205	2
all_values[15]	auto[0]	auto[0]	auto[1]	51	1		T204	2		T206	1		T288	3
all_values[15]	auto[0]	auto[1]	auto[0]	19	1		T203	1		T284	2		T289	3
all_values[15]	auto[0]	auto[1]	auto[1]	65	1		T203	2		T204	1		T205	2
all_values[15]	auto[1]	auto[0]	auto[1]	77	1		T203	2		T204	2		T205	1
all_values[15]	auto[1]	auto[1]	auto[1]	52	1		T203	1		T204	1		T205	2
all_values[16]	auto[0]	auto[0]	auto[0]	36	1		T204	2		T205	1		T288	4
all_values[16]	auto[0]	auto[0]	auto[1]	75	1		T203	5		T205	1		T206	2
all_values[16]	auto[0]	auto[1]	auto[0]	14	1		T206	1		T288	3		T294	1
all_values[16]	auto[0]	auto[1]	auto[1]	50	1		T204	2		T205	1		T206	2
all_values[16]	auto[1]	auto[0]	auto[1]	76	1		T203	2		T204	2		T205	2
all_values[16]	auto[1]	auto[1]	auto[1]	48	1		T204	1		T205	2		T206	2
all_values[17]	auto[0]	auto[0]	auto[0]	16	1		T283	1		T295	1		T296	1
all_values[17]	auto[0]	auto[0]	auto[1]	63	1		T203	2		T204	4		T205	2
all_values[17]	auto[0]	auto[1]	auto[0]	11	1		T294	1		T297	1		T298	2
all_values[17]	auto[0]	auto[1]	auto[1]	75	1		T204	1		T205	1		T206	2
all_values[17]	auto[1]	auto[0]	auto[1]	77	1		T203	5		T204	2		T205	3
all_values[17]	auto[1]	auto[1]	auto[1]	57	1		T205	1		T206	1		T280	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal