Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.79 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2809
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T268 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2773091277 Jul 09 05:03:14 PM PDT 24 Jul 09 05:03:15 PM PDT 24 39200754 ps
T2759 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2089267567 Jul 09 05:03:24 PM PDT 24 Jul 09 05:03:27 PM PDT 24 187939486 ps
T2760 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.324305576 Jul 09 05:03:38 PM PDT 24 Jul 09 05:03:40 PM PDT 24 52916195 ps
T2761 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.229336732 Jul 09 05:03:21 PM PDT 24 Jul 09 05:03:22 PM PDT 24 222868181 ps
T269 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3416209344 Jul 09 05:03:22 PM PDT 24 Jul 09 05:03:25 PM PDT 24 203567399 ps
T2762 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1705394744 Jul 09 05:03:40 PM PDT 24 Jul 09 05:03:43 PM PDT 24 136086228 ps
T2763 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1568603172 Jul 09 05:03:26 PM PDT 24 Jul 09 05:03:29 PM PDT 24 106340919 ps
T306 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1772162144 Jul 09 05:03:26 PM PDT 24 Jul 09 05:03:32 PM PDT 24 1080650904 ps
T2764 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2031214022 Jul 09 05:03:42 PM PDT 24 Jul 09 05:03:44 PM PDT 24 61496112 ps
T2765 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.746870993 Jul 09 05:03:38 PM PDT 24 Jul 09 05:03:41 PM PDT 24 142828844 ps
T2766 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3277910730 Jul 09 05:03:33 PM PDT 24 Jul 09 05:03:35 PM PDT 24 168266091 ps
T2767 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.601923182 Jul 09 05:03:24 PM PDT 24 Jul 09 05:03:26 PM PDT 24 96916350 ps
T2768 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2921393513 Jul 09 05:03:40 PM PDT 24 Jul 09 05:03:42 PM PDT 24 61527377 ps
T307 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2921649931 Jul 09 05:03:30 PM PDT 24 Jul 09 05:03:37 PM PDT 24 1504066503 ps
T2769 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3408887199 Jul 09 05:03:24 PM PDT 24 Jul 09 05:03:25 PM PDT 24 48313535 ps
T2770 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3337672045 Jul 09 05:03:38 PM PDT 24 Jul 09 05:03:41 PM PDT 24 115858223 ps
T308 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2713286262 Jul 09 05:03:39 PM PDT 24 Jul 09 05:03:46 PM PDT 24 807128801 ps
T2771 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1786184554 Jul 09 05:03:11 PM PDT 24 Jul 09 05:03:15 PM PDT 24 287348897 ps
T2772 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3076105226 Jul 09 05:03:38 PM PDT 24 Jul 09 05:03:42 PM PDT 24 453139511 ps
T2773 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3776660501 Jul 09 05:03:43 PM PDT 24 Jul 09 05:03:45 PM PDT 24 40599707 ps
T270 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4293020078 Jul 09 05:03:22 PM PDT 24 Jul 09 05:03:24 PM PDT 24 120699353 ps
T2774 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.772695077 Jul 09 05:03:25 PM PDT 24 Jul 09 05:03:26 PM PDT 24 58893039 ps
T2775 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3362898796 Jul 09 05:03:26 PM PDT 24 Jul 09 05:03:29 PM PDT 24 210315346 ps
T2776 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.24810122 Jul 09 05:03:39 PM PDT 24 Jul 09 05:03:41 PM PDT 24 54872691 ps
T2777 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3181123102 Jul 09 05:03:50 PM PDT 24 Jul 09 05:03:52 PM PDT 24 38196019 ps
T300 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.451914538 Jul 09 05:03:30 PM PDT 24 Jul 09 05:03:35 PM PDT 24 694293765 ps
T2778 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.6861211 Jul 09 05:03:37 PM PDT 24 Jul 09 05:03:40 PM PDT 24 174194813 ps
T2779 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2874382278 Jul 09 05:03:19 PM PDT 24 Jul 09 05:03:22 PM PDT 24 153950494 ps
T301 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2357949720 Jul 09 05:03:42 PM PDT 24 Jul 09 05:03:46 PM PDT 24 381479375 ps
T2780 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2239843455 Jul 09 05:03:44 PM PDT 24 Jul 09 05:03:45 PM PDT 24 75286207 ps
T2781 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1332975625 Jul 09 05:03:17 PM PDT 24 Jul 09 05:03:22 PM PDT 24 789486589 ps
T2782 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.129721877 Jul 09 05:03:46 PM PDT 24 Jul 09 05:03:48 PM PDT 24 41232709 ps
T2783 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1931317928 Jul 09 05:03:42 PM PDT 24 Jul 09 05:03:45 PM PDT 24 56204645 ps
T2784 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2459585805 Jul 09 05:03:26 PM PDT 24 Jul 09 05:03:28 PM PDT 24 46241098 ps
T2785 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1270194425 Jul 09 05:03:41 PM PDT 24 Jul 09 05:03:43 PM PDT 24 57891869 ps
T2786 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3303649458 Jul 09 05:03:39 PM PDT 24 Jul 09 05:03:42 PM PDT 24 34644553 ps
T2787 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2007131040 Jul 09 05:03:40 PM PDT 24 Jul 09 05:03:43 PM PDT 24 70807959 ps
T2788 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.656997426 Jul 09 05:03:40 PM PDT 24 Jul 09 05:03:42 PM PDT 24 56542647 ps
T2789 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2879316022 Jul 09 05:03:13 PM PDT 24 Jul 09 05:03:17 PM PDT 24 350383604 ps
T2790 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2743937899 Jul 09 05:03:37 PM PDT 24 Jul 09 05:03:39 PM PDT 24 125738696 ps
T2791 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2245205937 Jul 09 05:03:17 PM PDT 24 Jul 09 05:03:19 PM PDT 24 138675466 ps
T2792 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3090600137 Jul 09 05:03:39 PM PDT 24 Jul 09 05:03:41 PM PDT 24 71933725 ps
T2793 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2024394689 Jul 09 05:03:39 PM PDT 24 Jul 09 05:03:45 PM PDT 24 284115887 ps
T2794 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1740502915 Jul 09 05:03:29 PM PDT 24 Jul 09 05:03:31 PM PDT 24 95451819 ps
T2795 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1754648392 Jul 09 05:03:17 PM PDT 24 Jul 09 05:03:21 PM PDT 24 237797551 ps
T2796 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.284891809 Jul 09 05:03:44 PM PDT 24 Jul 09 05:03:45 PM PDT 24 33000262 ps
T2797 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1118283030 Jul 09 05:03:42 PM PDT 24 Jul 09 05:03:44 PM PDT 24 50457088 ps
T2798 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.899822595 Jul 09 05:03:37 PM PDT 24 Jul 09 05:03:38 PM PDT 24 70823159 ps
T2799 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3330510699 Jul 09 05:03:24 PM PDT 24 Jul 09 05:03:25 PM PDT 24 78183127 ps
T2800 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2699718566 Jul 09 05:03:15 PM PDT 24 Jul 09 05:03:17 PM PDT 24 51293652 ps
T2801 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2963200590 Jul 09 05:03:44 PM PDT 24 Jul 09 05:03:46 PM PDT 24 41439399 ps
T2802 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.888501810 Jul 09 05:03:42 PM PDT 24 Jul 09 05:03:46 PM PDT 24 196602879 ps
T2803 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3987980891 Jul 09 05:03:40 PM PDT 24 Jul 09 05:03:42 PM PDT 24 61027665 ps
T2804 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3983090986 Jul 09 05:03:40 PM PDT 24 Jul 09 05:03:43 PM PDT 24 34321046 ps
T2805 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1787435900 Jul 09 05:03:41 PM PDT 24 Jul 09 05:03:46 PM PDT 24 106090839 ps
T2806 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3210550058 Jul 09 05:03:44 PM PDT 24 Jul 09 05:03:46 PM PDT 24 45800868 ps
T2807 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1561047057 Jul 09 05:03:33 PM PDT 24 Jul 09 05:03:36 PM PDT 24 239007887 ps
T2808 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4136106425 Jul 09 05:03:13 PM PDT 24 Jul 09 05:03:15 PM PDT 24 99943441 ps
T2809 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2667699922 Jul 09 05:03:42 PM PDT 24 Jul 09 05:03:44 PM PDT 24 90585686 ps

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1685612155
Short name T6
Test name
Test status
Simulation time 7710225385 ps
CPU time 202.61 seconds
Started Jul 09 05:15:29 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206384 kb
Host smart-c8e5de0c-031e-4f23-81f1-a46c5c5f1876
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1685612155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1685612155
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2179988154
Short name T205
Test name
Test status
Simulation time 42979345 ps
CPU time 0.69 seconds
Started Jul 09 05:03:54 PM PDT 24
Finished Jul 09 05:03:58 PM PDT 24
Peak memory 205672 kb
Host smart-369d56fd-cd50-44e4-89e0-a1b2cf5733e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2179988154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2179988154
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3020049019
Short name T8
Test name
Test status
Simulation time 13416704688 ps
CPU time 13.62 seconds
Started Jul 09 05:18:34 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206096 kb
Host smart-07f816d5-8813-45fc-ad87-4e79a537a93b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3020049019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3020049019
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_device_address.861800838
Short name T82
Test name
Test status
Simulation time 20196859267 ps
CPU time 38.79 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206400 kb
Host smart-8b4fb817-36db-4ffb-ab0b-4a1b49033245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86180
0838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.861800838
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.619693334
Short name T226
Test name
Test status
Simulation time 486506277 ps
CPU time 3.19 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205892 kb
Host smart-0e642f07-a3ae-40c6-9454-ea3f5a8fb44d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=619693334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.619693334
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.4186546956
Short name T80
Test name
Test status
Simulation time 159471130 ps
CPU time 0.82 seconds
Started Jul 09 05:15:01 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206052 kb
Host smart-e8411443-6f97-44a3-ade0-dd80994c0eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41865
46956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.4186546956
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1656670295
Short name T204
Test name
Test status
Simulation time 67212722 ps
CPU time 0.73 seconds
Started Jul 09 05:03:53 PM PDT 24
Finished Jul 09 05:03:57 PM PDT 24
Peak memory 205652 kb
Host smart-594c163b-34f6-4ad8-9807-a80828b8690c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1656670295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1656670295
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1527612239
Short name T110
Test name
Test status
Simulation time 218538314 ps
CPU time 0.87 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 205988 kb
Host smart-4674163d-925a-4d62-803a-28171bc087dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
12239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1527612239
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1524628363
Short name T45
Test name
Test status
Simulation time 143603937 ps
CPU time 0.75 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206128 kb
Host smart-f66e19e9-1716-4f6b-84ad-3b9486a6cd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15246
28363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1524628363
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1635397522
Short name T7
Test name
Test status
Simulation time 3635950061 ps
CPU time 4.08 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:59 PM PDT 24
Peak memory 206192 kb
Host smart-7d8cf35c-cd58-4007-89e1-c9b1ec6b1c01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1635397522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1635397522
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.694999798
Short name T107
Test name
Test status
Simulation time 496956162 ps
CPU time 1.55 seconds
Started Jul 09 05:12:13 PM PDT 24
Finished Jul 09 05:12:16 PM PDT 24
Peak memory 206232 kb
Host smart-8223fc9d-17f4-4512-bbe6-0c04a583127e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69499
9798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.694999798
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2311452030
Short name T195
Test name
Test status
Simulation time 114488075 ps
CPU time 3.3 seconds
Started Jul 09 05:03:18 PM PDT 24
Finished Jul 09 05:03:22 PM PDT 24
Peak memory 222168 kb
Host smart-8036c878-f48b-4489-8c91-1cce556bebbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2311452030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2311452030
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3416079411
Short name T190
Test name
Test status
Simulation time 530732162 ps
CPU time 1.4 seconds
Started Jul 09 05:11:51 PM PDT 24
Finished Jul 09 05:11:53 PM PDT 24
Peak memory 224856 kb
Host smart-306f0715-a718-4b28-94b5-4bafbb850bd5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3416079411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3416079411
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3529711159
Short name T141
Test name
Test status
Simulation time 186056670 ps
CPU time 0.85 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206156 kb
Host smart-a3b39ccd-e6a3-41d4-ac38-f7d797ce52e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35297
11159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3529711159
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1291122808
Short name T26
Test name
Test status
Simulation time 27968240 ps
CPU time 0.65 seconds
Started Jul 09 05:12:25 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206112 kb
Host smart-911ae192-ad6f-4f53-8f2a-f39706a0dac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
22808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1291122808
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2374426681
Short name T206
Test name
Test status
Simulation time 48700666 ps
CPU time 0.73 seconds
Started Jul 09 05:03:46 PM PDT 24
Finished Jul 09 05:03:47 PM PDT 24
Peak memory 205636 kb
Host smart-f12fb372-1376-4352-b3b6-a0be10a2f8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2374426681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2374426681
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2196766894
Short name T48
Test name
Test status
Simulation time 222068032 ps
CPU time 0.9 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:59 PM PDT 24
Peak memory 205920 kb
Host smart-9cb15118-324a-47f7-bc20-e100be7fd3ea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2196766894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2196766894
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2078880059
Short name T1
Test name
Test status
Simulation time 10436699410 ps
CPU time 23.15 seconds
Started Jul 09 05:18:26 PM PDT 24
Finished Jul 09 05:18:50 PM PDT 24
Peak memory 206420 kb
Host smart-f282170f-64b3-431d-9731-83c62b1b42d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20788
80059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2078880059
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.253773859
Short name T76
Test name
Test status
Simulation time 302541518 ps
CPU time 0.98 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206160 kb
Host smart-5c437399-47ba-410c-a20a-e85b5fad222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25377
3859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.253773859
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.4199550286
Short name T47
Test name
Test status
Simulation time 20157090294 ps
CPU time 25.01 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:12:00 PM PDT 24
Peak memory 206188 kb
Host smart-8daf5c80-bdcf-49a2-884c-b2c0b16855ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
50286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.4199550286
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4081777659
Short name T258
Test name
Test status
Simulation time 127617466 ps
CPU time 0.94 seconds
Started Jul 09 05:03:44 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 205692 kb
Host smart-6175aafc-ef55-4c40-9c20-100090f65e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4081777659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4081777659
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2978761159
Short name T91
Test name
Test status
Simulation time 142699474 ps
CPU time 0.76 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206000 kb
Host smart-f3a84d81-d988-4bb5-993c-85cf06c4ca21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29787
61159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2978761159
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1063156425
Short name T193
Test name
Test status
Simulation time 347797001 ps
CPU time 2.6 seconds
Started Jul 09 05:03:25 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 205832 kb
Host smart-5cacafed-fdb2-40f4-a859-2f1d0bcf95cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1063156425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1063156425
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3187423444
Short name T105
Test name
Test status
Simulation time 10407366004 ps
CPU time 186.1 seconds
Started Jul 09 05:11:50 PM PDT 24
Finished Jul 09 05:14:57 PM PDT 24
Peak memory 206488 kb
Host smart-daae8317-0a62-47f0-b479-104ddbaf369b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3187423444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3187423444
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2683782045
Short name T294
Test name
Test status
Simulation time 53783745 ps
CPU time 0.71 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:39 PM PDT 24
Peak memory 205672 kb
Host smart-ff2013e4-7707-45d3-9a43-415ae69cdb18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2683782045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2683782045
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1323022668
Short name T302
Test name
Test status
Simulation time 704363373 ps
CPU time 4.69 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205968 kb
Host smart-5757c7b3-267f-4dc6-90ba-a491a34d0117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1323022668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1323022668
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3552768108
Short name T281
Test name
Test status
Simulation time 38234570 ps
CPU time 0.68 seconds
Started Jul 09 05:03:44 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 205692 kb
Host smart-351d837a-37ba-4348-9ebb-dce233f798a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3552768108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3552768108
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.963453013
Short name T286
Test name
Test status
Simulation time 171148360 ps
CPU time 0.83 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206040 kb
Host smart-8999bff6-e882-46d1-b263-4a8d7a71aa29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96345
3013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.963453013
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.532793455
Short name T50
Test name
Test status
Simulation time 496432033 ps
CPU time 1.51 seconds
Started Jul 09 05:11:49 PM PDT 24
Finished Jul 09 05:11:52 PM PDT 24
Peak memory 206164 kb
Host smart-37a0aa09-f996-4c0d-9fa6-83178696ea1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53279
3455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.532793455
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3186371905
Short name T103
Test name
Test status
Simulation time 1550397197 ps
CPU time 3.55 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:35 PM PDT 24
Peak memory 206380 kb
Host smart-acc6eac0-425c-4855-a597-9720c1a4d61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31863
71905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3186371905
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2363832703
Short name T36
Test name
Test status
Simulation time 48079752 ps
CPU time 0.69 seconds
Started Jul 09 05:11:51 PM PDT 24
Finished Jul 09 05:11:53 PM PDT 24
Peak memory 206024 kb
Host smart-260cb89d-e183-4eea-8a49-0350123b3847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2363832703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2363832703
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2386903441
Short name T67
Test name
Test status
Simulation time 420315359 ps
CPU time 1.29 seconds
Started Jul 09 05:11:29 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206148 kb
Host smart-0889ac0d-dd10-46c0-8c39-c1f007b1b9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23869
03441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2386903441
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2187898616
Short name T92
Test name
Test status
Simulation time 9136582231 ps
CPU time 89.01 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206452 kb
Host smart-9580ef8c-f6aa-4a1e-9d43-d3ae25ae07b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21878
98616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2187898616
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3209106175
Short name T72
Test name
Test status
Simulation time 12371964593 ps
CPU time 113.88 seconds
Started Jul 09 05:11:40 PM PDT 24
Finished Jul 09 05:13:35 PM PDT 24
Peak memory 206260 kb
Host smart-e72517d9-d099-480c-8366-281cc5da36a7
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3209106175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3209106175
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3473560949
Short name T86
Test name
Test status
Simulation time 135733181 ps
CPU time 0.86 seconds
Started Jul 09 05:11:23 PM PDT 24
Finished Jul 09 05:11:27 PM PDT 24
Peak memory 206060 kb
Host smart-19cf6584-d352-4221-b745-4cd4629ad51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34735
60949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3473560949
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.312022497
Short name T2737
Test name
Test status
Simulation time 39602332 ps
CPU time 0.67 seconds
Started Jul 09 05:03:13 PM PDT 24
Finished Jul 09 05:03:15 PM PDT 24
Peak memory 205640 kb
Host smart-9bd926da-4de7-41b8-b25a-7162c170aa94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=312022497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.312022497
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2921649931
Short name T307
Test name
Test status
Simulation time 1504066503 ps
CPU time 6.03 seconds
Started Jul 09 05:03:30 PM PDT 24
Finished Jul 09 05:03:37 PM PDT 24
Peak memory 205884 kb
Host smart-ccb1cb9f-8586-465c-be74-778a05eef129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2921649931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2921649931
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4058893379
Short name T299
Test name
Test status
Simulation time 768639315 ps
CPU time 4.38 seconds
Started Jul 09 05:03:35 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 205876 kb
Host smart-1cae3807-9fb5-439a-8ef1-9584dde747ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4058893379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4058893379
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2357949720
Short name T301
Test name
Test status
Simulation time 381479375 ps
CPU time 2.73 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 205768 kb
Host smart-0ed54514-6f8f-4872-bb14-ce48d68c88e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2357949720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2357949720
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.744863138
Short name T1173
Test name
Test status
Simulation time 23386313278 ps
CPU time 24.84 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:12:21 PM PDT 24
Peak memory 206104 kb
Host smart-a2674cc6-3734-4e1a-8a39-8ebf438e2d2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=744863138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.744863138
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2659856760
Short name T150
Test name
Test status
Simulation time 5210716980 ps
CPU time 48.93 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206380 kb
Host smart-190f2b01-203b-469c-98fe-3bf476697003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26598
56760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2659856760
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.682188339
Short name T236
Test name
Test status
Simulation time 81408435 ps
CPU time 1.83 seconds
Started Jul 09 05:03:11 PM PDT 24
Finished Jul 09 05:03:13 PM PDT 24
Peak memory 221720 kb
Host smart-e483f21d-a72e-4ec2-919e-75644e648977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=682188339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.682188339
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2520215262
Short name T167
Test name
Test status
Simulation time 1413133730 ps
CPU time 3.01 seconds
Started Jul 09 05:11:41 PM PDT 24
Finished Jul 09 05:11:45 PM PDT 24
Peak memory 206260 kb
Host smart-a9518c09-41d3-45f2-872f-7e13f897493f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
15262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2520215262
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.888852122
Short name T625
Test name
Test status
Simulation time 144579262 ps
CPU time 0.79 seconds
Started Jul 09 05:11:36 PM PDT 24
Finished Jul 09 05:11:37 PM PDT 24
Peak memory 206164 kb
Host smart-7bb7f3e4-9c69-40bb-b9b0-d108a9523bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88885
2122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.888852122
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2410676153
Short name T1798
Test name
Test status
Simulation time 3671994269 ps
CPU time 4.24 seconds
Started Jul 09 05:14:31 PM PDT 24
Finished Jul 09 05:14:38 PM PDT 24
Peak memory 206156 kb
Host smart-728c11e0-1825-48b1-8e05-1b4caeaba2a0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2410676153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2410676153
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_device_address.241939856
Short name T93
Test name
Test status
Simulation time 13239999991 ps
CPU time 26 seconds
Started Jul 09 05:11:37 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 206348 kb
Host smart-03a4f422-e773-4401-b459-11d0c3ca82e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24193
9856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.241939856
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2327981817
Short name T378
Test name
Test status
Simulation time 401224419 ps
CPU time 2.48 seconds
Started Jul 09 05:13:40 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206140 kb
Host smart-cab2c809-ec13-4aad-ac6b-10c65d99ebd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23279
81817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2327981817
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.115434199
Short name T63
Test name
Test status
Simulation time 151813442 ps
CPU time 0.77 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:00 PM PDT 24
Peak memory 206128 kb
Host smart-e9a1f329-8ec7-4b3e-8a27-83f889554cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11543
4199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.115434199
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2993678661
Short name T46
Test name
Test status
Simulation time 16241015332 ps
CPU time 325.25 seconds
Started Jul 09 05:12:00 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206408 kb
Host smart-02a01b54-86c6-4217-bf7a-f1143fe830bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2993678661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2993678661
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3116196318
Short name T55
Test name
Test status
Simulation time 144397372 ps
CPU time 0.78 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:29 PM PDT 24
Peak memory 206048 kb
Host smart-41ef8506-6002-455f-b366-82aeb2c2035b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31161
96318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3116196318
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1674062240
Short name T65
Test name
Test status
Simulation time 4160890739 ps
CPU time 9.74 seconds
Started Jul 09 05:11:28 PM PDT 24
Finished Jul 09 05:11:40 PM PDT 24
Peak memory 206468 kb
Host smart-fb095d28-764f-4dea-b3b5-e62d19ebbad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
62240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1674062240
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1665694457
Short name T66
Test name
Test status
Simulation time 168284678 ps
CPU time 0.78 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:29 PM PDT 24
Peak memory 206116 kb
Host smart-42bc2391-1bdb-4eb2-bb20-9ca9aa17f791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16656
94457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1665694457
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.4212649904
Short name T53
Test name
Test status
Simulation time 252073359 ps
CPU time 1.07 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206092 kb
Host smart-29a91ad8-fcc4-4def-91ef-a797f1bc8e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42126
49904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.4212649904
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2894492562
Short name T73
Test name
Test status
Simulation time 218114804 ps
CPU time 0.9 seconds
Started Jul 09 05:11:44 PM PDT 24
Finished Jul 09 05:11:46 PM PDT 24
Peak memory 206128 kb
Host smart-94a2bf62-bd8b-40aa-b3d5-290457ee5426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28944
92562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2894492562
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2248282295
Short name T1457
Test name
Test status
Simulation time 48060174 ps
CPU time 0.69 seconds
Started Jul 09 05:13:54 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 206156 kb
Host smart-c01fdce5-efae-42d8-99ca-01e0a5607766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22482
82295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2248282295
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1031301180
Short name T49
Test name
Test status
Simulation time 189378522 ps
CPU time 0.79 seconds
Started Jul 09 05:11:57 PM PDT 24
Finished Jul 09 05:11:59 PM PDT 24
Peak memory 206056 kb
Host smart-0c7800f2-c2b7-4cf4-993b-64f77296b11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10313
01180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1031301180
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1754648392
Short name T2795
Test name
Test status
Simulation time 237797551 ps
CPU time 2.5 seconds
Started Jul 09 05:03:17 PM PDT 24
Finished Jul 09 05:03:21 PM PDT 24
Peak memory 221548 kb
Host smart-022a5fba-90b8-42bc-8284-2111bbe1d2e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1754648392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1754648392
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.3097656459
Short name T2265
Test name
Test status
Simulation time 8905468903 ps
CPU time 88.87 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206400 kb
Host smart-ec06b983-3706-45b5-9d8b-b45e0076ffa1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3097656459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.3097656459
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1815421603
Short name T2328
Test name
Test status
Simulation time 278199828 ps
CPU time 0.98 seconds
Started Jul 09 05:11:29 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206044 kb
Host smart-60e46450-534d-40d0-b487-b9910b134d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18154
21603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1815421603
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1181536238
Short name T126
Test name
Test status
Simulation time 229203309 ps
CPU time 0.91 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206120 kb
Host smart-fdfb9410-7807-4c52-a85e-93e8d730dd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11815
36238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1181536238
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3489773174
Short name T1725
Test name
Test status
Simulation time 13161856414 ps
CPU time 29.32 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:14:00 PM PDT 24
Peak memory 206412 kb
Host smart-cc665d10-079f-47ed-b438-6aa0cd42f5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
73174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3489773174
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2881139332
Short name T2223
Test name
Test status
Simulation time 227709501 ps
CPU time 0.88 seconds
Started Jul 09 05:13:53 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 205992 kb
Host smart-22cd7d23-e9b2-45c3-8956-0f514f64461e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
39332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2881139332
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2864949124
Short name T116
Test name
Test status
Simulation time 200002799 ps
CPU time 0.88 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:07 PM PDT 24
Peak memory 206016 kb
Host smart-2600d2f7-e73d-4a0b-a45f-a2222e1baea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28649
49124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2864949124
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4257571465
Short name T140
Test name
Test status
Simulation time 190254144 ps
CPU time 0.85 seconds
Started Jul 09 05:14:12 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206004 kb
Host smart-07cad1ea-21fa-406a-b7f9-09976c93e4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
71465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4257571465
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2788269422
Short name T2340
Test name
Test status
Simulation time 505327156 ps
CPU time 1.48 seconds
Started Jul 09 05:14:18 PM PDT 24
Finished Jul 09 05:14:22 PM PDT 24
Peak memory 206324 kb
Host smart-c2602b71-01b0-428e-8b6d-4952fb0fdc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27882
69422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2788269422
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1321973517
Short name T137
Test name
Test status
Simulation time 186298498 ps
CPU time 0.83 seconds
Started Jul 09 05:14:51 PM PDT 24
Finished Jul 09 05:14:56 PM PDT 24
Peak memory 206060 kb
Host smart-7d6b20c9-b9bc-4369-ba29-712f67fa02f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13219
73517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1321973517
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3538191035
Short name T130
Test name
Test status
Simulation time 210841576 ps
CPU time 0.91 seconds
Started Jul 09 05:15:20 PM PDT 24
Finished Jul 09 05:15:23 PM PDT 24
Peak memory 206144 kb
Host smart-fe97291f-2f73-49b8-bc93-3e4fe792b454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35381
91035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3538191035
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2325535982
Short name T127
Test name
Test status
Simulation time 215200701 ps
CPU time 0.86 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:15:36 PM PDT 24
Peak memory 206168 kb
Host smart-6e4d09cc-1493-4c0e-8bee-333cd71a2d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23255
35982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2325535982
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3650169915
Short name T121
Test name
Test status
Simulation time 219439204 ps
CPU time 0.88 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:38 PM PDT 24
Peak memory 206148 kb
Host smart-e4ca946f-2a43-4c2b-92fa-f12d271f88e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
69915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3650169915
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2191422678
Short name T133
Test name
Test status
Simulation time 208359565 ps
CPU time 0.91 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206144 kb
Host smart-cb59fcb2-2397-4cf7-8481-2240f4d2c8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
22678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2191422678
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2631683637
Short name T241
Test name
Test status
Simulation time 161632665 ps
CPU time 2.15 seconds
Started Jul 09 05:03:10 PM PDT 24
Finished Jul 09 05:03:13 PM PDT 24
Peak memory 205860 kb
Host smart-a6530791-1a5b-4f32-9507-f44b12a989e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2631683637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2631683637
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.824691256
Short name T198
Test name
Test status
Simulation time 847252349 ps
CPU time 5.12 seconds
Started Jul 09 05:03:12 PM PDT 24
Finished Jul 09 05:03:17 PM PDT 24
Peak memory 205868 kb
Host smart-a4d0712a-d605-4f65-9aee-ec80139c845d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=824691256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.824691256
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4136106425
Short name T2808
Test name
Test status
Simulation time 99943441 ps
CPU time 0.86 seconds
Started Jul 09 05:03:13 PM PDT 24
Finished Jul 09 05:03:15 PM PDT 24
Peak memory 205760 kb
Host smart-38101cae-7195-4be4-aa22-b3666a6ab134
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4136106425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.4136106425
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2704651339
Short name T244
Test name
Test status
Simulation time 91013990 ps
CPU time 2.14 seconds
Started Jul 09 05:03:17 PM PDT 24
Finished Jul 09 05:03:20 PM PDT 24
Peak memory 214152 kb
Host smart-3aa8ec80-2c19-490c-b333-af2c6ecbcb3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704651339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2704651339
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2773091277
Short name T268
Test name
Test status
Simulation time 39200754 ps
CPU time 0.83 seconds
Started Jul 09 05:03:14 PM PDT 24
Finished Jul 09 05:03:15 PM PDT 24
Peak memory 205696 kb
Host smart-6917094b-5a53-46b3-827b-cbb0aab1d39a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2773091277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2773091277
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3951896989
Short name T254
Test name
Test status
Simulation time 87441796 ps
CPU time 2.25 seconds
Started Jul 09 05:03:11 PM PDT 24
Finished Jul 09 05:03:14 PM PDT 24
Peak memory 222208 kb
Host smart-c52b807f-8f7d-4dcb-b71e-ce98afa4fe6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3951896989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3951896989
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1786184554
Short name T2771
Test name
Test status
Simulation time 287348897 ps
CPU time 2.48 seconds
Started Jul 09 05:03:11 PM PDT 24
Finished Jul 09 05:03:15 PM PDT 24
Peak memory 205924 kb
Host smart-553b9051-7bf5-4193-a52b-fcb4239aa123
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1786184554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1786184554
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2024719242
Short name T199
Test name
Test status
Simulation time 176323353 ps
CPU time 1.75 seconds
Started Jul 09 05:03:14 PM PDT 24
Finished Jul 09 05:03:16 PM PDT 24
Peak memory 205820 kb
Host smart-15c56223-f3ea-4497-936a-f9a822251169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2024719242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2024719242
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2879316022
Short name T2789
Test name
Test status
Simulation time 350383604 ps
CPU time 2.68 seconds
Started Jul 09 05:03:13 PM PDT 24
Finished Jul 09 05:03:17 PM PDT 24
Peak memory 205916 kb
Host smart-b3859755-16d6-4c59-a678-3e75291d8cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2879316022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2879316022
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1575878484
Short name T260
Test name
Test status
Simulation time 211426437 ps
CPU time 2.16 seconds
Started Jul 09 05:03:15 PM PDT 24
Finished Jul 09 05:03:18 PM PDT 24
Peak memory 205888 kb
Host smart-53ff73af-b015-41ce-8e81-ec0a9fdeccad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1575878484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1575878484
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1941276078
Short name T2735
Test name
Test status
Simulation time 613440759 ps
CPU time 5.54 seconds
Started Jul 09 05:03:15 PM PDT 24
Finished Jul 09 05:03:21 PM PDT 24
Peak memory 205804 kb
Host smart-f8dd940c-ec75-45b8-90cd-f0cdf6c9c812
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1941276078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1941276078
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.882488493
Short name T2728
Test name
Test status
Simulation time 111668869 ps
CPU time 0.85 seconds
Started Jul 09 05:03:15 PM PDT 24
Finished Jul 09 05:03:17 PM PDT 24
Peak memory 205620 kb
Host smart-e5bbc3e9-388e-403a-a7f0-29d94507d393
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=882488493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.882488493
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3948694609
Short name T2749
Test name
Test status
Simulation time 202997940 ps
CPU time 1.34 seconds
Started Jul 09 05:03:17 PM PDT 24
Finished Jul 09 05:03:19 PM PDT 24
Peak memory 215756 kb
Host smart-15d05bb8-0e5d-4862-bc2d-4b5a5f3637ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948694609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3948694609
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2699718566
Short name T2800
Test name
Test status
Simulation time 51293652 ps
CPU time 0.78 seconds
Started Jul 09 05:03:15 PM PDT 24
Finished Jul 09 05:03:17 PM PDT 24
Peak memory 205648 kb
Host smart-5a45ff7e-2c25-4272-8b84-7cbb283a3e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2699718566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2699718566
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.711894243
Short name T291
Test name
Test status
Simulation time 108933027 ps
CPU time 0.77 seconds
Started Jul 09 05:03:17 PM PDT 24
Finished Jul 09 05:03:19 PM PDT 24
Peak memory 205612 kb
Host smart-d714c349-d047-4410-b731-e3d604018fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=711894243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.711894243
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3250058331
Short name T255
Test name
Test status
Simulation time 166662348 ps
CPU time 2.36 seconds
Started Jul 09 05:03:15 PM PDT 24
Finished Jul 09 05:03:18 PM PDT 24
Peak memory 215180 kb
Host smart-8d29318d-4b14-404e-ab9d-eb8cbb9be69d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3250058331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3250058331
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.431219803
Short name T2714
Test name
Test status
Simulation time 169426827 ps
CPU time 3.98 seconds
Started Jul 09 05:03:16 PM PDT 24
Finished Jul 09 05:03:21 PM PDT 24
Peak memory 205804 kb
Host smart-a4ce06be-e4dd-48f8-8ce7-e63c2006082d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=431219803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.431219803
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.356887524
Short name T279
Test name
Test status
Simulation time 194277221 ps
CPU time 1.67 seconds
Started Jul 09 05:03:18 PM PDT 24
Finished Jul 09 05:03:20 PM PDT 24
Peak memory 205816 kb
Host smart-15f741c7-1b06-4fbd-ac8e-e8339cd7ee52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=356887524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.356887524
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1332975625
Short name T2781
Test name
Test status
Simulation time 789486589 ps
CPU time 4.93 seconds
Started Jul 09 05:03:17 PM PDT 24
Finished Jul 09 05:03:22 PM PDT 24
Peak memory 205836 kb
Host smart-df284ce6-0abb-4790-bd3d-3ad73876d07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1332975625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1332975625
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2070079347
Short name T2756
Test name
Test status
Simulation time 105492195 ps
CPU time 1.45 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 214028 kb
Host smart-57f0acec-b95e-4ae4-8393-a95c80450fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070079347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2070079347
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3587735458
Short name T266
Test name
Test status
Simulation time 100459962 ps
CPU time 0.9 seconds
Started Jul 09 05:03:34 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 205776 kb
Host smart-618d61e8-2ec7-43ce-a603-683b78379d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3587735458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3587735458
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1750016996
Short name T297
Test name
Test status
Simulation time 50690057 ps
CPU time 0.66 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:38 PM PDT 24
Peak memory 205676 kb
Host smart-189bf83d-53f1-44d2-a83e-86126daafd88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1750016996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1750016996
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1766503930
Short name T272
Test name
Test status
Simulation time 86381780 ps
CPU time 1.18 seconds
Started Jul 09 05:03:31 PM PDT 24
Finished Jul 09 05:03:32 PM PDT 24
Peak memory 205804 kb
Host smart-2ae9c579-6244-4a1b-b248-3905f745be2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1766503930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1766503930
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3655499418
Short name T234
Test name
Test status
Simulation time 82906145 ps
CPU time 2.21 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 214116 kb
Host smart-43155164-2871-4dec-8014-11a395eddb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3655499418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3655499418
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2858402654
Short name T311
Test name
Test status
Simulation time 249030744 ps
CPU time 2.51 seconds
Started Jul 09 05:03:32 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 205968 kb
Host smart-ed1b54a0-6808-4c0f-a922-b989ec58c30a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2858402654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2858402654
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.238808109
Short name T237
Test name
Test status
Simulation time 100576631 ps
CPU time 1.3 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 214080 kb
Host smart-105fc7bd-aefb-4da8-b454-51059b3a2c10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238808109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.238808109
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1436660784
Short name T2729
Test name
Test status
Simulation time 59865608 ps
CPU time 0.99 seconds
Started Jul 09 05:03:32 PM PDT 24
Finished Jul 09 05:03:33 PM PDT 24
Peak memory 205932 kb
Host smart-a1d9bb49-3347-4413-8f0b-f35dd5c2c147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1436660784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1436660784
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2034971266
Short name T296
Test name
Test status
Simulation time 41372803 ps
CPU time 0.71 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205636 kb
Host smart-26171006-674d-47b6-b824-0726f4cc8bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034971266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2034971266
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3277910730
Short name T2766
Test name
Test status
Simulation time 168266091 ps
CPU time 1.53 seconds
Started Jul 09 05:03:33 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 206288 kb
Host smart-8d448ea7-8e47-4087-98cc-3b5e405d1837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3277910730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3277910730
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.746870993
Short name T2765
Test name
Test status
Simulation time 142828844 ps
CPU time 1.81 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 221500 kb
Host smart-fd688318-0952-41a8-b2ea-e5763d7ad883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=746870993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.746870993
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3076105226
Short name T2772
Test name
Test status
Simulation time 453139511 ps
CPU time 3.09 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205840 kb
Host smart-20a7f48d-03df-4126-8619-be047f356f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3076105226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3076105226
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.888501810
Short name T2802
Test name
Test status
Simulation time 196602879 ps
CPU time 1.9 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 214072 kb
Host smart-723959c3-80da-40fd-9c06-2bf7b325bc9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888501810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.888501810
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3546817026
Short name T2726
Test name
Test status
Simulation time 91481793 ps
CPU time 1.13 seconds
Started Jul 09 05:03:31 PM PDT 24
Finished Jul 09 05:03:33 PM PDT 24
Peak memory 205880 kb
Host smart-e85a51eb-1ce3-4f11-b314-dbc5a799f194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3546817026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3546817026
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.385197274
Short name T274
Test name
Test status
Simulation time 119305696 ps
CPU time 1.19 seconds
Started Jul 09 05:03:31 PM PDT 24
Finished Jul 09 05:03:33 PM PDT 24
Peak memory 205844 kb
Host smart-c88e65e0-27ea-4adc-bed2-5fc6070ddb50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=385197274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.385197274
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1561047057
Short name T2807
Test name
Test status
Simulation time 239007887 ps
CPU time 3.17 seconds
Started Jul 09 05:03:33 PM PDT 24
Finished Jul 09 05:03:36 PM PDT 24
Peak memory 221820 kb
Host smart-c2cc18ba-f4e1-4038-8cfe-066acff0e105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561047057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1561047057
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.6861211
Short name T2778
Test name
Test status
Simulation time 174194813 ps
CPU time 1.97 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 214500 kb
Host smart-60b28b9d-532e-4734-9fac-05b879503475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6861211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us
bdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_
csr_mem_rw_with_rand_reset.6861211
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2789497545
Short name T265
Test name
Test status
Simulation time 73270412 ps
CPU time 0.98 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:39 PM PDT 24
Peak memory 205868 kb
Host smart-ce6dc342-8c16-4b3e-b940-862df12566ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2789497545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2789497545
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1316378027
Short name T2758
Test name
Test status
Simulation time 36635855 ps
CPU time 0.71 seconds
Started Jul 09 05:03:35 PM PDT 24
Finished Jul 09 05:03:36 PM PDT 24
Peak memory 205620 kb
Host smart-71a1f49d-803e-4f84-8c95-6ec765b39056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1316378027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1316378027
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3964326664
Short name T2722
Test name
Test status
Simulation time 87665339 ps
CPU time 1.62 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 205844 kb
Host smart-f8323b93-cb17-4ac2-95f5-336cd14a007b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3964326664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3964326664
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1931317928
Short name T2783
Test name
Test status
Simulation time 56204645 ps
CPU time 1.46 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 221788 kb
Host smart-86de39cf-b582-49f1-b0f2-b270fd66500b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1931317928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1931317928
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3680731052
Short name T194
Test name
Test status
Simulation time 84454884 ps
CPU time 1.41 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 214040 kb
Host smart-9cffa433-68dd-4a33-8c54-9e08f157e15a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680731052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3680731052
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2839297573
Short name T256
Test name
Test status
Simulation time 47713962 ps
CPU time 0.96 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205768 kb
Host smart-4db78084-8588-4281-a750-9251d483b691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2839297573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2839297573
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.899822595
Short name T2798
Test name
Test status
Simulation time 70823159 ps
CPU time 0.77 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:38 PM PDT 24
Peak memory 205692 kb
Host smart-16c9ffdb-b7f9-46f1-9801-ebdbdd5b5dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=899822595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.899822595
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.220813661
Short name T273
Test name
Test status
Simulation time 135373178 ps
CPU time 1.23 seconds
Started Jul 09 05:03:35 PM PDT 24
Finished Jul 09 05:03:37 PM PDT 24
Peak memory 205900 kb
Host smart-5be2c4fc-b8a8-489e-9f19-d31812e280d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=220813661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.220813661
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.202294711
Short name T2717
Test name
Test status
Simulation time 70978530 ps
CPU time 1.49 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 221360 kb
Host smart-9497b984-c090-4c5b-bfe5-11349d28d85e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=202294711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.202294711
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3436550767
Short name T2741
Test name
Test status
Simulation time 73246855 ps
CPU time 1.67 seconds
Started Jul 09 05:03:36 PM PDT 24
Finished Jul 09 05:03:38 PM PDT 24
Peak memory 214100 kb
Host smart-ce5342be-ae98-42a8-a16e-10a9e8839617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436550767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3436550767
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3210048488
Short name T257
Test name
Test status
Simulation time 89341770 ps
CPU time 1.01 seconds
Started Jul 09 05:03:34 PM PDT 24
Finished Jul 09 05:03:36 PM PDT 24
Peak memory 205836 kb
Host smart-68b3cfab-7efc-4ed4-bfb5-bb9d74ca7ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3210048488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3210048488
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.324305576
Short name T2760
Test name
Test status
Simulation time 52916195 ps
CPU time 0.71 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 205652 kb
Host smart-a4bbd69d-bf6f-4d4f-9cb3-10100bcec192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=324305576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.324305576
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4165592578
Short name T275
Test name
Test status
Simulation time 113478941 ps
CPU time 1.17 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 205828 kb
Host smart-baa6ea5e-e95a-42ad-ae91-a023afde7f0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4165592578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4165592578
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2477791311
Short name T229
Test name
Test status
Simulation time 335580663 ps
CPU time 3.43 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 221564 kb
Host smart-9b65afc3-71b7-4b83-939a-3f1139187371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2477791311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2477791311
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2546374142
Short name T232
Test name
Test status
Simulation time 127117913 ps
CPU time 1.52 seconds
Started Jul 09 05:03:36 PM PDT 24
Finished Jul 09 05:03:38 PM PDT 24
Peak memory 214064 kb
Host smart-7fe45df8-f2cf-4fb6-8e09-eb4baf920d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546374142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2546374142
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2743937899
Short name T2790
Test name
Test status
Simulation time 125738696 ps
CPU time 0.93 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:39 PM PDT 24
Peak memory 205632 kb
Host smart-76111a7f-8304-485a-b0b8-7ab57881d439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2743937899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2743937899
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2498292735
Short name T2721
Test name
Test status
Simulation time 66677118 ps
CPU time 0.76 seconds
Started Jul 09 05:03:35 PM PDT 24
Finished Jul 09 05:03:37 PM PDT 24
Peak memory 205636 kb
Host smart-e355c1f6-56d7-4faa-8925-78da51e7edb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2498292735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2498292735
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2436968246
Short name T2750
Test name
Test status
Simulation time 74053579 ps
CPU time 1.03 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205836 kb
Host smart-888ce0bd-e24f-4610-b421-cdfa0ee652a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2436968246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2436968246
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3841819290
Short name T233
Test name
Test status
Simulation time 286436819 ps
CPU time 3.23 seconds
Started Jul 09 05:03:36 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 221472 kb
Host smart-08d4581c-e2fe-42b9-86a3-616c73b46267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3841819290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3841819290
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1848324564
Short name T305
Test name
Test status
Simulation time 985834098 ps
CPU time 5.16 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205888 kb
Host smart-b583664b-d16b-45ba-8a7e-4f6414d67bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1848324564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1848324564
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2007131040
Short name T2787
Test name
Test status
Simulation time 70807959 ps
CPU time 1.34 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 214004 kb
Host smart-ee1b6c83-b061-4033-8fd0-e2b1d5d9bac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007131040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2007131040
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2941385046
Short name T2733
Test name
Test status
Simulation time 123700423 ps
CPU time 1.09 seconds
Started Jul 09 05:03:41 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205856 kb
Host smart-6212844a-d004-4869-a483-b48dc2ea8658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2941385046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2941385046
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2239843455
Short name T2780
Test name
Test status
Simulation time 75286207 ps
CPU time 0.73 seconds
Started Jul 09 05:03:44 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 205692 kb
Host smart-f5c1da84-c738-491a-81e8-07e515b539e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2239843455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2239843455
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1332059489
Short name T278
Test name
Test status
Simulation time 221543495 ps
CPU time 1.73 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205832 kb
Host smart-745097e2-bd2f-45e1-87bb-f6487909a927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1332059489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1332059489
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1787435900
Short name T2805
Test name
Test status
Simulation time 106090839 ps
CPU time 3.07 seconds
Started Jul 09 05:03:41 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 222120 kb
Host smart-d743223c-2755-43d6-ab19-a594c9629d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1787435900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1787435900
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2713286262
Short name T308
Test name
Test status
Simulation time 807128801 ps
CPU time 5.36 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 205820 kb
Host smart-15d64b7e-3f2a-48b8-aebd-770d914e55fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2713286262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2713286262
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2335393385
Short name T2740
Test name
Test status
Simulation time 73637857 ps
CPU time 1.67 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 214080 kb
Host smart-43b66ecd-b9ac-40e9-ba1d-031a647935e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335393385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2335393385
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2667699922
Short name T2809
Test name
Test status
Simulation time 90585686 ps
CPU time 1.01 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205828 kb
Host smart-44274a34-c38a-40d7-bc1b-ffb9b1c402df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2667699922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2667699922
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3552294969
Short name T288
Test name
Test status
Simulation time 42244108 ps
CPU time 0.71 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 205688 kb
Host smart-cc945e9b-cdad-4e29-bbd9-3976236a431a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3552294969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3552294969
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2290350958
Short name T2730
Test name
Test status
Simulation time 168679098 ps
CPU time 1.64 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205896 kb
Host smart-06fd891d-8cde-48b8-86b9-aac188ce27fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2290350958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2290350958
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1688526274
Short name T2757
Test name
Test status
Simulation time 241620369 ps
CPU time 2.55 seconds
Started Jul 09 05:03:41 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 222312 kb
Host smart-0f1fb6d9-ee67-43f2-ac7b-9817b771acaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1688526274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1688526274
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1529351681
Short name T245
Test name
Test status
Simulation time 849336105 ps
CPU time 4.89 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205804 kb
Host smart-630bfc75-bd6d-4f75-a759-22b774582c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1529351681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1529351681
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3402585983
Short name T2747
Test name
Test status
Simulation time 157617323 ps
CPU time 1.49 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:48 PM PDT 24
Peak memory 214096 kb
Host smart-2997fc80-2473-4ec1-8e53-e63275fec8a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402585983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3402585983
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.129721877
Short name T2782
Test name
Test status
Simulation time 41232709 ps
CPU time 0.69 seconds
Started Jul 09 05:03:46 PM PDT 24
Finished Jul 09 05:03:48 PM PDT 24
Peak memory 205612 kb
Host smart-bc14bcda-b072-4cba-86ec-52060d10f102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=129721877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.129721877
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1705394744
Short name T2762
Test name
Test status
Simulation time 136086228 ps
CPU time 1.5 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205868 kb
Host smart-f355d0d2-0308-4c61-a58b-21d5519bcc73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1705394744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1705394744
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2024394689
Short name T2793
Test name
Test status
Simulation time 284115887 ps
CPU time 3.56 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 221720 kb
Host smart-3151fa30-423d-4e6b-9e67-8da64d4f2f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2024394689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2024394689
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1020196957
Short name T264
Test name
Test status
Simulation time 419053974 ps
CPU time 3.74 seconds
Started Jul 09 05:03:21 PM PDT 24
Finished Jul 09 05:03:25 PM PDT 24
Peak memory 205924 kb
Host smart-8ccf761f-c4c3-408e-aa80-3a13bc062652
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1020196957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1020196957
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2954481718
Short name T2715
Test name
Test status
Simulation time 737280040 ps
CPU time 4.6 seconds
Started Jul 09 05:03:21 PM PDT 24
Finished Jul 09 05:03:26 PM PDT 24
Peak memory 205848 kb
Host smart-86fd8ab6-5720-4801-8f62-72399c244ab4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2954481718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2954481718
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.229336732
Short name T2761
Test name
Test status
Simulation time 222868181 ps
CPU time 1.06 seconds
Started Jul 09 05:03:21 PM PDT 24
Finished Jul 09 05:03:22 PM PDT 24
Peak memory 205648 kb
Host smart-78a12264-689d-4e83-9bd9-2131492df16a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=229336732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.229336732
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1327029368
Short name T230
Test name
Test status
Simulation time 88956426 ps
CPU time 1.78 seconds
Started Jul 09 05:03:19 PM PDT 24
Finished Jul 09 05:03:21 PM PDT 24
Peak memory 214076 kb
Host smart-eb0d2d0d-9110-4ab2-b588-c75db9ee75ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327029368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1327029368
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2127593293
Short name T261
Test name
Test status
Simulation time 54155980 ps
CPU time 0.85 seconds
Started Jul 09 05:03:21 PM PDT 24
Finished Jul 09 05:03:23 PM PDT 24
Peak memory 205680 kb
Host smart-605149b5-7295-4426-8b1f-9c39d39b1ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2127593293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2127593293
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2501353150
Short name T293
Test name
Test status
Simulation time 56115535 ps
CPU time 0.66 seconds
Started Jul 09 05:03:16 PM PDT 24
Finished Jul 09 05:03:17 PM PDT 24
Peak memory 205604 kb
Host smart-174c0ec0-ab7d-444e-8473-ffb7b580d99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2501353150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2501353150
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4293020078
Short name T270
Test name
Test status
Simulation time 120699353 ps
CPU time 1.54 seconds
Started Jul 09 05:03:22 PM PDT 24
Finished Jul 09 05:03:24 PM PDT 24
Peak memory 213980 kb
Host smart-a1ae5960-9b68-48df-b71d-6c052daaa341
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4293020078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4293020078
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2874382278
Short name T2779
Test name
Test status
Simulation time 153950494 ps
CPU time 2.37 seconds
Started Jul 09 05:03:19 PM PDT 24
Finished Jul 09 05:03:22 PM PDT 24
Peak memory 205812 kb
Host smart-5c7aaaea-7b63-4f24-a73e-d463f72eede7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2874382278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2874382278
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2245205937
Short name T2791
Test name
Test status
Simulation time 138675466 ps
CPU time 1.07 seconds
Started Jul 09 05:03:17 PM PDT 24
Finished Jul 09 05:03:19 PM PDT 24
Peak memory 205828 kb
Host smart-9fffe4e3-368a-4aaa-9499-a8f1c9f27930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2245205937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2245205937
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.143187439
Short name T309
Test name
Test status
Simulation time 267489911 ps
CPU time 2.45 seconds
Started Jul 09 05:03:16 PM PDT 24
Finished Jul 09 05:03:20 PM PDT 24
Peak memory 205860 kb
Host smart-19fe8c90-e463-4f1c-82c5-b5e897097eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=143187439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.143187439
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3987980891
Short name T2803
Test name
Test status
Simulation time 61027665 ps
CPU time 0.73 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205620 kb
Host smart-6f5edd38-7e93-40bd-b213-261feb74dd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987980891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3987980891
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.515890010
Short name T298
Test name
Test status
Simulation time 48405666 ps
CPU time 0.78 seconds
Started Jul 09 05:03:41 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205648 kb
Host smart-831ed389-9e9d-47d8-ac49-6223fe65e74b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=515890010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.515890010
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.24810122
Short name T2776
Test name
Test status
Simulation time 54872691 ps
CPU time 0.78 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 205708 kb
Host smart-8703b8df-e1f8-4ef8-87f7-43305cfb45f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=24810122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.24810122
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.724841445
Short name T295
Test name
Test status
Simulation time 35530369 ps
CPU time 0.68 seconds
Started Jul 09 05:03:46 PM PDT 24
Finished Jul 09 05:03:47 PM PDT 24
Peak memory 205612 kb
Host smart-8ca4d383-39b7-4fc9-834a-2efa45ad46f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=724841445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.724841445
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1118283030
Short name T2797
Test name
Test status
Simulation time 50457088 ps
CPU time 0.7 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205636 kb
Host smart-122a501b-ca61-430f-b936-38e66bb5ebe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118283030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1118283030
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.388837190
Short name T282
Test name
Test status
Simulation time 44270444 ps
CPU time 0.7 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:40 PM PDT 24
Peak memory 205628 kb
Host smart-879a1cae-26d1-4a1f-8235-f501fa52a82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=388837190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.388837190
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.246893602
Short name T2725
Test name
Test status
Simulation time 48025502 ps
CPU time 0.71 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205704 kb
Host smart-d6168cb4-1182-4547-958a-247fbd9aa1eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=246893602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.246893602
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3303649458
Short name T2786
Test name
Test status
Simulation time 34644553 ps
CPU time 0.72 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 206032 kb
Host smart-3caf9d9f-843c-438e-a1d2-c2476a51ba29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3303649458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3303649458
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2089267567
Short name T2759
Test name
Test status
Simulation time 187939486 ps
CPU time 2.25 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:27 PM PDT 24
Peak memory 205772 kb
Host smart-1754fa06-6c6e-445d-a42c-0311b1e3fd29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2089267567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2089267567
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1736804927
Short name T2748
Test name
Test status
Simulation time 1048006424 ps
CPU time 5.57 seconds
Started Jul 09 05:03:23 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 205824 kb
Host smart-305b1b85-7313-4a87-b0c1-9f5e6e42092b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1736804927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1736804927
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.708459018
Short name T2720
Test name
Test status
Simulation time 128947918 ps
CPU time 1.01 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 205684 kb
Host smart-b6137fa4-476b-4165-9a93-c88da929141d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=708459018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.708459018
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2802941846
Short name T2727
Test name
Test status
Simulation time 187142243 ps
CPU time 2.02 seconds
Started Jul 09 05:03:22 PM PDT 24
Finished Jul 09 05:03:24 PM PDT 24
Peak memory 214068 kb
Host smart-93fadb1f-af17-4f7c-974a-79bfd107a02c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802941846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2802941846
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2459585805
Short name T2784
Test name
Test status
Simulation time 46241098 ps
CPU time 0.9 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 205860 kb
Host smart-878bab59-2355-4343-a0c5-37b642653ac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2459585805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2459585805
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.772695077
Short name T2774
Test name
Test status
Simulation time 58893039 ps
CPU time 0.72 seconds
Started Jul 09 05:03:25 PM PDT 24
Finished Jul 09 05:03:26 PM PDT 24
Peak memory 205636 kb
Host smart-2c667f1b-082e-49e6-9892-df5e005eba40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=772695077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.772695077
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2425355717
Short name T262
Test name
Test status
Simulation time 97550530 ps
CPU time 1.46 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 214000 kb
Host smart-9436688b-c26e-4806-9589-261ddc5e3a4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2425355717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2425355717
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3664984951
Short name T2724
Test name
Test status
Simulation time 476285748 ps
CPU time 4.64 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 205836 kb
Host smart-83533b93-11c4-45bf-acba-26494322884a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3664984951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3664984951
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.601923182
Short name T2767
Test name
Test status
Simulation time 96916350 ps
CPU time 1.05 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:26 PM PDT 24
Peak memory 205824 kb
Host smart-8144af58-452e-4306-aa6a-52e247bb4033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=601923182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.601923182
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2986063266
Short name T2734
Test name
Test status
Simulation time 227579297 ps
CPU time 3.03 seconds
Started Jul 09 05:03:20 PM PDT 24
Finished Jul 09 05:03:24 PM PDT 24
Peak memory 214140 kb
Host smart-b91a9068-2de4-4633-bc8c-fa407ccec226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2986063266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2986063266
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1270194425
Short name T2785
Test name
Test status
Simulation time 57891869 ps
CPU time 0.69 seconds
Started Jul 09 05:03:41 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205728 kb
Host smart-0b58ab28-ec5a-4ceb-a09d-5c3811bcfb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1270194425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1270194425
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2031214022
Short name T2764
Test name
Test status
Simulation time 61496112 ps
CPU time 0.71 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205612 kb
Host smart-7ee8af9b-a3b1-4a96-824f-6ef7595d5717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2031214022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2031214022
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3090600137
Short name T2792
Test name
Test status
Simulation time 71933725 ps
CPU time 0.7 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 205652 kb
Host smart-8409f582-8c66-4075-bf1f-76ce678495e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3090600137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3090600137
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2155607841
Short name T2753
Test name
Test status
Simulation time 46828265 ps
CPU time 0.67 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205612 kb
Host smart-4f708b1e-ef71-4134-8d4c-09e4856760f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2155607841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2155607841
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1516054697
Short name T2755
Test name
Test status
Simulation time 63346371 ps
CPU time 0.68 seconds
Started Jul 09 05:03:46 PM PDT 24
Finished Jul 09 05:03:47 PM PDT 24
Peak memory 205636 kb
Host smart-adfd329b-d37d-476b-bae1-ef7887970dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1516054697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1516054697
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1905116847
Short name T283
Test name
Test status
Simulation time 59043133 ps
CPU time 0.72 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205740 kb
Host smart-7e3329ae-300d-46a1-80fc-63668a6bd845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1905116847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1905116847
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1474200290
Short name T203
Test name
Test status
Simulation time 70460936 ps
CPU time 0.69 seconds
Started Jul 09 05:03:42 PM PDT 24
Finished Jul 09 05:03:44 PM PDT 24
Peak memory 205728 kb
Host smart-048d3728-26f6-4137-b95c-73d8c568f880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1474200290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1474200290
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.656997426
Short name T2788
Test name
Test status
Simulation time 56542647 ps
CPU time 0.78 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205628 kb
Host smart-da8896ab-ae12-4b9a-a202-96ab073999be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=656997426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.656997426
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2921393513
Short name T2768
Test name
Test status
Simulation time 61527377 ps
CPU time 0.72 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 205700 kb
Host smart-87520bdf-77c1-408f-a444-5e9f8e702a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2921393513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2921393513
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2963200590
Short name T2801
Test name
Test status
Simulation time 41439399 ps
CPU time 0.65 seconds
Started Jul 09 05:03:44 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 205692 kb
Host smart-94e82efe-0ea9-492f-ae35-51316b7b4dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2963200590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2963200590
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3002525424
Short name T2743
Test name
Test status
Simulation time 190126586 ps
CPU time 2.23 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 205860 kb
Host smart-5c178c0b-f4b5-4ce6-b8c4-06647056f269
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3002525424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3002525424
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.590187302
Short name T2723
Test name
Test status
Simulation time 2215238264 ps
CPU time 13.61 seconds
Started Jul 09 05:03:29 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205892 kb
Host smart-2f8f17ac-cad2-44f0-b17a-5e382f51395c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=590187302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.590187302
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3408887199
Short name T2769
Test name
Test status
Simulation time 48313535 ps
CPU time 0.78 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:25 PM PDT 24
Peak memory 205696 kb
Host smart-a4ecbcc3-b965-4246-af3b-4fe78b983c85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3408887199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3408887199
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1835888571
Short name T2744
Test name
Test status
Simulation time 151415026 ps
CPU time 1.8 seconds
Started Jul 09 05:03:28 PM PDT 24
Finished Jul 09 05:03:30 PM PDT 24
Peak memory 214036 kb
Host smart-ee011277-ba3d-4c34-a415-266deac6e37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835888571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1835888571
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3330510699
Short name T2799
Test name
Test status
Simulation time 78183127 ps
CPU time 0.9 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:25 PM PDT 24
Peak memory 205692 kb
Host smart-df842337-935b-4da6-8c26-f4424205327d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3330510699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3330510699
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1669002722
Short name T2738
Test name
Test status
Simulation time 41696808 ps
CPU time 0.68 seconds
Started Jul 09 05:03:25 PM PDT 24
Finished Jul 09 05:03:26 PM PDT 24
Peak memory 205712 kb
Host smart-8ae16f26-45de-4096-83ca-7b3518e587cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1669002722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1669002722
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3416209344
Short name T269
Test name
Test status
Simulation time 203567399 ps
CPU time 2.8 seconds
Started Jul 09 05:03:22 PM PDT 24
Finished Jul 09 05:03:25 PM PDT 24
Peak memory 214104 kb
Host smart-d386d33f-e04b-4bf3-8275-7c0491566231
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3416209344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3416209344
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.504729272
Short name T2731
Test name
Test status
Simulation time 257873501 ps
CPU time 2.91 seconds
Started Jul 09 05:03:23 PM PDT 24
Finished Jul 09 05:03:26 PM PDT 24
Peak memory 205824 kb
Host smart-1a8803ea-d6b5-4d97-b3d6-78da4ce332ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=504729272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.504729272
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2937750881
Short name T271
Test name
Test status
Simulation time 124852413 ps
CPU time 1.29 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:26 PM PDT 24
Peak memory 205908 kb
Host smart-2a6ce84f-19b4-4dbb-8645-6feb7c65ad9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2937750881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2937750881
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4219812618
Short name T222
Test name
Test status
Simulation time 199276975 ps
CPU time 2.3 seconds
Started Jul 09 05:03:24 PM PDT 24
Finished Jul 09 05:03:27 PM PDT 24
Peak memory 221416 kb
Host smart-91339c63-85b3-4849-84a3-92f7a3d524f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4219812618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.4219812618
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2500269692
Short name T227
Test name
Test status
Simulation time 262722783 ps
CPU time 2.45 seconds
Started Jul 09 05:03:25 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 205804 kb
Host smart-99a3ef9e-bca3-4ef0-a213-a010f68a7918
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2500269692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2500269692
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3983090986
Short name T2804
Test name
Test status
Simulation time 34321046 ps
CPU time 0.69 seconds
Started Jul 09 05:03:40 PM PDT 24
Finished Jul 09 05:03:43 PM PDT 24
Peak memory 205672 kb
Host smart-19c33def-a902-45f1-9dbc-dad527385223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3983090986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3983090986
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1334380190
Short name T284
Test name
Test status
Simulation time 33167230 ps
CPU time 0.71 seconds
Started Jul 09 05:03:39 PM PDT 24
Finished Jul 09 05:03:42 PM PDT 24
Peak memory 206000 kb
Host smart-f20e75de-3144-4f25-afb7-b10241d4d73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334380190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1334380190
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4124814767
Short name T289
Test name
Test status
Simulation time 76070071 ps
CPU time 0.74 seconds
Started Jul 09 05:03:46 PM PDT 24
Finished Jul 09 05:03:47 PM PDT 24
Peak memory 205640 kb
Host smart-f76a6c8a-ed81-4b01-9837-2297c4e0dc0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4124814767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4124814767
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3181123102
Short name T2777
Test name
Test status
Simulation time 38196019 ps
CPU time 0.66 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:52 PM PDT 24
Peak memory 205672 kb
Host smart-ec6e95f0-27c7-4946-8413-2b39060ef85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3181123102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3181123102
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.284891809
Short name T2796
Test name
Test status
Simulation time 33000262 ps
CPU time 0.69 seconds
Started Jul 09 05:03:44 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 205612 kb
Host smart-4597e98b-dd31-4777-8f15-5ac24a0b6134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=284891809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.284891809
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3776660501
Short name T2773
Test name
Test status
Simulation time 40599707 ps
CPU time 0.67 seconds
Started Jul 09 05:03:43 PM PDT 24
Finished Jul 09 05:03:45 PM PDT 24
Peak memory 205596 kb
Host smart-f19a15d9-ae69-4eba-a88d-96d5279a87a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3776660501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3776660501
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.864028656
Short name T2742
Test name
Test status
Simulation time 44622609 ps
CPU time 0.74 seconds
Started Jul 09 05:03:50 PM PDT 24
Finished Jul 09 05:03:52 PM PDT 24
Peak memory 205668 kb
Host smart-424445a9-97d6-4ae2-a443-005545a2accc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=864028656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.864028656
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3210550058
Short name T2806
Test name
Test status
Simulation time 45800868 ps
CPU time 0.7 seconds
Started Jul 09 05:03:44 PM PDT 24
Finished Jul 09 05:03:46 PM PDT 24
Peak memory 205652 kb
Host smart-49fa4a6d-495e-4961-8042-88d989cbf803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3210550058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3210550058
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1610649064
Short name T2719
Test name
Test status
Simulation time 81598347 ps
CPU time 1.74 seconds
Started Jul 09 05:03:27 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 214056 kb
Host smart-9ba05b5f-071a-44de-bfdf-f50c1115e6a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610649064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1610649064
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.30886935
Short name T2752
Test name
Test status
Simulation time 55752559 ps
CPU time 0.9 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 205732 kb
Host smart-e543ec90-4bac-459b-b42c-8bf44186b0ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=30886935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.30886935
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3638272822
Short name T290
Test name
Test status
Simulation time 52515969 ps
CPU time 0.7 seconds
Started Jul 09 05:03:27 PM PDT 24
Finished Jul 09 05:03:28 PM PDT 24
Peak memory 205712 kb
Host smart-d7362e3b-ab92-40aa-9151-59ef53da1cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3638272822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3638272822
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3242784435
Short name T2736
Test name
Test status
Simulation time 183015929 ps
CPU time 1.77 seconds
Started Jul 09 05:03:28 PM PDT 24
Finished Jul 09 05:03:30 PM PDT 24
Peak memory 205864 kb
Host smart-a1777a51-b88f-4d77-bbcd-65576c519c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3242784435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3242784435
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2095608249
Short name T228
Test name
Test status
Simulation time 95373510 ps
CPU time 2.51 seconds
Started Jul 09 05:03:30 PM PDT 24
Finished Jul 09 05:03:33 PM PDT 24
Peak memory 221876 kb
Host smart-dc4ff70f-1c73-425d-998c-d5296c7dc4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2095608249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2095608249
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1962868517
Short name T304
Test name
Test status
Simulation time 870061332 ps
CPU time 5.17 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:32 PM PDT 24
Peak memory 205840 kb
Host smart-c1f46a7b-3740-4e30-b700-46d7624486e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1962868517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1962868517
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2789667030
Short name T2745
Test name
Test status
Simulation time 270255451 ps
CPU time 1.83 seconds
Started Jul 09 05:03:27 PM PDT 24
Finished Jul 09 05:03:30 PM PDT 24
Peak memory 214060 kb
Host smart-17494549-5807-49bc-9575-80f54487bc84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789667030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2789667030
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2936831909
Short name T2716
Test name
Test status
Simulation time 77345030 ps
CPU time 1 seconds
Started Jul 09 05:03:29 PM PDT 24
Finished Jul 09 05:03:31 PM PDT 24
Peak memory 205684 kb
Host smart-c07e4d35-803a-40d0-9818-17f29c32c959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2936831909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2936831909
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3689078257
Short name T2739
Test name
Test status
Simulation time 65993340 ps
CPU time 0.74 seconds
Started Jul 09 05:03:28 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 205652 kb
Host smart-8132345f-8dae-45cc-9634-abdca714d60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689078257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3689078257
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1740502915
Short name T2794
Test name
Test status
Simulation time 95451819 ps
CPU time 1.12 seconds
Started Jul 09 05:03:29 PM PDT 24
Finished Jul 09 05:03:31 PM PDT 24
Peak memory 205892 kb
Host smart-7647e324-d3a5-4d8c-ad7e-7bd825d4c280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1740502915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1740502915
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1568603172
Short name T2763
Test name
Test status
Simulation time 106340919 ps
CPU time 2.98 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 221724 kb
Host smart-15a15e31-2c69-489e-9c86-8d655ced0e45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1568603172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1568603172
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1772162144
Short name T306
Test name
Test status
Simulation time 1080650904 ps
CPU time 5.41 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:32 PM PDT 24
Peak memory 205900 kb
Host smart-5aab7b22-756c-4257-9bee-1074fa441f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1772162144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1772162144
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3362898796
Short name T2775
Test name
Test status
Simulation time 210315346 ps
CPU time 2.24 seconds
Started Jul 09 05:03:26 PM PDT 24
Finished Jul 09 05:03:29 PM PDT 24
Peak memory 214132 kb
Host smart-c2a4c5e0-ef0c-4d3e-bcce-162e814b6ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362898796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3362898796
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.407071928
Short name T259
Test name
Test status
Simulation time 49567864 ps
CPU time 1.01 seconds
Started Jul 09 05:03:30 PM PDT 24
Finished Jul 09 05:03:31 PM PDT 24
Peak memory 205880 kb
Host smart-40dba649-4281-4060-a2bc-f6601931edd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=407071928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.407071928
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1491840142
Short name T2732
Test name
Test status
Simulation time 62724273 ps
CPU time 0.68 seconds
Started Jul 09 05:03:29 PM PDT 24
Finished Jul 09 05:03:31 PM PDT 24
Peak memory 205636 kb
Host smart-9cfddced-1371-44cc-852f-c4aac983c006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1491840142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1491840142
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2752962376
Short name T2746
Test name
Test status
Simulation time 272555828 ps
CPU time 1.93 seconds
Started Jul 09 05:03:27 PM PDT 24
Finished Jul 09 05:03:30 PM PDT 24
Peak memory 205828 kb
Host smart-96c83988-c7ef-48ff-9231-f9f5b89315b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2752962376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2752962376
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.136174896
Short name T221
Test name
Test status
Simulation time 73916609 ps
CPU time 1.83 seconds
Started Jul 09 05:03:45 PM PDT 24
Finished Jul 09 05:03:48 PM PDT 24
Peak memory 214052 kb
Host smart-f064b36f-13c0-4bab-a716-38cddb3a9f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=136174896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.136174896
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.451914538
Short name T300
Test name
Test status
Simulation time 694293765 ps
CPU time 4.75 seconds
Started Jul 09 05:03:30 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 205816 kb
Host smart-37c15d18-3b90-467e-bcf9-6f941c2f0794
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=451914538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.451914538
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3337672045
Short name T2770
Test name
Test status
Simulation time 115858223 ps
CPU time 1.31 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 222228 kb
Host smart-e0a23b48-0b92-4b8a-bdc4-2a0239340037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337672045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3337672045
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2514157358
Short name T263
Test name
Test status
Simulation time 37876002 ps
CPU time 0.86 seconds
Started Jul 09 05:03:33 PM PDT 24
Finished Jul 09 05:03:34 PM PDT 24
Peak memory 205648 kb
Host smart-0cf4d5c5-fca4-48a4-9b81-5e6b36492d1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2514157358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2514157358
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2396444966
Short name T292
Test name
Test status
Simulation time 36253058 ps
CPU time 0.68 seconds
Started Jul 09 05:03:37 PM PDT 24
Finished Jul 09 05:03:39 PM PDT 24
Peak memory 205652 kb
Host smart-95893379-fdc4-410e-a903-452cadc29b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2396444966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2396444966
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3276572238
Short name T2718
Test name
Test status
Simulation time 218358152 ps
CPU time 1.73 seconds
Started Jul 09 05:03:30 PM PDT 24
Finished Jul 09 05:03:33 PM PDT 24
Peak memory 205876 kb
Host smart-ceefb210-c4c6-4c61-a5e5-fb5e464c6db8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3276572238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3276572238
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1118597265
Short name T235
Test name
Test status
Simulation time 236756974 ps
CPU time 2.51 seconds
Started Jul 09 05:03:31 PM PDT 24
Finished Jul 09 05:03:34 PM PDT 24
Peak memory 222208 kb
Host smart-3e87beef-a078-4672-858d-eef37b46f620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118597265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1118597265
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.60234977
Short name T303
Test name
Test status
Simulation time 539713625 ps
CPU time 2.92 seconds
Started Jul 09 05:03:32 PM PDT 24
Finished Jul 09 05:03:36 PM PDT 24
Peak memory 205904 kb
Host smart-1f930b39-332a-4828-893e-c2458de375c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=60234977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.60234977
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.541171040
Short name T2754
Test name
Test status
Simulation time 254446551 ps
CPU time 2.02 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 214080 kb
Host smart-9fcbb70a-2396-47a5-b3bc-cf6f654be35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541171040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.541171040
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1768410077
Short name T267
Test name
Test status
Simulation time 65158421 ps
CPU time 0.94 seconds
Started Jul 09 05:03:31 PM PDT 24
Finished Jul 09 05:03:32 PM PDT 24
Peak memory 205684 kb
Host smart-3feb4d03-b267-4353-aab3-42bfe4534754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1768410077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1768410077
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2062386126
Short name T280
Test name
Test status
Simulation time 36754855 ps
CPU time 0.74 seconds
Started Jul 09 05:03:34 PM PDT 24
Finished Jul 09 05:03:36 PM PDT 24
Peak memory 205716 kb
Host smart-6b142036-f29f-4934-85dd-a392617cf16f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2062386126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2062386126
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1152667844
Short name T2751
Test name
Test status
Simulation time 235860645 ps
CPU time 1.6 seconds
Started Jul 09 05:03:33 PM PDT 24
Finished Jul 09 05:03:35 PM PDT 24
Peak memory 205880 kb
Host smart-cd5267af-c919-4b48-a21f-9a4c88c9a9d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1152667844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1152667844
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2403250112
Short name T231
Test name
Test status
Simulation time 163786869 ps
CPU time 2.09 seconds
Started Jul 09 05:03:38 PM PDT 24
Finished Jul 09 05:03:41 PM PDT 24
Peak memory 214128 kb
Host smart-e3e70b82-ae04-457d-8670-58dac0f98849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2403250112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2403250112
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1129582466
Short name T310
Test name
Test status
Simulation time 305453731 ps
CPU time 2.42 seconds
Started Jul 09 05:03:34 PM PDT 24
Finished Jul 09 05:03:37 PM PDT 24
Peak memory 205892 kb
Host smart-ac4ae771-0914-498c-9201-7dc63cafdfd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1129582466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1129582466
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2966632850
Short name T967
Test name
Test status
Simulation time 37021269 ps
CPU time 0.68 seconds
Started Jul 09 05:11:37 PM PDT 24
Finished Jul 09 05:11:38 PM PDT 24
Peak memory 206112 kb
Host smart-abcec39c-a9ce-48d6-b621-abd47f62cc79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2966632850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2966632850
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.332939116
Short name T2248
Test name
Test status
Simulation time 4431726608 ps
CPU time 6.27 seconds
Started Jul 09 05:11:22 PM PDT 24
Finished Jul 09 05:11:31 PM PDT 24
Peak memory 206364 kb
Host smart-25a3049b-3384-40e7-9893-ceebb04c2521
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=332939116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.332939116
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2851576146
Short name T604
Test name
Test status
Simulation time 13400572739 ps
CPU time 13.06 seconds
Started Jul 09 05:11:22 PM PDT 24
Finished Jul 09 05:11:38 PM PDT 24
Peak memory 206308 kb
Host smart-767194e6-c25c-4286-a6e7-18cef2ff2fde
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2851576146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2851576146
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3603040127
Short name T1175
Test name
Test status
Simulation time 23438691772 ps
CPU time 26.56 seconds
Started Jul 09 05:11:24 PM PDT 24
Finished Jul 09 05:11:54 PM PDT 24
Peak memory 206232 kb
Host smart-d6e558f3-b6d0-412a-86ab-c68056d57eb4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3603040127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3603040127
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.106134615
Short name T2140
Test name
Test status
Simulation time 173584895 ps
CPU time 0.81 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:28 PM PDT 24
Peak memory 206064 kb
Host smart-e2b1f5e8-3cb9-475b-b6d3-e91cecff7c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10613
4615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.106134615
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1403015683
Short name T1259
Test name
Test status
Simulation time 149131009 ps
CPU time 0.79 seconds
Started Jul 09 05:11:22 PM PDT 24
Finished Jul 09 05:11:26 PM PDT 24
Peak memory 206068 kb
Host smart-34589bd4-b31b-41a5-a1ff-45005542fc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14030
15683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1403015683
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2611515906
Short name T1978
Test name
Test status
Simulation time 433617513 ps
CPU time 1.36 seconds
Started Jul 09 05:11:23 PM PDT 24
Finished Jul 09 05:11:27 PM PDT 24
Peak memory 206064 kb
Host smart-a8e99e3e-bc9b-4ad6-b9a1-55f35bd4ce0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26115
15906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2611515906
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.4216012430
Short name T171
Test name
Test status
Simulation time 1121503992 ps
CPU time 2.31 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:30 PM PDT 24
Peak memory 206168 kb
Host smart-a020c405-2c8d-427a-9580-84c5184754ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42160
12430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.4216012430
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.4118008205
Short name T796
Test name
Test status
Simulation time 13178474599 ps
CPU time 26.27 seconds
Started Jul 09 05:11:23 PM PDT 24
Finished Jul 09 05:11:52 PM PDT 24
Peak memory 206416 kb
Host smart-51feee80-c182-4334-b84f-677f4d670d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
08205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.4118008205
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.1442288600
Short name T1848
Test name
Test status
Simulation time 384074991 ps
CPU time 1.31 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:29 PM PDT 24
Peak memory 205988 kb
Host smart-9ae37e7d-e247-4567-97f3-493f88136b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14422
88600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.1442288600
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2212698488
Short name T2383
Test name
Test status
Simulation time 158519063 ps
CPU time 0.79 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:28 PM PDT 24
Peak memory 206064 kb
Host smart-cc6be93d-6e5a-4620-a8d7-ca3afa48905f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126
98488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2212698488
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.836378197
Short name T1009
Test name
Test status
Simulation time 5116706009 ps
CPU time 45.13 seconds
Started Jul 09 05:11:24 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 206356 kb
Host smart-49b0e49c-217c-4741-8b85-ec6383656f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83637
8197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.836378197
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3635490312
Short name T1407
Test name
Test status
Simulation time 34157864 ps
CPU time 0.67 seconds
Started Jul 09 05:11:24 PM PDT 24
Finished Jul 09 05:11:28 PM PDT 24
Peak memory 206056 kb
Host smart-87a66ba9-fbde-409d-b24c-aa9f47b334c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36354
90312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3635490312
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.649637078
Short name T2049
Test name
Test status
Simulation time 939372028 ps
CPU time 2.13 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:30 PM PDT 24
Peak memory 206148 kb
Host smart-31bf641d-3c6b-456a-af3a-cb0f7ec63d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64963
7078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.649637078
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3151384252
Short name T2471
Test name
Test status
Simulation time 167177198 ps
CPU time 1.59 seconds
Started Jul 09 05:11:27 PM PDT 24
Finished Jul 09 05:11:31 PM PDT 24
Peak memory 206348 kb
Host smart-0efe9240-c490-460f-bf62-d66a19806834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31513
84252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3151384252
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1963727620
Short name T1824
Test name
Test status
Simulation time 117183635520 ps
CPU time 177.75 seconds
Started Jul 09 05:11:27 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206368 kb
Host smart-074641e0-17b0-4264-b5ca-60827746aa23
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1963727620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1963727620
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2733045624
Short name T2561
Test name
Test status
Simulation time 121334308923 ps
CPU time 187.97 seconds
Started Jul 09 05:11:29 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206400 kb
Host smart-8e0ac58d-9b12-45bb-84d5-2751b07f572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733045624 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2733045624
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.738352096
Short name T1652
Test name
Test status
Simulation time 81113591586 ps
CPU time 126.55 seconds
Started Jul 09 05:11:26 PM PDT 24
Finished Jul 09 05:13:35 PM PDT 24
Peak memory 206352 kb
Host smart-2b6e0ccc-b4d9-4a17-87de-8dc26a98646e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=738352096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.738352096
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.515801269
Short name T638
Test name
Test status
Simulation time 119973733681 ps
CPU time 186.07 seconds
Started Jul 09 05:11:26 PM PDT 24
Finished Jul 09 05:14:34 PM PDT 24
Peak memory 206628 kb
Host smart-099d7968-e075-4cf4-9e52-ffd21cf23aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515801269 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.515801269
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.1866013695
Short name T1847
Test name
Test status
Simulation time 107140294710 ps
CPU time 154.65 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 206304 kb
Host smart-cc99d8d5-9d92-4ed4-b461-4e96af218803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18660
13695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1866013695
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1083833310
Short name T2371
Test name
Test status
Simulation time 232539829 ps
CPU time 0.97 seconds
Started Jul 09 05:11:27 PM PDT 24
Finished Jul 09 05:11:30 PM PDT 24
Peak memory 206156 kb
Host smart-8ada4d8a-1b5e-4d7d-92d9-4c5a2636e0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838
33310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1083833310
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1982048845
Short name T2704
Test name
Test status
Simulation time 147208560 ps
CPU time 0.79 seconds
Started Jul 09 05:11:29 PM PDT 24
Finished Jul 09 05:11:31 PM PDT 24
Peak memory 206104 kb
Host smart-8ae779aa-ebeb-44b5-b8d0-c45d3c9990ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19820
48845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1982048845
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3659656096
Short name T1140
Test name
Test status
Simulation time 173328165 ps
CPU time 0.81 seconds
Started Jul 09 05:11:28 PM PDT 24
Finished Jul 09 05:11:30 PM PDT 24
Peak memory 206160 kb
Host smart-ccf14ca4-5207-4e3c-a86c-f852b4351ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36596
56096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3659656096
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1999806290
Short name T1174
Test name
Test status
Simulation time 217718885 ps
CPU time 0.87 seconds
Started Jul 09 05:11:25 PM PDT 24
Finished Jul 09 05:11:29 PM PDT 24
Peak memory 206372 kb
Host smart-01b951b4-743c-44be-aca6-4fbe3ca9f452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19998
06290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1999806290
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3497830245
Short name T68
Test name
Test status
Simulation time 494961567 ps
CPU time 1.31 seconds
Started Jul 09 05:11:27 PM PDT 24
Finished Jul 09 05:11:30 PM PDT 24
Peak memory 206108 kb
Host smart-1a185235-821b-4578-a33d-f5f1e694ffd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34978
30245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3497830245
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2153418508
Short name T1862
Test name
Test status
Simulation time 23278014529 ps
CPU time 28.97 seconds
Started Jul 09 05:11:24 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206176 kb
Host smart-73fa92ed-4fc8-4bed-a5be-ec8544b18cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21534
18508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2153418508
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1120057142
Short name T1508
Test name
Test status
Simulation time 3416220409 ps
CPU time 3.81 seconds
Started Jul 09 05:11:26 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206156 kb
Host smart-04bc8d74-feb0-4aff-ab53-7853d89fb522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11200
57142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1120057142
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.1197992555
Short name T1947
Test name
Test status
Simulation time 9061711236 ps
CPU time 239.54 seconds
Started Jul 09 05:11:30 PM PDT 24
Finished Jul 09 05:15:31 PM PDT 24
Peak memory 206500 kb
Host smart-e213d270-1cde-4673-b342-8879f5fee19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
92555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1197992555
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1253866837
Short name T1550
Test name
Test status
Simulation time 4842922268 ps
CPU time 134.78 seconds
Started Jul 09 05:11:30 PM PDT 24
Finished Jul 09 05:13:46 PM PDT 24
Peak memory 206400 kb
Host smart-fe4cbbcc-4bd6-4af9-82bd-52a0f1086985
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1253866837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1253866837
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2152181716
Short name T2096
Test name
Test status
Simulation time 241746781 ps
CPU time 0.93 seconds
Started Jul 09 05:11:29 PM PDT 24
Finished Jul 09 05:11:31 PM PDT 24
Peak memory 205972 kb
Host smart-700a791e-7b32-4198-ac7c-ad43fea11653
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2152181716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2152181716
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1775422264
Short name T1216
Test name
Test status
Simulation time 188229904 ps
CPU time 0.87 seconds
Started Jul 09 05:11:30 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206152 kb
Host smart-963ce69e-f4d3-4dff-8b81-e7f248df2ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17754
22264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1775422264
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.4105656734
Short name T1965
Test name
Test status
Simulation time 4230608606 ps
CPU time 38.68 seconds
Started Jul 09 05:11:29 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206424 kb
Host smart-1b8acbf5-9f1b-42a5-9ef2-a1ff3ebcbaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056
56734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.4105656734
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.266276693
Short name T340
Test name
Test status
Simulation time 5908171380 ps
CPU time 43.77 seconds
Started Jul 09 05:11:33 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206372 kb
Host smart-bf9378a0-b7e8-4786-bcad-8a04d2e9718f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=266276693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.266276693
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3219813430
Short name T1587
Test name
Test status
Simulation time 150539304 ps
CPU time 0.77 seconds
Started Jul 09 05:11:33 PM PDT 24
Finished Jul 09 05:11:34 PM PDT 24
Peak memory 206032 kb
Host smart-be45b69f-5d27-48eb-aa36-e1faa97466cc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3219813430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3219813430
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2136411225
Short name T2511
Test name
Test status
Simulation time 143310419 ps
CPU time 0.79 seconds
Started Jul 09 05:11:30 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206168 kb
Host smart-27d17bfb-e6ec-464f-b27d-7f0e47065916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21364
11225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2136411225
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2581289406
Short name T69
Test name
Test status
Simulation time 440348671 ps
CPU time 1.51 seconds
Started Jul 09 05:11:32 PM PDT 24
Finished Jul 09 05:11:35 PM PDT 24
Peak memory 206024 kb
Host smart-c2500515-26fe-4931-8942-0b51411f2cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25812
89406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2581289406
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3666635715
Short name T2696
Test name
Test status
Simulation time 169021473 ps
CPU time 0.86 seconds
Started Jul 09 05:11:30 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206156 kb
Host smart-6df1fd45-96bd-45b9-94c1-bb352a360ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36666
35715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3666635715
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2046738367
Short name T1920
Test name
Test status
Simulation time 172854262 ps
CPU time 0.81 seconds
Started Jul 09 05:11:30 PM PDT 24
Finished Jul 09 05:11:32 PM PDT 24
Peak memory 206068 kb
Host smart-846ed0b9-886f-4b31-9a89-75dd86688005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
38367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2046738367
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.484586893
Short name T2240
Test name
Test status
Simulation time 224187014 ps
CPU time 0.92 seconds
Started Jul 09 05:11:31 PM PDT 24
Finished Jul 09 05:11:34 PM PDT 24
Peak memory 206136 kb
Host smart-6a66c4ab-d297-4cfa-b868-50027fb0de99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48458
6893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.484586893
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.770873908
Short name T1938
Test name
Test status
Simulation time 160629817 ps
CPU time 0.8 seconds
Started Jul 09 05:11:31 PM PDT 24
Finished Jul 09 05:11:33 PM PDT 24
Peak memory 206060 kb
Host smart-41ab47f3-d6da-4c24-892f-c0f879eeeec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77087
3908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.770873908
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.4131970906
Short name T1539
Test name
Test status
Simulation time 150623301 ps
CPU time 0.78 seconds
Started Jul 09 05:11:31 PM PDT 24
Finished Jul 09 05:11:34 PM PDT 24
Peak memory 205964 kb
Host smart-4a2221da-2688-4688-b4b0-8fdba2bd4205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41319
70906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.4131970906
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1926598876
Short name T1950
Test name
Test status
Simulation time 219154873 ps
CPU time 0.94 seconds
Started Jul 09 05:11:33 PM PDT 24
Finished Jul 09 05:11:35 PM PDT 24
Peak memory 206112 kb
Host smart-60f07223-e5f0-4792-9cd9-9a0f0ee9236e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1926598876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1926598876
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.4185399437
Short name T2228
Test name
Test status
Simulation time 252770767 ps
CPU time 1.09 seconds
Started Jul 09 05:11:31 PM PDT 24
Finished Jul 09 05:11:34 PM PDT 24
Peak memory 206112 kb
Host smart-7825f4ca-9b84-4c74-af57-067825d38216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
99437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.4185399437
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.633120277
Short name T2138
Test name
Test status
Simulation time 320915163 ps
CPU time 1.05 seconds
Started Jul 09 05:11:32 PM PDT 24
Finished Jul 09 05:11:34 PM PDT 24
Peak memory 205988 kb
Host smart-fa95d78e-b721-4965-be2a-9054ab966a2d
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=633120277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.633120277
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.4058999235
Short name T202
Test name
Test status
Simulation time 221054105 ps
CPU time 0.94 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206108 kb
Host smart-6e411fe3-5b0c-45e2-a8c2-da22a3544646
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4058999235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.4058999235
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2812106701
Short name T1658
Test name
Test status
Simulation time 44311311 ps
CPU time 0.67 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206088 kb
Host smart-e2be57ce-6b95-4094-b32e-dcdc65393754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28121
06701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2812106701
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.255675587
Short name T253
Test name
Test status
Simulation time 20478861905 ps
CPU time 47.69 seconds
Started Jul 09 05:11:33 PM PDT 24
Finished Jul 09 05:12:22 PM PDT 24
Peak memory 206500 kb
Host smart-61751463-81bf-4f4d-b320-f43e64abcc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25567
5587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.255675587
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3034770538
Short name T1889
Test name
Test status
Simulation time 173861721 ps
CPU time 0.83 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206056 kb
Host smart-09a7c663-670c-47ca-98c7-a6dc74589149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30347
70538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3034770538
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3996377741
Short name T388
Test name
Test status
Simulation time 314398208 ps
CPU time 0.98 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206008 kb
Host smart-a66cf680-c8a3-47fe-b361-7a6f8f8992a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
77741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3996377741
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2590856696
Short name T1223
Test name
Test status
Simulation time 7248625059 ps
CPU time 96.81 seconds
Started Jul 09 05:11:32 PM PDT 24
Finished Jul 09 05:13:10 PM PDT 24
Peak memory 206372 kb
Host smart-36249874-0570-4618-945b-fb8d964e1068
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2590856696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2590856696
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1282779805
Short name T2121
Test name
Test status
Simulation time 9350219532 ps
CPU time 60.93 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206468 kb
Host smart-0219a80f-c234-49f5-ae02-9ecccfb900cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1282779805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1282779805
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1464892429
Short name T579
Test name
Test status
Simulation time 13040679715 ps
CPU time 70.68 seconds
Started Jul 09 05:11:36 PM PDT 24
Finished Jul 09 05:12:48 PM PDT 24
Peak memory 206416 kb
Host smart-f63bfb83-3290-4d5e-a521-bf88f873fe4c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1464892429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1464892429
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3588371167
Short name T1863
Test name
Test status
Simulation time 250671504 ps
CPU time 0.95 seconds
Started Jul 09 05:11:33 PM PDT 24
Finished Jul 09 05:11:35 PM PDT 24
Peak memory 206028 kb
Host smart-c93471a4-c67f-457c-9bfd-89de8a46f35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35883
71167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3588371167
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1824624727
Short name T1799
Test name
Test status
Simulation time 185377338 ps
CPU time 0.89 seconds
Started Jul 09 05:11:33 PM PDT 24
Finished Jul 09 05:11:35 PM PDT 24
Peak memory 206032 kb
Host smart-b9e18b5a-e259-4107-ba60-d3b9985d0a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18246
24727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1824624727
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3971679992
Short name T1524
Test name
Test status
Simulation time 165636176 ps
CPU time 0.81 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206148 kb
Host smart-c4e326ac-e114-4755-9983-145a6d61134b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39716
79992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3971679992
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1722169826
Short name T208
Test name
Test status
Simulation time 732739061 ps
CPU time 1.63 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:11:45 PM PDT 24
Peak memory 225020 kb
Host smart-33e3572b-5f53-49a3-ba05-951058b362a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1722169826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1722169826
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1496779868
Short name T1213
Test name
Test status
Simulation time 407765905 ps
CPU time 1.26 seconds
Started Jul 09 05:11:35 PM PDT 24
Finished Jul 09 05:11:38 PM PDT 24
Peak memory 206144 kb
Host smart-268cd9a7-1a9b-4bcb-b814-bd81eb6ed564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14967
79868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1496779868
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1373397791
Short name T152
Test name
Test status
Simulation time 217083190 ps
CPU time 0.88 seconds
Started Jul 09 05:11:34 PM PDT 24
Finished Jul 09 05:11:36 PM PDT 24
Peak memory 206096 kb
Host smart-9d031175-547c-4092-941b-ad104e53bf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13733
97791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1373397791
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3033591005
Short name T83
Test name
Test status
Simulation time 219018361 ps
CPU time 0.86 seconds
Started Jul 09 05:11:37 PM PDT 24
Finished Jul 09 05:11:39 PM PDT 24
Peak memory 206052 kb
Host smart-f1b39c06-d221-4ad2-a156-e4e21622ffab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30335
91005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3033591005
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3943780393
Short name T1973
Test name
Test status
Simulation time 153105790 ps
CPU time 0.8 seconds
Started Jul 09 05:11:37 PM PDT 24
Finished Jul 09 05:11:38 PM PDT 24
Peak memory 206024 kb
Host smart-cd59f913-b7dd-42df-b37e-1ddcf09e1f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39437
80393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3943780393
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3149680120
Short name T371
Test name
Test status
Simulation time 220122766 ps
CPU time 0.91 seconds
Started Jul 09 05:11:38 PM PDT 24
Finished Jul 09 05:11:40 PM PDT 24
Peak memory 205952 kb
Host smart-aa1158c3-03e1-4c88-8d25-bed97648f48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31496
80120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3149680120
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2329025882
Short name T1904
Test name
Test status
Simulation time 3362753106 ps
CPU time 93.58 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206404 kb
Host smart-39a0fc06-f5b5-4c0c-b64b-bf2b915cc619
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2329025882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2329025882
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1522996474
Short name T2366
Test name
Test status
Simulation time 156974947 ps
CPU time 0.83 seconds
Started Jul 09 05:11:41 PM PDT 24
Finished Jul 09 05:11:43 PM PDT 24
Peak memory 206068 kb
Host smart-c0e913fd-799e-4edf-921e-4eba6c2db54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15229
96474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1522996474
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3689179109
Short name T2175
Test name
Test status
Simulation time 214310144 ps
CPU time 0.86 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:11:57 PM PDT 24
Peak memory 206056 kb
Host smart-17e5981a-6fb2-448a-bb0f-8320de8c38e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36891
79109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3689179109
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.998922246
Short name T1095
Test name
Test status
Simulation time 906677099 ps
CPU time 2.04 seconds
Started Jul 09 05:11:40 PM PDT 24
Finished Jul 09 05:11:42 PM PDT 24
Peak memory 206324 kb
Host smart-98c5e0fc-20c5-45de-b3c5-dcdf2d7128dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99892
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.998922246
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1638635940
Short name T868
Test name
Test status
Simulation time 4211296927 ps
CPU time 36.1 seconds
Started Jul 09 05:11:39 PM PDT 24
Finished Jul 09 05:12:16 PM PDT 24
Peak memory 206456 kb
Host smart-6b639fb0-8296-483d-9ec4-b0e0cdbcbf8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16386
35940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1638635940
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1282528034
Short name T12
Test name
Test status
Simulation time 3531622679 ps
CPU time 3.99 seconds
Started Jul 09 05:11:40 PM PDT 24
Finished Jul 09 05:11:44 PM PDT 24
Peak memory 206164 kb
Host smart-86d414d4-c85c-478b-aca2-e20080fede7d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1282528034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1282528034
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1202466075
Short name T2447
Test name
Test status
Simulation time 13327482478 ps
CPU time 12.93 seconds
Started Jul 09 05:11:44 PM PDT 24
Finished Jul 09 05:11:58 PM PDT 24
Peak memory 206104 kb
Host smart-9a1e0061-cd3a-45fe-941a-cf284256dbdd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1202466075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1202466075
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2492347659
Short name T13
Test name
Test status
Simulation time 23353992372 ps
CPU time 25.24 seconds
Started Jul 09 05:11:38 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206032 kb
Host smart-2ce15105-7d87-41cd-a981-0b1cd8527a95
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2492347659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2492347659
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2596649732
Short name T673
Test name
Test status
Simulation time 156643496 ps
CPU time 0.81 seconds
Started Jul 09 05:11:40 PM PDT 24
Finished Jul 09 05:11:42 PM PDT 24
Peak memory 206068 kb
Host smart-2e55c412-c250-44be-b275-761ec416e243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25966
49732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2596649732
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3866978683
Short name T1489
Test name
Test status
Simulation time 157396750 ps
CPU time 0.87 seconds
Started Jul 09 05:11:38 PM PDT 24
Finished Jul 09 05:11:40 PM PDT 24
Peak memory 206128 kb
Host smart-5cfec172-f594-4e27-a20b-68eb41e88299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
78683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3866978683
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3286985766
Short name T64
Test name
Test status
Simulation time 175260950 ps
CPU time 0.8 seconds
Started Jul 09 05:11:41 PM PDT 24
Finished Jul 09 05:11:43 PM PDT 24
Peak memory 206052 kb
Host smart-88b2717a-722f-45cd-aed0-c16a13c28f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32869
85766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3286985766
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2008550007
Short name T508
Test name
Test status
Simulation time 183979757 ps
CPU time 0.81 seconds
Started Jul 09 05:11:38 PM PDT 24
Finished Jul 09 05:11:39 PM PDT 24
Peak memory 206068 kb
Host smart-d0d04c72-b94d-4c39-862d-62c897e470ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085
50007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2008550007
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.4159871308
Short name T58
Test name
Test status
Simulation time 218525449 ps
CPU time 1.01 seconds
Started Jul 09 05:11:39 PM PDT 24
Finished Jul 09 05:11:41 PM PDT 24
Peak memory 206004 kb
Host smart-249c5411-5b9b-4ff0-ac4b-952bf8db9983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41598
71308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.4159871308
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1691705817
Short name T2572
Test name
Test status
Simulation time 370421033 ps
CPU time 1.2 seconds
Started Jul 09 05:11:37 PM PDT 24
Finished Jul 09 05:11:38 PM PDT 24
Peak memory 206064 kb
Host smart-37dda0e5-dce2-4de2-a68b-725409e27888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16917
05817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1691705817
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.187355520
Short name T875
Test name
Test status
Simulation time 137023337 ps
CPU time 0.77 seconds
Started Jul 09 05:11:38 PM PDT 24
Finished Jul 09 05:11:39 PM PDT 24
Peak memory 205992 kb
Host smart-20fd32fc-f53b-45c0-8ec0-3e54d772f790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18735
5520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.187355520
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3471745017
Short name T365
Test name
Test status
Simulation time 44155087 ps
CPU time 0.67 seconds
Started Jul 09 05:11:37 PM PDT 24
Finished Jul 09 05:11:39 PM PDT 24
Peak memory 206120 kb
Host smart-40e0e7ce-9d35-401b-aea6-cb1101215ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
45017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3471745017
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4145779183
Short name T1662
Test name
Test status
Simulation time 913562838 ps
CPU time 2.34 seconds
Started Jul 09 05:11:44 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206292 kb
Host smart-dce4ffb7-f7df-42be-a93e-c82e207f56a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
79183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4145779183
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1737396169
Short name T1454
Test name
Test status
Simulation time 305462118 ps
CPU time 2.28 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:11:47 PM PDT 24
Peak memory 206316 kb
Host smart-0fd538d8-e1b0-4206-a40e-8fe36a3980d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17373
96169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1737396169
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.949948849
Short name T1156
Test name
Test status
Simulation time 112250188058 ps
CPU time 156.14 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206292 kb
Host smart-2072f0ed-b37d-449e-83e6-00bb2a2a4db9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=949948849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.949948849
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1032856856
Short name T635
Test name
Test status
Simulation time 121168211164 ps
CPU time 211.46 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206296 kb
Host smart-60577f8f-ae37-4897-8488-73e19b0edd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032856856 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1032856856
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.1333492566
Short name T640
Test name
Test status
Simulation time 112100232598 ps
CPU time 147.52 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:14:11 PM PDT 24
Peak memory 206380 kb
Host smart-ed976af6-3cdc-4cad-9387-af951421976c
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1333492566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1333492566
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3695735178
Short name T2610
Test name
Test status
Simulation time 93978794237 ps
CPU time 143.08 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:14:10 PM PDT 24
Peak memory 206336 kb
Host smart-248cba1a-41a2-4972-8721-343ce537b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695735178 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3695735178
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3922762377
Short name T2624
Test name
Test status
Simulation time 118150978586 ps
CPU time 174.91 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206280 kb
Host smart-0b77322c-a330-4653-ae4f-5851702890c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39227
62377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3922762377
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.423298938
Short name T928
Test name
Test status
Simulation time 151902461 ps
CPU time 0.85 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:11:45 PM PDT 24
Peak memory 206128 kb
Host smart-f1b2d69a-5721-4372-98cb-ffc44af7c641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42329
8938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.423298938
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1459743312
Short name T2303
Test name
Test status
Simulation time 147013087 ps
CPU time 0.77 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:11:46 PM PDT 24
Peak memory 206144 kb
Host smart-3c853057-afcb-4628-a854-ffc1491d3c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597
43312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1459743312
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.4260691661
Short name T846
Test name
Test status
Simulation time 227094741 ps
CPU time 0.98 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:11:44 PM PDT 24
Peak memory 206056 kb
Host smart-a25bf3bb-958a-4587-9010-5238bd2fcee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42606
91661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.4260691661
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2199115376
Short name T566
Test name
Test status
Simulation time 7315684560 ps
CPU time 53.65 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206292 kb
Host smart-749139d7-09c0-45c4-80d7-58d35679ce40
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2199115376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2199115376
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2057337092
Short name T1019
Test name
Test status
Simulation time 200240440 ps
CPU time 0.83 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:11:44 PM PDT 24
Peak memory 206116 kb
Host smart-c3e50493-eb2e-4d78-b06e-deb75e6e6986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
37092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2057337092
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1560463560
Short name T391
Test name
Test status
Simulation time 23289957391 ps
CPU time 24.52 seconds
Started Jul 09 05:11:41 PM PDT 24
Finished Jul 09 05:12:07 PM PDT 24
Peak memory 206060 kb
Host smart-1775c938-4a54-424b-833c-9f619a1ab915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15604
63560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1560463560
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.4156288653
Short name T1934
Test name
Test status
Simulation time 3327173032 ps
CPU time 4.22 seconds
Started Jul 09 05:11:42 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206132 kb
Host smart-096975a6-9c00-41be-836c-7c107b60f106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41562
88653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.4156288653
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.383585670
Short name T1543
Test name
Test status
Simulation time 7834316464 ps
CPU time 61.99 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206380 kb
Host smart-8706bb3e-2792-49e9-a4bf-4f9ac97cdeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358
5670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.383585670
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.362388143
Short name T2007
Test name
Test status
Simulation time 3313814123 ps
CPU time 31.33 seconds
Started Jul 09 05:11:43 PM PDT 24
Finished Jul 09 05:12:16 PM PDT 24
Peak memory 206448 kb
Host smart-caa0c179-808c-4d88-a1bf-00d5bcef8023
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=362388143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.362388143
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2033220603
Short name T1870
Test name
Test status
Simulation time 261056971 ps
CPU time 0.99 seconds
Started Jul 09 05:11:41 PM PDT 24
Finished Jul 09 05:11:42 PM PDT 24
Peak memory 205972 kb
Host smart-d1c046bb-fb99-43a8-8dad-a511b8d0c4da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2033220603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2033220603
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3598886013
Short name T2410
Test name
Test status
Simulation time 188279781 ps
CPU time 0.88 seconds
Started Jul 09 05:11:45 PM PDT 24
Finished Jul 09 05:11:47 PM PDT 24
Peak memory 206100 kb
Host smart-8dac5cd7-4542-48fb-be88-8d95249186be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35988
86013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3598886013
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2586957880
Short name T4
Test name
Test status
Simulation time 3485795575 ps
CPU time 34.24 seconds
Started Jul 09 05:11:44 PM PDT 24
Finished Jul 09 05:12:20 PM PDT 24
Peak memory 206368 kb
Host smart-a9cebdbd-d856-4af1-bea2-41781699d1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
57880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2586957880
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.1315522138
Short name T2532
Test name
Test status
Simulation time 4690381888 ps
CPU time 32.34 seconds
Started Jul 09 05:11:48 PM PDT 24
Finished Jul 09 05:12:21 PM PDT 24
Peak memory 206396 kb
Host smart-484c2f3e-e7b5-4a0c-922a-8b8f29e5b22c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1315522138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.1315522138
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2170213632
Short name T2451
Test name
Test status
Simulation time 198045398 ps
CPU time 0.84 seconds
Started Jul 09 05:11:48 PM PDT 24
Finished Jul 09 05:11:50 PM PDT 24
Peak memory 206060 kb
Host smart-3f949c1c-c2ad-4e04-a6d6-4bad70a1b47d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2170213632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2170213632
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2670386446
Short name T2501
Test name
Test status
Simulation time 141509432 ps
CPU time 0.81 seconds
Started Jul 09 05:11:45 PM PDT 24
Finished Jul 09 05:11:47 PM PDT 24
Peak memory 206152 kb
Host smart-6cf1b10a-65f7-411e-b5d0-6f39109df401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26703
86446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2670386446
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.481331124
Short name T113
Test name
Test status
Simulation time 211765065 ps
CPU time 0.9 seconds
Started Jul 09 05:11:48 PM PDT 24
Finished Jul 09 05:11:50 PM PDT 24
Peak memory 206004 kb
Host smart-d1b47810-c642-4d30-a42d-5b6b9ecb5d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48133
1124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.481331124
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1335970778
Short name T1822
Test name
Test status
Simulation time 202971260 ps
CPU time 0.85 seconds
Started Jul 09 05:11:47 PM PDT 24
Finished Jul 09 05:11:49 PM PDT 24
Peak memory 206160 kb
Host smart-f35abbd1-6fd7-416e-b07f-78ae4bf12142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359
70778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1335970778
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1248595974
Short name T2591
Test name
Test status
Simulation time 158642973 ps
CPU time 0.81 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206060 kb
Host smart-6582eefd-700d-4ee1-8543-f72b4c98ba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12485
95974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1248595974
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.917105094
Short name T2073
Test name
Test status
Simulation time 198611220 ps
CPU time 0.85 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206020 kb
Host smart-2d16e3dd-4086-4da1-adde-68b5293d4177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91710
5094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.917105094
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2961169298
Short name T912
Test name
Test status
Simulation time 162811321 ps
CPU time 0.83 seconds
Started Jul 09 05:11:49 PM PDT 24
Finished Jul 09 05:11:51 PM PDT 24
Peak memory 206012 kb
Host smart-fdab4e84-dbbb-41a3-a0b9-069d3fc889fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611
69298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2961169298
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3296629098
Short name T1840
Test name
Test status
Simulation time 238244258 ps
CPU time 0.96 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206036 kb
Host smart-eec20341-489d-499f-ae6c-9fe8414453f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3296629098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3296629098
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3199936476
Short name T200
Test name
Test status
Simulation time 215631174 ps
CPU time 0.92 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206096 kb
Host smart-939af051-3091-4777-844c-974b9a16374c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
36476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3199936476
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.130908805
Short name T2291
Test name
Test status
Simulation time 175139236 ps
CPU time 0.76 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 206156 kb
Host smart-2259fc3a-099a-465a-802a-eca0ee357b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13090
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.130908805
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1382423368
Short name T1232
Test name
Test status
Simulation time 60202902 ps
CPU time 0.7 seconds
Started Jul 09 05:11:46 PM PDT 24
Finished Jul 09 05:11:48 PM PDT 24
Peak memory 205960 kb
Host smart-f8c8c5d1-31a3-4c65-bffc-590524dab507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13824
23368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1382423368
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3982912207
Short name T729
Test name
Test status
Simulation time 17433673785 ps
CPU time 36.17 seconds
Started Jul 09 05:11:47 PM PDT 24
Finished Jul 09 05:12:24 PM PDT 24
Peak memory 206444 kb
Host smart-50204aa7-14e2-4ed4-8213-a84bad4573a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39829
12207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3982912207
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3389923454
Short name T1823
Test name
Test status
Simulation time 192448432 ps
CPU time 0.9 seconds
Started Jul 09 05:11:48 PM PDT 24
Finished Jul 09 05:11:50 PM PDT 24
Peak memory 206116 kb
Host smart-27761b33-3b2e-4c9c-a77d-a84f17293f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
23454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3389923454
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2625300277
Short name T158
Test name
Test status
Simulation time 6592035030 ps
CPU time 162.9 seconds
Started Jul 09 05:11:47 PM PDT 24
Finished Jul 09 05:14:31 PM PDT 24
Peak memory 206476 kb
Host smart-e8ef1a71-ed19-437e-bfb6-e3b3728dd35e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625300277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2625300277
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.3848584272
Short name T965
Test name
Test status
Simulation time 8981117158 ps
CPU time 235.26 seconds
Started Jul 09 05:11:45 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 206336 kb
Host smart-a6ca7257-bb68-4c5a-92df-ed5d39e0c887
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3848584272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.3848584272
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.4293883340
Short name T1108
Test name
Test status
Simulation time 10968494684 ps
CPU time 67.28 seconds
Started Jul 09 05:11:50 PM PDT 24
Finished Jul 09 05:12:58 PM PDT 24
Peak memory 206284 kb
Host smart-b3cde16f-8fc7-48b5-8e2c-6e5d1cbb15f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4293883340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.4293883340
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3126956848
Short name T618
Test name
Test status
Simulation time 238085493 ps
CPU time 0.94 seconds
Started Jul 09 05:11:45 PM PDT 24
Finished Jul 09 05:11:47 PM PDT 24
Peak memory 205996 kb
Host smart-c58f7516-d85d-434e-9b7d-a77410f58c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31269
56848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3126956848
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.9783340
Short name T1229
Test name
Test status
Simulation time 179637643 ps
CPU time 0.85 seconds
Started Jul 09 05:11:47 PM PDT 24
Finished Jul 09 05:11:49 PM PDT 24
Peak memory 206164 kb
Host smart-5101f08b-88fe-41ce-b79a-38d345370c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97833
40 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.9783340
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2214376619
Short name T428
Test name
Test status
Simulation time 182898836 ps
CPU time 0.79 seconds
Started Jul 09 05:11:48 PM PDT 24
Finished Jul 09 05:11:50 PM PDT 24
Peak memory 206160 kb
Host smart-c274edd4-36ed-423e-8bae-bbc8a5a28302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22143
76619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2214376619
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2717745729
Short name T75
Test name
Test status
Simulation time 167284180 ps
CPU time 0.8 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:11:53 PM PDT 24
Peak memory 206148 kb
Host smart-7ae3f16b-1ee7-43f4-a8b4-dbd6ac5b6dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27177
45729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2717745729
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2186911746
Short name T1511
Test name
Test status
Simulation time 173736992 ps
CPU time 0.85 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:11:54 PM PDT 24
Peak memory 206128 kb
Host smart-c1929ecc-b32e-4eb6-85ef-3176db8d897d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21869
11746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2186911746
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3128883886
Short name T1701
Test name
Test status
Simulation time 149925069 ps
CPU time 0.75 seconds
Started Jul 09 05:11:53 PM PDT 24
Finished Jul 09 05:11:54 PM PDT 24
Peak memory 206160 kb
Host smart-87206b2f-8cce-4cfd-82e8-e6050ae8cadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31288
83886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3128883886
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3723422997
Short name T1144
Test name
Test status
Simulation time 150338829 ps
CPU time 0.78 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:11:53 PM PDT 24
Peak memory 206156 kb
Host smart-ba4a7ba2-6ab0-4a4a-ac7a-90aef9581137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37234
22997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3723422997
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4264725349
Short name T408
Test name
Test status
Simulation time 236378724 ps
CPU time 0.99 seconds
Started Jul 09 05:11:49 PM PDT 24
Finished Jul 09 05:11:51 PM PDT 24
Peak memory 206144 kb
Host smart-059be2f4-2245-4132-869e-ea3208ba0387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
25349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4264725349
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.4245423809
Short name T1993
Test name
Test status
Simulation time 4804448583 ps
CPU time 46.36 seconds
Started Jul 09 05:11:51 PM PDT 24
Finished Jul 09 05:12:37 PM PDT 24
Peak memory 206296 kb
Host smart-189ca8dc-fa52-47e4-a1fc-8756db6b2f0c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4245423809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.4245423809
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2346311654
Short name T2129
Test name
Test status
Simulation time 198600208 ps
CPU time 0.91 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:11:53 PM PDT 24
Peak memory 206092 kb
Host smart-f8201caa-ae3f-4945-be00-1b28add781a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
11654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2346311654
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2196873398
Short name T701
Test name
Test status
Simulation time 232762171 ps
CPU time 0.94 seconds
Started Jul 09 05:11:53 PM PDT 24
Finished Jul 09 05:11:55 PM PDT 24
Peak memory 206160 kb
Host smart-e0b6c3b2-2a6c-4bad-9793-9e24e65e3c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21968
73398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2196873398
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2460127949
Short name T2565
Test name
Test status
Simulation time 1368677276 ps
CPU time 3.11 seconds
Started Jul 09 05:11:50 PM PDT 24
Finished Jul 09 05:11:54 PM PDT 24
Peak memory 206240 kb
Host smart-bf45ca0e-bba6-4274-be84-4571fc13f581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
27949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2460127949
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1901319123
Short name T2270
Test name
Test status
Simulation time 5681061151 ps
CPU time 53.63 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206396 kb
Host smart-0140f5bd-560b-408b-b8bc-e20f9701bd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19013
19123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1901319123
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3423850805
Short name T1721
Test name
Test status
Simulation time 57798468 ps
CPU time 0.7 seconds
Started Jul 09 05:13:39 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206168 kb
Host smart-5b124518-0b89-4f61-a93b-85ade66aff9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3423850805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3423850805
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.4216815687
Short name T1580
Test name
Test status
Simulation time 3715528536 ps
CPU time 4.32 seconds
Started Jul 09 05:13:23 PM PDT 24
Finished Jul 09 05:13:28 PM PDT 24
Peak memory 206052 kb
Host smart-1e5f98dd-e588-43c7-9542-5a14063be1a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4216815687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.4216815687
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3578174247
Short name T617
Test name
Test status
Simulation time 13371482924 ps
CPU time 12.92 seconds
Started Jul 09 05:13:24 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206200 kb
Host smart-81d05fe0-ffc0-498b-b473-a38e186208c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3578174247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3578174247
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3324292915
Short name T2707
Test name
Test status
Simulation time 23398139207 ps
CPU time 22.09 seconds
Started Jul 09 05:13:27 PM PDT 24
Finished Jul 09 05:13:50 PM PDT 24
Peak memory 206340 kb
Host smart-e6719636-b115-43f8-9e4e-b944130dcc34
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3324292915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3324292915
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.275492354
Short name T823
Test name
Test status
Simulation time 147032692 ps
CPU time 0.83 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206128 kb
Host smart-ce27eba9-bb16-4887-bab9-7ff279d5ffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27549
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.275492354
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2275893617
Short name T2256
Test name
Test status
Simulation time 159425654 ps
CPU time 0.84 seconds
Started Jul 09 05:13:27 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 206148 kb
Host smart-fe8028fc-fc5f-4a36-b7a1-bd7f2a13afce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22758
93617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2275893617
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3482100655
Short name T1247
Test name
Test status
Simulation time 333244198 ps
CPU time 1.21 seconds
Started Jul 09 05:13:27 PM PDT 24
Finished Jul 09 05:13:28 PM PDT 24
Peak memory 206112 kb
Host smart-9fc1b675-44b9-4ab8-9fbb-9573376e920e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34821
00655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3482100655
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3150967147
Short name T2405
Test name
Test status
Simulation time 1494149466 ps
CPU time 3.16 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206352 kb
Host smart-774e0053-9bef-4a5e-ad41-20da97bbdcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
67147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3150967147
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.4278834194
Short name T841
Test name
Test status
Simulation time 22058391143 ps
CPU time 40.27 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 206300 kb
Host smart-26fa94be-c4a2-47b5-adf3-dd502145c2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42788
34194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.4278834194
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2967032189
Short name T659
Test name
Test status
Simulation time 503110464 ps
CPU time 1.54 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206164 kb
Host smart-4bd3832e-09b6-4b9b-b67b-210db48f9f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
32189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2967032189
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.715508942
Short name T2698
Test name
Test status
Simulation time 145536211 ps
CPU time 0.79 seconds
Started Jul 09 05:13:26 PM PDT 24
Finished Jul 09 05:13:27 PM PDT 24
Peak memory 206084 kb
Host smart-d836283a-a5bd-4453-ace3-e9ff4379f114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71550
8942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.715508942
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2727396366
Short name T1888
Test name
Test status
Simulation time 40547378 ps
CPU time 0.64 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206012 kb
Host smart-63f81498-203d-4231-84ba-6af2aa65b022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27273
96366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2727396366
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1442487175
Short name T1743
Test name
Test status
Simulation time 832700631 ps
CPU time 2 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:34 PM PDT 24
Peak memory 206236 kb
Host smart-df479cdd-52b1-416f-9f12-db09e640758b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
87175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1442487175
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.4264295916
Short name T910
Test name
Test status
Simulation time 265152429 ps
CPU time 1.89 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206228 kb
Host smart-43242e68-46ea-4fbd-a73b-25181113baf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
95916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.4264295916
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3521529716
Short name T2703
Test name
Test status
Simulation time 187742815 ps
CPU time 0.86 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:30 PM PDT 24
Peak memory 206084 kb
Host smart-1a9b507e-6ce8-4cae-a69e-90d92970b005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35215
29716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3521529716
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2820850962
Short name T430
Test name
Test status
Simulation time 148522154 ps
CPU time 0.82 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:30 PM PDT 24
Peak memory 206140 kb
Host smart-3e4d6489-4dca-498a-accb-0e99d3268b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
50962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2820850962
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.714423303
Short name T1116
Test name
Test status
Simulation time 225366534 ps
CPU time 0.93 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206124 kb
Host smart-3ac2ce4c-f988-44f9-8d5e-019b1fbbcb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71442
3303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.714423303
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.68547355
Short name T710
Test name
Test status
Simulation time 170578872 ps
CPU time 0.81 seconds
Started Jul 09 05:13:25 PM PDT 24
Finished Jul 09 05:13:26 PM PDT 24
Peak memory 205992 kb
Host smart-2ddfea1a-7182-4dac-9251-98eaf978d778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68547
355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.68547355
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1718033400
Short name T815
Test name
Test status
Simulation time 23364313392 ps
CPU time 24.54 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 206152 kb
Host smart-2db9f497-ffc7-4af2-a44f-a11f11bda9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
33400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1718033400
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3271278057
Short name T482
Test name
Test status
Simulation time 3277305019 ps
CPU time 3.93 seconds
Started Jul 09 05:13:31 PM PDT 24
Finished Jul 09 05:13:36 PM PDT 24
Peak memory 206188 kb
Host smart-ed99e4d9-d737-46cc-8718-d2443fd495fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32712
78057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3271278057
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3519550955
Short name T991
Test name
Test status
Simulation time 8594255355 ps
CPU time 229.97 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206368 kb
Host smart-1411cf2d-b42d-4151-a52d-b138f05f2200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35195
50955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3519550955
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.334736278
Short name T1717
Test name
Test status
Simulation time 6599674659 ps
CPU time 63.77 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:14:34 PM PDT 24
Peak memory 206360 kb
Host smart-b783ab2f-36d8-40f2-b16c-496704e1bb2b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=334736278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.334736278
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2583462770
Short name T1052
Test name
Test status
Simulation time 268135904 ps
CPU time 0.95 seconds
Started Jul 09 05:13:27 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 205996 kb
Host smart-c583bebe-1b3f-4ae7-8452-4016bb83d6f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2583462770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2583462770
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2602347431
Short name T327
Test name
Test status
Simulation time 201069302 ps
CPU time 0.88 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206160 kb
Host smart-436d71dc-7d61-448d-8937-58b83780373f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26023
47431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2602347431
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.592186427
Short name T1578
Test name
Test status
Simulation time 3940794318 ps
CPU time 104.24 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206436 kb
Host smart-396dbbf5-506f-4016-84a6-d1ebed0f8e32
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=592186427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.592186427
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.4285277730
Short name T1070
Test name
Test status
Simulation time 159723442 ps
CPU time 0.79 seconds
Started Jul 09 05:13:31 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206104 kb
Host smart-88b15301-3eca-457a-bb5c-3fb11bd0c0e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4285277730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.4285277730
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.564647111
Short name T2015
Test name
Test status
Simulation time 164658171 ps
CPU time 0.82 seconds
Started Jul 09 05:13:31 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206128 kb
Host smart-3aa5e3fe-a45d-4e6a-9f7e-239a5cd040c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56464
7111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.564647111
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3093786160
Short name T2632
Test name
Test status
Simulation time 173755908 ps
CPU time 0.81 seconds
Started Jul 09 05:13:32 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206020 kb
Host smart-55e929df-4c9a-4664-ac86-71f00ea0e174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30937
86160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3093786160
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2800895067
Short name T1981
Test name
Test status
Simulation time 160021191 ps
CPU time 0.85 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206148 kb
Host smart-1feab1ac-a286-45b4-9676-823687b1ba2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28008
95067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2800895067
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2080397750
Short name T692
Test name
Test status
Simulation time 187390138 ps
CPU time 0.83 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206052 kb
Host smart-20091dd6-4746-487b-8e1f-8fecbc46b4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20803
97750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2080397750
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.749447064
Short name T172
Test name
Test status
Simulation time 206530578 ps
CPU time 0.83 seconds
Started Jul 09 05:13:31 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206132 kb
Host smart-12408d87-dcdf-42c6-87f3-7bd2adad738e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74944
7064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.749447064
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1077407024
Short name T874
Test name
Test status
Simulation time 217438033 ps
CPU time 0.93 seconds
Started Jul 09 05:13:31 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206060 kb
Host smart-e46a8828-d4a7-4087-a6b0-a136849bef1b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1077407024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1077407024
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1500470749
Short name T536
Test name
Test status
Simulation time 169202534 ps
CPU time 0.77 seconds
Started Jul 09 05:13:29 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 205992 kb
Host smart-c8a3ed97-5da0-4322-9150-c81a49a425f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15004
70749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1500470749
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.495193443
Short name T2238
Test name
Test status
Simulation time 83040959 ps
CPU time 0.7 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206088 kb
Host smart-aa5db7b4-7208-4efb-95e3-427b1eed4e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49519
3443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.495193443
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3422138621
Short name T458
Test name
Test status
Simulation time 189939735 ps
CPU time 0.97 seconds
Started Jul 09 05:13:32 PM PDT 24
Finished Jul 09 05:13:34 PM PDT 24
Peak memory 206028 kb
Host smart-85aa1d3a-00e8-40f7-8be1-a4c4c6f97ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221
38621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3422138621
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.4004639026
Short name T1552
Test name
Test status
Simulation time 215780625 ps
CPU time 0.86 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206128 kb
Host smart-97995671-040c-479e-b8f2-0e6f74ea2d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40046
39026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.4004639026
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.4220543364
Short name T977
Test name
Test status
Simulation time 227528566 ps
CPU time 0.91 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:13:32 PM PDT 24
Peak memory 206028 kb
Host smart-1bb20a25-7318-4ad7-b12b-78ea66899aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42205
43364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.4220543364
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1800692568
Short name T634
Test name
Test status
Simulation time 180501439 ps
CPU time 0.84 seconds
Started Jul 09 05:13:35 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 205996 kb
Host smart-6a551c57-3188-4de1-ad81-5701017524bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
92568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1800692568
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2299048078
Short name T2426
Test name
Test status
Simulation time 143454969 ps
CPU time 0.77 seconds
Started Jul 09 05:13:34 PM PDT 24
Finished Jul 09 05:13:36 PM PDT 24
Peak memory 206052 kb
Host smart-19acb427-503e-42f6-8f07-b5636d3b9f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22990
48078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2299048078
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2308094041
Short name T29
Test name
Test status
Simulation time 156265834 ps
CPU time 0.78 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:13:39 PM PDT 24
Peak memory 206120 kb
Host smart-00540048-aad6-4036-ba9d-ecafa3b70193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23080
94041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2308094041
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3230026148
Short name T2364
Test name
Test status
Simulation time 205677541 ps
CPU time 0.81 seconds
Started Jul 09 05:13:35 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206024 kb
Host smart-9f28774f-ea54-4a43-ae54-a0cb160151b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
26148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3230026148
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.839395301
Short name T35
Test name
Test status
Simulation time 224736715 ps
CPU time 1 seconds
Started Jul 09 05:13:36 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206136 kb
Host smart-81f13b1a-2ee8-4102-861e-fdb65aaf0ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83939
5301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.839395301
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2950297469
Short name T2142
Test name
Test status
Simulation time 4993790416 ps
CPU time 134.1 seconds
Started Jul 09 05:13:38 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206420 kb
Host smart-7e1cbe02-ce9b-43e7-ad30-747bdd0d0adf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2950297469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2950297469
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2768764715
Short name T145
Test name
Test status
Simulation time 224032354 ps
CPU time 0.87 seconds
Started Jul 09 05:13:36 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206108 kb
Host smart-f6a5d3c9-9109-4dd8-a65b-ac5f139259c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27687
64715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2768764715
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.880166243
Short name T1082
Test name
Test status
Simulation time 180525755 ps
CPU time 0.83 seconds
Started Jul 09 05:13:38 PM PDT 24
Finished Jul 09 05:13:39 PM PDT 24
Peak memory 206136 kb
Host smart-8c99ec0b-1697-4a4e-b486-da6e98a1ab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88016
6243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.880166243
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1577741599
Short name T1556
Test name
Test status
Simulation time 397590422 ps
CPU time 1.15 seconds
Started Jul 09 05:13:35 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206088 kb
Host smart-00edc115-6e18-4193-abe4-110bdfc58daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
41599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1577741599
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2650731140
Short name T1157
Test name
Test status
Simulation time 5028935599 ps
CPU time 139.98 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206472 kb
Host smart-117fe6e5-ffa9-4d8a-a20e-aeca60f64ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
31140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2650731140
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3694727424
Short name T1169
Test name
Test status
Simulation time 69159089 ps
CPU time 0.73 seconds
Started Jul 09 05:13:48 PM PDT 24
Finished Jul 09 05:13:50 PM PDT 24
Peak memory 206088 kb
Host smart-bc5c0e3c-f6f4-4ff3-9428-bf2673ba5fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3694727424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3694727424
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.587284643
Short name T2002
Test name
Test status
Simulation time 3959316129 ps
CPU time 4.71 seconds
Started Jul 09 05:13:38 PM PDT 24
Finished Jul 09 05:13:44 PM PDT 24
Peak memory 206104 kb
Host smart-e33bad54-aaa4-4fad-a304-0931a60b98d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=587284643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.587284643
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1539123308
Short name T524
Test name
Test status
Simulation time 13339880732 ps
CPU time 15.85 seconds
Started Jul 09 05:13:36 PM PDT 24
Finished Jul 09 05:13:52 PM PDT 24
Peak memory 206088 kb
Host smart-380a9388-0841-4f3c-8542-b911cc3e2497
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1539123308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1539123308
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.359287331
Short name T1584
Test name
Test status
Simulation time 23348065479 ps
CPU time 22.64 seconds
Started Jul 09 05:13:38 PM PDT 24
Finished Jul 09 05:14:01 PM PDT 24
Peak memory 206040 kb
Host smart-7714668c-5745-49f7-90c2-8ca15a8a5636
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=359287331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.359287331
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1345685782
Short name T660
Test name
Test status
Simulation time 184306209 ps
CPU time 0.82 seconds
Started Jul 09 05:13:35 PM PDT 24
Finished Jul 09 05:13:36 PM PDT 24
Peak memory 206048 kb
Host smart-7a904554-b5cd-4d37-8a81-8d362b7c525a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13456
85782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1345685782
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3229205641
Short name T2477
Test name
Test status
Simulation time 199440595 ps
CPU time 0.83 seconds
Started Jul 09 05:13:36 PM PDT 24
Finished Jul 09 05:13:38 PM PDT 24
Peak memory 206160 kb
Host smart-56a20272-61fa-4ea9-90a7-5565c0cd8b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32292
05641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3229205641
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2805700316
Short name T863
Test name
Test status
Simulation time 243402217 ps
CPU time 1.02 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206124 kb
Host smart-76739c9a-5beb-41f7-b49d-c277420b9c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28057
00316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2805700316
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3681290395
Short name T2369
Test name
Test status
Simulation time 531637163 ps
CPU time 1.56 seconds
Started Jul 09 05:13:40 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206112 kb
Host smart-163645ab-0389-4795-adb1-27b9c0c25216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36812
90395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3681290395
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2989254542
Short name T2652
Test name
Test status
Simulation time 19134810677 ps
CPU time 36.08 seconds
Started Jul 09 05:13:40 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206416 kb
Host smart-b91fb460-c637-4dbd-ba83-3cc532c4c19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
54542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2989254542
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.310025012
Short name T1746
Test name
Test status
Simulation time 440542553 ps
CPU time 1.4 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:13:39 PM PDT 24
Peak memory 206104 kb
Host smart-42e54c99-5df9-4948-a0f3-047c9ca577ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31002
5012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.310025012
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2135852570
Short name T767
Test name
Test status
Simulation time 142600762 ps
CPU time 0.77 seconds
Started Jul 09 05:13:40 PM PDT 24
Finished Jul 09 05:13:42 PM PDT 24
Peak memory 206108 kb
Host smart-51ac957c-4922-4184-aa97-132bf68c5af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
52570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2135852570
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1550255710
Short name T756
Test name
Test status
Simulation time 72196421 ps
CPU time 0.67 seconds
Started Jul 09 05:13:39 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 205956 kb
Host smart-1be71ee1-3178-469e-bff8-5b2564576c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
55710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1550255710
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2614303367
Short name T859
Test name
Test status
Simulation time 897638933 ps
CPU time 2.16 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206360 kb
Host smart-f236dc79-4541-42cc-98da-e87c4e335b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143
03367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2614303367
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2129142565
Short name T1573
Test name
Test status
Simulation time 235181819 ps
CPU time 0.91 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 205952 kb
Host smart-a5656cb9-3a21-48ff-87af-7f14a9ba9589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291
42565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2129142565
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1262685194
Short name T1087
Test name
Test status
Simulation time 177510713 ps
CPU time 0.82 seconds
Started Jul 09 05:13:39 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206012 kb
Host smart-fa68daf3-2e06-461b-8c58-e3677ab73b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12626
85194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1262685194
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1111592622
Short name T2559
Test name
Test status
Simulation time 190664814 ps
CPU time 0.81 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206120 kb
Host smart-9a5f02ef-deab-4f09-a0ee-80c84d5684e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11115
92622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1111592622
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1387487619
Short name T362
Test name
Test status
Simulation time 194999380 ps
CPU time 0.84 seconds
Started Jul 09 05:13:39 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206056 kb
Host smart-bc78bfce-4075-4d50-bc00-ffc0ca2d506b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13874
87619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1387487619
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.729106681
Short name T1820
Test name
Test status
Simulation time 23329405363 ps
CPU time 25.7 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:14:04 PM PDT 24
Peak memory 206124 kb
Host smart-8df918f6-af53-42ec-912c-b7c07891ed81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72910
6681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.729106681
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1891952112
Short name T620
Test name
Test status
Simulation time 3332304012 ps
CPU time 3.82 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:13:42 PM PDT 24
Peak memory 206132 kb
Host smart-dcea5f2d-2532-4179-ad60-89319e3ca0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18919
52112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1891952112
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3847676129
Short name T773
Test name
Test status
Simulation time 10180805691 ps
CPU time 287.18 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:18:30 PM PDT 24
Peak memory 206436 kb
Host smart-abe03637-feec-4c35-a689-8ba33c9fa52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3847676129
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3948495316
Short name T1266
Test name
Test status
Simulation time 4194199640 ps
CPU time 117.35 seconds
Started Jul 09 05:13:40 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 206388 kb
Host smart-f1edfa5d-88c9-4e74-bd22-bbdc6675bf1a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3948495316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3948495316
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2372463094
Short name T771
Test name
Test status
Simulation time 248636064 ps
CPU time 0.9 seconds
Started Jul 09 05:13:38 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206088 kb
Host smart-ccfcd732-38ed-4adf-aeec-9ab9a658bf97
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2372463094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2372463094
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2218316448
Short name T454
Test name
Test status
Simulation time 186866828 ps
CPU time 0.86 seconds
Started Jul 09 05:13:37 PM PDT 24
Finished Jul 09 05:13:39 PM PDT 24
Peak memory 206064 kb
Host smart-40e8d154-cb88-45ea-8d91-e53d61af699f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22183
16448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2218316448
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2621384301
Short name T451
Test name
Test status
Simulation time 5697605015 ps
CPU time 170.16 seconds
Started Jul 09 05:13:43 PM PDT 24
Finished Jul 09 05:16:34 PM PDT 24
Peak memory 206288 kb
Host smart-8cf9789a-4793-4858-81db-602f7fb974c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26213
84301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2621384301
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.2736814196
Short name T336
Test name
Test status
Simulation time 5034776394 ps
CPU time 50.01 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206276 kb
Host smart-ac801032-b086-4aad-a56d-1b616e1c1994
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2736814196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.2736814196
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.60156524
Short name T957
Test name
Test status
Simulation time 150811160 ps
CPU time 0.8 seconds
Started Jul 09 05:13:43 PM PDT 24
Finished Jul 09 05:13:44 PM PDT 24
Peak memory 206044 kb
Host smart-cf960e08-2f4b-4027-85f6-d7d9ceee5fdb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=60156524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.60156524
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2474036964
Short name T466
Test name
Test status
Simulation time 180060676 ps
CPU time 0.8 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:44 PM PDT 24
Peak memory 206112 kb
Host smart-aa20c15b-8421-4050-a611-7f52ae237f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24740
36964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2474036964
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2441550731
Short name T2298
Test name
Test status
Simulation time 224919354 ps
CPU time 0.88 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:44 PM PDT 24
Peak memory 206020 kb
Host smart-ee9413f2-f8a3-4153-9bb9-6d5e097472fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24415
50731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2441550731
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.265864455
Short name T2052
Test name
Test status
Simulation time 198081153 ps
CPU time 0.91 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206108 kb
Host smart-5371fe85-5816-4856-868c-4686dfd80913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26586
4455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.265864455
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1209269929
Short name T1449
Test name
Test status
Simulation time 167940439 ps
CPU time 0.79 seconds
Started Jul 09 05:13:43 PM PDT 24
Finished Jul 09 05:13:45 PM PDT 24
Peak memory 206108 kb
Host smart-8cad5253-0a9e-40d8-a882-a0d379081570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
69929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1209269929
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2692776894
Short name T2124
Test name
Test status
Simulation time 189779785 ps
CPU time 0.87 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206132 kb
Host smart-7a3c757e-9c1f-4e97-9e41-e1f57dfec152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26927
76894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2692776894
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1333320447
Short name T1375
Test name
Test status
Simulation time 141312136 ps
CPU time 0.85 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:44 PM PDT 24
Peak memory 206148 kb
Host smart-89c0ac8b-ad20-465f-a22c-ffefd1e9baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
20447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1333320447
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2361107353
Short name T1040
Test name
Test status
Simulation time 219030310 ps
CPU time 0.96 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206116 kb
Host smart-aeac09d5-b40f-4920-ab2f-fe2175e6c54c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2361107353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2361107353
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1429965169
Short name T1943
Test name
Test status
Simulation time 209928529 ps
CPU time 0.81 seconds
Started Jul 09 05:13:45 PM PDT 24
Finished Jul 09 05:13:46 PM PDT 24
Peak memory 206004 kb
Host smart-3439689c-4b2b-4659-9061-30b25288c937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299
65169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1429965169
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.879516342
Short name T2205
Test name
Test status
Simulation time 75937856 ps
CPU time 0.68 seconds
Started Jul 09 05:13:42 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206132 kb
Host smart-d5414ad4-aa1f-40ff-8931-1ac4f6131815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87951
6342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.879516342
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.86873371
Short name T87
Test name
Test status
Simulation time 7909539083 ps
CPU time 17.55 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:14:00 PM PDT 24
Peak memory 206468 kb
Host smart-2cc00678-9bb2-4c47-8d55-96b0f4a45c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86873
371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.86873371
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2842737517
Short name T2450
Test name
Test status
Simulation time 228848329 ps
CPU time 0.88 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206156 kb
Host smart-e6e5f45d-e2a7-456d-abde-3bd5a68e2f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
37517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2842737517
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4284101930
Short name T626
Test name
Test status
Simulation time 202555732 ps
CPU time 0.83 seconds
Started Jul 09 05:13:44 PM PDT 24
Finished Jul 09 05:13:45 PM PDT 24
Peak memory 206064 kb
Host smart-2134e71f-bfa6-4053-b7a8-61cab528e73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
01930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4284101930
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.205037749
Short name T1399
Test name
Test status
Simulation time 178445465 ps
CPU time 0.82 seconds
Started Jul 09 05:13:41 PM PDT 24
Finished Jul 09 05:13:43 PM PDT 24
Peak memory 206108 kb
Host smart-358bbcac-8be6-43a6-ac21-fdda4751f512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20503
7749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.205037749
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.379110255
Short name T1265
Test name
Test status
Simulation time 212902011 ps
CPU time 0.84 seconds
Started Jul 09 05:13:47 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206124 kb
Host smart-99a23231-1f0d-47fa-9084-a480ef478703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37911
0255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.379110255
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.316845673
Short name T1409
Test name
Test status
Simulation time 183217330 ps
CPU time 0.83 seconds
Started Jul 09 05:13:53 PM PDT 24
Finished Jul 09 05:13:54 PM PDT 24
Peak memory 206108 kb
Host smart-8a3255a1-8e5b-42dc-bd08-5e7ed1ab7565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
5673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.316845673
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4152753399
Short name T652
Test name
Test status
Simulation time 176139611 ps
CPU time 0.77 seconds
Started Jul 09 05:13:45 PM PDT 24
Finished Jul 09 05:13:46 PM PDT 24
Peak memory 206088 kb
Host smart-cb09a2a7-b51a-4739-a1fe-aad15054c531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41527
53399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4152753399
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.117270798
Short name T1080
Test name
Test status
Simulation time 197483887 ps
CPU time 0.9 seconds
Started Jul 09 05:13:45 PM PDT 24
Finished Jul 09 05:13:46 PM PDT 24
Peak memory 205992 kb
Host smart-1abd672e-6b0a-4180-a744-ec91d6bdaaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11727
0798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.117270798
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.566279501
Short name T1133
Test name
Test status
Simulation time 219618422 ps
CPU time 0.96 seconds
Started Jul 09 05:13:46 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206084 kb
Host smart-dc03c273-991d-4f38-b1de-716713c97c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56627
9501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.566279501
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1972930179
Short name T2667
Test name
Test status
Simulation time 5140667483 ps
CPU time 148.89 seconds
Started Jul 09 05:13:49 PM PDT 24
Finished Jul 09 05:16:18 PM PDT 24
Peak memory 206452 kb
Host smart-0edc89f4-d65f-48dd-b8dc-3e39f340e575
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1972930179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1972930179
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3467976134
Short name T1152
Test name
Test status
Simulation time 203920565 ps
CPU time 0.86 seconds
Started Jul 09 05:13:47 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206164 kb
Host smart-631ed0ee-4b52-4f33-9cd6-7b289c4eb04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
76134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3467976134
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1309194384
Short name T2319
Test name
Test status
Simulation time 156583003 ps
CPU time 0.79 seconds
Started Jul 09 05:13:45 PM PDT 24
Finished Jul 09 05:13:46 PM PDT 24
Peak memory 206004 kb
Host smart-7196f28c-43a5-4bec-80f4-1e3a6f81053f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13091
94384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1309194384
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1185339481
Short name T1050
Test name
Test status
Simulation time 423050191 ps
CPU time 1.22 seconds
Started Jul 09 05:13:46 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206088 kb
Host smart-89d46100-7f88-45d2-8a63-fd546d8324c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11853
39481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1185339481
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1409908992
Short name T1517
Test name
Test status
Simulation time 5520961841 ps
CPU time 158.82 seconds
Started Jul 09 05:13:43 PM PDT 24
Finished Jul 09 05:16:22 PM PDT 24
Peak memory 206368 kb
Host smart-72dc275d-dc4d-43a0-bb7c-d0c7978c9510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14099
08992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1409908992
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.135274043
Short name T1187
Test name
Test status
Simulation time 81536495 ps
CPU time 0.76 seconds
Started Jul 09 05:14:00 PM PDT 24
Finished Jul 09 05:14:02 PM PDT 24
Peak memory 206452 kb
Host smart-98d61cff-72fb-42c5-82f4-73ebabc48c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=135274043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.135274043
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3385074153
Short name T476
Test name
Test status
Simulation time 4049271756 ps
CPU time 4.97 seconds
Started Jul 09 05:13:45 PM PDT 24
Finished Jul 09 05:13:51 PM PDT 24
Peak memory 206292 kb
Host smart-3774a8df-a1b1-40f8-95f7-8ee049950cbf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3385074153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3385074153
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.299527536
Short name T2653
Test name
Test status
Simulation time 13381189037 ps
CPU time 13.45 seconds
Started Jul 09 05:13:46 PM PDT 24
Finished Jul 09 05:14:00 PM PDT 24
Peak memory 206072 kb
Host smart-a8e17b83-b310-4c18-a71f-44dfe3100bb1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=299527536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.299527536
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.4236496250
Short name T722
Test name
Test status
Simulation time 23403349372 ps
CPU time 26.97 seconds
Started Jul 09 05:13:44 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 206180 kb
Host smart-01f37083-a40c-4592-8645-075552657eca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4236496250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.4236496250
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3961312671
Short name T1886
Test name
Test status
Simulation time 193680901 ps
CPU time 0.83 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 206056 kb
Host smart-700ff23e-d616-4c28-b8f9-32502e8669f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
12671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3961312671
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2593705997
Short name T1415
Test name
Test status
Simulation time 153298766 ps
CPU time 0.87 seconds
Started Jul 09 05:13:50 PM PDT 24
Finished Jul 09 05:13:52 PM PDT 24
Peak memory 206148 kb
Host smart-39d114e9-f82d-4ff0-9f88-f75c573ff0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25937
05997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2593705997
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3044520989
Short name T2085
Test name
Test status
Simulation time 476563604 ps
CPU time 1.46 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 206160 kb
Host smart-9ceb474a-eba3-4a71-a5d6-0d27f7f84e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
20989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3044520989
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3621533498
Short name T2336
Test name
Test status
Simulation time 878986774 ps
CPU time 1.95 seconds
Started Jul 09 05:13:50 PM PDT 24
Finished Jul 09 05:13:52 PM PDT 24
Peak memory 206356 kb
Host smart-02ec0411-7472-48b5-ad59-0c16c297a54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
33498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3621533498
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1725578965
Short name T1203
Test name
Test status
Simulation time 21549659707 ps
CPU time 40.45 seconds
Started Jul 09 05:13:50 PM PDT 24
Finished Jul 09 05:14:31 PM PDT 24
Peak memory 206324 kb
Host smart-c99dffda-f4fb-461c-89fa-b4ae0f603766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17255
78965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1725578965
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.881438043
Short name T1382
Test name
Test status
Simulation time 373844475 ps
CPU time 1.27 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 206168 kb
Host smart-8e09517f-1008-476a-983a-9881bd8ce6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88143
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.881438043
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.1119298247
Short name T588
Test name
Test status
Simulation time 138697904 ps
CPU time 0.81 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:52 PM PDT 24
Peak memory 206164 kb
Host smart-e6d8a13e-09b0-46bf-a0d9-9ae6dd6e221c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192
98247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.1119298247
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2320245740
Short name T818
Test name
Test status
Simulation time 35823303 ps
CPU time 0.66 seconds
Started Jul 09 05:13:49 PM PDT 24
Finished Jul 09 05:13:50 PM PDT 24
Peak memory 206052 kb
Host smart-78597f15-f1ce-44bc-91d6-bc2faf8862cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
45740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2320245740
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1271486090
Short name T2032
Test name
Test status
Simulation time 943295789 ps
CPU time 2.48 seconds
Started Jul 09 05:13:50 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 206380 kb
Host smart-1e89e816-4ea7-48e8-86b4-7a09bec9e3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12714
86090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1271486090
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1339725990
Short name T2159
Test name
Test status
Simulation time 312996668 ps
CPU time 2.2 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:54 PM PDT 24
Peak memory 206388 kb
Host smart-6f294cf3-5ca5-479f-8c09-ff73eb900f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13397
25990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1339725990
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.15705408
Short name T2456
Test name
Test status
Simulation time 182780763 ps
CPU time 0.88 seconds
Started Jul 09 05:13:52 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 205956 kb
Host smart-1b702be8-c3ab-4cb9-9ed0-8f32d21f8d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15705
408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.15705408
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1445281315
Short name T1434
Test name
Test status
Simulation time 139074834 ps
CPU time 0.77 seconds
Started Jul 09 05:13:53 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 206368 kb
Host smart-d94fffea-a2b5-46f3-9bc0-02c53a233f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14452
81315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1445281315
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2760324425
Short name T1805
Test name
Test status
Simulation time 229796756 ps
CPU time 1.01 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 205960 kb
Host smart-70beff8c-41a4-4a74-8724-4c499c1f78c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27603
24425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2760324425
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3757340133
Short name T1742
Test name
Test status
Simulation time 8885193654 ps
CPU time 257.07 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206444 kb
Host smart-1a536348-b520-4a1b-88fc-16b731e600b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3757340133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3757340133
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2585425094
Short name T1383
Test name
Test status
Simulation time 191764540 ps
CPU time 0.83 seconds
Started Jul 09 05:13:53 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 206372 kb
Host smart-094549f0-a596-40db-a4b5-40a6b93ae730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
25094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2585425094
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2646689282
Short name T2100
Test name
Test status
Simulation time 23366660931 ps
CPU time 25.76 seconds
Started Jul 09 05:13:50 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206096 kb
Host smart-72aca4cc-c2cc-4fa0-9312-634a6e8565c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26466
89282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2646689282
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2433813402
Short name T2608
Test name
Test status
Simulation time 3288007032 ps
CPU time 3.68 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 206120 kb
Host smart-fb02cb48-189a-4679-866f-9893fd3e3801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24338
13402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2433813402
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.4016408102
Short name T1381
Test name
Test status
Simulation time 9204775567 ps
CPU time 243.68 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206468 kb
Host smart-d423fdde-acc3-4d26-97ce-0a2b4243de94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40164
08102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.4016408102
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2737166776
Short name T1788
Test name
Test status
Simulation time 3553470944 ps
CPU time 98.44 seconds
Started Jul 09 05:14:02 PM PDT 24
Finished Jul 09 05:15:42 PM PDT 24
Peak memory 206400 kb
Host smart-e28edd52-c918-44fc-b9f4-fc0e039e37b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2737166776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2737166776
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2493278420
Short name T437
Test name
Test status
Simulation time 239639556 ps
CPU time 0.92 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 206144 kb
Host smart-fe8dea8f-192d-4cc6-b96b-8f41a044c323
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2493278420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2493278420
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2703065742
Short name T1089
Test name
Test status
Simulation time 191963421 ps
CPU time 0.88 seconds
Started Jul 09 05:13:50 PM PDT 24
Finished Jul 09 05:13:52 PM PDT 24
Peak memory 206112 kb
Host smart-170573dc-78a7-41ae-ba96-0efb653331b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27030
65742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2703065742
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2784683992
Short name T1072
Test name
Test status
Simulation time 4143254924 ps
CPU time 117.48 seconds
Started Jul 09 05:13:51 PM PDT 24
Finished Jul 09 05:15:49 PM PDT 24
Peak memory 206424 kb
Host smart-cded8b83-aead-4cee-a881-8d673f4660ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
83992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2784683992
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2658722977
Short name T842
Test name
Test status
Simulation time 6147204763 ps
CPU time 46.86 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206296 kb
Host smart-03f8e597-681f-40b9-b3bd-e329d37348d0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2658722977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2658722977
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2975776240
Short name T937
Test name
Test status
Simulation time 146228194 ps
CPU time 0.8 seconds
Started Jul 09 05:13:55 PM PDT 24
Finished Jul 09 05:13:57 PM PDT 24
Peak memory 206060 kb
Host smart-815ec2a7-d47d-4946-93cd-c983568551bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2975776240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2975776240
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.774584258
Short name T1907
Test name
Test status
Simulation time 144741586 ps
CPU time 0.79 seconds
Started Jul 09 05:13:57 PM PDT 24
Finished Jul 09 05:13:58 PM PDT 24
Peak memory 206152 kb
Host smart-1fcedd2e-80b8-4864-bd96-723df97a56ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77458
4258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.774584258
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.4077047168
Short name T2114
Test name
Test status
Simulation time 179358616 ps
CPU time 0.91 seconds
Started Jul 09 05:13:53 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 205988 kb
Host smart-2b618b9c-caa2-4591-bc25-61a12003e518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
47168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.4077047168
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3974395861
Short name T714
Test name
Test status
Simulation time 153207224 ps
CPU time 0.75 seconds
Started Jul 09 05:13:55 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 206160 kb
Host smart-9db888fd-1fcd-4aeb-979b-aef6700649ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39743
95861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3974395861
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.980165096
Short name T1315
Test name
Test status
Simulation time 159980808 ps
CPU time 0.8 seconds
Started Jul 09 05:13:53 PM PDT 24
Finished Jul 09 05:13:54 PM PDT 24
Peak memory 206016 kb
Host smart-625a2189-e7ec-41a5-8a40-5245ee09e044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98016
5096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.980165096
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1622841315
Short name T2519
Test name
Test status
Simulation time 155576467 ps
CPU time 0.76 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:13:57 PM PDT 24
Peak memory 206060 kb
Host smart-95261d0c-8c37-469b-962a-959da2e0cfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
41315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1622841315
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.741866592
Short name T2197
Test name
Test status
Simulation time 201639328 ps
CPU time 0.89 seconds
Started Jul 09 05:13:54 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 206044 kb
Host smart-8c8b31c6-6fce-4b82-af65-cc1680413192
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=741866592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.741866592
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.630481505
Short name T2316
Test name
Test status
Simulation time 154785354 ps
CPU time 0.8 seconds
Started Jul 09 05:13:54 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 206108 kb
Host smart-d2f8d628-33e4-4b15-8256-3bf916e1cc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63048
1505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.630481505
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.644722894
Short name T1654
Test name
Test status
Simulation time 11697378239 ps
CPU time 24.39 seconds
Started Jul 09 05:13:57 PM PDT 24
Finished Jul 09 05:14:22 PM PDT 24
Peak memory 206492 kb
Host smart-cf80f31f-3237-4107-b62e-25b5585a514f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64472
2894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.644722894
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1130045713
Short name T1784
Test name
Test status
Simulation time 189457488 ps
CPU time 0.83 seconds
Started Jul 09 05:13:57 PM PDT 24
Finished Jul 09 05:13:58 PM PDT 24
Peak memory 206044 kb
Host smart-bc073332-da1b-4e46-8145-84e5678fae06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11300
45713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1130045713
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2495614356
Short name T1134
Test name
Test status
Simulation time 161423040 ps
CPU time 0.86 seconds
Started Jul 09 05:13:54 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 206368 kb
Host smart-d623b877-2c3b-49ae-a4b8-42901eae73d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24956
14356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2495614356
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3653541463
Short name T539
Test name
Test status
Simulation time 191297555 ps
CPU time 0.86 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:13:58 PM PDT 24
Peak memory 206060 kb
Host smart-f91bf18b-648a-4779-9e63-b613e8f7da9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
41463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3653541463
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2512355750
Short name T1410
Test name
Test status
Simulation time 166266268 ps
CPU time 0.82 seconds
Started Jul 09 05:13:57 PM PDT 24
Finished Jul 09 05:13:59 PM PDT 24
Peak memory 206096 kb
Host smart-64ca1b71-895d-4b6d-a66f-9658aada7d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25123
55750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2512355750
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.4261821418
Short name T1252
Test name
Test status
Simulation time 189565409 ps
CPU time 0.82 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:13:58 PM PDT 24
Peak memory 206120 kb
Host smart-a5329376-3bfa-4f89-b3cc-0424b2b9aa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42618
21418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.4261821418
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3708003427
Short name T1557
Test name
Test status
Simulation time 245402816 ps
CPU time 0.89 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:13:57 PM PDT 24
Peak memory 206152 kb
Host smart-570d1233-8d91-49e3-b213-e17fb0920556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37080
03427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3708003427
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.514712943
Short name T783
Test name
Test status
Simulation time 217512443 ps
CPU time 0.84 seconds
Started Jul 09 05:13:54 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 205956 kb
Host smart-db6379ad-ca6a-4b3c-8102-47871b4b3d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51471
2943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.514712943
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.375431055
Short name T426
Test name
Test status
Simulation time 240409003 ps
CPU time 0.96 seconds
Started Jul 09 05:13:55 PM PDT 24
Finished Jul 09 05:13:56 PM PDT 24
Peak memory 206144 kb
Host smart-527ccb76-e2ff-453c-a580-2f1ac8d0c42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
1055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.375431055
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3702563345
Short name T542
Test name
Test status
Simulation time 4161990891 ps
CPU time 27.9 seconds
Started Jul 09 05:13:54 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 206632 kb
Host smart-5950a9f1-6ba3-40fd-bfc0-db82fd9e44bc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3702563345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3702563345
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2715587266
Short name T446
Test name
Test status
Simulation time 155426379 ps
CPU time 0.83 seconds
Started Jul 09 05:13:55 PM PDT 24
Finished Jul 09 05:13:57 PM PDT 24
Peak memory 206068 kb
Host smart-fc0e0740-366e-4288-9acb-babe32cba1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27155
87266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2715587266
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2619573706
Short name T845
Test name
Test status
Simulation time 175081479 ps
CPU time 0.85 seconds
Started Jul 09 05:13:59 PM PDT 24
Finished Jul 09 05:14:01 PM PDT 24
Peak memory 206116 kb
Host smart-a6be31eb-662b-48b6-a64c-5f84cdabf82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26195
73706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2619573706
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.1529771352
Short name T1347
Test name
Test status
Simulation time 270590053 ps
CPU time 1.02 seconds
Started Jul 09 05:13:57 PM PDT 24
Finished Jul 09 05:13:59 PM PDT 24
Peak memory 206156 kb
Host smart-49465ea2-8cdc-4c27-a296-9e8ce564455f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15297
71352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1529771352
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3020157625
Short name T1123
Test name
Test status
Simulation time 6542663810 ps
CPU time 191.96 seconds
Started Jul 09 05:14:00 PM PDT 24
Finished Jul 09 05:17:13 PM PDT 24
Peak memory 206440 kb
Host smart-9ccd986e-2131-4f3f-b6a9-0da47168a5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201
57625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3020157625
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.976298210
Short name T211
Test name
Test status
Simulation time 48787884 ps
CPU time 0.69 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206092 kb
Host smart-f1702eef-a782-4181-9612-018b3867d0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=976298210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.976298210
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2791001989
Short name T1034
Test name
Test status
Simulation time 4173054126 ps
CPU time 5.17 seconds
Started Jul 09 05:13:58 PM PDT 24
Finished Jul 09 05:14:04 PM PDT 24
Peak memory 206360 kb
Host smart-e7d41a56-62d1-47dd-827a-7bb2478301e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2791001989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2791001989
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3127979891
Short name T15
Test name
Test status
Simulation time 13412008003 ps
CPU time 16.79 seconds
Started Jul 09 05:13:59 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206172 kb
Host smart-1b36aaf3-ce4f-4542-9075-08f3d1cf95c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3127979891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3127979891
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.946306199
Short name T1142
Test name
Test status
Simulation time 23304588591 ps
CPU time 23.18 seconds
Started Jul 09 05:13:58 PM PDT 24
Finished Jul 09 05:14:22 PM PDT 24
Peak memory 206184 kb
Host smart-be931e7c-8789-47c8-ab20-6a2207635f4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=946306199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.946306199
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1255695948
Short name T1871
Test name
Test status
Simulation time 157916526 ps
CPU time 0.83 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:13:58 PM PDT 24
Peak memory 206156 kb
Host smart-d8f4eabc-2b4d-4e01-9770-53a757dadfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12556
95948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1255695948
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2638204178
Short name T2126
Test name
Test status
Simulation time 152912694 ps
CPU time 0.79 seconds
Started Jul 09 05:13:59 PM PDT 24
Finished Jul 09 05:14:01 PM PDT 24
Peak memory 206116 kb
Host smart-72b84241-abf8-429f-964d-cc11b7ed34fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26382
04178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2638204178
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1695245550
Short name T631
Test name
Test status
Simulation time 388695305 ps
CPU time 1.34 seconds
Started Jul 09 05:13:56 PM PDT 24
Finished Jul 09 05:13:58 PM PDT 24
Peak memory 206064 kb
Host smart-36fc0a81-c61d-432b-a3a5-50c693d5207e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16952
45550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1695245550
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.160360555
Short name T1958
Test name
Test status
Simulation time 263284431 ps
CPU time 0.94 seconds
Started Jul 09 05:14:00 PM PDT 24
Finished Jul 09 05:14:02 PM PDT 24
Peak memory 206128 kb
Host smart-7bdb27b5-5bf0-4885-91ca-d0d6fdb32783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
0555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.160360555
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.2339155779
Short name T589
Test name
Test status
Simulation time 18116329113 ps
CPU time 36.72 seconds
Started Jul 09 05:14:00 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206444 kb
Host smart-f3371d71-baf2-4cae-9200-c39dcc834ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391
55779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.2339155779
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2094583580
Short name T786
Test name
Test status
Simulation time 347464652 ps
CPU time 1.29 seconds
Started Jul 09 05:13:58 PM PDT 24
Finished Jul 09 05:14:00 PM PDT 24
Peak memory 206096 kb
Host smart-2f206d6a-0f69-4649-a9c0-bea029f86482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
83580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2094583580
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.4025367256
Short name T2017
Test name
Test status
Simulation time 144418377 ps
CPU time 0.74 seconds
Started Jul 09 05:13:59 PM PDT 24
Finished Jul 09 05:14:01 PM PDT 24
Peak memory 206060 kb
Host smart-cd40e908-f03a-4f5e-899d-c0b44e0eee36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
67256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.4025367256
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.447291026
Short name T2213
Test name
Test status
Simulation time 49398771 ps
CPU time 0.7 seconds
Started Jul 09 05:13:59 PM PDT 24
Finished Jul 09 05:14:01 PM PDT 24
Peak memory 206056 kb
Host smart-a2ada44e-876e-4bb8-9da7-b8f4235394da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44729
1026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.447291026
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2277543267
Short name T31
Test name
Test status
Simulation time 904029759 ps
CPU time 2.1 seconds
Started Jul 09 05:13:59 PM PDT 24
Finished Jul 09 05:14:02 PM PDT 24
Peak memory 206372 kb
Host smart-91c6c16e-ac89-41a1-b0a4-7c27b95e006b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22775
43267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2277543267
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2136181684
Short name T2592
Test name
Test status
Simulation time 456610868 ps
CPU time 2.71 seconds
Started Jul 09 05:14:02 PM PDT 24
Finished Jul 09 05:14:06 PM PDT 24
Peak memory 206352 kb
Host smart-1fff46e2-8093-427b-ac3e-fe4b28dd5460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21361
81684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2136181684
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2829677445
Short name T1340
Test name
Test status
Simulation time 186128593 ps
CPU time 0.96 seconds
Started Jul 09 05:14:01 PM PDT 24
Finished Jul 09 05:14:03 PM PDT 24
Peak memory 206116 kb
Host smart-fe9ce11f-8c59-4a08-8cc9-2f124d6b673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28296
77445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2829677445
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3256455087
Short name T1469
Test name
Test status
Simulation time 170453668 ps
CPU time 0.84 seconds
Started Jul 09 05:14:02 PM PDT 24
Finished Jul 09 05:14:04 PM PDT 24
Peak memory 206136 kb
Host smart-83e10b5d-371c-4e4e-8689-71112ea195bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32564
55087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3256455087
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1299735805
Short name T421
Test name
Test status
Simulation time 252869196 ps
CPU time 1.02 seconds
Started Jul 09 05:14:02 PM PDT 24
Finished Jul 09 05:14:04 PM PDT 24
Peak memory 206144 kb
Host smart-01c7c54c-37fb-4d0b-9def-5c1c31e50455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12997
35805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1299735805
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.406201914
Short name T890
Test name
Test status
Simulation time 4934826908 ps
CPU time 127.31 seconds
Started Jul 09 05:14:04 PM PDT 24
Finished Jul 09 05:16:12 PM PDT 24
Peak memory 206424 kb
Host smart-2c2255d6-a799-483d-ba93-3b0a3f18c540
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=406201914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.406201914
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3291044997
Short name T1636
Test name
Test status
Simulation time 169585790 ps
CPU time 0.79 seconds
Started Jul 09 05:14:03 PM PDT 24
Finished Jul 09 05:14:05 PM PDT 24
Peak memory 206140 kb
Host smart-1cfa5c32-066e-4530-962b-bce015335c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32910
44997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3291044997
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1744801555
Short name T2407
Test name
Test status
Simulation time 23262664833 ps
CPU time 23.76 seconds
Started Jul 09 05:14:02 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206128 kb
Host smart-6c7bdc8a-12c8-4c50-8e40-b1b4352f32cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17448
01555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1744801555
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2077885030
Short name T641
Test name
Test status
Simulation time 3332459349 ps
CPU time 4.18 seconds
Started Jul 09 05:14:02 PM PDT 24
Finished Jul 09 05:14:08 PM PDT 24
Peak memory 206204 kb
Host smart-d1697e11-9895-4d52-b898-890ecf238d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20778
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2077885030
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2310500035
Short name T768
Test name
Test status
Simulation time 8303902752 ps
CPU time 64.78 seconds
Started Jul 09 05:14:00 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206476 kb
Host smart-4e4c4ac9-2ed1-466b-9629-e1ee8e41ad1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
00035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2310500035
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3591719172
Short name T878
Test name
Test status
Simulation time 5815334913 ps
CPU time 167.83 seconds
Started Jul 09 05:14:01 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206368 kb
Host smart-72b6c1ae-d4bb-4fb7-a619-84b0a48d22a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3591719172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3591719172
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2725378635
Short name T585
Test name
Test status
Simulation time 239166561 ps
CPU time 0.93 seconds
Started Jul 09 05:14:08 PM PDT 24
Finished Jul 09 05:14:09 PM PDT 24
Peak memory 206120 kb
Host smart-a6a02bc5-a559-4bea-98b4-66f2d789449d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2725378635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2725378635
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3645094719
Short name T750
Test name
Test status
Simulation time 190324065 ps
CPU time 0.9 seconds
Started Jul 09 05:14:08 PM PDT 24
Finished Jul 09 05:14:10 PM PDT 24
Peak memory 206020 kb
Host smart-b6971a45-36b4-4ceb-a063-2875d4025e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450
94719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3645094719
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1419468598
Short name T405
Test name
Test status
Simulation time 4947983092 ps
CPU time 141.54 seconds
Started Jul 09 05:14:08 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 206408 kb
Host smart-6366edd0-94a1-437d-b9cd-4fd832decba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
68598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1419468598
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.903606381
Short name T2165
Test name
Test status
Simulation time 3980045818 ps
CPU time 112.01 seconds
Started Jul 09 05:14:04 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206264 kb
Host smart-26682d82-3c19-42f2-b97c-cc5345ea327c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=903606381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.903606381
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3082037009
Short name T1067
Test name
Test status
Simulation time 160397284 ps
CPU time 0.85 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 206040 kb
Host smart-f608c9c9-898b-44af-866e-3724dae0de93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3082037009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3082037009
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2890398445
Short name T897
Test name
Test status
Simulation time 170183487 ps
CPU time 0.82 seconds
Started Jul 09 05:14:08 PM PDT 24
Finished Jul 09 05:14:10 PM PDT 24
Peak memory 206084 kb
Host smart-6d941106-0885-428b-b0b2-d9c22d9a129f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903
98445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2890398445
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1014876119
Short name T1018
Test name
Test status
Simulation time 242796978 ps
CPU time 0.9 seconds
Started Jul 09 05:14:04 PM PDT 24
Finished Jul 09 05:14:06 PM PDT 24
Peak memory 205988 kb
Host smart-da1cccaa-b67c-47d1-8f21-72f1bc8328e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10148
76119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1014876119
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1691851821
Short name T1719
Test name
Test status
Simulation time 187049845 ps
CPU time 0.98 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:07 PM PDT 24
Peak memory 206056 kb
Host smart-95015347-6be7-4c07-8d15-91ecc6cfbdd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
51821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1691851821
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3998419701
Short name T1027
Test name
Test status
Simulation time 210568974 ps
CPU time 0.84 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:07 PM PDT 24
Peak memory 206136 kb
Host smart-8f555358-da7f-46ec-aca6-de754df5f64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
19701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3998419701
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1489271696
Short name T948
Test name
Test status
Simulation time 165207494 ps
CPU time 0.79 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:11 PM PDT 24
Peak memory 206060 kb
Host smart-3c567fba-2c2f-464b-b220-78935b3ebd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
71696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1489271696
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.930489529
Short name T2545
Test name
Test status
Simulation time 197268192 ps
CPU time 0.97 seconds
Started Jul 09 05:14:07 PM PDT 24
Finished Jul 09 05:14:09 PM PDT 24
Peak memory 206136 kb
Host smart-c2910598-ef85-4d91-b7e7-7e4447bb79d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=930489529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.930489529
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.974736439
Short name T2128
Test name
Test status
Simulation time 150213005 ps
CPU time 0.76 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 206060 kb
Host smart-039a7774-22e3-46fc-b500-9a588ea19bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97473
6439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.974736439
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.904917117
Short name T827
Test name
Test status
Simulation time 59405230 ps
CPU time 0.67 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206064 kb
Host smart-d0cd2e78-7d54-4e4c-94ee-e54ba658d2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90491
7117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.904917117
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2322181249
Short name T802
Test name
Test status
Simulation time 9052240879 ps
CPU time 22.42 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:30 PM PDT 24
Peak memory 206508 kb
Host smart-702f679b-0f66-45e3-889e-09a7805af319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
81249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2322181249
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2914289252
Short name T1069
Test name
Test status
Simulation time 149697817 ps
CPU time 0.84 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206060 kb
Host smart-add8228f-0cb3-49d1-af99-c4692fc25caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29142
89252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2914289252
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.64454625
Short name T34
Test name
Test status
Simulation time 185222048 ps
CPU time 0.86 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:07 PM PDT 24
Peak memory 206128 kb
Host smart-bc279f48-fb0b-4c02-9dff-d2c9a47e5067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64454
625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.64454625
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3311890791
Short name T738
Test name
Test status
Simulation time 192896905 ps
CPU time 0.85 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:08 PM PDT 24
Peak memory 206016 kb
Host smart-e5d8e83d-4b7f-4ca7-ba58-807b83ae4c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
90791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3311890791
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1107658260
Short name T1989
Test name
Test status
Simulation time 191040750 ps
CPU time 0.9 seconds
Started Jul 09 05:14:07 PM PDT 24
Finished Jul 09 05:14:09 PM PDT 24
Peak memory 206088 kb
Host smart-f4ca3778-b545-4a90-a810-376506664790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076
58260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1107658260
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1817201127
Short name T2149
Test name
Test status
Simulation time 175940387 ps
CPU time 0.82 seconds
Started Jul 09 05:14:07 PM PDT 24
Finished Jul 09 05:14:09 PM PDT 24
Peak memory 206152 kb
Host smart-66de37ce-344b-4b7d-83d3-efab37693284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18172
01127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1817201127
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2726752767
Short name T781
Test name
Test status
Simulation time 182344138 ps
CPU time 0.82 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:07 PM PDT 24
Peak memory 206120 kb
Host smart-4129af1b-a771-4a08-823b-c2a5edbaef09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27267
52767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2726752767
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4145754435
Short name T1962
Test name
Test status
Simulation time 159814387 ps
CPU time 0.77 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206056 kb
Host smart-d3380d6d-5bda-4fee-ad5d-51312db36c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
54435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4145754435
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.15925730
Short name T413
Test name
Test status
Simulation time 249092764 ps
CPU time 0.98 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206060 kb
Host smart-306088b5-33ef-41e1-8200-1d3dfc1c9b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.15925730
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1367248634
Short name T655
Test name
Test status
Simulation time 3706688435 ps
CPU time 95.92 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206344 kb
Host smart-0997e39b-a2be-4039-8105-94fcd86570aa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1367248634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1367248634
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2736690390
Short name T1342
Test name
Test status
Simulation time 192869223 ps
CPU time 0.81 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:08 PM PDT 24
Peak memory 206112 kb
Host smart-7221e479-5351-43cf-9e9d-5d63b5a26288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
90390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2736690390
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4285342510
Short name T1384
Test name
Test status
Simulation time 232990819 ps
CPU time 0.9 seconds
Started Jul 09 05:14:07 PM PDT 24
Finished Jul 09 05:14:09 PM PDT 24
Peak memory 206104 kb
Host smart-cb06364d-b934-4064-b406-f93f1b9a80ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42853
42510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4285342510
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.646331533
Short name T2373
Test name
Test status
Simulation time 845221759 ps
CPU time 1.9 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206248 kb
Host smart-b80c27cb-b5be-4d15-b043-484d21c8e66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64633
1533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.646331533
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1214645058
Short name T1571
Test name
Test status
Simulation time 3907399778 ps
CPU time 36.63 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:48 PM PDT 24
Peak memory 206376 kb
Host smart-23522866-dc71-4759-89b3-7c57e94c6b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
45058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1214645058
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2799349328
Short name T185
Test name
Test status
Simulation time 89596001 ps
CPU time 0.75 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206080 kb
Host smart-038b1e61-705c-4700-afc3-964057e64828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2799349328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2799349328
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.955025917
Short name T906
Test name
Test status
Simulation time 4127202505 ps
CPU time 5.16 seconds
Started Jul 09 05:14:06 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 206404 kb
Host smart-d91b23a2-758a-4bd9-b0f8-7e0a5fdfda52
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=955025917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.955025917
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2736196535
Short name T197
Test name
Test status
Simulation time 13424742436 ps
CPU time 12.85 seconds
Started Jul 09 05:14:07 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206148 kb
Host smart-4caa5417-1d5c-4013-b6b5-18da7cc1508e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2736196535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2736196535
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1791054938
Short name T711
Test name
Test status
Simulation time 23363043379 ps
CPU time 30.37 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:42 PM PDT 24
Peak memory 206092 kb
Host smart-86fddf50-3987-4da8-aab1-7df36362a6f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1791054938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1791054938
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2824994699
Short name T1727
Test name
Test status
Simulation time 161066630 ps
CPU time 0.76 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 206060 kb
Host smart-deff4b66-6161-4896-8fdf-a0b3deb78e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
94699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2824994699
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.610374771
Short name T1735
Test name
Test status
Simulation time 199090603 ps
CPU time 0.83 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:11 PM PDT 24
Peak memory 206148 kb
Host smart-0b64b5bc-3b91-4663-973c-0264c3400911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61037
4771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.610374771
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.15281720
Short name T2641
Test name
Test status
Simulation time 472886911 ps
CPU time 1.38 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:11 PM PDT 24
Peak memory 206160 kb
Host smart-0320b33e-89f3-413b-a6e1-85c4f17ffba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.15281720
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3052811350
Short name T2202
Test name
Test status
Simulation time 938929603 ps
CPU time 2.25 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206248 kb
Host smart-262269f1-3967-40c2-9f8c-9a4414cff0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30528
11350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3052811350
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.792702929
Short name T562
Test name
Test status
Simulation time 6560208310 ps
CPU time 16.53 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206384 kb
Host smart-f5b6e194-a891-45c5-8b0b-d3a2203de780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79270
2929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.792702929
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3609752831
Short name T672
Test name
Test status
Simulation time 431981646 ps
CPU time 1.37 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206088 kb
Host smart-bb8b4720-9e0c-4616-8066-a9b4c1afcc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36097
52831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3609752831
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.532345797
Short name T2635
Test name
Test status
Simulation time 142567327 ps
CPU time 0.81 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206164 kb
Host smart-9d8dd0b5-f2ca-462d-aee0-473fd799b813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53234
5797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.532345797
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3223702634
Short name T1135
Test name
Test status
Simulation time 84919240 ps
CPU time 0.74 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:15 PM PDT 24
Peak memory 206144 kb
Host smart-9c6c6a80-7497-4781-a41b-48c7cc90f99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32237
02634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3223702634
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2012192692
Short name T2061
Test name
Test status
Simulation time 842565894 ps
CPU time 2.07 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:15 PM PDT 24
Peak memory 206360 kb
Host smart-9df11c46-42de-421a-9d29-4eb07365aa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121
92692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2012192692
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1328686806
Short name T182
Test name
Test status
Simulation time 201584634 ps
CPU time 2.3 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:15 PM PDT 24
Peak memory 206324 kb
Host smart-3032fb69-cd93-4380-81be-27959297d03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13286
86806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1328686806
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.302765141
Short name T2185
Test name
Test status
Simulation time 179495152 ps
CPU time 0.86 seconds
Started Jul 09 05:14:12 PM PDT 24
Finished Jul 09 05:14:15 PM PDT 24
Peak memory 206112 kb
Host smart-8413cbf1-b358-47c9-83f4-61c0687f8e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30276
5141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.302765141
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2720088760
Short name T708
Test name
Test status
Simulation time 232831457 ps
CPU time 0.84 seconds
Started Jul 09 05:14:10 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206116 kb
Host smart-35714d6b-32ce-478f-bf74-996887d55e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27200
88760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2720088760
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1040457822
Short name T1311
Test name
Test status
Simulation time 266099593 ps
CPU time 1.11 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:15 PM PDT 24
Peak memory 205992 kb
Host smart-91a46a8e-fb91-448c-a748-95fed6de1fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10404
57822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1040457822
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.2038554000
Short name T2528
Test name
Test status
Simulation time 9870766024 ps
CPU time 98.81 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206292 kb
Host smart-c9056a00-4468-4e6f-a9e6-17bd89114e71
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2038554000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2038554000
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1154852292
Short name T57
Test name
Test status
Simulation time 210715709 ps
CPU time 0.89 seconds
Started Jul 09 05:14:13 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206160 kb
Host smart-3fdca662-955e-4869-9fd2-e6fb7fe640ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11548
52292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1154852292
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1941057584
Short name T1542
Test name
Test status
Simulation time 23286578634 ps
CPU time 24.08 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:35 PM PDT 24
Peak memory 206192 kb
Host smart-de58757c-f5de-46fc-bdb9-7ebd8be658f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19410
57584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1941057584
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3435118142
Short name T2505
Test name
Test status
Simulation time 3316728262 ps
CPU time 3.95 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206084 kb
Host smart-6b106e76-8402-424b-a808-5b5fe5a76266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351
18142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3435118142
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2254270427
Short name T1369
Test name
Test status
Simulation time 11480326349 ps
CPU time 321.28 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:19:34 PM PDT 24
Peak memory 206480 kb
Host smart-5186825c-2170-461b-8125-675dca46f5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22542
70427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2254270427
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2225587372
Short name T1711
Test name
Test status
Simulation time 5214190405 ps
CPU time 52.28 seconds
Started Jul 09 05:14:08 PM PDT 24
Finished Jul 09 05:15:02 PM PDT 24
Peak memory 206372 kb
Host smart-22b9ba88-dfe7-4c84-9889-18f05dfee805
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2225587372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2225587372
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3334477695
Short name T2352
Test name
Test status
Simulation time 268285018 ps
CPU time 0.95 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:15 PM PDT 24
Peak memory 206108 kb
Host smart-7e619273-8be2-4e93-9400-c1275acd6195
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3334477695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3334477695
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1762148174
Short name T597
Test name
Test status
Simulation time 179869477 ps
CPU time 0.85 seconds
Started Jul 09 05:14:11 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 205956 kb
Host smart-11dcbab6-17c6-49ec-907e-970c0c44e9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17621
48174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1762148174
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2695617761
Short name T1307
Test name
Test status
Simulation time 3773123681 ps
CPU time 28.91 seconds
Started Jul 09 05:14:09 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206252 kb
Host smart-54c92c45-5d2b-4d34-85a3-ca07a68cc4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26956
17761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2695617761
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.1313525611
Short name T464
Test name
Test status
Simulation time 6653427442 ps
CPU time 63.26 seconds
Started Jul 09 05:14:15 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206364 kb
Host smart-f15ea060-87a7-4aaf-97f6-9337a7b8dccf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1313525611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1313525611
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.800207816
Short name T1419
Test name
Test status
Simulation time 176625137 ps
CPU time 0.86 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206048 kb
Host smart-51615994-28b4-4940-a256-f565b4794605
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=800207816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.800207816
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.175319259
Short name T332
Test name
Test status
Simulation time 172594489 ps
CPU time 0.8 seconds
Started Jul 09 05:14:13 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206028 kb
Host smart-20e3f7bf-1e24-4176-96d3-39a22e0db0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
9259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.175319259
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1290960125
Short name T2649
Test name
Test status
Simulation time 193309257 ps
CPU time 0.89 seconds
Started Jul 09 05:14:15 PM PDT 24
Finished Jul 09 05:14:18 PM PDT 24
Peak memory 206128 kb
Host smart-dc91faff-cbd7-4a79-825f-b8c4866bbb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12909
60125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1290960125
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1473478921
Short name T2151
Test name
Test status
Simulation time 192432752 ps
CPU time 0.83 seconds
Started Jul 09 05:14:15 PM PDT 24
Finished Jul 09 05:14:18 PM PDT 24
Peak memory 206040 kb
Host smart-7f14ab3c-0648-4de5-a626-af83198f972d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14734
78921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1473478921
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1198619154
Short name T2343
Test name
Test status
Simulation time 153745230 ps
CPU time 0.78 seconds
Started Jul 09 05:14:16 PM PDT 24
Finished Jul 09 05:14:18 PM PDT 24
Peak memory 206040 kb
Host smart-a45d30b3-4454-4b2f-81bd-535692583753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
19154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1198619154
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2742020418
Short name T2071
Test name
Test status
Simulation time 155397806 ps
CPU time 0.81 seconds
Started Jul 09 05:14:16 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206164 kb
Host smart-1255ae23-31ec-4e50-b367-51528c7e5986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27420
20418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2742020418
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3597068410
Short name T1975
Test name
Test status
Simulation time 251079771 ps
CPU time 1.06 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:21 PM PDT 24
Peak memory 206128 kb
Host smart-d0fb8b22-4b22-4e7b-bb5a-95e0b66bdfb4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3597068410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3597068410
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3121348992
Short name T2290
Test name
Test status
Simulation time 218219217 ps
CPU time 0.82 seconds
Started Jul 09 05:14:14 PM PDT 24
Finished Jul 09 05:14:17 PM PDT 24
Peak memory 206056 kb
Host smart-e6f1aaaf-28cf-4e20-b5c9-9a249d4ba0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31213
48992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3121348992
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1708195328
Short name T40
Test name
Test status
Simulation time 48507840 ps
CPU time 0.7 seconds
Started Jul 09 05:14:12 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206056 kb
Host smart-45dad356-3338-404a-9c2a-81d3f4b99e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17081
95328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1708195328
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.263103413
Short name T1525
Test name
Test status
Simulation time 21222733680 ps
CPU time 48.94 seconds
Started Jul 09 05:14:12 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 206420 kb
Host smart-72a7aa65-ba59-4c9b-b42d-58ad16857ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26310
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.263103413
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2385185341
Short name T1194
Test name
Test status
Simulation time 219507360 ps
CPU time 0.86 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206132 kb
Host smart-c3ca9dda-dbf3-4189-be0f-92475842577b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
85341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2385185341
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2160391767
Short name T545
Test name
Test status
Simulation time 152799333 ps
CPU time 0.8 seconds
Started Jul 09 05:14:13 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206024 kb
Host smart-c76e2ade-a92e-4742-9261-462ef270460d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603
91767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2160391767
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3980490918
Short name T2161
Test name
Test status
Simulation time 182347961 ps
CPU time 0.87 seconds
Started Jul 09 05:14:13 PM PDT 24
Finished Jul 09 05:14:17 PM PDT 24
Peak memory 206124 kb
Host smart-85e26d53-8e73-4985-8e21-4c3189e20e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804
90918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3980490918
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1983748162
Short name T1605
Test name
Test status
Simulation time 161860107 ps
CPU time 0.84 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206140 kb
Host smart-26b15ffd-f81d-4169-8ad4-cce015151c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19837
48162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1983748162
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3354717545
Short name T2013
Test name
Test status
Simulation time 135385620 ps
CPU time 0.79 seconds
Started Jul 09 05:14:15 PM PDT 24
Finished Jul 09 05:14:18 PM PDT 24
Peak memory 206112 kb
Host smart-6ff084ec-a237-428c-90e0-8644df77ff4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
17545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3354717545
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2185527148
Short name T1683
Test name
Test status
Simulation time 150098759 ps
CPU time 0.77 seconds
Started Jul 09 05:14:12 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206092 kb
Host smart-2c16ab4f-fca5-4e21-baf9-0c1072b7669c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21855
27148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2185527148
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2400525416
Short name T1148
Test name
Test status
Simulation time 151870097 ps
CPU time 0.77 seconds
Started Jul 09 05:14:13 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206140 kb
Host smart-b50e761f-ae03-484a-87b6-5d301fa21e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24005
25416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2400525416
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3642211320
Short name T1282
Test name
Test status
Simulation time 204627811 ps
CPU time 0.91 seconds
Started Jul 09 05:14:13 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206148 kb
Host smart-8d09b549-4bd6-4711-95e5-15825fc9cc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
11320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3642211320
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.4222909475
Short name T2070
Test name
Test status
Simulation time 5810667524 ps
CPU time 60.65 seconds
Started Jul 09 05:14:15 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206392 kb
Host smart-b877cde2-f019-4077-8bb2-5eee92a532dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4222909475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.4222909475
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.467267171
Short name T1852
Test name
Test status
Simulation time 193122580 ps
CPU time 0.95 seconds
Started Jul 09 05:14:16 PM PDT 24
Finished Jul 09 05:14:19 PM PDT 24
Peak memory 206160 kb
Host smart-561a3ced-1f30-4bae-88fb-0e9d01541e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46726
7171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.467267171
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.4228452103
Short name T1532
Test name
Test status
Simulation time 172897207 ps
CPU time 0.83 seconds
Started Jul 09 05:14:16 PM PDT 24
Finished Jul 09 05:14:19 PM PDT 24
Peak memory 206124 kb
Host smart-b0cb90de-c6ef-429b-8e7c-fdbbc381daad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284
52103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.4228452103
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2677433416
Short name T702
Test name
Test status
Simulation time 636172630 ps
CPU time 1.55 seconds
Started Jul 09 05:14:16 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206108 kb
Host smart-ca3f617c-2919-430f-8f37-36b093f5f9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26774
33416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2677433416
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2598958813
Short name T1941
Test name
Test status
Simulation time 3155986163 ps
CPU time 85.69 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206440 kb
Host smart-39b501bb-a72d-4d54-b1f5-35c4bb18f55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
58813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2598958813
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3265840814
Short name T2487
Test name
Test status
Simulation time 38922062 ps
CPU time 0.66 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206028 kb
Host smart-721d6f4b-fb5b-4a0d-846b-005ab2ad4200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3265840814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3265840814
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3952563603
Short name T883
Test name
Test status
Simulation time 4131788900 ps
CPU time 5.68 seconds
Started Jul 09 05:14:21 PM PDT 24
Finished Jul 09 05:14:28 PM PDT 24
Peak memory 206004 kb
Host smart-33237577-1403-4788-bb26-a7da51668e10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3952563603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.3952563603
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.213148089
Short name T1180
Test name
Test status
Simulation time 13451050243 ps
CPU time 13.66 seconds
Started Jul 09 05:14:18 PM PDT 24
Finished Jul 09 05:14:35 PM PDT 24
Peak memory 206136 kb
Host smart-f84f2293-e1fd-42ee-90f8-cb6de5b418ea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=213148089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.213148089
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1981179388
Short name T735
Test name
Test status
Simulation time 23374269407 ps
CPU time 24.05 seconds
Started Jul 09 05:14:18 PM PDT 24
Finished Jul 09 05:14:45 PM PDT 24
Peak memory 206172 kb
Host smart-8917aa60-5d81-4038-957c-b88e2c7df95f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1981179388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1981179388
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1961302912
Short name T657
Test name
Test status
Simulation time 166785411 ps
CPU time 0.83 seconds
Started Jul 09 05:14:18 PM PDT 24
Finished Jul 09 05:14:21 PM PDT 24
Peak memory 206060 kb
Host smart-89d1579c-92f9-4133-a675-919dab9aa426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
02912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1961302912
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3043529862
Short name T2280
Test name
Test status
Simulation time 175498979 ps
CPU time 0.82 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206028 kb
Host smart-3477dfbc-1303-4fa2-9dc5-17675c6778b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30435
29862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3043529862
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3215929674
Short name T1758
Test name
Test status
Simulation time 618378111 ps
CPU time 1.67 seconds
Started Jul 09 05:14:18 PM PDT 24
Finished Jul 09 05:14:22 PM PDT 24
Peak memory 206128 kb
Host smart-2c5fe956-1800-41d2-b53b-ce733ce5dabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32159
29674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3215929674
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2002584648
Short name T97
Test name
Test status
Simulation time 20337681485 ps
CPU time 37.95 seconds
Started Jul 09 05:14:15 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 206400 kb
Host smart-ad0ff0c7-2507-463a-a8a8-e6081d614e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20025
84648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2002584648
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1273906609
Short name T386
Test name
Test status
Simulation time 362640012 ps
CPU time 1.18 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206140 kb
Host smart-d21be610-9622-4cf3-af20-ab035e8aa07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12739
06609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1273906609
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.729999401
Short name T2455
Test name
Test status
Simulation time 176333280 ps
CPU time 0.81 seconds
Started Jul 09 05:14:20 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 206108 kb
Host smart-bf752a39-61fd-44cf-8974-6be5db9ed313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72999
9401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.729999401
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2933451239
Short name T1164
Test name
Test status
Simulation time 102707696 ps
CPU time 0.73 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 205988 kb
Host smart-73b8902a-e81e-4cbb-b4c0-255e04c32a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29334
51239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2933451239
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2460983823
Short name T972
Test name
Test status
Simulation time 827005529 ps
CPU time 2.13 seconds
Started Jul 09 05:14:18 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 206264 kb
Host smart-1fb924bd-8f5b-4d2b-b209-9c92859c549b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609
83823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2460983823
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2216928918
Short name T1696
Test name
Test status
Simulation time 258282220 ps
CPU time 1.55 seconds
Started Jul 09 05:14:19 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 206352 kb
Host smart-b4713911-dd0e-4ba8-8248-21d4d6695022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
28918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2216928918
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.4171799984
Short name T2551
Test name
Test status
Simulation time 230906198 ps
CPU time 0.97 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:21 PM PDT 24
Peak memory 206092 kb
Host smart-95e3c693-f1d6-401a-b0a1-44991e27a2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41717
99984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.4171799984
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3204467781
Short name T2054
Test name
Test status
Simulation time 144175879 ps
CPU time 0.77 seconds
Started Jul 09 05:14:17 PM PDT 24
Finished Jul 09 05:14:21 PM PDT 24
Peak memory 206048 kb
Host smart-94781830-4755-4f73-b588-d6bdb7b135cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32044
67781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3204467781
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1765697140
Short name T2010
Test name
Test status
Simulation time 236235856 ps
CPU time 1.05 seconds
Started Jul 09 05:14:20 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 206104 kb
Host smart-1c133122-420e-422a-ac7d-599a25676d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17656
97140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1765697140
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2086955267
Short name T1816
Test name
Test status
Simulation time 194011710 ps
CPU time 0.82 seconds
Started Jul 09 05:14:20 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 206132 kb
Host smart-039ef0f0-34f8-4af3-92ac-7880d7d80a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20869
55267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2086955267
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3901322569
Short name T2687
Test name
Test status
Simulation time 23318219170 ps
CPU time 23.32 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:47 PM PDT 24
Peak memory 206176 kb
Host smart-00483d56-8c58-4c0f-9168-366f82e1748d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013
22569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3901322569
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2227606133
Short name T1875
Test name
Test status
Simulation time 3267229850 ps
CPU time 3.68 seconds
Started Jul 09 05:14:21 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206176 kb
Host smart-30e226ea-6495-4e8d-ba92-4e69e0e9c4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22276
06133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2227606133
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2472024699
Short name T952
Test name
Test status
Simulation time 6821274434 ps
CPU time 51.85 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206424 kb
Host smart-2da4a4fe-93c2-4bd2-a7de-b39bc4b170f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24720
24699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2472024699
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.874570541
Short name T1270
Test name
Test status
Simulation time 5137939704 ps
CPU time 46.29 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:15:10 PM PDT 24
Peak memory 206384 kb
Host smart-5a406442-d09e-4f1c-9bcd-b74bdfa3539a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=874570541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.874570541
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1826900406
Short name T2710
Test name
Test status
Simulation time 249173896 ps
CPU time 0.98 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:24 PM PDT 24
Peak memory 206120 kb
Host smart-d4963be3-195d-4f67-9ee6-26c643832a8d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1826900406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1826900406
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.81138534
Short name T414
Test name
Test status
Simulation time 199694840 ps
CPU time 0.92 seconds
Started Jul 09 05:14:20 PM PDT 24
Finished Jul 09 05:14:23 PM PDT 24
Peak memory 205964 kb
Host smart-9fe3e606-edb1-4126-913a-4e3a91592eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81138
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.81138534
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3049559140
Short name T2513
Test name
Test status
Simulation time 6280587222 ps
CPU time 46.64 seconds
Started Jul 09 05:14:21 PM PDT 24
Finished Jul 09 05:15:10 PM PDT 24
Peak memory 206372 kb
Host smart-c7ac4fda-46dd-436f-ad35-21a49de5db56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30495
59140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3049559140
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1656062986
Short name T2542
Test name
Test status
Simulation time 4780732172 ps
CPU time 49.18 seconds
Started Jul 09 05:14:20 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206392 kb
Host smart-c7d8d68a-e91b-4508-98f6-64fe979f0e0b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1656062986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1656062986
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1728283539
Short name T395
Test name
Test status
Simulation time 189161771 ps
CPU time 0.87 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206100 kb
Host smart-cbdb92e8-5e94-47ea-aca4-75d6eb7fe1e4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1728283539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1728283539
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3501717520
Short name T1676
Test name
Test status
Simulation time 147412436 ps
CPU time 0.81 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:24 PM PDT 24
Peak memory 206060 kb
Host smart-ab9d1a71-ebad-4ff6-9276-3e4475dec62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35017
17520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3501717520
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2323541846
Short name T1484
Test name
Test status
Simulation time 233056913 ps
CPU time 0.85 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:24 PM PDT 24
Peak memory 205988 kb
Host smart-d41e0c6a-5c25-4fda-a8e5-26b747ab64b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23235
41846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2323541846
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1406698541
Short name T505
Test name
Test status
Simulation time 177775783 ps
CPU time 0.84 seconds
Started Jul 09 05:14:22 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206064 kb
Host smart-14155520-ba07-4fcf-8d6d-2b558eca7adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
98541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1406698541
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.541083249
Short name T754
Test name
Test status
Simulation time 155236576 ps
CPU time 0.82 seconds
Started Jul 09 05:14:23 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206108 kb
Host smart-1b810865-6acc-4424-9ba4-3272edf3fc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54108
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.541083249
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1739420291
Short name T1679
Test name
Test status
Simulation time 149137172 ps
CPU time 0.82 seconds
Started Jul 09 05:14:23 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206152 kb
Host smart-ae6c0b23-024c-4a8e-a897-468d8d476201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17394
20291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1739420291
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3757689421
Short name T77
Test name
Test status
Simulation time 226133634 ps
CPU time 1 seconds
Started Jul 09 05:14:25 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206080 kb
Host smart-144901f1-af21-41ea-a1b8-ef4ac676c202
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3757689421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3757689421
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3847613646
Short name T2644
Test name
Test status
Simulation time 158391728 ps
CPU time 0.77 seconds
Started Jul 09 05:14:26 PM PDT 24
Finished Jul 09 05:14:28 PM PDT 24
Peak memory 206024 kb
Host smart-be0318f9-5ea3-43e3-99aa-749c6afdba29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476
13646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3847613646
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3523379890
Short name T506
Test name
Test status
Simulation time 65557231 ps
CPU time 0.72 seconds
Started Jul 09 05:14:24 PM PDT 24
Finished Jul 09 05:14:26 PM PDT 24
Peak memory 206056 kb
Host smart-ea770469-28a8-4fee-8bcc-ae85dbffc01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
79890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3523379890
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.555148215
Short name T1378
Test name
Test status
Simulation time 16809874323 ps
CPU time 35.42 seconds
Started Jul 09 05:14:26 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 214624 kb
Host smart-6780def9-455a-4d41-9137-b0284c7d1286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55514
8215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.555148215
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3771089168
Short name T1497
Test name
Test status
Simulation time 193196507 ps
CPU time 0.86 seconds
Started Jul 09 05:14:26 PM PDT 24
Finished Jul 09 05:14:28 PM PDT 24
Peak memory 206060 kb
Host smart-a22dd06c-c5ad-481a-9156-26f52d2f338b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37710
89168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3771089168
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.826894302
Short name T1117
Test name
Test status
Simulation time 161600549 ps
CPU time 0.8 seconds
Started Jul 09 05:14:25 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206060 kb
Host smart-d6cf2edd-a555-4641-8d49-97a85a72ce41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82689
4302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.826894302
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.631142275
Short name T1540
Test name
Test status
Simulation time 163699504 ps
CPU time 0.82 seconds
Started Jul 09 05:14:25 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206088 kb
Host smart-0e953d7a-3b58-43cd-aae4-bc6df2c57cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63114
2275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.631142275
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1283201306
Short name T324
Test name
Test status
Simulation time 189754712 ps
CPU time 0.87 seconds
Started Jul 09 05:14:28 PM PDT 24
Finished Jul 09 05:14:30 PM PDT 24
Peak memory 205956 kb
Host smart-268016d6-1919-451c-9dea-a8f0e22cdcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
01306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1283201306
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.4037998075
Short name T70
Test name
Test status
Simulation time 152458602 ps
CPU time 0.78 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206020 kb
Host smart-1fc4b49d-b33d-43ae-9b94-21d5a1208086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40379
98075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.4037998075
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2751120033
Short name T1248
Test name
Test status
Simulation time 150257426 ps
CPU time 0.76 seconds
Started Jul 09 05:14:26 PM PDT 24
Finished Jul 09 05:14:28 PM PDT 24
Peak memory 206088 kb
Host smart-ee0a487e-28d7-4ebe-a9ce-7641b15a1923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27511
20033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2751120033
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.149046562
Short name T438
Test name
Test status
Simulation time 146458837 ps
CPU time 0.77 seconds
Started Jul 09 05:14:25 PM PDT 24
Finished Jul 09 05:14:26 PM PDT 24
Peak memory 206104 kb
Host smart-18b69212-6811-4112-b188-2dea8e4b7139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
6562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.149046562
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3949323820
Short name T753
Test name
Test status
Simulation time 261784508 ps
CPU time 0.9 seconds
Started Jul 09 05:14:28 PM PDT 24
Finished Jul 09 05:14:30 PM PDT 24
Peak memory 205952 kb
Host smart-ec9f2d32-3126-41a5-a123-821e1ff44d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39493
23820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3949323820
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1593257724
Short name T1483
Test name
Test status
Simulation time 4136510807 ps
CPU time 31.79 seconds
Started Jul 09 05:14:28 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206300 kb
Host smart-8dcc5912-3436-45ff-a947-888c7e1d125c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1593257724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1593257724
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3139026168
Short name T1716
Test name
Test status
Simulation time 165389804 ps
CPU time 0.82 seconds
Started Jul 09 05:14:26 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206028 kb
Host smart-d7cb8296-2ec8-4091-82d9-dedef84ea3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
26168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3139026168
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3273713541
Short name T2598
Test name
Test status
Simulation time 143027066 ps
CPU time 0.81 seconds
Started Jul 09 05:14:32 PM PDT 24
Finished Jul 09 05:14:35 PM PDT 24
Peak memory 206136 kb
Host smart-b1a8f960-59d4-4619-8760-6586f5782794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
13541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3273713541
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.812127898
Short name T849
Test name
Test status
Simulation time 811654054 ps
CPU time 1.99 seconds
Started Jul 09 05:14:29 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206360 kb
Host smart-eacbeac7-69b3-4cc0-99a9-9bab4f1b11d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81212
7898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.812127898
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.4005618534
Short name T2669
Test name
Test status
Simulation time 5009262275 ps
CPU time 37.03 seconds
Started Jul 09 05:14:27 PM PDT 24
Finished Jul 09 05:15:05 PM PDT 24
Peak memory 206368 kb
Host smart-50400d68-4247-43f1-aec3-a08a43a60575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
18534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.4005618534
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1906152304
Short name T909
Test name
Test status
Simulation time 86341620 ps
CPU time 0.72 seconds
Started Jul 09 05:14:37 PM PDT 24
Finished Jul 09 05:14:40 PM PDT 24
Peak memory 206184 kb
Host smart-101b6803-bd6f-4a90-81f5-59356d669e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1906152304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1906152304
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1279197762
Short name T2079
Test name
Test status
Simulation time 13410221421 ps
CPU time 12.83 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:44 PM PDT 24
Peak memory 206032 kb
Host smart-2621d20e-d3a2-4f10-9b3c-4730627962a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1279197762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1279197762
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3969758885
Short name T223
Test name
Test status
Simulation time 23415434475 ps
CPU time 22.33 seconds
Started Jul 09 05:14:29 PM PDT 24
Finished Jul 09 05:14:52 PM PDT 24
Peak memory 206392 kb
Host smart-3ab6d258-e28a-4b72-8d14-b00d9788d552
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3969758885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3969758885
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2961213654
Short name T316
Test name
Test status
Simulation time 170707730 ps
CPU time 0.8 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:33 PM PDT 24
Peak memory 206088 kb
Host smart-61cce96f-6383-45fd-84a4-89e19c8f4e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29612
13654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2961213654
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.2710728142
Short name T1918
Test name
Test status
Simulation time 177654952 ps
CPU time 0.83 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:14:36 PM PDT 24
Peak memory 206164 kb
Host smart-9919758d-0f28-4b78-b35f-e3f3f4bc9e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27107
28142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.2710728142
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.838896834
Short name T2122
Test name
Test status
Simulation time 434248856 ps
CPU time 1.48 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206048 kb
Host smart-a7e1ee95-9043-48dd-a3c0-767d447581fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83889
6834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.838896834
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.394443781
Short name T751
Test name
Test status
Simulation time 429381583 ps
CPU time 1.28 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:33 PM PDT 24
Peak memory 206052 kb
Host smart-439bdf0a-1ae6-4e61-80d8-c46554191f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
3781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.394443781
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.4110631784
Short name T2330
Test name
Test status
Simulation time 16702949150 ps
CPU time 28.42 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 206420 kb
Host smart-25490f78-8e05-4ac5-aa06-d86d647d8c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
31784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.4110631784
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1347350913
Short name T2058
Test name
Test status
Simulation time 322987813 ps
CPU time 1.08 seconds
Started Jul 09 05:14:29 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206068 kb
Host smart-c21c3ac3-2f38-48f3-9558-ea0d6e8d717c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13473
50913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1347350913
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3722570551
Short name T614
Test name
Test status
Simulation time 138640281 ps
CPU time 0.89 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206056 kb
Host smart-aa66c1bf-9b00-435e-bc48-a88eccede732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37225
70551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3722570551
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1915670408
Short name T899
Test name
Test status
Simulation time 86104061 ps
CPU time 0.72 seconds
Started Jul 09 05:14:32 PM PDT 24
Finished Jul 09 05:14:35 PM PDT 24
Peak memory 206156 kb
Host smart-3a0400a1-05d5-4607-bb9d-a2da00acf92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
70408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1915670408
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.989308095
Short name T358
Test name
Test status
Simulation time 926314295 ps
CPU time 2.16 seconds
Started Jul 09 05:14:30 PM PDT 24
Finished Jul 09 05:14:34 PM PDT 24
Peak memory 206364 kb
Host smart-debc8a9c-81ca-46b2-b07c-4b974089d9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98930
8095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.989308095
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2945440562
Short name T926
Test name
Test status
Simulation time 350548535 ps
CPU time 2.11 seconds
Started Jul 09 05:14:31 PM PDT 24
Finished Jul 09 05:14:36 PM PDT 24
Peak memory 206356 kb
Host smart-1cb2d7cd-3971-4c85-8ab5-39204d23cab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454
40562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2945440562
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3097532215
Short name T1769
Test name
Test status
Simulation time 169331416 ps
CPU time 0.84 seconds
Started Jul 09 05:14:31 PM PDT 24
Finished Jul 09 05:14:33 PM PDT 24
Peak memory 206148 kb
Host smart-82e66064-e543-438a-89d9-149c1f90384c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30975
32215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3097532215
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.493610272
Short name T1230
Test name
Test status
Simulation time 187669146 ps
CPU time 0.79 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206152 kb
Host smart-06f54891-8af7-4054-8768-bc8aca0e9ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49361
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.493610272
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2634338304
Short name T1171
Test name
Test status
Simulation time 182983319 ps
CPU time 0.83 seconds
Started Jul 09 05:14:31 PM PDT 24
Finished Jul 09 05:14:34 PM PDT 24
Peak memory 206056 kb
Host smart-2b7adc9e-947e-4e34-9a52-6ee38bcb7808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26343
38304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2634338304
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1827943462
Short name T1151
Test name
Test status
Simulation time 6018254661 ps
CPU time 174.67 seconds
Started Jul 09 05:14:29 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206352 kb
Host smart-354e80cb-440b-49e5-a8b2-5b4632777966
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1827943462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1827943462
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.978039588
Short name T758
Test name
Test status
Simulation time 179774232 ps
CPU time 0.86 seconds
Started Jul 09 05:14:31 PM PDT 24
Finished Jul 09 05:14:33 PM PDT 24
Peak memory 205952 kb
Host smart-5f7f6977-2579-440d-bda8-ba66550234bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97803
9588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.978039588
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1161935669
Short name T2573
Test name
Test status
Simulation time 23297851962 ps
CPU time 22.97 seconds
Started Jul 09 05:14:31 PM PDT 24
Finished Jul 09 05:14:56 PM PDT 24
Peak memory 206224 kb
Host smart-228c622f-578a-40c1-958e-edadb242bd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619
35669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1161935669
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2388565530
Short name T1091
Test name
Test status
Simulation time 3280835424 ps
CPU time 4.19 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206184 kb
Host smart-6ba6bdbd-ea0a-4a4f-9aa4-dd7cecbc9a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
65530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2388565530
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1337914173
Short name T2448
Test name
Test status
Simulation time 9236473305 ps
CPU time 85.55 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:16:01 PM PDT 24
Peak memory 206368 kb
Host smart-73b202b3-3f96-4b70-ab1d-7562282db9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13379
14173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1337914173
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3266419528
Short name T2285
Test name
Test status
Simulation time 4449884335 ps
CPU time 32.14 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206360 kb
Host smart-097ed4d2-28f6-49f5-8209-ef54f619c981
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3266419528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3266419528
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1830533554
Short name T321
Test name
Test status
Simulation time 272446745 ps
CPU time 0.96 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:14:36 PM PDT 24
Peak memory 206124 kb
Host smart-24b8cca1-ddc2-4584-9c48-4286af573953
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1830533554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1830533554
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2522104940
Short name T2066
Test name
Test status
Simulation time 214989471 ps
CPU time 0.9 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206148 kb
Host smart-5ee883ad-1a10-47d5-b2e2-3b5a44baea2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25221
04940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2522104940
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3797357705
Short name T2044
Test name
Test status
Simulation time 4325963486 ps
CPU time 30.55 seconds
Started Jul 09 05:14:35 PM PDT 24
Finished Jul 09 05:15:08 PM PDT 24
Peak memory 206372 kb
Host smart-9d6f3d18-84b0-4f97-8e53-40048829bcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37973
57705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3797357705
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.102963847
Short name T2158
Test name
Test status
Simulation time 7468805493 ps
CPU time 53.54 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206232 kb
Host smart-6eabad84-e2ae-443f-b54f-778c2ebbb327
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=102963847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.102963847
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2377583383
Short name T2321
Test name
Test status
Simulation time 178335263 ps
CPU time 0.87 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206140 kb
Host smart-1f2017cb-3ca4-4310-bb48-11f244b3dc02
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2377583383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2377583383
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2527289863
Short name T1536
Test name
Test status
Simulation time 139188398 ps
CPU time 0.78 seconds
Started Jul 09 05:14:32 PM PDT 24
Finished Jul 09 05:14:35 PM PDT 24
Peak memory 206016 kb
Host smart-59b6c8f9-f93a-481d-80ff-2301df5a31a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25272
89863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2527289863
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3586598614
Short name T114
Test name
Test status
Simulation time 251529117 ps
CPU time 0.85 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206160 kb
Host smart-ed2ce73d-42d1-46dd-bcda-506333a71c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
98614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3586598614
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1923881780
Short name T1995
Test name
Test status
Simulation time 162010528 ps
CPU time 0.81 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206140 kb
Host smart-498faea1-d447-4e1d-826a-998e6da63476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
81780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1923881780
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.956999972
Short name T1391
Test name
Test status
Simulation time 175142699 ps
CPU time 0.79 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:14:38 PM PDT 24
Peak memory 206156 kb
Host smart-ef422df0-8db2-4c30-92e5-8e279852efd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95699
9972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.956999972
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1288688614
Short name T1555
Test name
Test status
Simulation time 169637367 ps
CPU time 0.8 seconds
Started Jul 09 05:14:32 PM PDT 24
Finished Jul 09 05:14:35 PM PDT 24
Peak memory 205996 kb
Host smart-3db80506-bd6c-4c8d-8b86-821f4fbacc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
88614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1288688614
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4146943730
Short name T1607
Test name
Test status
Simulation time 177647720 ps
CPU time 0.8 seconds
Started Jul 09 05:14:36 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206164 kb
Host smart-a172867b-8055-4afa-bf7d-ebadd77d9b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41469
43730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4146943730
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3554405640
Short name T872
Test name
Test status
Simulation time 226305441 ps
CPU time 0.99 seconds
Started Jul 09 05:14:33 PM PDT 24
Finished Jul 09 05:14:36 PM PDT 24
Peak memory 206080 kb
Host smart-4456f379-ec00-41f0-95c0-70445ea432fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3554405640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3554405640
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2870293732
Short name T1750
Test name
Test status
Simulation time 182471609 ps
CPU time 0.85 seconds
Started Jul 09 05:14:36 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206156 kb
Host smart-3773260d-34fd-4053-8512-2263189d4518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28702
93732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2870293732
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2938319578
Short name T1103
Test name
Test status
Simulation time 44891523 ps
CPU time 0.67 seconds
Started Jul 09 05:14:37 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206132 kb
Host smart-c8933c3e-38ea-4c3f-a161-d40aef34bad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29383
19578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2938319578
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.978850286
Short name T89
Test name
Test status
Simulation time 17960529759 ps
CPU time 41.21 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206304 kb
Host smart-e14f4467-de3f-4905-863a-389f354945d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97885
0286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.978850286
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2980264606
Short name T605
Test name
Test status
Simulation time 172189346 ps
CPU time 0.83 seconds
Started Jul 09 05:14:34 PM PDT 24
Finished Jul 09 05:14:37 PM PDT 24
Peak memory 206132 kb
Host smart-15517eba-67c5-47f2-9fc4-bb57b7e48fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29802
64606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2980264606
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2323165754
Short name T457
Test name
Test status
Simulation time 171082907 ps
CPU time 0.82 seconds
Started Jul 09 05:14:35 PM PDT 24
Finished Jul 09 05:14:38 PM PDT 24
Peak memory 206064 kb
Host smart-8663e962-bacb-4f03-9b8a-56f39157a966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
65754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2323165754
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1654524669
Short name T2089
Test name
Test status
Simulation time 237995748 ps
CPU time 0.85 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:44 PM PDT 24
Peak memory 206056 kb
Host smart-55a68bdb-898c-4a6e-8ca7-17acce12208d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
24669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1654524669
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1139298196
Short name T1130
Test name
Test status
Simulation time 186837310 ps
CPU time 0.93 seconds
Started Jul 09 05:14:39 PM PDT 24
Finished Jul 09 05:14:42 PM PDT 24
Peak memory 206124 kb
Host smart-fc67a23f-9bb2-4ff8-9a1a-db9fa696c6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11392
98196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1139298196
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2812351105
Short name T1356
Test name
Test status
Simulation time 160452460 ps
CPU time 0.8 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:44 PM PDT 24
Peak memory 206136 kb
Host smart-a78715c3-a82b-4d9b-8cd3-787a74a48ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
51105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2812351105
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.589704590
Short name T676
Test name
Test status
Simulation time 144764636 ps
CPU time 0.72 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:42 PM PDT 24
Peak memory 206048 kb
Host smart-aada0ea3-6508-4a9e-8bf7-78138e96583d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58970
4590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.589704590
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.817961654
Short name T1468
Test name
Test status
Simulation time 160181934 ps
CPU time 0.84 seconds
Started Jul 09 05:14:39 PM PDT 24
Finished Jul 09 05:14:42 PM PDT 24
Peak memory 206140 kb
Host smart-5a973a94-dbf4-4a8d-96d5-d669b139dfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81796
1654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.817961654
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3086474567
Short name T1297
Test name
Test status
Simulation time 215988881 ps
CPU time 0.92 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 205904 kb
Host smart-2d31c6bd-bb8c-4c4f-8eaa-ad4c94382f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864
74567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3086474567
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.980887338
Short name T801
Test name
Test status
Simulation time 4935012303 ps
CPU time 46.53 seconds
Started Jul 09 05:14:39 PM PDT 24
Finished Jul 09 05:15:28 PM PDT 24
Peak memory 206392 kb
Host smart-e8485ed1-5d57-48f5-a96f-809aea931282
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=980887338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.980887338
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2560773995
Short name T1119
Test name
Test status
Simulation time 258992055 ps
CPU time 0.92 seconds
Started Jul 09 05:14:39 PM PDT 24
Finished Jul 09 05:14:42 PM PDT 24
Peak memory 206028 kb
Host smart-5e00d99d-a00e-4d3c-8489-67ecd94afb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
73995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2560773995
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3849478408
Short name T2272
Test name
Test status
Simulation time 185407131 ps
CPU time 0.85 seconds
Started Jul 09 05:14:37 PM PDT 24
Finished Jul 09 05:14:39 PM PDT 24
Peak memory 206040 kb
Host smart-2f2f3722-cdec-42e0-bc27-5fd6c37c6bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
78408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3849478408
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3117901330
Short name T1220
Test name
Test status
Simulation time 667064275 ps
CPU time 1.64 seconds
Started Jul 09 05:14:38 PM PDT 24
Finished Jul 09 05:14:41 PM PDT 24
Peak memory 206300 kb
Host smart-c0327dc1-d6b1-45cb-9e39-9918c821becc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31179
01330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3117901330
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3006205453
Short name T1143
Test name
Test status
Simulation time 4010011502 ps
CPU time 107.71 seconds
Started Jul 09 05:14:38 PM PDT 24
Finished Jul 09 05:16:27 PM PDT 24
Peak memory 206336 kb
Host smart-f79aaf8a-01c4-4ca7-8b35-06d6c3c8fb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30062
05453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3006205453
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.2835216602
Short name T1049
Test name
Test status
Simulation time 37302184 ps
CPU time 0.66 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:14:59 PM PDT 24
Peak memory 206040 kb
Host smart-9d13d0e1-df3d-4006-be2c-b63a0f849a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2835216602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2835216602
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3891231903
Short name T2622
Test name
Test status
Simulation time 4185218314 ps
CPU time 5.1 seconds
Started Jul 09 05:14:41 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206400 kb
Host smart-5a92bb0b-bc59-4648-bb8d-1ef2e7a0fdd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3891231903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3891231903
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.930860789
Short name T1980
Test name
Test status
Simulation time 13463921053 ps
CPU time 15 seconds
Started Jul 09 05:14:37 PM PDT 24
Finished Jul 09 05:14:53 PM PDT 24
Peak memory 206324 kb
Host smart-62358cbd-0c7b-4189-95e2-08a536e84e9c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=930860789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.930860789
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.417390252
Short name T196
Test name
Test status
Simulation time 23378877019 ps
CPU time 24.5 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206356 kb
Host smart-88a5e3db-d0b8-4242-b3be-a262af69e7e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=417390252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.417390252
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1313492273
Short name T989
Test name
Test status
Simulation time 192566306 ps
CPU time 0.89 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206096 kb
Host smart-458856ad-f38c-449a-89d5-7372d5ef9cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
92273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1313492273
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.4104663610
Short name T2093
Test name
Test status
Simulation time 165689063 ps
CPU time 0.8 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206120 kb
Host smart-bbc04101-12da-4bfe-954e-12a62776d7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046
63610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4104663610
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1160158275
Short name T2187
Test name
Test status
Simulation time 214100054 ps
CPU time 0.94 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206068 kb
Host smart-a101bee9-e682-4761-989b-50f23bb2ac1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11601
58275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1160158275
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2040623990
Short name T697
Test name
Test status
Simulation time 630924596 ps
CPU time 1.57 seconds
Started Jul 09 05:14:37 PM PDT 24
Finished Jul 09 05:14:40 PM PDT 24
Peak memory 206156 kb
Host smart-35a8172b-6b57-4333-97fa-2b132c2c15ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
23990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2040623990
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3717964988
Short name T1624
Test name
Test status
Simulation time 22393659757 ps
CPU time 49.2 seconds
Started Jul 09 05:14:41 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206388 kb
Host smart-bd192700-deb7-4f64-92ff-536a890ce866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37179
64988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3717964988
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.214511153
Short name T2055
Test name
Test status
Simulation time 431074906 ps
CPU time 1.38 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:44 PM PDT 24
Peak memory 206116 kb
Host smart-d0c78603-f31f-480d-9031-38e20a09cfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21451
1153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.214511153
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3009561370
Short name T774
Test name
Test status
Simulation time 147545945 ps
CPU time 0.77 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206068 kb
Host smart-c9431795-a408-4062-b8bd-de8d77f1541c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30095
61370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3009561370
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2356282236
Short name T333
Test name
Test status
Simulation time 36013443 ps
CPU time 0.66 seconds
Started Jul 09 05:14:39 PM PDT 24
Finished Jul 09 05:14:42 PM PDT 24
Peak memory 206144 kb
Host smart-424e1022-d9a4-4ade-940a-987a139ec228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23562
82236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2356282236
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.4090836590
Short name T500
Test name
Test status
Simulation time 1036617216 ps
CPU time 2.46 seconds
Started Jul 09 05:14:43 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206264 kb
Host smart-476160e9-73f2-449b-98ce-d1997d42a4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40908
36590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.4090836590
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2286987707
Short name T1016
Test name
Test status
Simulation time 324845524 ps
CPU time 1.8 seconds
Started Jul 09 05:14:43 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206372 kb
Host smart-cb586ffd-b407-4cd7-b6d6-e66e4e44a590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
87707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2286987707
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1285692946
Short name T403
Test name
Test status
Simulation time 219387374 ps
CPU time 0.9 seconds
Started Jul 09 05:14:41 PM PDT 24
Finished Jul 09 05:14:46 PM PDT 24
Peak memory 206148 kb
Host smart-a0c50fca-d40f-41ef-9ad8-91cb4fe88854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
92946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1285692946
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2261684452
Short name T2080
Test name
Test status
Simulation time 160283057 ps
CPU time 0.83 seconds
Started Jul 09 05:14:42 PM PDT 24
Finished Jul 09 05:14:47 PM PDT 24
Peak memory 206052 kb
Host smart-dfe53054-ae84-4feb-b8ca-bbd831aa92fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
84452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2261684452
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1834211191
Short name T743
Test name
Test status
Simulation time 171438412 ps
CPU time 0.85 seconds
Started Jul 09 05:14:42 PM PDT 24
Finished Jul 09 05:14:47 PM PDT 24
Peak memory 205992 kb
Host smart-dfbf7fec-4dc1-44b8-a681-8bcc715c4826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18342
11191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1834211191
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3413756247
Short name T1626
Test name
Test status
Simulation time 4740306859 ps
CPU time 125.12 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206352 kb
Host smart-61558bdc-6c8a-4a0a-bed8-6340ff19f10c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3413756247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3413756247
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3397754658
Short name T2452
Test name
Test status
Simulation time 242286785 ps
CPU time 0.91 seconds
Started Jul 09 05:14:42 PM PDT 24
Finished Jul 09 05:14:46 PM PDT 24
Peak memory 206016 kb
Host smart-6ecaa99f-5cc7-47bc-8e4b-c053457a5c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
54658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3397754658
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.849426209
Short name T2278
Test name
Test status
Simulation time 23293471175 ps
CPU time 22.74 seconds
Started Jul 09 05:14:43 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206220 kb
Host smart-f4fe7b34-1a9d-4bc2-8c95-403929c63ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84942
6209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.849426209
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1702561561
Short name T725
Test name
Test status
Simulation time 3288331661 ps
CPU time 3.76 seconds
Started Jul 09 05:14:42 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206192 kb
Host smart-e1d156e1-1f9a-4fd0-a19e-bb72915673d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17025
61561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1702561561
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1857512834
Short name T396
Test name
Test status
Simulation time 5563201593 ps
CPU time 47.83 seconds
Started Jul 09 05:14:44 PM PDT 24
Finished Jul 09 05:15:36 PM PDT 24
Peak memory 206500 kb
Host smart-7c349f73-d236-440d-ab4b-d9c877e872ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575
12834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1857512834
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.341952358
Short name T1643
Test name
Test status
Simulation time 4313930028 ps
CPU time 125.7 seconds
Started Jul 09 05:14:40 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206360 kb
Host smart-e2af8d4b-0f13-4513-828c-b9019dc5d9eb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=341952358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.341952358
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1144105073
Short name T2692
Test name
Test status
Simulation time 251837108 ps
CPU time 1.02 seconds
Started Jul 09 05:14:41 PM PDT 24
Finished Jul 09 05:14:45 PM PDT 24
Peak memory 206028 kb
Host smart-625338ab-7ccc-4023-9fc8-566a7df3a825
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1144105073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1144105073
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3748223820
Short name T1650
Test name
Test status
Simulation time 205733137 ps
CPU time 0.93 seconds
Started Jul 09 05:14:44 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206132 kb
Host smart-db1a8538-f129-4878-a114-20860aeaa178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37482
23820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3748223820
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1768684225
Short name T2299
Test name
Test status
Simulation time 4874149483 ps
CPU time 134.57 seconds
Started Jul 09 05:14:42 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206432 kb
Host smart-9280e973-0a74-4f95-b775-3cde767bd54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17686
84225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1768684225
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1385611656
Short name T656
Test name
Test status
Simulation time 7370215076 ps
CPU time 214.41 seconds
Started Jul 09 05:14:42 PM PDT 24
Finished Jul 09 05:18:21 PM PDT 24
Peak memory 206328 kb
Host smart-4383d1ca-9431-43ae-ad1f-14699fc64e33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1385611656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1385611656
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1657762689
Short name T1181
Test name
Test status
Simulation time 166655714 ps
CPU time 0.82 seconds
Started Jul 09 05:14:43 PM PDT 24
Finished Jul 09 05:14:47 PM PDT 24
Peak memory 206096 kb
Host smart-a018aa5c-a8a9-437f-9804-4bb7a7c45f6f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1657762689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1657762689
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1517212178
Short name T1869
Test name
Test status
Simulation time 153781737 ps
CPU time 0.85 seconds
Started Jul 09 05:14:44 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206132 kb
Host smart-43062e5f-273b-46a5-82ad-407ebf766a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172
12178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1517212178
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.165195885
Short name T2337
Test name
Test status
Simulation time 194286480 ps
CPU time 0.84 seconds
Started Jul 09 05:14:43 PM PDT 24
Finished Jul 09 05:14:48 PM PDT 24
Peak memory 206148 kb
Host smart-0d0c10b1-7dc3-40f0-8ff9-6f05a7c83638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16519
5885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.165195885
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.864246347
Short name T901
Test name
Test status
Simulation time 244386713 ps
CPU time 0.81 seconds
Started Jul 09 05:14:51 PM PDT 24
Finished Jul 09 05:14:56 PM PDT 24
Peak memory 206048 kb
Host smart-3c356500-7404-4cd4-88f9-3fc1a70ce831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86424
6347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.864246347
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2882688465
Short name T1985
Test name
Test status
Simulation time 164274557 ps
CPU time 0.81 seconds
Started Jul 09 05:14:44 PM PDT 24
Finished Jul 09 05:14:49 PM PDT 24
Peak memory 206128 kb
Host smart-4dcbd02f-4212-48cf-9549-566453699111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28826
88465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2882688465
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1148982715
Short name T2322
Test name
Test status
Simulation time 221330370 ps
CPU time 0.82 seconds
Started Jul 09 05:14:45 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 206100 kb
Host smart-4abe1eaf-6088-4ff0-8da7-2aa8c081b0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11489
82715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1148982715
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3166080269
Short name T565
Test name
Test status
Simulation time 175261974 ps
CPU time 0.82 seconds
Started Jul 09 05:14:48 PM PDT 24
Finished Jul 09 05:14:52 PM PDT 24
Peak memory 206140 kb
Host smart-056bd286-3bb5-4349-92eb-879c8a6499ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
80269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3166080269
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.405181613
Short name T2422
Test name
Test status
Simulation time 225671549 ps
CPU time 0.97 seconds
Started Jul 09 05:14:47 PM PDT 24
Finished Jul 09 05:14:52 PM PDT 24
Peak memory 205996 kb
Host smart-acc2d827-42f6-4368-98e4-7cd540e5b47e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=405181613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.405181613
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3427534350
Short name T2329
Test name
Test status
Simulation time 141618453 ps
CPU time 0.77 seconds
Started Jul 09 05:14:45 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 206144 kb
Host smart-8b47e13a-329a-4020-88c1-a27b63d67929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
34350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3427534350
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2594745620
Short name T844
Test name
Test status
Simulation time 50253838 ps
CPU time 0.71 seconds
Started Jul 09 05:14:46 PM PDT 24
Finished Jul 09 05:14:51 PM PDT 24
Peak memory 206128 kb
Host smart-ce1899ed-915c-41af-b057-66457313dffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25947
45620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2594745620
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.4174295728
Short name T1692
Test name
Test status
Simulation time 18371042585 ps
CPU time 40.63 seconds
Started Jul 09 05:14:47 PM PDT 24
Finished Jul 09 05:15:32 PM PDT 24
Peak memory 206492 kb
Host smart-7234c86a-cb0e-4a60-b405-cb3b9fceaccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41742
95728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.4174295728
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2545983803
Short name T571
Test name
Test status
Simulation time 176238878 ps
CPU time 0.81 seconds
Started Jul 09 05:14:46 PM PDT 24
Finished Jul 09 05:14:51 PM PDT 24
Peak memory 206128 kb
Host smart-86948c5b-9520-453c-b6d9-205f67fc1c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25459
83803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2545983803
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1975474411
Short name T763
Test name
Test status
Simulation time 219945869 ps
CPU time 0.89 seconds
Started Jul 09 05:14:49 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 206060 kb
Host smart-ad686622-d822-4f3d-8327-241ded698332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
74411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1975474411
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1790875068
Short name T2160
Test name
Test status
Simulation time 188230911 ps
CPU time 0.84 seconds
Started Jul 09 05:14:45 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 206160 kb
Host smart-1bc8137a-5f14-43e5-a935-3f0a2babd050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17908
75068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1790875068
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3760379907
Short name T416
Test name
Test status
Simulation time 185828038 ps
CPU time 0.88 seconds
Started Jul 09 05:14:48 PM PDT 24
Finished Jul 09 05:14:53 PM PDT 24
Peak memory 205836 kb
Host smart-809e848e-cc85-4710-b8e3-69b48b3226e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37603
79907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3760379907
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3354551221
Short name T700
Test name
Test status
Simulation time 147376758 ps
CPU time 0.84 seconds
Started Jul 09 05:14:45 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 205992 kb
Host smart-53d7c619-c321-461d-90ae-216b46d3b1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
51221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3354551221
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2080722644
Short name T1021
Test name
Test status
Simulation time 153804542 ps
CPU time 0.81 seconds
Started Jul 09 05:14:46 PM PDT 24
Finished Jul 09 05:14:51 PM PDT 24
Peak memory 206048 kb
Host smart-c7721309-bfb2-48f2-88c7-f263fcc2ac92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
22644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2080722644
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3233117838
Short name T377
Test name
Test status
Simulation time 154906395 ps
CPU time 0.77 seconds
Started Jul 09 05:14:47 PM PDT 24
Finished Jul 09 05:14:51 PM PDT 24
Peak memory 206160 kb
Host smart-41acc8d0-4beb-4bce-aa99-dcc54ffa7ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
17838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3233117838
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3587188439
Short name T1047
Test name
Test status
Simulation time 247466761 ps
CPU time 0.92 seconds
Started Jul 09 05:14:47 PM PDT 24
Finished Jul 09 05:14:52 PM PDT 24
Peak memory 206140 kb
Host smart-86c08b14-272a-4726-a8bc-1cf3181508ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35871
88439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3587188439
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1001859521
Short name T2166
Test name
Test status
Simulation time 5183210502 ps
CPU time 149.9 seconds
Started Jul 09 05:14:45 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206392 kb
Host smart-c120fb70-1243-47c5-944c-2c3c636d0d0d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1001859521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1001859521
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1001386520
Short name T1226
Test name
Test status
Simulation time 175244679 ps
CPU time 0.82 seconds
Started Jul 09 05:14:48 PM PDT 24
Finished Jul 09 05:14:53 PM PDT 24
Peak memory 205848 kb
Host smart-e69ae352-978a-4f03-a2d8-b1ecbad80a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
86520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1001386520
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.4025575848
Short name T1160
Test name
Test status
Simulation time 172778563 ps
CPU time 0.84 seconds
Started Jul 09 05:14:46 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 206056 kb
Host smart-948ec551-c395-4830-82cf-edb3180bea49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40255
75848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.4025575848
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3567102765
Short name T2283
Test name
Test status
Simulation time 1203756923 ps
CPU time 2.33 seconds
Started Jul 09 05:14:54 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206184 kb
Host smart-d0746e42-4242-4675-a92b-006cbe2e4c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35671
02765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3567102765
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1487971960
Short name T2101
Test name
Test status
Simulation time 4119619986 ps
CPU time 40.08 seconds
Started Jul 09 05:14:46 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206320 kb
Host smart-680907e0-bb5b-473d-bf7d-a356c04c570c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14879
71960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1487971960
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.2187160450
Short name T559
Test name
Test status
Simulation time 56385398 ps
CPU time 0.67 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 205984 kb
Host smart-b4339254-8f19-4c2b-9cd9-f90382ef9878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2187160450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2187160450
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.946618138
Short name T10
Test name
Test status
Simulation time 4062693197 ps
CPU time 4.82 seconds
Started Jul 09 05:14:49 PM PDT 24
Finished Jul 09 05:14:57 PM PDT 24
Peak memory 206156 kb
Host smart-bb8c3d2e-a8b8-47d3-bff8-f25ca4e2dcb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=946618138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.946618138
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2461267250
Short name T764
Test name
Test status
Simulation time 13301042926 ps
CPU time 11.86 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 205720 kb
Host smart-ddf8ca78-9318-4903-93aa-52f7c55bab4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2461267250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2461267250
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3514901651
Short name T2678
Test name
Test status
Simulation time 23382045512 ps
CPU time 27.77 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:15:25 PM PDT 24
Peak memory 205940 kb
Host smart-5e2ca2b6-ef91-47fe-9726-cc2731b345bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3514901651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3514901651
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3067820726
Short name T1291
Test name
Test status
Simulation time 192953123 ps
CPU time 0.81 seconds
Started Jul 09 05:14:50 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 206056 kb
Host smart-74e5ced9-2c92-4c1f-a145-9b63a362617d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
20726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3067820726
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.72026480
Short name T1564
Test name
Test status
Simulation time 162641412 ps
CPU time 0.75 seconds
Started Jul 09 05:14:48 PM PDT 24
Finished Jul 09 05:14:53 PM PDT 24
Peak memory 206068 kb
Host smart-21107c50-72ac-41b2-841f-64e5a840b3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72026
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.72026480
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1696712169
Short name T1280
Test name
Test status
Simulation time 171418074 ps
CPU time 0.86 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:14:58 PM PDT 24
Peak memory 206132 kb
Host smart-8676f795-3964-47df-83df-901348c35160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16967
12169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1696712169
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2281814034
Short name T160
Test name
Test status
Simulation time 1059368639 ps
CPU time 2.37 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:14:59 PM PDT 24
Peak memory 206248 kb
Host smart-3a3f2128-4e8c-4063-8a20-cb739a929ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22818
14034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2281814034
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1384974950
Short name T809
Test name
Test status
Simulation time 21981041069 ps
CPU time 46.14 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206304 kb
Host smart-1458d8d1-7247-46a1-a220-2b0315868e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13849
74950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1384974950
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1668668093
Short name T2022
Test name
Test status
Simulation time 391799354 ps
CPU time 1.25 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206160 kb
Host smart-f1a3ad24-9c4b-4110-b1bb-d32cc85a3826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16686
68093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1668668093
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2378473063
Short name T820
Test name
Test status
Simulation time 167398134 ps
CPU time 0.82 seconds
Started Jul 09 05:14:49 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 206148 kb
Host smart-3ce2c15c-88ad-4f44-b627-cc2f39943f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23784
73063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2378473063
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1210760600
Short name T1077
Test name
Test status
Simulation time 67932585 ps
CPU time 0.68 seconds
Started Jul 09 05:14:48 PM PDT 24
Finished Jul 09 05:14:52 PM PDT 24
Peak memory 206080 kb
Host smart-03af7ec0-c4f7-4744-b772-7e3061e8496a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
60600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1210760600
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.4065027604
Short name T1859
Test name
Test status
Simulation time 1010861585 ps
CPU time 2.13 seconds
Started Jul 09 05:14:49 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 206148 kb
Host smart-4f4b057e-0e11-4fd7-93fc-376f34a67df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
27604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.4065027604
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1126886320
Short name T1911
Test name
Test status
Simulation time 151810004 ps
CPU time 1.27 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206320 kb
Host smart-b8283bb5-61aa-426b-91dd-5e5db4234dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268
86320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1126886320
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3838134589
Short name T407
Test name
Test status
Simulation time 233184201 ps
CPU time 0.92 seconds
Started Jul 09 05:14:50 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 206104 kb
Host smart-a76b6e8f-b640-4209-8925-5e4777ea3d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38381
34589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3838134589
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3511827081
Short name T356
Test name
Test status
Simulation time 176513161 ps
CPU time 0.8 seconds
Started Jul 09 05:14:51 PM PDT 24
Finished Jul 09 05:14:57 PM PDT 24
Peak memory 206076 kb
Host smart-aa1a8de6-fbdc-4e89-bc33-f160e9ca166e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35118
27081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3511827081
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.4052556529
Short name T1389
Test name
Test status
Simulation time 218616307 ps
CPU time 0.93 seconds
Started Jul 09 05:14:50 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 206132 kb
Host smart-0aa7d9c1-bb90-4282-a7fe-d8d56078ac78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
56529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.4052556529
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2080950460
Short name T1112
Test name
Test status
Simulation time 198149689 ps
CPU time 0.86 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:14:58 PM PDT 24
Peak memory 206128 kb
Host smart-822c2646-4645-4d01-a6c7-ce1090d12fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20809
50460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2080950460
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3733231697
Short name T682
Test name
Test status
Simulation time 23374117364 ps
CPU time 24.81 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206116 kb
Host smart-52e4312b-54de-4f8d-ae09-6fd532f761dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332
31697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3733231697
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1680082308
Short name T1145
Test name
Test status
Simulation time 3295316397 ps
CPU time 3.98 seconds
Started Jul 09 05:14:51 PM PDT 24
Finished Jul 09 05:14:59 PM PDT 24
Peak memory 206128 kb
Host smart-a12549a5-fe69-4452-b5b9-05869fa590e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16800
82308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1680082308
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1178182581
Short name T1423
Test name
Test status
Simulation time 10214256713 ps
CPU time 67.07 seconds
Started Jul 09 05:14:51 PM PDT 24
Finished Jul 09 05:16:02 PM PDT 24
Peak memory 206460 kb
Host smart-3f63780b-f281-4fc2-8e66-6dc72e27adef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
82581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1178182581
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1535331913
Short name T1360
Test name
Test status
Simulation time 7369014149 ps
CPU time 213.77 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:18:32 PM PDT 24
Peak memory 206712 kb
Host smart-7a97c5ce-8351-44b0-b7c0-5a337e5a8dab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1535331913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1535331913
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.35886584
Short name T434
Test name
Test status
Simulation time 294509641 ps
CPU time 0.96 seconds
Started Jul 09 05:14:52 PM PDT 24
Finished Jul 09 05:14:58 PM PDT 24
Peak memory 206396 kb
Host smart-a3cc1608-e998-4d57-9714-a4ce6af1dac5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=35886584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.35886584
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.258068189
Short name T1201
Test name
Test status
Simulation time 206178290 ps
CPU time 0.89 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:14:59 PM PDT 24
Peak memory 206068 kb
Host smart-8b4d4d0f-15a8-4f85-bcb9-c7303194b2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25806
8189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.258068189
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.844517576
Short name T1705
Test name
Test status
Simulation time 6126646974 ps
CPU time 57.12 seconds
Started Jul 09 05:14:49 PM PDT 24
Finished Jul 09 05:15:50 PM PDT 24
Peak memory 206276 kb
Host smart-ff98812f-4084-4b9a-aea9-dd3195ca0083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84451
7576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.844517576
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3851230449
Short name T699
Test name
Test status
Simulation time 4992991099 ps
CPU time 48.68 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206712 kb
Host smart-1134030f-e68b-4cdc-befc-ee7b5fbc3e72
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3851230449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3851230449
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1792724998
Short name T1959
Test name
Test status
Simulation time 157520847 ps
CPU time 0.83 seconds
Started Jul 09 05:14:49 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 206120 kb
Host smart-dc81c80d-c0b4-4a7e-aa44-d966f4bb579a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1792724998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1792724998
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2681506511
Short name T1099
Test name
Test status
Simulation time 149989868 ps
CPU time 0.82 seconds
Started Jul 09 05:14:51 PM PDT 24
Finished Jul 09 05:14:56 PM PDT 24
Peak memory 206084 kb
Host smart-24e40f82-5417-4651-84b4-908607237d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26815
06511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2681506511
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.698243485
Short name T1373
Test name
Test status
Simulation time 146638811 ps
CPU time 0.77 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:14:59 PM PDT 24
Peak memory 206000 kb
Host smart-9f13961d-242d-4438-a103-0a358d784687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69824
3485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.698243485
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1256223365
Short name T734
Test name
Test status
Simulation time 189738012 ps
CPU time 0.86 seconds
Started Jul 09 05:14:50 PM PDT 24
Finished Jul 09 05:14:54 PM PDT 24
Peak memory 206124 kb
Host smart-bb1fc451-ccb9-4a94-8dcd-55b1094e3bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
23365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1256223365
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3382072770
Short name T1256
Test name
Test status
Simulation time 178847513 ps
CPU time 0.82 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:02 PM PDT 24
Peak memory 206004 kb
Host smart-952f4665-120e-4ede-953f-36dd97cc337e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33820
72770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3382072770
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.946025629
Short name T2589
Test name
Test status
Simulation time 155817229 ps
CPU time 0.82 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206060 kb
Host smart-1ef8f234-521c-4561-90d0-0f416b853b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94602
5629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.946025629
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1733428256
Short name T1127
Test name
Test status
Simulation time 226354158 ps
CPU time 0.92 seconds
Started Jul 09 05:14:57 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 205992 kb
Host smart-c171eb18-15b4-40b2-8ef9-d56c5bf81613
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1733428256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1733428256
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2652111224
Short name T527
Test name
Test status
Simulation time 197083834 ps
CPU time 0.81 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:02 PM PDT 24
Peak memory 206056 kb
Host smart-7c7dba91-452d-48eb-ab50-886b6a94d5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26521
11224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2652111224
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1502907532
Short name T1589
Test name
Test status
Simulation time 97160377 ps
CPU time 0.71 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206148 kb
Host smart-e54b5702-a3bc-41e9-8817-8464a8c23ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15029
07532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1502907532
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1793327909
Short name T1883
Test name
Test status
Simulation time 20442539955 ps
CPU time 46.23 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206428 kb
Host smart-96a631ce-202e-4c8c-b66e-8126708617bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
27909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1793327909
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2197450190
Short name T1535
Test name
Test status
Simulation time 155549398 ps
CPU time 0.77 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206136 kb
Host smart-84c38099-1e7f-4d8e-a8e7-9eb07d18a09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
50190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2197450190
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1770015452
Short name T1671
Test name
Test status
Simulation time 176198521 ps
CPU time 0.81 seconds
Started Jul 09 05:14:53 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206020 kb
Host smart-9ecb7854-5e95-44f0-9669-44810065a614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
15452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1770015452
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1578795770
Short name T2215
Test name
Test status
Simulation time 313185059 ps
CPU time 0.97 seconds
Started Jul 09 05:14:57 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 206092 kb
Host smart-ccd6b597-efff-42d9-91c8-4c578207069e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
95770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1578795770
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1824467432
Short name T2282
Test name
Test status
Simulation time 176618903 ps
CPU time 0.86 seconds
Started Jul 09 05:14:54 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206164 kb
Host smart-6441c09c-541c-4241-b750-bfaf4addec6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18244
67432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1824467432
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1196836816
Short name T950
Test name
Test status
Simulation time 190611471 ps
CPU time 0.81 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206016 kb
Host smart-f7f6e2c9-a17b-41b7-ada8-779d6154bc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11968
36816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1196836816
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.639662821
Short name T1011
Test name
Test status
Simulation time 179525034 ps
CPU time 0.82 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:02 PM PDT 24
Peak memory 206112 kb
Host smart-a65a12f3-eab9-466b-b6dc-d52582303241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63966
2821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.639662821
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3071455090
Short name T343
Test name
Test status
Simulation time 153776881 ps
CPU time 0.78 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206104 kb
Host smart-cc20dd9c-b18c-4909-9c1d-6d1767b9eda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30714
55090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3071455090
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.575090823
Short name T2384
Test name
Test status
Simulation time 240845803 ps
CPU time 0.94 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:02 PM PDT 24
Peak memory 205992 kb
Host smart-4a05c90f-6bde-432e-9976-3d0f8dd71604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57509
0823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.575090823
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3401479937
Short name T1664
Test name
Test status
Simulation time 6156146300 ps
CPU time 165.87 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:17:46 PM PDT 24
Peak memory 206380 kb
Host smart-d875b6a0-d1c2-4ea1-afa7-aa7a17a16b37
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3401479937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3401479937
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.819283933
Short name T1846
Test name
Test status
Simulation time 169103699 ps
CPU time 0.81 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206160 kb
Host smart-dff36aca-4166-420b-b472-3cd1bde6b12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81928
3933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.819283933
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1765752855
Short name T2631
Test name
Test status
Simulation time 226937661 ps
CPU time 0.87 seconds
Started Jul 09 05:14:58 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 206372 kb
Host smart-91181c6e-038d-4485-879a-5b9f02688faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17657
52855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1765752855
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3551181023
Short name T1931
Test name
Test status
Simulation time 449199336 ps
CPU time 1.23 seconds
Started Jul 09 05:14:56 PM PDT 24
Finished Jul 09 05:15:02 PM PDT 24
Peak memory 206160 kb
Host smart-562e3b88-bdfa-4ee6-b36d-8465413480a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
81023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3551181023
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2932830294
Short name T2067
Test name
Test status
Simulation time 5806381346 ps
CPU time 162.67 seconds
Started Jul 09 05:14:57 PM PDT 24
Finished Jul 09 05:17:45 PM PDT 24
Peak memory 206432 kb
Host smart-c22834bc-c3c0-4428-83dc-c668f1d3ac79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29328
30294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2932830294
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.4248156496
Short name T2059
Test name
Test status
Simulation time 86816351 ps
CPU time 0.76 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206092 kb
Host smart-7b719f39-831c-4f6b-be0b-0b24303d5d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4248156496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.4248156496
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1555432596
Short name T1507
Test name
Test status
Simulation time 3783525174 ps
CPU time 4.61 seconds
Started Jul 09 05:14:54 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 206172 kb
Host smart-f2716465-d2e9-4c5a-a466-4ecb184f74cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1555432596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1555432596
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3131004859
Short name T1917
Test name
Test status
Simulation time 13368065583 ps
CPU time 12.41 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206432 kb
Host smart-17215786-6b16-4fdb-8650-4b4ae1f5640e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3131004859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3131004859
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2992096530
Short name T2218
Test name
Test status
Simulation time 23380313230 ps
CPU time 23.62 seconds
Started Jul 09 05:14:57 PM PDT 24
Finished Jul 09 05:15:26 PM PDT 24
Peak memory 206156 kb
Host smart-e03f0821-43fd-41c6-9593-7e2fc3b71890
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2992096530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2992096530
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1180672940
Short name T397
Test name
Test status
Simulation time 156643030 ps
CPU time 0.88 seconds
Started Jul 09 05:14:54 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206116 kb
Host smart-30fa44d8-02b6-484b-b047-467d6eaf1298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806
72940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1180672940
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3754132905
Short name T1350
Test name
Test status
Simulation time 178803007 ps
CPU time 0.79 seconds
Started Jul 09 05:14:55 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 206056 kb
Host smart-aa88b0b5-a0bc-4cfc-8370-e4ff1ef153c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541
32905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3754132905
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2049092803
Short name T2042
Test name
Test status
Simulation time 197713667 ps
CPU time 0.87 seconds
Started Jul 09 05:15:00 PM PDT 24
Finished Jul 09 05:15:05 PM PDT 24
Peak memory 206060 kb
Host smart-38c77c09-ed7a-4ec6-a1a3-581bcfbc36f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
92803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2049092803
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2687289440
Short name T156
Test name
Test status
Simulation time 1466822835 ps
CPU time 3.19 seconds
Started Jul 09 05:14:59 PM PDT 24
Finished Jul 09 05:15:07 PM PDT 24
Peak memory 206372 kb
Host smart-22c45d92-16a0-4043-8f60-476313853d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26872
89440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2687289440
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1902510782
Short name T2526
Test name
Test status
Simulation time 15281742088 ps
CPU time 33.18 seconds
Started Jul 09 05:15:01 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 206416 kb
Host smart-1ca5f369-fb63-43ff-9453-d5e16c01d711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19025
10782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1902510782
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1939200843
Short name T1403
Test name
Test status
Simulation time 307749417 ps
CPU time 1.07 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206124 kb
Host smart-4c2366cd-91a9-48d3-9013-9d53d9800734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19392
00843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1939200843
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_enable.726960549
Short name T1760
Test name
Test status
Simulation time 44395907 ps
CPU time 0.67 seconds
Started Jul 09 05:14:59 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 206084 kb
Host smart-02828552-b3c1-4f6f-8087-4b4e0be89865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72696
0549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.726960549
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.158873753
Short name T803
Test name
Test status
Simulation time 823273743 ps
CPU time 1.98 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:07 PM PDT 24
Peak memory 206364 kb
Host smart-abd78916-234b-4253-a963-ded1421287b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
3753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.158873753
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4181491082
Short name T394
Test name
Test status
Simulation time 179790933 ps
CPU time 1.97 seconds
Started Jul 09 05:14:58 PM PDT 24
Finished Jul 09 05:15:05 PM PDT 24
Peak memory 206292 kb
Host smart-943ead70-543c-4a28-8705-8bc1dbb942b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
91082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4181491082
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2133653383
Short name T214
Test name
Test status
Simulation time 234221091 ps
CPU time 0.95 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206056 kb
Host smart-aa38419d-9cbb-4fcf-8ac1-97052580ddc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21336
53383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2133653383
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.642034230
Short name T1472
Test name
Test status
Simulation time 138560175 ps
CPU time 0.77 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206104 kb
Host smart-398601fd-30fd-4015-9a99-f1f3db43e8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64203
4230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.642034230
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1933282980
Short name T341
Test name
Test status
Simulation time 167721701 ps
CPU time 0.86 seconds
Started Jul 09 05:14:58 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 206116 kb
Host smart-487b2fd0-66bf-41ac-854f-e6521648f333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19332
82980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1933282980
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3630781057
Short name T218
Test name
Test status
Simulation time 6291354522 ps
CPU time 173.24 seconds
Started Jul 09 05:14:59 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 206288 kb
Host smart-7001cb1b-aac9-4d8e-b843-5ff88c831caa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3630781057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3630781057
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2554532456
Short name T884
Test name
Test status
Simulation time 232243127 ps
CPU time 0.98 seconds
Started Jul 09 05:14:59 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 206132 kb
Host smart-6703e971-682d-4aec-98f3-78a08db27bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25545
32456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2554532456
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1314135156
Short name T2253
Test name
Test status
Simulation time 23344005733 ps
CPU time 23.24 seconds
Started Jul 09 05:15:01 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206176 kb
Host smart-6be0ac7c-3ecc-464a-9a5c-21a6cdee6be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13141
35156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1314135156
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3602402206
Short name T2482
Test name
Test status
Simulation time 3315435185 ps
CPU time 4.27 seconds
Started Jul 09 05:14:59 PM PDT 24
Finished Jul 09 05:15:07 PM PDT 24
Peak memory 206060 kb
Host smart-a058f247-9fcb-41e3-8146-750ab6983912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
02206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3602402206
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2389290623
Short name T1866
Test name
Test status
Simulation time 8019296165 ps
CPU time 60.81 seconds
Started Jul 09 05:15:03 PM PDT 24
Finished Jul 09 05:16:08 PM PDT 24
Peak memory 206452 kb
Host smart-cb02fbbf-92cc-4ea7-9096-def930709fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23892
90623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2389290623
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.137244791
Short name T2143
Test name
Test status
Simulation time 5423277103 ps
CPU time 43.12 seconds
Started Jul 09 05:15:00 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206264 kb
Host smart-b084fd67-3fde-4f81-8d38-3a1db4a2fb49
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=137244791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.137244791
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3762359962
Short name T2376
Test name
Test status
Simulation time 279254368 ps
CPU time 0.95 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206020 kb
Host smart-19476e40-b7ad-42f1-bd4e-a4bad2b59a6e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3762359962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3762359962
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.33122535
Short name T2491
Test name
Test status
Simulation time 191524910 ps
CPU time 0.94 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206044 kb
Host smart-e10489a5-d739-4858-8642-b4f68aefd853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33122
535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.33122535
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1490033975
Short name T798
Test name
Test status
Simulation time 3432866697 ps
CPU time 91.21 seconds
Started Jul 09 05:15:01 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206412 kb
Host smart-e405b407-7c72-4bcf-aac3-76054841ff5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14900
33975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1490033975
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1653467516
Short name T84
Test name
Test status
Simulation time 5798415570 ps
CPU time 162.83 seconds
Started Jul 09 05:15:00 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206332 kb
Host smart-b7ed5778-62d5-461b-a145-2a0d96f8d522
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1653467516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1653467516
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3737437235
Short name T1474
Test name
Test status
Simulation time 225372233 ps
CPU time 0.86 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206104 kb
Host smart-73117b03-6d33-41b2-974c-8312e5c3d0f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3737437235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3737437235
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3284368332
Short name T642
Test name
Test status
Simulation time 154033669 ps
CPU time 0.81 seconds
Started Jul 09 05:15:00 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 206024 kb
Host smart-580315e2-59f3-4173-a075-cbdcd1ce8ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32843
68332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3284368332
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3881240638
Short name T135
Test name
Test status
Simulation time 219245353 ps
CPU time 0.98 seconds
Started Jul 09 05:15:01 PM PDT 24
Finished Jul 09 05:15:05 PM PDT 24
Peak memory 206152 kb
Host smart-63d8262d-5b28-4fe1-8a89-741a8e6a637d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38812
40638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3881240638
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3915413938
Short name T348
Test name
Test status
Simulation time 180640552 ps
CPU time 0.83 seconds
Started Jul 09 05:15:00 PM PDT 24
Finished Jul 09 05:15:05 PM PDT 24
Peak memory 206092 kb
Host smart-cb52c978-3e48-456d-bc68-445a237330c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
13938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3915413938
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1207956598
Short name T2012
Test name
Test status
Simulation time 170859018 ps
CPU time 0.88 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206040 kb
Host smart-6fe37af5-c585-4cfa-9334-d4f2b81a6f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12079
56598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1207956598
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1771124697
Short name T2379
Test name
Test status
Simulation time 158245005 ps
CPU time 0.77 seconds
Started Jul 09 05:15:00 PM PDT 24
Finished Jul 09 05:15:04 PM PDT 24
Peak memory 206140 kb
Host smart-7d86ac26-34a7-4cd4-b05c-4113b29b2d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17711
24697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1771124697
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.40996851
Short name T719
Test name
Test status
Simulation time 234533238 ps
CPU time 0.99 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206372 kb
Host smart-b76ee07f-9dd0-42e4-aeb0-f6b28ac5bbbc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=40996851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.40996851
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2097631802
Short name T43
Test name
Test status
Simulation time 141443983 ps
CPU time 0.8 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206128 kb
Host smart-1dc5ec1f-e077-4645-898f-1751fbe2f662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20976
31802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2097631802
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1123950065
Short name T42
Test name
Test status
Simulation time 50042310 ps
CPU time 0.68 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206048 kb
Host smart-70f5b0e4-f109-40cf-b1a3-bd39e7696b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11239
50065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1123950065
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3154329368
Short name T1800
Test name
Test status
Simulation time 8679044508 ps
CPU time 20.83 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206288 kb
Host smart-abdce38b-21a5-4835-b7a3-0d5d98d29499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543
29368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3154329368
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2416666152
Short name T1456
Test name
Test status
Simulation time 180250726 ps
CPU time 0.84 seconds
Started Jul 09 05:15:05 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206160 kb
Host smart-79227e88-7120-4b6d-9171-f00278a774ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24166
66152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2416666152
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.492808287
Short name T2413
Test name
Test status
Simulation time 210892849 ps
CPU time 0.93 seconds
Started Jul 09 05:15:05 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206124 kb
Host smart-96bad98f-9d2e-45ac-a182-7c3c3d7036cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49280
8287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.492808287
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3807762415
Short name T2472
Test name
Test status
Simulation time 213360347 ps
CPU time 0.86 seconds
Started Jul 09 05:15:06 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206152 kb
Host smart-276e75c9-cdff-402f-b0cb-e1c1dc7c44e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
62415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3807762415
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1250130880
Short name T2131
Test name
Test status
Simulation time 201496002 ps
CPU time 0.9 seconds
Started Jul 09 05:15:06 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206152 kb
Host smart-2a81b3b9-87f4-4052-a9fa-c8ac55c0d705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12501
30880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1250130880
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3711441641
Short name T956
Test name
Test status
Simulation time 169975582 ps
CPU time 0.78 seconds
Started Jul 09 05:15:05 PM PDT 24
Finished Jul 09 05:15:10 PM PDT 24
Peak memory 206128 kb
Host smart-25e08529-342f-4ef6-bcd5-50cc8ebdf6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37114
41641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3711441641
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1950478418
Short name T887
Test name
Test status
Simulation time 166681172 ps
CPU time 0.87 seconds
Started Jul 09 05:15:03 PM PDT 24
Finished Jul 09 05:15:08 PM PDT 24
Peak memory 206144 kb
Host smart-00f5b256-d394-4cef-bd24-4e190ec006f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19504
78418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1950478418
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.576185735
Short name T1739
Test name
Test status
Simulation time 159346839 ps
CPU time 0.79 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206156 kb
Host smart-5aff0e09-b3d4-4e1e-a52b-b6b28de6daa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57618
5735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.576185735
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1317537645
Short name T2679
Test name
Test status
Simulation time 232444452 ps
CPU time 1.11 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:07 PM PDT 24
Peak memory 206064 kb
Host smart-c5f59ebf-3187-4e92-9cc0-284cef44dc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
37645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1317537645
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2181531059
Short name T1429
Test name
Test status
Simulation time 3862308974 ps
CPU time 28.44 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:37 PM PDT 24
Peak memory 206448 kb
Host smart-0d0dd638-7332-4a8d-81ea-81bb5d6d33e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2181531059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2181531059
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.946392497
Short name T2636
Test name
Test status
Simulation time 171846950 ps
CPU time 0.81 seconds
Started Jul 09 05:15:03 PM PDT 24
Finished Jul 09 05:15:08 PM PDT 24
Peak memory 206056 kb
Host smart-525afc8e-b198-4cfd-8829-e514469ccb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94639
2497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.946392497
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3679632140
Short name T1998
Test name
Test status
Simulation time 193393698 ps
CPU time 0.95 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:07 PM PDT 24
Peak memory 205992 kb
Host smart-1a2a6aac-0ff5-4be1-95ff-bdbb38a917a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36796
32140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3679632140
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1693533795
Short name T2311
Test name
Test status
Simulation time 403995960 ps
CPU time 1.2 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206140 kb
Host smart-9990d5fd-3e37-43e3-8b4a-3f04bbef426b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16935
33795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1693533795
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1499282355
Short name T2596
Test name
Test status
Simulation time 5612023528 ps
CPU time 41.18 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206628 kb
Host smart-72cb26eb-7b2b-433e-ba97-bc103dd7d080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14992
82355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1499282355
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.902997962
Short name T1559
Test name
Test status
Simulation time 41115554 ps
CPU time 0.7 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:05 PM PDT 24
Peak memory 206124 kb
Host smart-63ef47de-15e1-46c2-960e-7846982a1569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=902997962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.902997962
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1218795917
Short name T1602
Test name
Test status
Simulation time 4393382411 ps
CPU time 4.56 seconds
Started Jul 09 05:11:51 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206232 kb
Host smart-64fc9e7b-e160-46ab-8f12-9b5054e606e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1218795917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1218795917
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2235630059
Short name T1224
Test name
Test status
Simulation time 13379130855 ps
CPU time 16.51 seconds
Started Jul 09 05:11:53 PM PDT 24
Finished Jul 09 05:12:11 PM PDT 24
Peak memory 206112 kb
Host smart-5c68579e-7661-45f5-9439-019b0f42251f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2235630059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2235630059
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.647533467
Short name T1606
Test name
Test status
Simulation time 188181337 ps
CPU time 0.86 seconds
Started Jul 09 05:11:54 PM PDT 24
Finished Jul 09 05:11:55 PM PDT 24
Peak memory 206056 kb
Host smart-b3f573bb-0834-4da4-b006-4ef01c20f8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64753
3467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.647533467
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.4186294573
Short name T54
Test name
Test status
Simulation time 149916407 ps
CPU time 0.81 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:11:57 PM PDT 24
Peak memory 206056 kb
Host smart-72b0ca79-8b7f-44be-ad81-381f2321f8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41862
94573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.4186294573
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3396452787
Short name T2266
Test name
Test status
Simulation time 178256943 ps
CPU time 0.81 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:11:57 PM PDT 24
Peak memory 206052 kb
Host smart-a65cd7f6-1a84-4cff-9fd8-5b98a1d2c6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33964
52787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3396452787
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3153226131
Short name T1568
Test name
Test status
Simulation time 183565861 ps
CPU time 0.83 seconds
Started Jul 09 05:11:54 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206016 kb
Host smart-1787f689-3b14-4f8b-9606-6eadc6c4a0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
26131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3153226131
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3702948202
Short name T1915
Test name
Test status
Simulation time 878985823 ps
CPU time 2.15 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:05 PM PDT 24
Peak memory 206308 kb
Host smart-84d3f45d-2fc4-4980-a678-0d41d93bf8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
48202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3702948202
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3259458969
Short name T94
Test name
Test status
Simulation time 11054726234 ps
CPU time 19.88 seconds
Started Jul 09 05:11:57 PM PDT 24
Finished Jul 09 05:12:17 PM PDT 24
Peak memory 206316 kb
Host smart-50baf67a-eb2b-4dfd-aa48-9b0126a515a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32594
58969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3259458969
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2311322860
Short name T828
Test name
Test status
Simulation time 325265242 ps
CPU time 1.08 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206064 kb
Host smart-f2965e39-60bf-4804-acea-ee36099232d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
22860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2311322860
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2281015459
Short name T250
Test name
Test status
Simulation time 142745323 ps
CPU time 0.79 seconds
Started Jul 09 05:11:54 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206120 kb
Host smart-5df869b9-de9c-47ef-b2f7-d7c29c5aa52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
15459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2281015459
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3389339605
Short name T2570
Test name
Test status
Simulation time 46459603 ps
CPU time 0.66 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206052 kb
Host smart-5ab31e5a-19f7-4e73-843f-a3f6c7589b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33893
39605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3389339605
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1177440868
Short name T1349
Test name
Test status
Simulation time 911990733 ps
CPU time 2.34 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:07 PM PDT 24
Peak memory 206320 kb
Host smart-b60246b2-3c81-4d72-9eda-c9fa2bd7cfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11774
40868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1177440868
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.856965902
Short name T498
Test name
Test status
Simulation time 247813531 ps
CPU time 1.46 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:02 PM PDT 24
Peak memory 206352 kb
Host smart-34356297-e7a9-45ff-84f1-e4df5b436021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85696
5902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.856965902
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1845359955
Short name T1757
Test name
Test status
Simulation time 114190646558 ps
CPU time 160.58 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206308 kb
Host smart-86422a09-ab61-49ec-907f-e66e068b370f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1845359955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1845359955
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3357731849
Short name T1056
Test name
Test status
Simulation time 98038658008 ps
CPU time 129.37 seconds
Started Jul 09 05:11:53 PM PDT 24
Finished Jul 09 05:14:03 PM PDT 24
Peak memory 206416 kb
Host smart-2321586d-6c1f-4680-822b-28ef4443ef0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357731849 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3357731849
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.3020127051
Short name T1595
Test name
Test status
Simulation time 103102435505 ps
CPU time 160.76 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:14:33 PM PDT 24
Peak memory 206368 kb
Host smart-ba338bd0-1683-4ccd-bc3d-de6eddb8ac1f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3020127051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3020127051
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2993612157
Short name T390
Test name
Test status
Simulation time 83177497726 ps
CPU time 112.18 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206324 kb
Host smart-422e9504-6483-4baf-8af8-2135361c99cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993612157 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2993612157
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3315241234
Short name T936
Test name
Test status
Simulation time 103176190231 ps
CPU time 139.48 seconds
Started Jul 09 05:11:56 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 206424 kb
Host smart-5aa5ecb3-ab96-46c2-ad5e-b60f5633ac6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33152
41234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3315241234
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2147273557
Short name T1308
Test name
Test status
Simulation time 166117433 ps
CPU time 0.81 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:01 PM PDT 24
Peak memory 206112 kb
Host smart-e355f5f1-66f5-4819-be86-255f2a080c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21472
73557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2147273557
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1108659676
Short name T1416
Test name
Test status
Simulation time 143305684 ps
CPU time 0.74 seconds
Started Jul 09 05:11:57 PM PDT 24
Finished Jul 09 05:11:58 PM PDT 24
Peak memory 206124 kb
Host smart-999ae6c6-d940-423c-a11e-d89e7caebcf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11086
59676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1108659676
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2577157090
Short name T1912
Test name
Test status
Simulation time 256300039 ps
CPU time 0.9 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206128 kb
Host smart-75b26f5e-de77-4e4d-a4c7-c1ba08cbead3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25771
57090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2577157090
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.373513988
Short name T1269
Test name
Test status
Simulation time 6644331623 ps
CPU time 63.37 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:13:08 PM PDT 24
Peak memory 206392 kb
Host smart-2d727d0f-db21-4ae8-b7bd-386854cc85df
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=373513988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.373513988
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.194376834
Short name T1792
Test name
Test status
Simulation time 151395372 ps
CPU time 0.82 seconds
Started Jul 09 05:11:56 PM PDT 24
Finished Jul 09 05:11:58 PM PDT 24
Peak memory 206068 kb
Host smart-49f9d984-7a53-408d-9793-97cc1cf8c7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
6834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.194376834
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2248407931
Short name T1921
Test name
Test status
Simulation time 23300041241 ps
CPU time 23.43 seconds
Started Jul 09 05:11:56 PM PDT 24
Finished Jul 09 05:12:20 PM PDT 24
Peak memory 206188 kb
Host smart-01feef5b-f216-48aa-9592-19ce618516a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22484
07931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2248407931
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2983539221
Short name T2119
Test name
Test status
Simulation time 3309808690 ps
CPU time 3.71 seconds
Started Jul 09 05:11:58 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 206196 kb
Host smart-2e351e74-d80f-4520-83bb-bed1d18224e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
39221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2983539221
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.105538651
Short name T1093
Test name
Test status
Simulation time 11657394961 ps
CPU time 111.78 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206368 kb
Host smart-06542b8a-e42f-46ef-b652-b1dc99593f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10553
8651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.105538651
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2822424185
Short name T1628
Test name
Test status
Simulation time 5404816096 ps
CPU time 36.48 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206352 kb
Host smart-c1fc63d4-b604-4819-9923-859ac633cb96
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2822424185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2822424185
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1073427218
Short name T2547
Test name
Test status
Simulation time 234058873 ps
CPU time 0.88 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:05 PM PDT 24
Peak memory 206116 kb
Host smart-ad72420a-81ab-4510-b764-81542c2fc244
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1073427218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1073427218
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.527841713
Short name T2293
Test name
Test status
Simulation time 198684165 ps
CPU time 0.9 seconds
Started Jul 09 05:11:58 PM PDT 24
Finished Jul 09 05:11:59 PM PDT 24
Peak memory 206132 kb
Host smart-b2a1a485-6ae2-4188-99f8-6875f76c1d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52784
1713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.527841713
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2362315958
Short name T2349
Test name
Test status
Simulation time 5379220340 ps
CPU time 51.15 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 206332 kb
Host smart-106ee87b-b935-4e17-a9d9-2966b19c1216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23623
15958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2362315958
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3436077108
Short name T817
Test name
Test status
Simulation time 5712575139 ps
CPU time 156.45 seconds
Started Jul 09 05:11:55 PM PDT 24
Finished Jul 09 05:14:33 PM PDT 24
Peak memory 206388 kb
Host smart-17d91f32-eaf9-4442-9027-8fbd61b5bc74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3436077108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3436077108
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3328569256
Short name T606
Test name
Test status
Simulation time 156642085 ps
CPU time 0.82 seconds
Started Jul 09 05:11:54 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206004 kb
Host smart-9d5ccc59-8467-4be6-a64e-e5d5b9f96035
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3328569256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3328569256
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3915379045
Short name T2490
Test name
Test status
Simulation time 146356100 ps
CPU time 0.72 seconds
Started Jul 09 05:11:52 PM PDT 24
Finished Jul 09 05:11:54 PM PDT 24
Peak memory 206052 kb
Host smart-bab0cd45-9652-425c-ab92-6c6d43b03c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39153
79045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3915379045
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3473293080
Short name T2498
Test name
Test status
Simulation time 218128317 ps
CPU time 0.92 seconds
Started Jul 09 05:11:54 PM PDT 24
Finished Jul 09 05:11:56 PM PDT 24
Peak memory 206036 kb
Host smart-c035d702-74bb-4beb-a830-c14a4a75b7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34732
93080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3473293080
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2591625024
Short name T213
Test name
Test status
Simulation time 208366722 ps
CPU time 0.9 seconds
Started Jul 09 05:11:56 PM PDT 24
Finished Jul 09 05:11:58 PM PDT 24
Peak memory 206056 kb
Host smart-74c9c40e-1a21-4633-8e72-c6b7fca0b9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25916
25024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2591625024
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2282439153
Short name T2432
Test name
Test status
Simulation time 173659571 ps
CPU time 0.82 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206088 kb
Host smart-c65bebc4-9a94-48e9-bec9-5ab9cf5c8a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22824
39153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2282439153
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1036306446
Short name T1453
Test name
Test status
Simulation time 197849308 ps
CPU time 0.83 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206064 kb
Host smart-58a05989-6c4a-4997-9ed8-dcec80e18fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10363
06446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1036306446
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3743650289
Short name T1496
Test name
Test status
Simulation time 167745485 ps
CPU time 0.82 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:01 PM PDT 24
Peak memory 206116 kb
Host smart-0f6a4d43-9fb5-48c8-9d52-e0a0ee1bc6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
50289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3743650289
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1628029954
Short name T544
Test name
Test status
Simulation time 219712601 ps
CPU time 0.89 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206040 kb
Host smart-297443ad-eae8-4130-9841-d993a88a680f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1628029954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1628029954
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1408915451
Short name T201
Test name
Test status
Simulation time 219336570 ps
CPU time 0.91 seconds
Started Jul 09 05:12:00 PM PDT 24
Finished Jul 09 05:12:01 PM PDT 24
Peak memory 206116 kb
Host smart-a2f6d27d-8612-4c36-929c-4d8497ee34f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14089
15451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1408915451
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.891190013
Short name T2582
Test name
Test status
Simulation time 153622682 ps
CPU time 0.79 seconds
Started Jul 09 05:12:00 PM PDT 24
Finished Jul 09 05:12:02 PM PDT 24
Peak memory 206128 kb
Host smart-e16fb0a1-edec-4152-b54c-b36832e35038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89119
0013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.891190013
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3509677294
Short name T1165
Test name
Test status
Simulation time 57000029 ps
CPU time 0.65 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:01 PM PDT 24
Peak memory 206124 kb
Host smart-78483085-2c15-495b-a2e9-9c12d5686de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
77294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3509677294
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.168615159
Short name T976
Test name
Test status
Simulation time 11259892259 ps
CPU time 23.34 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:25 PM PDT 24
Peak memory 206452 kb
Host smart-21f56c8c-a454-4699-a5c9-511800edd7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
5159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.168615159
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1482300861
Short name T2651
Test name
Test status
Simulation time 210678325 ps
CPU time 0.93 seconds
Started Jul 09 05:11:57 PM PDT 24
Finished Jul 09 05:11:58 PM PDT 24
Peak memory 206056 kb
Host smart-8bfe8ab2-31de-42b4-ab14-97879972c86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823
00861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1482300861
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.4151335392
Short name T1960
Test name
Test status
Simulation time 238103780 ps
CPU time 0.92 seconds
Started Jul 09 05:12:00 PM PDT 24
Finished Jul 09 05:12:02 PM PDT 24
Peak memory 206092 kb
Host smart-850223f8-c839-464f-9925-e141834b1c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41513
35392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4151335392
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1633068866
Short name T164
Test name
Test status
Simulation time 10417565649 ps
CPU time 68.13 seconds
Started Jul 09 05:12:00 PM PDT 24
Finished Jul 09 05:13:09 PM PDT 24
Peak memory 206448 kb
Host smart-2b384927-8153-4182-a7b5-81f8aec3623b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1633068866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1633068866
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.291739268
Short name T1775
Test name
Test status
Simulation time 10616245757 ps
CPU time 68.91 seconds
Started Jul 09 05:11:57 PM PDT 24
Finished Jul 09 05:13:06 PM PDT 24
Peak memory 206432 kb
Host smart-6b06bbbf-1397-462a-982b-ac846bbaf746
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=291739268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.291739268
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1586064926
Short name T551
Test name
Test status
Simulation time 8514762308 ps
CPU time 54.53 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206380 kb
Host smart-5a7e27d8-9b78-44f8-aeae-06f57012c3e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1586064926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1586064926
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.569961372
Short name T2230
Test name
Test status
Simulation time 217040886 ps
CPU time 0.89 seconds
Started Jul 09 05:11:58 PM PDT 24
Finished Jul 09 05:11:59 PM PDT 24
Peak memory 206124 kb
Host smart-2a514eed-a43a-4ad9-8cea-5cbdd23689eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56996
1372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.569961372
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2810466900
Short name T2209
Test name
Test status
Simulation time 196312469 ps
CPU time 0.85 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:00 PM PDT 24
Peak memory 205964 kb
Host smart-67352a25-b6a1-4754-8095-55e68c13062c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28104
66900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2810466900
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3016539404
Short name T1809
Test name
Test status
Simulation time 181987833 ps
CPU time 0.8 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 206136 kb
Host smart-1d7fbaed-705d-461a-8ebd-dd037eeed9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30165
39404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3016539404
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.85045699
Short name T1458
Test name
Test status
Simulation time 172700886 ps
CPU time 0.81 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206016 kb
Host smart-9193be84-1877-4b02-b6be-54bcbb6c504f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85045
699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.85045699
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.142414316
Short name T191
Test name
Test status
Simulation time 1085765347 ps
CPU time 1.9 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 224976 kb
Host smart-5a84ade2-d5cf-4f3b-8214-78b2c88ad48d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=142414316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.142414316
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.466093004
Short name T1014
Test name
Test status
Simulation time 407536557 ps
CPU time 1.28 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:02 PM PDT 24
Peak memory 206148 kb
Host smart-8dde77bc-74fc-4d9a-ba01-7ec14c625f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46609
3004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.466093004
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1891605353
Short name T1966
Test name
Test status
Simulation time 216530876 ps
CPU time 0.92 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:00 PM PDT 24
Peak memory 206148 kb
Host smart-6e83767f-9921-470b-8764-3c6e07ab38b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
05353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1891605353
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2864460126
Short name T836
Test name
Test status
Simulation time 163317658 ps
CPU time 0.79 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206132 kb
Host smart-4e14abfd-d900-4a54-9aef-5bde8ca1da0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
60126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2864460126
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.985010524
Short name T2289
Test name
Test status
Simulation time 154419021 ps
CPU time 0.86 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206148 kb
Host smart-05d22179-9a6e-4eff-8371-28485141acdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98501
0524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.985010524
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3127080532
Short name T1825
Test name
Test status
Simulation time 193470757 ps
CPU time 0.88 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206136 kb
Host smart-0db7638e-9e46-4441-a71f-720bf35f618c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31270
80532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3127080532
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.4006875479
Short name T1370
Test name
Test status
Simulation time 4370311054 ps
CPU time 121.31 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:14:04 PM PDT 24
Peak memory 206484 kb
Host smart-fac6b4d4-8eef-4101-b99e-9198b8d583c5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4006875479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4006875479
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3296739752
Short name T1477
Test name
Test status
Simulation time 160721776 ps
CPU time 0.87 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 206084 kb
Host smart-605d8917-8228-4220-82fa-c39ba894cc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32967
39752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3296739752
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.966909981
Short name T422
Test name
Test status
Simulation time 176978338 ps
CPU time 0.85 seconds
Started Jul 09 05:11:58 PM PDT 24
Finished Jul 09 05:12:00 PM PDT 24
Peak memory 206156 kb
Host smart-ec4c66b0-25f1-42d6-9015-a4bc700c6062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96690
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.966909981
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.3170024698
Short name T2507
Test name
Test status
Simulation time 1273218732 ps
CPU time 2.65 seconds
Started Jul 09 05:11:59 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 206272 kb
Host smart-3e039137-866a-4726-b84d-a47f3c77d1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700
24698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.3170024698
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1736165614
Short name T1877
Test name
Test status
Simulation time 3538837999 ps
CPU time 94.94 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206416 kb
Host smart-83eb3044-fb1f-4284-953e-fabaa8db0a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17361
65614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1736165614
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2516869065
Short name T2229
Test name
Test status
Simulation time 33292248 ps
CPU time 0.67 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206052 kb
Host smart-81cfaa6b-b8d5-4788-a093-a71b019acbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2516869065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2516869065
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2343466587
Short name T1919
Test name
Test status
Simulation time 4010121416 ps
CPU time 4.85 seconds
Started Jul 09 05:15:02 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206152 kb
Host smart-0cc60c8c-aefd-46bd-b991-b53caa69486b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2343466587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2343466587
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2092799319
Short name T549
Test name
Test status
Simulation time 13448284743 ps
CPU time 12.31 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206248 kb
Host smart-f0115be8-4e55-410d-a353-73e5904dca7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2092799319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2092799319
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.241686453
Short name T1338
Test name
Test status
Simulation time 23498706012 ps
CPU time 25.94 seconds
Started Jul 09 05:15:04 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206360 kb
Host smart-c421c7e8-2f9b-4cd4-92de-31e5b7683203
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=241686453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.241686453
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1854569528
Short name T2338
Test name
Test status
Simulation time 178629608 ps
CPU time 0.85 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206064 kb
Host smart-af6fbfbc-c712-417e-80cd-066cb77c94c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545
69528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1854569528
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1701385699
Short name T1275
Test name
Test status
Simulation time 192060361 ps
CPU time 0.84 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206060 kb
Host smart-01334137-5046-47d6-8f3c-9d0f346a0afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17013
85699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1701385699
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3356534376
Short name T944
Test name
Test status
Simulation time 145003814 ps
CPU time 0.85 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:15:13 PM PDT 24
Peak memory 206064 kb
Host smart-1c1a094e-979a-4909-9836-9ec156458302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
34376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3356534376
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1624547450
Short name T854
Test name
Test status
Simulation time 265907990 ps
CPU time 0.91 seconds
Started Jul 09 05:15:06 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206128 kb
Host smart-c9f0dce1-4772-49eb-8f63-53512a5e87e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
47450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1624547450
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2845744612
Short name T2414
Test name
Test status
Simulation time 7652093922 ps
CPU time 16.34 seconds
Started Jul 09 05:15:09 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206356 kb
Host smart-3788838c-7c03-409a-bf50-108e7b3335bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457
44612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2845744612
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3935460829
Short name T1295
Test name
Test status
Simulation time 443482250 ps
CPU time 1.4 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:15:13 PM PDT 24
Peak memory 206024 kb
Host smart-03cc912e-b4bf-4045-b84e-91e23e935200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354
60829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3935460829
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2500682938
Short name T249
Test name
Test status
Simulation time 135759463 ps
CPU time 0.76 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206104 kb
Host smart-b88a5ec1-4590-4659-9841-b1d98367e28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25006
82938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2500682938
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1866646861
Short name T833
Test name
Test status
Simulation time 75800711 ps
CPU time 0.73 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206020 kb
Host smart-1b2a28fe-e287-499e-915e-f97d0403bfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
46861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1866646861
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3256370480
Short name T359
Test name
Test status
Simulation time 843725271 ps
CPU time 1.96 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:15:14 PM PDT 24
Peak memory 206304 kb
Host smart-164e8cd7-51f5-4a02-b583-25ce0087c1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
70480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3256370480
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2474551712
Short name T1147
Test name
Test status
Simulation time 228709520 ps
CPU time 1.29 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206304 kb
Host smart-d008da6c-d3a1-49a1-971c-b5a386a9697d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
51712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2474551712
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1532315859
Short name T2579
Test name
Test status
Simulation time 195305903 ps
CPU time 0.88 seconds
Started Jul 09 05:15:06 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 205960 kb
Host smart-7f5d17eb-adc9-4c5d-b00b-e59cc3b35f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
15859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1532315859
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2339524919
Short name T487
Test name
Test status
Simulation time 141656488 ps
CPU time 0.87 seconds
Started Jul 09 05:15:09 PM PDT 24
Finished Jul 09 05:15:13 PM PDT 24
Peak memory 206060 kb
Host smart-01eff1f6-a9c5-472a-a409-ebf2428563d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23395
24919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2339524919
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3952799044
Short name T2706
Test name
Test status
Simulation time 321525750 ps
CPU time 1.01 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206160 kb
Host smart-b8646316-812d-4327-ae39-454ad4ede594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
99044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3952799044
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.937495717
Short name T220
Test name
Test status
Simulation time 9574012306 ps
CPU time 88.61 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:16:40 PM PDT 24
Peak memory 206224 kb
Host smart-467616f7-b222-4570-b669-d77380e6ccb8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=937495717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.937495717
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3895127237
Short name T1068
Test name
Test status
Simulation time 218065210 ps
CPU time 0.87 seconds
Started Jul 09 05:15:10 PM PDT 24
Finished Jul 09 05:15:15 PM PDT 24
Peak memory 206120 kb
Host smart-976124ef-b1dd-4be9-899a-613189c8e210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38951
27237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3895127237
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.966027554
Short name T1278
Test name
Test status
Simulation time 23325152791 ps
CPU time 26.35 seconds
Started Jul 09 05:15:10 PM PDT 24
Finished Jul 09 05:15:40 PM PDT 24
Peak memory 206172 kb
Host smart-1ef9d878-04fe-49e2-ba30-1a5b2ef5850c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96602
7554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.966027554
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.874190213
Short name T367
Test name
Test status
Simulation time 3348316148 ps
CPU time 3.57 seconds
Started Jul 09 05:15:09 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206172 kb
Host smart-0480cca9-e896-49fd-8b01-961efe778460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87419
0213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.874190213
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.814811447
Short name T2468
Test name
Test status
Simulation time 5508449202 ps
CPU time 156.01 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 206388 kb
Host smart-32e8d771-e4f6-4bdf-b6f2-e6246a933a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81481
1447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.814811447
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2595992562
Short name T974
Test name
Test status
Simulation time 4346412996 ps
CPU time 40.46 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206444 kb
Host smart-ef23e406-d030-4c8e-96f1-f150df125416
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2595992562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2595992562
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2153547392
Short name T2494
Test name
Test status
Simulation time 298672676 ps
CPU time 0.98 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206060 kb
Host smart-63ab7775-ee3d-4687-947f-a0babb9eb62c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2153547392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2153547392
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3058186537
Short name T1292
Test name
Test status
Simulation time 199992793 ps
CPU time 0.85 seconds
Started Jul 09 05:15:07 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206060 kb
Host smart-b555e9bf-12ea-4c78-aafe-a556a9c7c6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
86537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3058186537
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1335382705
Short name T933
Test name
Test status
Simulation time 4508642891 ps
CPU time 118.34 seconds
Started Jul 09 05:15:10 PM PDT 24
Finished Jul 09 05:17:13 PM PDT 24
Peak memory 206372 kb
Host smart-e2ce1a0a-7891-48a4-8002-7f6ac832e6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13353
82705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1335382705
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.4092977325
Short name T1996
Test name
Test status
Simulation time 5484408805 ps
CPU time 153.99 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:17:50 PM PDT 24
Peak memory 206304 kb
Host smart-203d2100-8e83-464b-885e-d89e0ae851a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4092977325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.4092977325
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1972178833
Short name T2581
Test name
Test status
Simulation time 148027020 ps
CPU time 0.81 seconds
Started Jul 09 05:15:13 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206140 kb
Host smart-51e13209-7081-4bb6-b8e3-24c76a06cbc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1972178833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1972178833
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.355040106
Short name T1215
Test name
Test status
Simulation time 139139652 ps
CPU time 0.8 seconds
Started Jul 09 05:15:14 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206164 kb
Host smart-d934081c-28c6-4814-9f45-1792f1572b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35504
0106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.355040106
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1148694053
Short name T1519
Test name
Test status
Simulation time 216863838 ps
CPU time 0.86 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:17 PM PDT 24
Peak memory 206128 kb
Host smart-9e5e0815-b53b-40a8-8665-3a6652e22575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11486
94053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1148694053
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3994112236
Short name T2713
Test name
Test status
Simulation time 205132590 ps
CPU time 0.88 seconds
Started Jul 09 05:15:11 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206052 kb
Host smart-f05fb08e-3b99-46eb-b951-aeb29d3b16f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39941
12236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3994112236
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4138487060
Short name T1637
Test name
Test status
Simulation time 170556503 ps
CPU time 0.81 seconds
Started Jul 09 05:15:13 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206136 kb
Host smart-d49dae96-160f-465b-8c22-da5336161217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41384
87060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4138487060
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3993085178
Short name T1197
Test name
Test status
Simulation time 182552547 ps
CPU time 0.84 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:17 PM PDT 24
Peak memory 206156 kb
Host smart-dd3e46bb-71fc-43e2-be24-a49e50817a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39930
85178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3993085178
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.865249084
Short name T1830
Test name
Test status
Simulation time 163653235 ps
CPU time 0.86 seconds
Started Jul 09 05:15:11 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206084 kb
Host smart-eb097092-7919-4c05-b00b-d42ffdf94cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86524
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.865249084
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1476946243
Short name T78
Test name
Test status
Simulation time 233101861 ps
CPU time 0.94 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:17 PM PDT 24
Peak memory 206016 kb
Host smart-5d346403-a2bb-411f-8428-3192af5715b3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1476946243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1476946243
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4201430905
Short name T1083
Test name
Test status
Simulation time 146591861 ps
CPU time 0.78 seconds
Started Jul 09 05:15:08 PM PDT 24
Finished Jul 09 05:15:12 PM PDT 24
Peak memory 206064 kb
Host smart-38d1692e-3df8-4fcf-957c-5a9b3403fffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42014
30905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4201430905
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.589790554
Short name T1657
Test name
Test status
Simulation time 54643278 ps
CPU time 0.69 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206100 kb
Host smart-6cf14ee8-6b8c-4f8f-8ecd-de4b36291fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58979
0554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.589790554
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3582130179
Short name T2617
Test name
Test status
Simulation time 21402886485 ps
CPU time 43.36 seconds
Started Jul 09 05:15:10 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206400 kb
Host smart-6296c724-9594-4419-a356-683e43324f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35821
30179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3582130179
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.173681253
Short name T2152
Test name
Test status
Simulation time 195463996 ps
CPU time 0.83 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:17 PM PDT 24
Peak memory 206116 kb
Host smart-258a502f-67e6-4326-84ab-c14459b2e84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17368
1253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.173681253
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2566730826
Short name T1688
Test name
Test status
Simulation time 230787754 ps
CPU time 0.89 seconds
Started Jul 09 05:15:11 PM PDT 24
Finished Jul 09 05:15:15 PM PDT 24
Peak memory 206152 kb
Host smart-d5fc06ff-b79a-4e1d-bee4-70d28aa6f8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25667
30826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2566730826
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3464182313
Short name T2074
Test name
Test status
Simulation time 172072364 ps
CPU time 0.85 seconds
Started Jul 09 05:15:13 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206052 kb
Host smart-cd9974d4-b3d0-423c-951a-6a169864700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34641
82313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3464182313
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.99954539
Short name T369
Test name
Test status
Simulation time 188976843 ps
CPU time 0.88 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:16 PM PDT 24
Peak memory 206092 kb
Host smart-6202def0-5bf7-43bd-af74-ba8be62bf619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99954
539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.99954539
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3705529633
Short name T1528
Test name
Test status
Simulation time 192645771 ps
CPU time 0.82 seconds
Started Jul 09 05:15:14 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206064 kb
Host smart-b16bf719-95e4-4403-859d-787d8d325e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
29633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3705529633
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2935719438
Short name T1431
Test name
Test status
Simulation time 159473002 ps
CPU time 0.78 seconds
Started Jul 09 05:15:13 PM PDT 24
Finished Jul 09 05:15:18 PM PDT 24
Peak memory 206052 kb
Host smart-99982d4d-269c-4a6b-a26b-a644b89886ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29357
19438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2935719438
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.859441519
Short name T2588
Test name
Test status
Simulation time 175526235 ps
CPU time 0.84 seconds
Started Jul 09 05:15:12 PM PDT 24
Finished Jul 09 05:15:17 PM PDT 24
Peak memory 206104 kb
Host smart-aec75d38-a575-4338-b353-9cbe7f7a705f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85944
1519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.859441519
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1953719802
Short name T1000
Test name
Test status
Simulation time 212111218 ps
CPU time 0.93 seconds
Started Jul 09 05:15:13 PM PDT 24
Finished Jul 09 05:15:17 PM PDT 24
Peak memory 206064 kb
Host smart-14f3150a-3c20-4113-b067-9ed4ccf8ceaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19537
19802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1953719802
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2499575268
Short name T2711
Test name
Test status
Simulation time 3543680957 ps
CPU time 25.58 seconds
Started Jul 09 05:15:09 PM PDT 24
Finished Jul 09 05:15:39 PM PDT 24
Peak memory 206260 kb
Host smart-c9b87c7e-8c7a-4cb8-9a36-8e2eabf206a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2499575268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2499575268
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3196180516
Short name T624
Test name
Test status
Simulation time 146739450 ps
CPU time 0.81 seconds
Started Jul 09 05:15:17 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206148 kb
Host smart-bc881777-3038-4597-8bb6-c90e46e9dc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
80516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3196180516
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.217107815
Short name T1436
Test name
Test status
Simulation time 165140047 ps
CPU time 0.8 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206160 kb
Host smart-b4a06f48-d99a-4120-a92b-c20161f06651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21710
7815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.217107815
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2594123706
Short name T1523
Test name
Test status
Simulation time 894429528 ps
CPU time 1.95 seconds
Started Jul 09 05:15:17 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206372 kb
Host smart-33564774-beb0-430c-87bf-2cf152f1d28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25941
23706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2594123706
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.531996846
Short name T556
Test name
Test status
Simulation time 4736831947 ps
CPU time 139.46 seconds
Started Jul 09 05:15:15 PM PDT 24
Finished Jul 09 05:17:38 PM PDT 24
Peak memory 206324 kb
Host smart-560107ca-15c6-45ec-9de3-c9c2115bb165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53199
6846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.531996846
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1245483522
Short name T2566
Test name
Test status
Simulation time 48585499 ps
CPU time 0.74 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206156 kb
Host smart-b1d287a3-e49b-4a02-ac71-32978a5a2ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1245483522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1245483522
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2272337910
Short name T2499
Test name
Test status
Simulation time 4192440882 ps
CPU time 5.81 seconds
Started Jul 09 05:15:18 PM PDT 24
Finished Jul 09 05:15:26 PM PDT 24
Peak memory 206184 kb
Host smart-fc799775-8366-4448-a15a-bbfa0e9aecd6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2272337910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2272337910
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.228124114
Short name T1590
Test name
Test status
Simulation time 13398826661 ps
CPU time 14.97 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206232 kb
Host smart-4d3b18c2-f837-4715-8093-e9cd7f7b7af8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=228124114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.228124114
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2800072361
Short name T2312
Test name
Test status
Simulation time 23370558770 ps
CPU time 26.1 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206172 kb
Host smart-d69d4821-1c36-4034-bdce-37ba63f11ef9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2800072361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2800072361
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2132394273
Short name T1158
Test name
Test status
Simulation time 170675952 ps
CPU time 0.82 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206148 kb
Host smart-99f6c2df-94cf-419e-80da-4ed55866c672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
94273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2132394273
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.889640782
Short name T60
Test name
Test status
Simulation time 160168733 ps
CPU time 0.87 seconds
Started Jul 09 05:15:15 PM PDT 24
Finished Jul 09 05:15:19 PM PDT 24
Peak memory 206376 kb
Host smart-4ffea08f-7b5e-4a44-9e33-7d28c09088df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88964
0782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.889640782
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.4122505659
Short name T1368
Test name
Test status
Simulation time 490133008 ps
CPU time 1.41 seconds
Started Jul 09 05:15:15 PM PDT 24
Finished Jul 09 05:15:19 PM PDT 24
Peak memory 206092 kb
Host smart-ad5ea3f6-b040-4a59-b6fb-1f18667ee6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41225
05659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.4122505659
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1361847746
Short name T1037
Test name
Test status
Simulation time 754243858 ps
CPU time 1.84 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206344 kb
Host smart-b92186e8-4552-4ce0-9c13-d3744e5c56a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
47746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1361847746
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1011421036
Short name T1592
Test name
Test status
Simulation time 12602824010 ps
CPU time 26.29 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206372 kb
Host smart-d2130fb8-5115-4be3-9d04-ec7cddd05cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10114
21036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1011421036
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.46694639
Short name T2306
Test name
Test status
Simulation time 519976937 ps
CPU time 1.61 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206124 kb
Host smart-3a8bf391-b8d6-4721-aa7b-3c1716267c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46694
639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.46694639
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2291954570
Short name T578
Test name
Test status
Simulation time 160881658 ps
CPU time 0.86 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:21 PM PDT 24
Peak memory 206132 kb
Host smart-b0232f29-f4b1-433a-914a-ca67a4b3c505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22919
54570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2291954570
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2154977170
Short name T662
Test name
Test status
Simulation time 44791251 ps
CPU time 0.66 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:19 PM PDT 24
Peak memory 206116 kb
Host smart-8766349c-c552-4247-9ff5-218f4a0a932d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
77170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2154977170
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1749678248
Short name T2569
Test name
Test status
Simulation time 877776399 ps
CPU time 2.29 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:23 PM PDT 24
Peak memory 206380 kb
Host smart-4d501e61-21db-4a0f-8ddb-9b0840571cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
78248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1749678248
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3205128647
Short name T693
Test name
Test status
Simulation time 161026461 ps
CPU time 1.26 seconds
Started Jul 09 05:15:16 PM PDT 24
Finished Jul 09 05:15:20 PM PDT 24
Peak memory 206340 kb
Host smart-13e91def-91df-4eb2-8715-a05218df74b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32051
28647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3205128647
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1573239662
Short name T1239
Test name
Test status
Simulation time 214623166 ps
CPU time 0.83 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206148 kb
Host smart-0dc9572d-33ee-4d51-b657-d6320387672b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15732
39662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1573239662
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4277104570
Short name T1195
Test name
Test status
Simulation time 183576849 ps
CPU time 0.81 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206116 kb
Host smart-24e933a4-5a85-4f54-a414-c8f5aac4d7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42771
04570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4277104570
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3524778008
Short name T2390
Test name
Test status
Simulation time 197760106 ps
CPU time 0.85 seconds
Started Jul 09 05:15:19 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206016 kb
Host smart-55aa8ba2-1397-40e3-8c6c-9c4ec72b965e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35247
78008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3524778008
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.205960721
Short name T712
Test name
Test status
Simulation time 257685727 ps
CPU time 0.91 seconds
Started Jul 09 05:15:22 PM PDT 24
Finished Jul 09 05:15:24 PM PDT 24
Peak memory 206040 kb
Host smart-d1c49a3a-b66b-470f-b7b4-187e48edd354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596
0721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.205960721
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.603942592
Short name T186
Test name
Test status
Simulation time 23256401556 ps
CPU time 26.07 seconds
Started Jul 09 05:15:20 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206208 kb
Host smart-2a576cc5-c83d-4fd4-8f76-2a67d9e0c268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60394
2592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.603942592
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1005475564
Short name T2693
Test name
Test status
Simulation time 3324055164 ps
CPU time 3.89 seconds
Started Jul 09 05:15:22 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206124 kb
Host smart-cbd4668e-f485-42e0-8003-53c1bc092768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054
75564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1005475564
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.139305556
Short name T1518
Test name
Test status
Simulation time 8659594900 ps
CPU time 239.14 seconds
Started Jul 09 05:15:21 PM PDT 24
Finished Jul 09 05:19:22 PM PDT 24
Peak memory 206476 kb
Host smart-8d1b2245-1881-4d7b-ba02-a362fbdae72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13930
5556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.139305556
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2931475524
Short name T1441
Test name
Test status
Simulation time 6127409634 ps
CPU time 43.49 seconds
Started Jul 09 05:15:22 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206396 kb
Host smart-dbaae8a8-dde7-4e08-9d74-f6b683c7534a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2931475524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2931475524
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1406158081
Short name T1222
Test name
Test status
Simulation time 261701909 ps
CPU time 0.91 seconds
Started Jul 09 05:15:20 PM PDT 24
Finished Jul 09 05:15:22 PM PDT 24
Peak memory 206092 kb
Host smart-df9b71de-d36e-4386-bcf3-c84d9495bd07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1406158081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1406158081
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.757756312
Short name T436
Test name
Test status
Simulation time 188220737 ps
CPU time 0.9 seconds
Started Jul 09 05:15:20 PM PDT 24
Finished Jul 09 05:15:23 PM PDT 24
Peak memory 206068 kb
Host smart-53f5700f-983a-4e3e-a3a1-c5cc120636b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75775
6312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.757756312
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3767898345
Short name T2473
Test name
Test status
Simulation time 5265728863 ps
CPU time 151.19 seconds
Started Jul 09 05:15:17 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206372 kb
Host smart-3ddf27a9-0dd2-42c1-98e2-1511d0a0d63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
98345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3767898345
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3251130050
Short name T2135
Test name
Test status
Simulation time 5308419780 ps
CPU time 37.3 seconds
Started Jul 09 05:15:21 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206396 kb
Host smart-c55a2a77-6f3a-4b4e-a324-72de031216ab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3251130050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3251130050
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1498762100
Short name T1582
Test name
Test status
Simulation time 182934098 ps
CPU time 0.85 seconds
Started Jul 09 05:15:21 PM PDT 24
Finished Jul 09 05:15:24 PM PDT 24
Peak memory 206100 kb
Host smart-cfad0692-5694-4055-b977-4a89ec0fcf78
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1498762100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1498762100
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2323240530
Short name T1601
Test name
Test status
Simulation time 145276476 ps
CPU time 0.76 seconds
Started Jul 09 05:15:18 PM PDT 24
Finished Jul 09 05:15:21 PM PDT 24
Peak memory 205996 kb
Host smart-6922b0f6-7782-4b0a-bcb3-71ffa9534a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
40530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2323240530
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3690396649
Short name T1053
Test name
Test status
Simulation time 201183304 ps
CPU time 0.93 seconds
Started Jul 09 05:15:20 PM PDT 24
Finished Jul 09 05:15:23 PM PDT 24
Peak memory 206128 kb
Host smart-456cda33-9af4-48fe-855f-ec267f81a580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36903
96649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3690396649
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2109795818
Short name T1058
Test name
Test status
Simulation time 201277676 ps
CPU time 0.87 seconds
Started Jul 09 05:15:23 PM PDT 24
Finished Jul 09 05:15:25 PM PDT 24
Peak memory 206160 kb
Host smart-1a121f42-b009-4358-a0dc-5314c3ecfe93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21097
95818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2109795818
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1409072659
Short name T1913
Test name
Test status
Simulation time 178357133 ps
CPU time 0.83 seconds
Started Jul 09 05:15:23 PM PDT 24
Finished Jul 09 05:15:25 PM PDT 24
Peak memory 206164 kb
Host smart-0a8f4b83-735f-498b-a440-67ed89768882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14090
72659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1409072659
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3974836881
Short name T1290
Test name
Test status
Simulation time 155067586 ps
CPU time 0.81 seconds
Started Jul 09 05:15:21 PM PDT 24
Finished Jul 09 05:15:24 PM PDT 24
Peak memory 206060 kb
Host smart-d9aac94f-cd83-4396-9958-408ecae6a652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39748
36881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3974836881
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2475772727
Short name T622
Test name
Test status
Simulation time 221633506 ps
CPU time 0.94 seconds
Started Jul 09 05:15:27 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206032 kb
Host smart-0e0860e4-a640-4ae2-8228-729deff9e753
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2475772727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2475772727
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1537457809
Short name T1844
Test name
Test status
Simulation time 141632993 ps
CPU time 0.8 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206140 kb
Host smart-d520a421-3027-497e-b335-6e58278f0e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15374
57809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1537457809
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3626257382
Short name T38
Test name
Test status
Simulation time 32723859 ps
CPU time 0.67 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206120 kb
Host smart-38d092c5-4155-464e-98bb-1a788cb3d2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36262
57382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3626257382
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.228406802
Short name T1549
Test name
Test status
Simulation time 12758289351 ps
CPU time 26.91 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 214652 kb
Host smart-185589ea-53b1-446c-9c6d-d7a10f6ef3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22840
6802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.228406802
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3944612168
Short name T985
Test name
Test status
Simulation time 168785692 ps
CPU time 0.89 seconds
Started Jul 09 05:15:24 PM PDT 24
Finished Jul 09 05:15:26 PM PDT 24
Peak memory 205992 kb
Host smart-08cf927b-ac9f-41fd-addc-75a83600dcf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
12168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3944612168
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.213077120
Short name T2181
Test name
Test status
Simulation time 223168838 ps
CPU time 0.95 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:28 PM PDT 24
Peak memory 206132 kb
Host smart-ec8eb31d-a6ce-4f75-b04c-bbbf37d3049a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21307
7120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.213077120
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.745042231
Short name T2460
Test name
Test status
Simulation time 207865983 ps
CPU time 0.88 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206164 kb
Host smart-03fa8df1-aea3-4885-a3a3-6ef56c655864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74504
2231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.745042231
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3987673548
Short name T629
Test name
Test status
Simulation time 184138264 ps
CPU time 0.87 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:28 PM PDT 24
Peak memory 206064 kb
Host smart-4b58615b-9448-41a0-b8f2-db6cfe46fe7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39876
73548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3987673548
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.247526575
Short name T1481
Test name
Test status
Simulation time 174802547 ps
CPU time 0.82 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:28 PM PDT 24
Peak memory 206164 kb
Host smart-e87fd796-b352-40a8-b898-5fb665350484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24752
6575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.247526575
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1696966390
Short name T1755
Test name
Test status
Simulation time 154029198 ps
CPU time 0.77 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206120 kb
Host smart-37f4c049-f8e3-4eaa-bff6-d3a00b4eee1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
66390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1696966390
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2048546310
Short name T2348
Test name
Test status
Simulation time 158400101 ps
CPU time 0.83 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206104 kb
Host smart-fc65e2dc-7b1b-4e2a-a2dc-f6c11b24c070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20485
46310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2048546310
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.604100058
Short name T2699
Test name
Test status
Simulation time 271906328 ps
CPU time 0.99 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206156 kb
Host smart-c3bc703d-bda9-4ac9-8004-b0a3e5c2aa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60410
0058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.604100058
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.581731518
Short name T5
Test name
Test status
Simulation time 7166614164 ps
CPU time 54.81 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:16:22 PM PDT 24
Peak memory 206384 kb
Host smart-b22216cf-e4a4-4123-8f69-77bc234a9a63
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=581731518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.581731518
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.4061133654
Short name T2370
Test name
Test status
Simulation time 202487259 ps
CPU time 0.84 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206120 kb
Host smart-61a17edc-a134-46cd-bfa7-61e32a129f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40611
33654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.4061133654
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2396288225
Short name T1227
Test name
Test status
Simulation time 178853281 ps
CPU time 0.81 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206048 kb
Host smart-f7564756-be91-4d24-8c22-cf7f62f88529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
88225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2396288225
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.653249636
Short name T1808
Test name
Test status
Simulation time 262369894 ps
CPU time 0.93 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:28 PM PDT 24
Peak memory 206068 kb
Host smart-5fb9157a-1e17-4aef-8c08-14ed588ad753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65324
9636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.653249636
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.4152374076
Short name T2257
Test name
Test status
Simulation time 2911151918 ps
CPU time 78.17 seconds
Started Jul 09 05:15:24 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206372 kb
Host smart-deb68f70-304f-4c5b-bd8f-0fdee3b2edaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41523
74076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.4152374076
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2326601036
Short name T2005
Test name
Test status
Simulation time 41737336 ps
CPU time 0.67 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 206100 kb
Host smart-67174eee-98c9-415c-85a8-75673fcd2a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2326601036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2326601036
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2301512031
Short name T1598
Test name
Test status
Simulation time 4148620021 ps
CPU time 4.95 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206192 kb
Host smart-680a3616-cb8e-4c78-8b41-31784dc7adb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2301512031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2301512031
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1613485335
Short name T1944
Test name
Test status
Simulation time 13340732889 ps
CPU time 13.2 seconds
Started Jul 09 05:15:27 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 206172 kb
Host smart-e26947fe-11d0-4168-80a4-f9febd191f85
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1613485335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1613485335
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.227978855
Short name T2232
Test name
Test status
Simulation time 23351002616 ps
CPU time 26.88 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:56 PM PDT 24
Peak memory 206296 kb
Host smart-47549fed-c8aa-4a28-a649-02b9446e34e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=227978855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.227978855
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1871040950
Short name T780
Test name
Test status
Simulation time 153979463 ps
CPU time 0.81 seconds
Started Jul 09 05:15:25 PM PDT 24
Finished Jul 09 05:15:27 PM PDT 24
Peak memory 206144 kb
Host smart-7749febd-4bff-4d50-a49b-54d24ecc472f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18710
40950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1871040950
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2300389959
Short name T1836
Test name
Test status
Simulation time 134668386 ps
CPU time 0.77 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206064 kb
Host smart-87b7ac83-78f6-4fe4-a8c9-19f0baa519f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23003
89959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2300389959
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1479339628
Short name T163
Test name
Test status
Simulation time 153448164 ps
CPU time 0.77 seconds
Started Jul 09 05:15:27 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206116 kb
Host smart-e4148f6a-f3ab-4ae3-8fdc-1b51208ec724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14793
39628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1479339628
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1573946318
Short name T162
Test name
Test status
Simulation time 1268947539 ps
CPU time 2.71 seconds
Started Jul 09 05:15:26 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206188 kb
Host smart-3ea93b5e-6e0d-4e49-bd06-25a935f306be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15739
46318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1573946318
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.653534667
Short name T563
Test name
Test status
Simulation time 13108407140 ps
CPU time 24.87 seconds
Started Jul 09 05:15:27 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206252 kb
Host smart-57be6d72-536d-4c45-a87a-69052c07bf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65353
4667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.653534667
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3374008646
Short name T630
Test name
Test status
Simulation time 501450048 ps
CPU time 1.62 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:31 PM PDT 24
Peak memory 206068 kb
Host smart-3a4e7ddb-976d-4077-978b-1f5a73d637f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740
08646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3374008646
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2201788173
Short name T1594
Test name
Test status
Simulation time 164901777 ps
CPU time 0.75 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:31 PM PDT 24
Peak memory 206132 kb
Host smart-4d69076e-7d21-4a6b-a14a-71ea26487232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22017
88173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2201788173
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3369000560
Short name T1629
Test name
Test status
Simulation time 87157317 ps
CPU time 0.7 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206060 kb
Host smart-276b14b1-1764-4cfa-a17f-e8489c3ad571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690
00560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3369000560
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.92633764
Short name T2069
Test name
Test status
Simulation time 846785917 ps
CPU time 2.08 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:32 PM PDT 24
Peak memory 206336 kb
Host smart-81d01723-1532-466d-b7a3-35d5f2f03416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92633
764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.92633764
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3791893564
Short name T1475
Test name
Test status
Simulation time 246074863 ps
CPU time 1.56 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:31 PM PDT 24
Peak memory 206332 kb
Host smart-6618172c-e139-4e22-bb72-35ec5ff100d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37918
93564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3791893564
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2917027992
Short name T2246
Test name
Test status
Simulation time 238113036 ps
CPU time 0.92 seconds
Started Jul 09 05:15:27 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206056 kb
Host smart-ca7a7bff-fb8a-4c7e-b433-8ccb2571e63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29170
27992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2917027992
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3929452453
Short name T2083
Test name
Test status
Simulation time 144620289 ps
CPU time 0.78 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:30 PM PDT 24
Peak memory 206152 kb
Host smart-eb5cb4c7-bf6f-4e40-91bb-c448ad3284f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39294
52453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3929452453
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2467423976
Short name T538
Test name
Test status
Simulation time 173618256 ps
CPU time 0.87 seconds
Started Jul 09 05:15:29 PM PDT 24
Finished Jul 09 05:15:31 PM PDT 24
Peak memory 206016 kb
Host smart-ef151103-9870-4079-ae42-8f951e825abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24674
23976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2467423976
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2314410213
Short name T2178
Test name
Test status
Simulation time 302546227 ps
CPU time 0.94 seconds
Started Jul 09 05:15:27 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206052 kb
Host smart-60a08c05-f022-4b95-976c-afb254d4eee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23144
10213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2314410213
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3143755875
Short name T1795
Test name
Test status
Simulation time 23275084137 ps
CPU time 21.57 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 206184 kb
Host smart-a363d10a-4146-4de5-9e57-e9a916855b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31437
55875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3143755875
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.103621354
Short name T1976
Test name
Test status
Simulation time 3304296757 ps
CPU time 4.24 seconds
Started Jul 09 05:15:28 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206224 kb
Host smart-e341b1a4-33c5-44d9-b45f-8aa70c17555c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
1354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.103621354
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3455161587
Short name T1096
Test name
Test status
Simulation time 4874916859 ps
CPU time 44.09 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:16:16 PM PDT 24
Peak memory 206228 kb
Host smart-5b494713-1335-4071-b505-d3fe204a2086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34551
61587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3455161587
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2860670353
Short name T1968
Test name
Test status
Simulation time 3278548690 ps
CPU time 23.54 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206360 kb
Host smart-757b3e22-1f16-4388-8ab9-bb771abbb4de
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2860670353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2860670353
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3023239702
Short name T361
Test name
Test status
Simulation time 245078803 ps
CPU time 0.96 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206136 kb
Host smart-88231266-4d82-482c-92ca-585a77361baa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3023239702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3023239702
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3856242481
Short name T1102
Test name
Test status
Simulation time 273678674 ps
CPU time 0.94 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206108 kb
Host smart-123757fd-12d1-4da1-a671-48c2e988120f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562
42481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3856242481
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2763811238
Short name T2433
Test name
Test status
Simulation time 3533512509 ps
CPU time 96.68 seconds
Started Jul 09 05:15:30 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206388 kb
Host smart-cbfe0555-8850-4dc5-9172-7c329320cf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27638
11238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2763811238
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2343079847
Short name T1467
Test name
Test status
Simulation time 7600373044 ps
CPU time 207.18 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206380 kb
Host smart-38096a32-0ee9-4505-9ea3-5c91ebc2f450
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2343079847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2343079847
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2781770099
Short name T1132
Test name
Test status
Simulation time 214673043 ps
CPU time 0.86 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:15:36 PM PDT 24
Peak memory 205928 kb
Host smart-37b907bd-c953-4d6d-965c-a4a0d66857ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2781770099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2781770099
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.685699551
Short name T2535
Test name
Test status
Simulation time 160936816 ps
CPU time 0.83 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206060 kb
Host smart-3972fb7d-1996-44bd-bb11-84da2f485698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68569
9551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.685699551
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2199614049
Short name T99
Test name
Test status
Simulation time 181949413 ps
CPU time 0.87 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206080 kb
Host smart-1a5888f6-7323-43c6-a58a-fa80ba086554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21996
14049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2199614049
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.444461288
Short name T2531
Test name
Test status
Simulation time 178190142 ps
CPU time 0.88 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206160 kb
Host smart-d1e41223-031c-4d4e-a82f-7dca04e2abe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44446
1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.444461288
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2252681065
Short name T1963
Test name
Test status
Simulation time 165561406 ps
CPU time 0.83 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206144 kb
Host smart-3a26a791-65c0-4d91-964c-2b778268195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
81065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2252681065
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3403941879
Short name T379
Test name
Test status
Simulation time 156439738 ps
CPU time 0.8 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206140 kb
Host smart-c7f49f34-3bd8-45b0-9030-e6bae9a8eb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34039
41879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3403941879
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3495755470
Short name T2251
Test name
Test status
Simulation time 232486719 ps
CPU time 1 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206116 kb
Host smart-d54d5920-5753-4dac-aaa3-d855900e4c76
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3495755470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3495755470
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.651573640
Short name T330
Test name
Test status
Simulation time 200449971 ps
CPU time 0.83 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:15:32 PM PDT 24
Peak memory 206052 kb
Host smart-990e5783-6f21-4f6c-95af-5a375abe8140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65157
3640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.651573640
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.855049474
Short name T1331
Test name
Test status
Simulation time 38943226 ps
CPU time 0.68 seconds
Started Jul 09 05:15:33 PM PDT 24
Finished Jul 09 05:15:35 PM PDT 24
Peak memory 206132 kb
Host smart-fa317b74-94d9-43a9-a922-e5939c9c5f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85504
9474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.855049474
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.504954044
Short name T2488
Test name
Test status
Simulation time 6437273968 ps
CPU time 14.29 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206340 kb
Host smart-4cb3036a-c94d-43fb-b070-c0fe894ed099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50495
4044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.504954044
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2353670283
Short name T1892
Test name
Test status
Simulation time 174764223 ps
CPU time 0.78 seconds
Started Jul 09 05:15:34 PM PDT 24
Finished Jul 09 05:15:35 PM PDT 24
Peak memory 206132 kb
Host smart-63ae2b3c-6a11-4490-be96-e088a7d6ecc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
70283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2353670283
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.739517067
Short name T837
Test name
Test status
Simulation time 161655980 ps
CPU time 0.85 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:15:36 PM PDT 24
Peak memory 205960 kb
Host smart-87f7e848-9903-40c5-9c58-1272dc21e564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73951
7067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.739517067
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.3238509809
Short name T338
Test name
Test status
Simulation time 253146127 ps
CPU time 0.98 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206068 kb
Host smart-d6434123-2c18-42e2-b8bc-2bc218570e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32385
09809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.3238509809
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.933595732
Short name T1268
Test name
Test status
Simulation time 190679747 ps
CPU time 0.81 seconds
Started Jul 09 05:15:32 PM PDT 24
Finished Jul 09 05:15:34 PM PDT 24
Peak memory 206020 kb
Host smart-4fd32b95-637c-41da-9f0c-8dfd57a65b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93359
5732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.933595732
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2514421163
Short name T2437
Test name
Test status
Simulation time 144726605 ps
CPU time 0.78 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:15:37 PM PDT 24
Peak memory 206124 kb
Host smart-91522c0e-56dc-4d62-bafd-71802bb9a4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25144
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2514421163
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4072262795
Short name T2137
Test name
Test status
Simulation time 188044634 ps
CPU time 0.87 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:15:36 PM PDT 24
Peak memory 206120 kb
Host smart-7aec9729-52cd-4cf7-bd73-c5abf9dffd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
62795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4072262795
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.985046960
Short name T1569
Test name
Test status
Simulation time 159888025 ps
CPU time 0.82 seconds
Started Jul 09 05:15:31 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 206164 kb
Host smart-c9edb777-67f8-43ea-9ac8-0a6eb5eb4115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98504
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.985046960
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.442839956
Short name T351
Test name
Test status
Simulation time 235261203 ps
CPU time 0.97 seconds
Started Jul 09 05:15:34 PM PDT 24
Finished Jul 09 05:15:36 PM PDT 24
Peak memory 206128 kb
Host smart-2899df2e-c87c-489d-834a-8b4d6111fbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44283
9956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.442839956
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1317755028
Short name T2684
Test name
Test status
Simulation time 4963261319 ps
CPU time 45.3 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:16:22 PM PDT 24
Peak memory 206408 kb
Host smart-a80ce22c-ad2b-42bc-a087-1adf88d2125b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1317755028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1317755028
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.4080937934
Short name T888
Test name
Test status
Simulation time 223316195 ps
CPU time 0.9 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:15:49 PM PDT 24
Peak memory 205956 kb
Host smart-a2dc2d6c-3f98-4e0f-bb3c-c2edb250fb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809
37934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4080937934
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.4249226688
Short name T1402
Test name
Test status
Simulation time 166881127 ps
CPU time 0.82 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 206056 kb
Host smart-e61e6f94-18bf-40bd-b4e0-b2bf82bc85dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
26688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.4249226688
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2670470461
Short name T2147
Test name
Test status
Simulation time 880481422 ps
CPU time 2 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:39 PM PDT 24
Peak memory 206332 kb
Host smart-f05a0a96-9d6d-4e7c-ad29-c45528532840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26704
70461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2670470461
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3917185039
Short name T587
Test name
Test status
Simulation time 7522787083 ps
CPU time 208.29 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:19:12 PM PDT 24
Peak memory 206372 kb
Host smart-1997f7f9-a4a4-48df-91b0-a3c13b219cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
85039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3917185039
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1543775262
Short name T2554
Test name
Test status
Simulation time 56022651 ps
CPU time 0.76 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206052 kb
Host smart-d736a5dd-4d99-4d61-86f2-0efe1a392acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1543775262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1543775262
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1453553259
Short name T491
Test name
Test status
Simulation time 3926077046 ps
CPU time 4.73 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:42 PM PDT 24
Peak memory 206092 kb
Host smart-13a00be9-9346-4331-b184-c4062c0a52d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1453553259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1453553259
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3272239439
Short name T2398
Test name
Test status
Simulation time 13376982382 ps
CPU time 12.02 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:50 PM PDT 24
Peak memory 206412 kb
Host smart-3435e932-8fc7-40d9-9d60-315d0e7a68b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3272239439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3272239439
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4275591740
Short name T2686
Test name
Test status
Simulation time 23319730838 ps
CPU time 24.19 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:16:01 PM PDT 24
Peak memory 206196 kb
Host smart-1b4f1da5-55b6-4efc-b2be-39183255803f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4275591740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.4275591740
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.920954716
Short name T613
Test name
Test status
Simulation time 148976306 ps
CPU time 0.8 seconds
Started Jul 09 05:15:37 PM PDT 24
Finished Jul 09 05:15:40 PM PDT 24
Peak memory 206140 kb
Host smart-9b4c36e4-b3f9-4f7f-a32c-f779f0fc8558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92095
4716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.920954716
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1921660342
Short name T1936
Test name
Test status
Simulation time 160458525 ps
CPU time 0.78 seconds
Started Jul 09 05:15:37 PM PDT 24
Finished Jul 09 05:15:40 PM PDT 24
Peak memory 206144 kb
Host smart-1ea08cc6-d281-404b-8745-72e8abf52ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
60342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1921660342
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2831247960
Short name T2479
Test name
Test status
Simulation time 243411048 ps
CPU time 0.95 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206064 kb
Host smart-14b1cd70-7d65-4cbf-8c6f-cadd11eb42e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28312
47960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2831247960
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2329937830
Short name T1811
Test name
Test status
Simulation time 293323255 ps
CPU time 1.02 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:39 PM PDT 24
Peak memory 206016 kb
Host smart-7e44545b-76a0-4981-99d8-62493cb27561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23299
37830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2329937830
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2631396411
Short name T1465
Test name
Test status
Simulation time 22407618990 ps
CPU time 45.48 seconds
Started Jul 09 05:15:37 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206400 kb
Host smart-438a8edc-20db-4d6f-ab63-13dabb0c4b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26313
96411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2631396411
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.104855635
Short name T1897
Test name
Test status
Simulation time 411832612 ps
CPU time 1.25 seconds
Started Jul 09 05:15:38 PM PDT 24
Finished Jul 09 05:15:42 PM PDT 24
Peak memory 206088 kb
Host smart-f16ed3ba-59fa-474f-8e8d-276a1a014182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.104855635
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.709631119
Short name T1639
Test name
Test status
Simulation time 142508232 ps
CPU time 0.78 seconds
Started Jul 09 05:15:37 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 205824 kb
Host smart-cfba67e0-256f-4450-9a63-93601d8274a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70963
1119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.709631119
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2032261280
Short name T1898
Test name
Test status
Simulation time 41213762 ps
CPU time 0.69 seconds
Started Jul 09 05:15:37 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 205872 kb
Host smart-a775e8e4-4bf4-45e2-9301-972b26796cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
61280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2032261280
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.346076488
Short name T523
Test name
Test status
Simulation time 807568883 ps
CPU time 1.92 seconds
Started Jul 09 05:15:34 PM PDT 24
Finished Jul 09 05:15:37 PM PDT 24
Peak memory 206368 kb
Host smart-717cd40e-d61b-4051-bbaf-445696c57a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
6488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.346076488
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3674957768
Short name T1796
Test name
Test status
Simulation time 334999027 ps
CPU time 1.94 seconds
Started Jul 09 05:15:35 PM PDT 24
Finished Jul 09 05:15:37 PM PDT 24
Peak memory 206188 kb
Host smart-cae333b5-7413-482b-8c40-609ce458a00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
57768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3674957768
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3380182021
Short name T1051
Test name
Test status
Simulation time 154629775 ps
CPU time 0.81 seconds
Started Jul 09 05:15:37 PM PDT 24
Finished Jul 09 05:15:40 PM PDT 24
Peak memory 206140 kb
Host smart-67c84a4f-7934-4583-9c30-a40ceac91856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801
82021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3380182021
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3335730700
Short name T808
Test name
Test status
Simulation time 139633481 ps
CPU time 0.77 seconds
Started Jul 09 05:15:38 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 206080 kb
Host smart-eb906345-2b1a-4329-a865-da512084209d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
30700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3335730700
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.480938748
Short name T637
Test name
Test status
Simulation time 150423122 ps
CPU time 0.82 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:39 PM PDT 24
Peak memory 206060 kb
Host smart-4af1f59d-160f-4ac7-b8d5-c1dc9d6c983b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48093
8748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.480938748
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3957336215
Short name T2406
Test name
Test status
Simulation time 202230531 ps
CPU time 0.92 seconds
Started Jul 09 05:15:38 PM PDT 24
Finished Jul 09 05:15:42 PM PDT 24
Peak memory 206024 kb
Host smart-3364e2cb-3bc2-41d3-b63e-5daff1e879ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
36215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3957336215
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3424266257
Short name T1583
Test name
Test status
Simulation time 23305248360 ps
CPU time 22.78 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206012 kb
Host smart-d1ccdf10-c2cf-4cba-be37-beed0bcb7fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34242
66257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3424266257
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1633381350
Short name T1565
Test name
Test status
Simulation time 3320617108 ps
CPU time 4.58 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206172 kb
Host smart-b77881e1-62cc-4314-a204-bc4d1a632083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16333
81350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1633381350
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1073542820
Short name T2170
Test name
Test status
Simulation time 13192096148 ps
CPU time 129.99 seconds
Started Jul 09 05:15:40 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 206724 kb
Host smart-b6f82bf9-2050-4cb6-9aab-15f8b1c11097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10735
42820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1073542820
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1070164794
Short name T1697
Test name
Test status
Simulation time 3139414700 ps
CPU time 89.94 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206316 kb
Host smart-b46ec31b-6538-4718-ab62-a731e3e77749
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1070164794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1070164794
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1121671093
Short name T2315
Test name
Test status
Simulation time 239258228 ps
CPU time 0.92 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206140 kb
Host smart-0d394739-25a7-4012-a4cf-38630b6ca839
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1121671093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1121671093
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1080318106
Short name T615
Test name
Test status
Simulation time 201075852 ps
CPU time 0.91 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206008 kb
Host smart-2cdfffb5-3c3b-45fa-8507-fac00c34eaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
18106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1080318106
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2759590098
Short name T485
Test name
Test status
Simulation time 6180120095 ps
CPU time 44.28 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 206316 kb
Host smart-5ad88c41-4001-44f0-8904-d7b19dd15712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27595
90098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2759590098
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.4200124333
Short name T1379
Test name
Test status
Simulation time 7016770388 ps
CPU time 49.9 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206384 kb
Host smart-e943b52c-3db9-4647-858a-162106720e81
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4200124333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.4200124333
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.3033803269
Short name T2625
Test name
Test status
Simulation time 179508164 ps
CPU time 0.82 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206136 kb
Host smart-be42b39c-964e-4952-9014-adb1cbfe973e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3033803269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3033803269
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.927737763
Short name T1336
Test name
Test status
Simulation time 150001029 ps
CPU time 0.78 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:15:46 PM PDT 24
Peak memory 206068 kb
Host smart-95108ef2-ad1a-464a-a09b-d7ba1b0bfd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92773
7763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.927737763
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.546800042
Short name T1720
Test name
Test status
Simulation time 205639864 ps
CPU time 0.91 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:15:49 PM PDT 24
Peak memory 205952 kb
Host smart-aa8ac60e-8fca-478f-99e4-b0b872ffefeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54680
0042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.546800042
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2974866534
Short name T481
Test name
Test status
Simulation time 209941553 ps
CPU time 0.86 seconds
Started Jul 09 05:15:42 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206056 kb
Host smart-868dfc95-7b33-4cfa-b40c-8d298a886900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29748
66534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2974866534
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.262465614
Short name T1243
Test name
Test status
Simulation time 171948903 ps
CPU time 0.88 seconds
Started Jul 09 05:15:40 PM PDT 24
Finished Jul 09 05:15:43 PM PDT 24
Peak memory 206156 kb
Host smart-fab038ab-a083-4d9f-893f-b19cf8a30cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
5614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.262465614
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2918063202
Short name T102
Test name
Test status
Simulation time 189709186 ps
CPU time 0.87 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:15:49 PM PDT 24
Peak memory 205956 kb
Host smart-b39ca4b2-5191-493d-a524-2b4f93cdbb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
63202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2918063202
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1573506483
Short name T2616
Test name
Test status
Simulation time 175921734 ps
CPU time 0.8 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 205964 kb
Host smart-a8dce538-dad8-478d-a2a6-094a1da987ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735
06483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1573506483
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1260592139
Short name T1455
Test name
Test status
Simulation time 318000499 ps
CPU time 1.08 seconds
Started Jul 09 05:15:38 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 206088 kb
Host smart-fdc91780-8960-4b5d-a160-578d666c4c00
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1260592139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1260592139
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2929937003
Short name T2025
Test name
Test status
Simulation time 156720633 ps
CPU time 0.74 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206052 kb
Host smart-749df048-c5ba-43b7-99bb-a88cb3ce702e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
37003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2929937003
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3565771933
Short name T1074
Test name
Test status
Simulation time 54024652 ps
CPU time 0.69 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206156 kb
Host smart-c27b8a1e-2136-470b-903b-741cdad8bc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657
71933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3565771933
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.977592091
Short name T535
Test name
Test status
Simulation time 6206466737 ps
CPU time 15.49 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:16:04 PM PDT 24
Peak memory 206300 kb
Host smart-f8911130-f0fa-4e6c-971d-4cc0d0f544f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97759
2091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.977592091
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1659592721
Short name T1425
Test name
Test status
Simulation time 167190544 ps
CPU time 0.86 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:15:46 PM PDT 24
Peak memory 206092 kb
Host smart-38a972b0-58ff-4d02-8535-a24032d6c53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16595
92721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1659592721
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3125522860
Short name T2148
Test name
Test status
Simulation time 233366819 ps
CPU time 0.89 seconds
Started Jul 09 05:15:40 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206004 kb
Host smart-a9a09772-fb9a-44c6-a513-b44dad459878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31255
22860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3125522860
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4141864765
Short name T1267
Test name
Test status
Simulation time 233491864 ps
CPU time 0.92 seconds
Started Jul 09 05:15:36 PM PDT 24
Finished Jul 09 05:15:39 PM PDT 24
Peak memory 206116 kb
Host smart-772829c3-c0f7-4e95-aedb-21de0ca33db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41418
64765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4141864765
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.870233461
Short name T2449
Test name
Test status
Simulation time 265258437 ps
CPU time 0.99 seconds
Started Jul 09 05:15:40 PM PDT 24
Finished Jul 09 05:15:43 PM PDT 24
Peak memory 206096 kb
Host smart-c928b159-0d89-41a6-946d-df8a750cfd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87023
3461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.870233461
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.119910178
Short name T1815
Test name
Test status
Simulation time 168038747 ps
CPU time 0.84 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 205960 kb
Host smart-0883bbbe-85b8-447f-95e3-51b6778ecf58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11991
0178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.119910178
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2887303192
Short name T2350
Test name
Test status
Simulation time 148951619 ps
CPU time 0.81 seconds
Started Jul 09 05:15:40 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206152 kb
Host smart-62153143-1e02-4987-80de-943d2aadb34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28873
03192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2887303192
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.950736128
Short name T864
Test name
Test status
Simulation time 157666296 ps
CPU time 0.78 seconds
Started Jul 09 05:15:42 PM PDT 24
Finished Jul 09 05:15:46 PM PDT 24
Peak memory 206064 kb
Host smart-62ea85bb-2a6a-4a33-934c-d8a534a7af20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95073
6128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.950736128
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.791564613
Short name T1984
Test name
Test status
Simulation time 243158605 ps
CPU time 0.96 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:15:46 PM PDT 24
Peak memory 206128 kb
Host smart-ea409afe-70a6-4f85-9118-10f570bcd9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79156
4613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.791564613
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.777194454
Short name T2510
Test name
Test status
Simulation time 5465292168 ps
CPU time 52.18 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206424 kb
Host smart-742a14c6-f2fc-4f9e-9cbc-408eacad9f41
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=777194454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.777194454
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3572718597
Short name T1778
Test name
Test status
Simulation time 173585975 ps
CPU time 0.84 seconds
Started Jul 09 05:15:39 PM PDT 24
Finished Jul 09 05:15:42 PM PDT 24
Peak memory 206020 kb
Host smart-3d3aa96b-976d-4f41-8bc6-4be5c5d305de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35727
18597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3572718597
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.4102232494
Short name T2195
Test name
Test status
Simulation time 148767161 ps
CPU time 0.85 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206052 kb
Host smart-c35b6b16-e500-4757-97dd-4080e35016a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41022
32494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.4102232494
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.470705571
Short name T776
Test name
Test status
Simulation time 737728591 ps
CPU time 1.7 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:59 PM PDT 24
Peak memory 206236 kb
Host smart-dad31480-3f0a-4ad6-aaae-806559901e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47070
5571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.470705571
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1950402818
Short name T685
Test name
Test status
Simulation time 4526678570 ps
CPU time 132.4 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206400 kb
Host smart-be9e0191-5911-4246-ac70-4a2c642c0be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19504
02818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1950402818
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3740250170
Short name T17
Test name
Test status
Simulation time 94490325 ps
CPU time 0.79 seconds
Started Jul 09 05:15:46 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 206124 kb
Host smart-2b068149-c42b-4d14-838a-f8f1b6dc5090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3740250170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3740250170
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3280005875
Short name T1322
Test name
Test status
Simulation time 3480927075 ps
CPU time 4.16 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206192 kb
Host smart-68643629-eaff-4877-8858-3af05a1356c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3280005875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3280005875
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.336766112
Short name T2480
Test name
Test status
Simulation time 13361818597 ps
CPU time 13.46 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206072 kb
Host smart-20100471-83c6-4ce8-974f-b63441cfadd4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=336766112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.336766112
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.713427584
Short name T1575
Test name
Test status
Simulation time 23417075357 ps
CPU time 23.66 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:16:10 PM PDT 24
Peak memory 206336 kb
Host smart-de9746e6-d27b-4868-94a9-ad34c1100cca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=713427584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.713427584
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2580515322
Short name T2363
Test name
Test status
Simulation time 164188626 ps
CPU time 0.8 seconds
Started Jul 09 05:15:42 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 205988 kb
Host smart-747e0096-fd77-4165-a9a1-a487bd3de820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
15322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2580515322
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3267702314
Short name T1137
Test name
Test status
Simulation time 169735166 ps
CPU time 0.8 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206148 kb
Host smart-1210eeda-6ebe-4e69-8d63-18f6810a6038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32677
02314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3267702314
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1216576550
Short name T108
Test name
Test status
Simulation time 389955470 ps
CPU time 1.41 seconds
Started Jul 09 05:15:41 PM PDT 24
Finished Jul 09 05:15:45 PM PDT 24
Peak memory 206124 kb
Host smart-84156123-6210-4e0e-bd4a-4dfeeca40a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12165
76550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1216576550
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1326089813
Short name T104
Test name
Test status
Simulation time 856839532 ps
CPU time 2.09 seconds
Started Jul 09 05:15:46 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206252 kb
Host smart-31eaef0f-08a1-4569-a663-3297e58700be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13260
89813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1326089813
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.171208378
Short name T2164
Test name
Test status
Simulation time 8736688390 ps
CPU time 18.35 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:16:05 PM PDT 24
Peak memory 206436 kb
Host smart-b0488203-d880-483c-ad3a-f6271475ad50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17120
8378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.171208378
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.857584293
Short name T1635
Test name
Test status
Simulation time 375517503 ps
CPU time 1.24 seconds
Started Jul 09 05:15:42 PM PDT 24
Finished Jul 09 05:15:46 PM PDT 24
Peak memory 206112 kb
Host smart-45756c80-c67f-4fad-97ce-525d4fc906d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85758
4293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.857584293
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.160793710
Short name T439
Test name
Test status
Simulation time 145601648 ps
CPU time 0.8 seconds
Started Jul 09 05:15:49 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206060 kb
Host smart-5ee3dd2a-7fb2-4cfe-836c-ac6926d1c180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16079
3710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.160793710
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.824064217
Short name T460
Test name
Test status
Simulation time 48772755 ps
CPU time 0.66 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206156 kb
Host smart-ad68d3d2-024e-42f6-bf3b-17833e4352be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82406
4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.824064217
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2004487292
Short name T1285
Test name
Test status
Simulation time 1051745781 ps
CPU time 2.44 seconds
Started Jul 09 05:15:42 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206328 kb
Host smart-086cd650-8da1-4008-8092-3bd34a13af3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
87292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2004487292
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3880661900
Short name T759
Test name
Test status
Simulation time 156080446 ps
CPU time 1.22 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 206320 kb
Host smart-9accbd2e-cad1-4b34-b50c-0ed39bc79d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
61900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3880661900
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.4252255628
Short name T941
Test name
Test status
Simulation time 201515666 ps
CPU time 0.88 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206116 kb
Host smart-877ca7b8-f21c-4b55-aea0-b8c40ff90baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42522
55628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.4252255628
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2059615923
Short name T1655
Test name
Test status
Simulation time 204795211 ps
CPU time 0.84 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:15:47 PM PDT 24
Peak memory 206124 kb
Host smart-6192bfe4-1ac2-4ffd-ace7-d329d2eaaa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596
15923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2059615923
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1372710054
Short name T1642
Test name
Test status
Simulation time 195650830 ps
CPU time 0.84 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206080 kb
Host smart-7fdc9045-8557-4fdb-8844-4978db36d0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13727
10054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1372710054
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3773691833
Short name T2662
Test name
Test status
Simulation time 9123157111 ps
CPU time 259.87 seconds
Started Jul 09 05:15:42 PM PDT 24
Finished Jul 09 05:20:04 PM PDT 24
Peak memory 206404 kb
Host smart-7ef1bbc4-db4f-4073-8dec-09cca112c8b7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3773691833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3773691833
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1133055906
Short name T2222
Test name
Test status
Simulation time 247700493 ps
CPU time 0.95 seconds
Started Jul 09 05:15:40 PM PDT 24
Finished Jul 09 05:15:44 PM PDT 24
Peak memory 206056 kb
Host smart-e60a0682-dcab-49b5-957b-30ffbefac934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11330
55906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1133055906
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.347315335
Short name T1560
Test name
Test status
Simulation time 23343308497 ps
CPU time 24.56 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:16:25 PM PDT 24
Peak memory 206200 kb
Host smart-80b25122-1ad8-4fcf-861d-ca0d8e095969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
5335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.347315335
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3853271477
Short name T2586
Test name
Test status
Simulation time 3349138065 ps
CPU time 4.23 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:15:54 PM PDT 24
Peak memory 206196 kb
Host smart-a03c39fd-260d-4899-8181-57d9722ed87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38532
71477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3853271477
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1205911937
Short name T1323
Test name
Test status
Simulation time 10950728898 ps
CPU time 104.39 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206516 kb
Host smart-6b3a24ab-210f-46c3-baa0-74803f9670d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
11937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1205911937
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.4068316150
Short name T1240
Test name
Test status
Simulation time 3568374669 ps
CPU time 103.34 seconds
Started Jul 09 05:15:43 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206660 kb
Host smart-03968aef-f1b7-4733-8842-f2de9defea88
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4068316150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.4068316150
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1909995444
Short name T718
Test name
Test status
Simulation time 257124844 ps
CPU time 0.88 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206116 kb
Host smart-7fe5c053-b7ad-4e77-aaac-1f85f5781a96
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1909995444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1909995444
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.364504115
Short name T1774
Test name
Test status
Simulation time 215336521 ps
CPU time 0.9 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 206136 kb
Host smart-89e4b49e-e253-4648-8e14-cfdb1f45c9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.364504115
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.4242243323
Short name T1666
Test name
Test status
Simulation time 4129746937 ps
CPU time 118.66 seconds
Started Jul 09 05:15:45 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206444 kb
Host smart-4e7e9d4c-a2cd-4c7a-a0cc-0655b9c61674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
43323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.4242243323
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3851530044
Short name T320
Test name
Test status
Simulation time 6237457348 ps
CPU time 172.57 seconds
Started Jul 09 05:15:49 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 206296 kb
Host smart-02ec3c2e-f15d-4484-af25-c0af4fdbdcef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3851530044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3851530044
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3825648448
Short name T525
Test name
Test status
Simulation time 174973594 ps
CPU time 0.83 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 205856 kb
Host smart-afe13dac-d13c-4b7f-8438-489968f715b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3825648448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3825648448
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3851832707
Short name T1017
Test name
Test status
Simulation time 137726317 ps
CPU time 0.79 seconds
Started Jul 09 05:15:50 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206148 kb
Host smart-8d694067-d21d-4f91-b32c-182fab767a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38518
32707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3851832707
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.176271820
Short name T136
Test name
Test status
Simulation time 188709709 ps
CPU time 0.9 seconds
Started Jul 09 05:15:48 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 206120 kb
Host smart-ed3984a7-b146-4a3d-8b6f-33a3d7e68e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17627
1820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.176271820
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3176144118
Short name T2402
Test name
Test status
Simulation time 186964787 ps
CPU time 0.85 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 205988 kb
Host smart-6148dc85-cb76-4a74-ba9d-381af354b620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
44118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3176144118
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3840154196
Short name T1773
Test name
Test status
Simulation time 204548956 ps
CPU time 0.88 seconds
Started Jul 09 05:15:48 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206148 kb
Host smart-ab3107e4-ddf7-4aee-980d-1fd32642b688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38401
54196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3840154196
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2564585500
Short name T1659
Test name
Test status
Simulation time 148854406 ps
CPU time 0.79 seconds
Started Jul 09 05:15:49 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206116 kb
Host smart-7861b16e-5938-4440-bb1c-9e00a4954775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25645
85500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2564585500
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2590315619
Short name T2611
Test name
Test status
Simulation time 222680345 ps
CPU time 0.88 seconds
Started Jul 09 05:15:49 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206060 kb
Host smart-68549831-f7de-4751-9141-70a071c93700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25903
15619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2590315619
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3179235108
Short name T2539
Test name
Test status
Simulation time 201058794 ps
CPU time 0.89 seconds
Started Jul 09 05:15:46 PM PDT 24
Finished Jul 09 05:15:50 PM PDT 24
Peak memory 206060 kb
Host smart-131862c0-e645-48d8-8e2a-8c465a402499
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3179235108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3179235108
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1761848917
Short name T1864
Test name
Test status
Simulation time 150831781 ps
CPU time 0.81 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206052 kb
Host smart-0f365fed-9780-4c76-8feb-1b2207d88c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
48917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1761848917
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.827014233
Short name T2092
Test name
Test status
Simulation time 36580991 ps
CPU time 0.65 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 206152 kb
Host smart-255d1095-f9aa-4d5d-b24a-f2601495469a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82701
4233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.827014233
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3815896656
Short name T277
Test name
Test status
Simulation time 19394991659 ps
CPU time 47.73 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206340 kb
Host smart-13e89142-301b-41a4-bd67-2269c6b3176c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38158
96656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3815896656
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1503511092
Short name T1499
Test name
Test status
Simulation time 223676105 ps
CPU time 0.98 seconds
Started Jul 09 05:15:48 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206164 kb
Host smart-6b03bb0b-6645-4779-8071-6727fa1ac882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
11092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1503511092
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.4055532000
Short name T2674
Test name
Test status
Simulation time 206815107 ps
CPU time 0.9 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:59 PM PDT 24
Peak memory 206052 kb
Host smart-04436b7e-ae5a-4545-8eb4-13c99136ee83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555
32000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4055532000
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2127290141
Short name T1237
Test name
Test status
Simulation time 243884038 ps
CPU time 0.94 seconds
Started Jul 09 05:15:46 PM PDT 24
Finished Jul 09 05:15:50 PM PDT 24
Peak memory 206056 kb
Host smart-963c2bf2-a9ee-4ad4-85e0-bc3791105c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21272
90141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2127290141
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1686283445
Short name T2081
Test name
Test status
Simulation time 196084427 ps
CPU time 0.98 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:15:51 PM PDT 24
Peak memory 206068 kb
Host smart-1703b3dd-75aa-46bd-ae14-88bf2b097459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16862
83445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1686283445
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.4122530716
Short name T966
Test name
Test status
Simulation time 141141268 ps
CPU time 0.78 seconds
Started Jul 09 05:15:46 PM PDT 24
Finished Jul 09 05:15:50 PM PDT 24
Peak memory 205988 kb
Host smart-1b172df5-d562-44bc-b71f-ace9e9ea63ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41225
30716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.4122530716
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3612085277
Short name T513
Test name
Test status
Simulation time 153832322 ps
CPU time 0.8 seconds
Started Jul 09 05:15:49 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206000 kb
Host smart-010b6f88-bacb-4b07-b965-283a9a06b590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
85277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3612085277
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1245590484
Short name T2627
Test name
Test status
Simulation time 162005882 ps
CPU time 0.79 seconds
Started Jul 09 05:15:50 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206004 kb
Host smart-7b2b19b5-3ded-4b8a-b4e9-660d7fcea243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12455
90484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1245590484
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2051036947
Short name T2623
Test name
Test status
Simulation time 237692887 ps
CPU time 0.95 seconds
Started Jul 09 05:15:49 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206120 kb
Host smart-fb6fd5fc-2bf7-420d-9e25-9ec435193302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20510
36947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2051036947
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.488810606
Short name T968
Test name
Test status
Simulation time 5336436860 ps
CPU time 156.92 seconds
Started Jul 09 05:15:47 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206340 kb
Host smart-375facf3-54b3-4bb6-84a6-e370bb82dd07
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=488810606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.488810606
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4126015380
Short name T2105
Test name
Test status
Simulation time 192861126 ps
CPU time 0.83 seconds
Started Jul 09 05:15:48 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206060 kb
Host smart-65f41fc6-ebb2-4540-8b37-2d4a4a9f5932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41260
15380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4126015380
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3126199780
Short name T427
Test name
Test status
Simulation time 280138065 ps
CPU time 0.96 seconds
Started Jul 09 05:15:48 PM PDT 24
Finished Jul 09 05:15:52 PM PDT 24
Peak memory 206128 kb
Host smart-9dea8d26-831e-498a-a8d6-74b7ed79d8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31261
99780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3126199780
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.4028256441
Short name T2583
Test name
Test status
Simulation time 351160867 ps
CPU time 1.1 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206052 kb
Host smart-6479f793-3245-43a0-83bb-bf36b4dd3374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40282
56441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.4028256441
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.577108354
Short name T1209
Test name
Test status
Simulation time 7982445043 ps
CPU time 77.48 seconds
Started Jul 09 05:15:48 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206320 kb
Host smart-51b7a352-b286-474b-acca-a2c5dc564ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57710
8354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.577108354
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.635684535
Short name T2108
Test name
Test status
Simulation time 35119869 ps
CPU time 0.7 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206164 kb
Host smart-b55c43dc-3241-4daf-9c92-4d92eba7dad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=635684535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.635684535
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.409496439
Short name T1162
Test name
Test status
Simulation time 3919321522 ps
CPU time 5.55 seconds
Started Jul 09 05:15:46 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 206708 kb
Host smart-6173422a-39e2-4ac0-979b-9bacd06e8a36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=409496439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.409496439
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1561537880
Short name T1813
Test name
Test status
Simulation time 13341570006 ps
CPU time 12.93 seconds
Started Jul 09 05:15:44 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206104 kb
Host smart-468e8236-7c44-4828-8da9-0ed958fcc674
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1561537880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1561537880
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3524657796
Short name T515
Test name
Test status
Simulation time 23341300198 ps
CPU time 27.31 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 206176 kb
Host smart-33a2cc9d-7a7b-492b-bbe0-8638273a7c04
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3524657796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.3524657796
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.47014353
Short name T1783
Test name
Test status
Simulation time 154773007 ps
CPU time 0.79 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206124 kb
Host smart-1ba31c45-86a9-4d60-b2f6-1fd4f6aeb424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47014
353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.47014353
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2074669993
Short name T797
Test name
Test status
Simulation time 154290285 ps
CPU time 0.78 seconds
Started Jul 09 05:15:50 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206112 kb
Host smart-4a651e77-906d-4c3d-a63f-c7e13a0ff46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
69993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2074669993
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3607119484
Short name T2098
Test name
Test status
Simulation time 494589594 ps
CPU time 1.49 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 206256 kb
Host smart-d554d883-e45f-4bf0-85d0-a0d23c58b55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36071
19484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3607119484
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.442558858
Short name T2605
Test name
Test status
Simulation time 1105733122 ps
CPU time 2.55 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:56 PM PDT 24
Peak memory 206224 kb
Host smart-c20e3b2d-1f03-46ba-a2fc-e6d02079758a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44255
8858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.442558858
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2602408822
Short name T96
Test name
Test status
Simulation time 6667506682 ps
CPU time 14.19 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206456 kb
Host smart-58587dc6-5670-4b60-b99e-4c1f397b5177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
08822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2602408822
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3462530115
Short name T1896
Test name
Test status
Simulation time 436290570 ps
CPU time 1.39 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:54 PM PDT 24
Peak memory 206156 kb
Host smart-abc99a2b-4180-4d7d-893a-61a2bb009eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625
30115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3462530115
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.271297797
Short name T2676
Test name
Test status
Simulation time 163537618 ps
CPU time 0.79 seconds
Started Jul 09 05:15:50 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206056 kb
Host smart-3b420de7-62fd-4417-9379-2717c0447ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.271297797
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2340273691
Short name T1104
Test name
Test status
Simulation time 33182590 ps
CPU time 0.68 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:53 PM PDT 24
Peak memory 206140 kb
Host smart-df45611a-58f2-4798-b241-d2c2ed12c606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23402
73691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2340273691
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.18713769
Short name T2301
Test name
Test status
Simulation time 959406137 ps
CPU time 2.34 seconds
Started Jul 09 05:15:50 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 206292 kb
Host smart-86c4d65c-f05e-4f1c-855e-8198f3d32e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18713
769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.18713769
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2579743624
Short name T1479
Test name
Test status
Simulation time 284938355 ps
CPU time 1.52 seconds
Started Jul 09 05:15:52 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 206220 kb
Host smart-c489f26b-3570-47b2-8dd7-4123e8c01c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25797
43624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2579743624
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2189822390
Short name T2527
Test name
Test status
Simulation time 230680023 ps
CPU time 0.94 seconds
Started Jul 09 05:15:52 PM PDT 24
Finished Jul 09 05:15:54 PM PDT 24
Peak memory 206156 kb
Host smart-b901adbb-3532-4ce0-817d-834083e56c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21898
22390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2189822390
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.428653809
Short name T1982
Test name
Test status
Simulation time 148216726 ps
CPU time 0.78 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 205836 kb
Host smart-7dfd03a1-debb-4023-8d79-c1f74fcb7f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42865
3809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.428653809
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3049897888
Short name T1884
Test name
Test status
Simulation time 213582328 ps
CPU time 0.91 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:54 PM PDT 24
Peak memory 206092 kb
Host smart-0f8f6509-a0df-4102-adf1-469507b75820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
97888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3049897888
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1665409472
Short name T2475
Test name
Test status
Simulation time 7441132980 ps
CPU time 217.62 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:19:39 PM PDT 24
Peak memory 206464 kb
Host smart-f6666db4-e2e8-482f-8337-49016ebdfa20
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1665409472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1665409472
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2997931926
Short name T923
Test name
Test status
Simulation time 209475375 ps
CPU time 0.89 seconds
Started Jul 09 05:15:51 PM PDT 24
Finished Jul 09 05:15:54 PM PDT 24
Peak memory 206084 kb
Host smart-92c7d27f-3605-482e-8a4d-23c7eb05e25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29979
31926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2997931926
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3845928516
Short name T2458
Test name
Test status
Simulation time 23332175298 ps
CPU time 29.85 seconds
Started Jul 09 05:15:53 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206120 kb
Host smart-5c6307ed-9c96-429f-919d-5ed82a40c6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
28516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3845928516
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3282599331
Short name T1448
Test name
Test status
Simulation time 3342686365 ps
CPU time 3.55 seconds
Started Jul 09 05:15:54 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206220 kb
Host smart-197b73a7-6dcd-4d2e-918e-0dd9e4f7e677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
99331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3282599331
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.497376586
Short name T1003
Test name
Test status
Simulation time 9754578750 ps
CPU time 70.15 seconds
Started Jul 09 05:15:57 PM PDT 24
Finished Jul 09 05:17:09 PM PDT 24
Peak memory 206388 kb
Host smart-b24b890e-ea89-4851-b73a-f830550ff9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49737
6586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.497376586
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3114270094
Short name T355
Test name
Test status
Simulation time 3242974904 ps
CPU time 89.62 seconds
Started Jul 09 05:15:54 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206304 kb
Host smart-8db01b80-d25a-4f78-b285-2e923a59dfb0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3114270094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3114270094
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3589564050
Short name T733
Test name
Test status
Simulation time 273242042 ps
CPU time 0.95 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206084 kb
Host smart-a6e84ae5-f800-4b07-95d6-3c6f614ca6e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3589564050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3589564050
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.406675869
Short name T2409
Test name
Test status
Simulation time 241751615 ps
CPU time 0.9 seconds
Started Jul 09 05:15:54 PM PDT 24
Finished Jul 09 05:15:56 PM PDT 24
Peak memory 205964 kb
Host smart-68cd6967-0c24-4f15-86b6-3ed0ac7ea06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40667
5869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.406675869
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2119162170
Short name T2408
Test name
Test status
Simulation time 4051603453 ps
CPU time 29.41 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:16:30 PM PDT 24
Peak memory 206392 kb
Host smart-60affdd2-636b-4bc6-8c0c-02995e925c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
62170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2119162170
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.4111827946
Short name T1790
Test name
Test status
Simulation time 3178013161 ps
CPU time 88.94 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206360 kb
Host smart-b15374b7-f62e-4f55-ba79-82b76967783d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4111827946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4111827946
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.1699418582
Short name T1233
Test name
Test status
Simulation time 174941054 ps
CPU time 0.86 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206044 kb
Host smart-c1a5eb78-d5c2-4c3e-ba4d-10dae4563d91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699418582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1699418582
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.841476737
Short name T489
Test name
Test status
Simulation time 157603736 ps
CPU time 0.8 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206060 kb
Host smart-da665561-c1dc-400c-a2fa-b5ec950261cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84147
6737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.841476737
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2861622037
Short name T115
Test name
Test status
Simulation time 227686270 ps
CPU time 0.91 seconds
Started Jul 09 05:15:52 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 206108 kb
Host smart-2045a524-3277-4d22-b27e-0066546c6445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28616
22037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2861622037
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.760061816
Short name T2008
Test name
Test status
Simulation time 183555445 ps
CPU time 0.84 seconds
Started Jul 09 05:15:58 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206052 kb
Host smart-201ac78a-b3c3-4354-985e-55d7aac224b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76006
1816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.760061816
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3941302113
Short name T2259
Test name
Test status
Simulation time 183014344 ps
CPU time 0.78 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206108 kb
Host smart-9074a9bc-b93a-4bb7-9d5c-bd791f7c475d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39413
02113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3941302113
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1557971176
Short name T2118
Test name
Test status
Simulation time 206923992 ps
CPU time 0.8 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:15:59 PM PDT 24
Peak memory 205952 kb
Host smart-19d6c4bd-36f7-426a-8d32-73ff2e451526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15579
71176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1557971176
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.343198408
Short name T161
Test name
Test status
Simulation time 172673416 ps
CPU time 0.87 seconds
Started Jul 09 05:15:53 PM PDT 24
Finished Jul 09 05:15:55 PM PDT 24
Peak memory 206028 kb
Host smart-3320e2f7-4226-443f-8e8b-28a7a6e84e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34319
8408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.343198408
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.479211724
Short name T2476
Test name
Test status
Simulation time 163525747 ps
CPU time 0.84 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206092 kb
Host smart-00526936-ec24-42a5-b019-c7f2d3cb3d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47921
1724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.479211724
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.890409785
Short name T2345
Test name
Test status
Simulation time 29237296 ps
CPU time 0.65 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:56 PM PDT 24
Peak memory 206156 kb
Host smart-f3d4c67a-3fa0-43e1-ac10-28ee66ae1392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89040
9785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.890409785
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1731234695
Short name T1450
Test name
Test status
Simulation time 23644616813 ps
CPU time 52.45 seconds
Started Jul 09 05:15:56 PM PDT 24
Finished Jul 09 05:16:51 PM PDT 24
Peak memory 214496 kb
Host smart-4e5a7a64-e78a-4ba8-b892-e9ab222d8fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
34695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1731234695
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.639334551
Short name T1759
Test name
Test status
Simulation time 195566546 ps
CPU time 0.9 seconds
Started Jul 09 05:15:58 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206060 kb
Host smart-d6bc864b-a115-4f9b-bdf6-bcb5145a506c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63933
4551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.639334551
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2897923197
Short name T898
Test name
Test status
Simulation time 205914350 ps
CPU time 0.91 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:16:02 PM PDT 24
Peak memory 206128 kb
Host smart-8e1e0400-f275-498d-9f0a-4566c21338a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28979
23197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2897923197
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2260873765
Short name T529
Test name
Test status
Simulation time 213334714 ps
CPU time 0.92 seconds
Started Jul 09 05:15:55 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206116 kb
Host smart-339a84a4-dcce-4fb6-942e-9a94093065a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22608
73765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2260873765
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3972829926
Short name T721
Test name
Test status
Simulation time 226024526 ps
CPU time 0.93 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:16:02 PM PDT 24
Peak memory 206152 kb
Host smart-e5b4b860-648c-46cd-adb8-b18eb76519ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728
29926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3972829926
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1951995760
Short name T945
Test name
Test status
Simulation time 162872224 ps
CPU time 0.79 seconds
Started Jul 09 05:15:58 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206144 kb
Host smart-7f1c25a9-c99c-4fee-b4a0-9a4d5321cb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19519
95760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1951995760
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1568024513
Short name T1314
Test name
Test status
Simulation time 146464013 ps
CPU time 0.82 seconds
Started Jul 09 05:15:58 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206060 kb
Host smart-0b64336f-9d9f-4530-82d7-c4e524ff1035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15680
24513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1568024513
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3465182597
Short name T1630
Test name
Test status
Simulation time 161933849 ps
CPU time 0.75 seconds
Started Jul 09 05:15:57 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 205952 kb
Host smart-a84d77be-7a69-44d1-8fe7-dbeb9439a469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34651
82597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3465182597
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1438973961
Short name T1346
Test name
Test status
Simulation time 182806062 ps
CPU time 0.88 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:16:02 PM PDT 24
Peak memory 206128 kb
Host smart-5169efd2-3acd-44b3-ba76-f0f12dd3d7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
73961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1438973961
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3300680264
Short name T612
Test name
Test status
Simulation time 4833546687 ps
CPU time 45.47 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206352 kb
Host smart-52dfd63f-bad2-4ba0-9ed3-e3761f3b2c0c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3300680264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3300680264
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.387350298
Short name T1828
Test name
Test status
Simulation time 193735585 ps
CPU time 0.83 seconds
Started Jul 09 05:16:02 PM PDT 24
Finished Jul 09 05:16:04 PM PDT 24
Peak memory 206148 kb
Host smart-eb12e6d4-737d-46ed-9aa8-6bb38db189f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38735
0298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.387350298
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.692512452
Short name T1030
Test name
Test status
Simulation time 187941109 ps
CPU time 0.83 seconds
Started Jul 09 05:16:04 PM PDT 24
Finished Jul 09 05:16:06 PM PDT 24
Peak memory 205952 kb
Host smart-ddd3579e-ecac-41f6-848a-248addf5f798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69251
2452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.692512452
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3689984692
Short name T1061
Test name
Test status
Simulation time 1195744786 ps
CPU time 2.51 seconds
Started Jul 09 05:15:58 PM PDT 24
Finished Jul 09 05:16:02 PM PDT 24
Peak memory 206404 kb
Host smart-e339089d-0af9-4cec-b89a-33d0350a1f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899
84692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3689984692
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3388744549
Short name T1078
Test name
Test status
Simulation time 7523742649 ps
CPU time 56.09 seconds
Started Jul 09 05:15:59 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206632 kb
Host smart-7bc59492-37ab-4cb8-a76d-ecd52d93ce41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33887
44549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3388744549
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1691888115
Short name T1367
Test name
Test status
Simulation time 68569803 ps
CPU time 0.74 seconds
Started Jul 09 05:16:09 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206196 kb
Host smart-967d8d0a-f6b1-466e-9a9b-86b1b85c1622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1691888115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1691888115
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2506518723
Short name T1627
Test name
Test status
Simulation time 4179597038 ps
CPU time 4.63 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206400 kb
Host smart-06752673-796d-400d-893c-472a3a722ced
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2506518723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2506518723
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.838976161
Short name T1131
Test name
Test status
Simulation time 13397585102 ps
CPU time 15.16 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 206452 kb
Host smart-0fe9cfe1-9ab2-43ef-9cf4-2de1774b5b0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=838976161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.838976161
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.110633715
Short name T2691
Test name
Test status
Simulation time 23383893105 ps
CPU time 22.19 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206320 kb
Host smart-204b3e87-e595-4b77-9cf9-99fab6c744a7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=110633715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.110633715
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.4021861741
Short name T1693
Test name
Test status
Simulation time 187181159 ps
CPU time 0.87 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206132 kb
Host smart-54aae498-5b22-421f-b60f-7bd33e5026b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
61741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4021861741
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1787435282
Short name T2533
Test name
Test status
Simulation time 157607277 ps
CPU time 0.77 seconds
Started Jul 09 05:15:57 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206108 kb
Host smart-47f80a2a-c5dc-4d10-bd7e-6031580d41bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17874
35282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1787435282
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.185269421
Short name T1964
Test name
Test status
Simulation time 169234323 ps
CPU time 0.81 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206088 kb
Host smart-481ff670-650c-474a-8e51-412f8aa4df9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526
9421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.185269421
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3483652841
Short name T1599
Test name
Test status
Simulation time 329503327 ps
CPU time 1.04 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:02 PM PDT 24
Peak memory 206048 kb
Host smart-bfd7a1ee-43ae-468f-a6ad-c5e1942df90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
52841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3483652841
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3639730799
Short name T696
Test name
Test status
Simulation time 15815308089 ps
CPU time 31.68 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206404 kb
Host smart-a78271b0-3caf-4ce5-93ab-36d194107cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36397
30799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3639730799
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3131544476
Short name T757
Test name
Test status
Simulation time 433707288 ps
CPU time 1.39 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206136 kb
Host smart-ab73f656-2ef1-4e5b-98c4-2bd1caa82cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31315
44476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3131544476
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.4077016211
Short name T1673
Test name
Test status
Simulation time 144951392 ps
CPU time 0.76 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206068 kb
Host smart-d1364b30-0dc1-488c-8d62-80c7df7ce56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
16211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.4077016211
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2040549344
Short name T1298
Test name
Test status
Simulation time 70295419 ps
CPU time 0.74 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:05 PM PDT 24
Peak memory 206108 kb
Host smart-7cf49b75-779e-4d42-8ba0-096c137be2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20405
49344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2040549344
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.275730900
Short name T564
Test name
Test status
Simulation time 844071298 ps
CPU time 2.15 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206224 kb
Host smart-7760ff5d-70e4-4b7b-ac4c-1f9c05058208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27573
0900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.275730900
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3085706747
Short name T984
Test name
Test status
Simulation time 157879561 ps
CPU time 1.22 seconds
Started Jul 09 05:16:05 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206208 kb
Host smart-3151dc5b-506b-4b74-a12d-df5eb7af922d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
06747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3085706747
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3434936499
Short name T1066
Test name
Test status
Simulation time 172599967 ps
CPU time 0.81 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:05 PM PDT 24
Peak memory 206128 kb
Host smart-6309106c-e3e0-4fe8-a41e-4619650153b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349
36499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3434936499
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2240662999
Short name T1832
Test name
Test status
Simulation time 149374334 ps
CPU time 0.75 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:04 PM PDT 24
Peak memory 206144 kb
Host smart-906152fe-dd14-4ebf-863e-0054e4befbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
62999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2240662999
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2029087337
Short name T2478
Test name
Test status
Simulation time 230992343 ps
CPU time 0.96 seconds
Started Jul 09 05:16:02 PM PDT 24
Finished Jul 09 05:16:04 PM PDT 24
Peak memory 205960 kb
Host smart-d2a11b6d-d69d-444c-b29a-e915db05f8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20290
87337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2029087337
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.871868517
Short name T1205
Test name
Test status
Simulation time 5870137686 ps
CPU time 40.22 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206256 kb
Host smart-ea9a5a78-a90e-449e-b83d-a9c00025d402
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=871868517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.871868517
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.141100047
Short name T1561
Test name
Test status
Simulation time 186843071 ps
CPU time 0.88 seconds
Started Jul 09 05:16:05 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206120 kb
Host smart-3a0f51e1-4510-46f5-bf37-642712becec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14110
0047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.141100047
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.498649228
Short name T2443
Test name
Test status
Simulation time 23288000953 ps
CPU time 24.66 seconds
Started Jul 09 05:16:04 PM PDT 24
Finished Jul 09 05:16:30 PM PDT 24
Peak memory 206128 kb
Host smart-5633bab0-ee5c-4718-a9f0-2adb06f6c104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49864
9228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.498649228
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.700882600
Short name T410
Test name
Test status
Simulation time 3342279979 ps
CPU time 3.86 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206156 kb
Host smart-c94ebb04-6daa-4b7c-99a2-9ea1636de495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70088
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.700882600
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.153826650
Short name T242
Test name
Test status
Simulation time 12343735549 ps
CPU time 87.54 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 206468 kb
Host smart-b24d001d-1ce1-4e5d-8b62-7e56cbc45f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15382
6650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.153826650
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1957533131
Short name T2439
Test name
Test status
Simulation time 5563717869 ps
CPU time 51.61 seconds
Started Jul 09 05:16:02 PM PDT 24
Finished Jul 09 05:16:54 PM PDT 24
Peak memory 206368 kb
Host smart-6a37a023-3728-41d5-b403-3aad7bcbb9c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1957533131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1957533131
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1114324293
Short name T215
Test name
Test status
Simulation time 246284996 ps
CPU time 1 seconds
Started Jul 09 05:16:00 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206100 kb
Host smart-1be52f6e-be79-4a4c-814a-77d6703061b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1114324293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1114324293
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1910649204
Short name T2146
Test name
Test status
Simulation time 194700803 ps
CPU time 0.89 seconds
Started Jul 09 05:16:04 PM PDT 24
Finished Jul 09 05:16:06 PM PDT 24
Peak memory 206116 kb
Host smart-64e974d0-5046-4d5b-97d8-2dd66659b828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19106
49204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1910649204
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.37082
Short name T769
Test name
Test status
Simulation time 5717778974 ps
CPU time 155.85 seconds
Started Jul 09 05:16:06 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206412 kb
Host smart-ebc19e8b-3a9b-473c-8584-6abf42f099d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
-assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.37082
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.56704689
Short name T2534
Test name
Test status
Simulation time 5284239479 ps
CPU time 150.14 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206436 kb
Host smart-6e5352f9-6b4f-4368-80e6-3f27ac89a23f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=56704689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.56704689
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3130774525
Short name T2467
Test name
Test status
Simulation time 238186870 ps
CPU time 0.87 seconds
Started Jul 09 05:16:01 PM PDT 24
Finished Jul 09 05:16:03 PM PDT 24
Peak memory 206132 kb
Host smart-81c64678-fab7-4357-859a-db9a5716a1a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3130774525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3130774525
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.771010051
Short name T1909
Test name
Test status
Simulation time 146450888 ps
CPU time 0.77 seconds
Started Jul 09 05:16:04 PM PDT 24
Finished Jul 09 05:16:06 PM PDT 24
Peak memory 206132 kb
Host smart-4d075bca-8f0a-4c43-8524-6730d4e087d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77101
0051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.771010051
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.725695811
Short name T2690
Test name
Test status
Simulation time 239038872 ps
CPU time 0.89 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:05 PM PDT 24
Peak memory 205992 kb
Host smart-1ce7e151-9774-471f-a6b2-8c9cfafe32b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72569
5811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.725695811
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1440534334
Short name T1588
Test name
Test status
Simulation time 170852491 ps
CPU time 0.82 seconds
Started Jul 09 05:16:03 PM PDT 24
Finished Jul 09 05:16:06 PM PDT 24
Peak memory 206144 kb
Host smart-5ab5ec52-4622-4d7d-a547-c9f0d96e9083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14405
34334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1440534334
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3373139160
Short name T1908
Test name
Test status
Simulation time 162414599 ps
CPU time 0.81 seconds
Started Jul 09 05:16:02 PM PDT 24
Finished Jul 09 05:16:04 PM PDT 24
Peak memory 206164 kb
Host smart-0f4249ee-700e-451b-915a-fe21ac1e9a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
39160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3373139160
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.4150639418
Short name T1320
Test name
Test status
Simulation time 145217731 ps
CPU time 0.81 seconds
Started Jul 09 05:16:04 PM PDT 24
Finished Jul 09 05:16:06 PM PDT 24
Peak memory 206124 kb
Host smart-f09afaa4-9193-4761-b17c-0209b80cb06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
39418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.4150639418
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2044319286
Short name T843
Test name
Test status
Simulation time 150699677 ps
CPU time 0.81 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:14 PM PDT 24
Peak memory 206020 kb
Host smart-50ed84cc-8ec3-4ea6-ab4a-b8c145600d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
19286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2044319286
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1125201806
Short name T558
Test name
Test status
Simulation time 209591811 ps
CPU time 0.89 seconds
Started Jul 09 05:16:02 PM PDT 24
Finished Jul 09 05:16:04 PM PDT 24
Peak memory 206024 kb
Host smart-2fdd35ec-143b-4338-b9bf-84676625377d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1125201806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1125201806
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1192987222
Short name T1954
Test name
Test status
Simulation time 134606790 ps
CPU time 0.77 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:16:13 PM PDT 24
Peak memory 206056 kb
Host smart-09397f15-d051-4481-afd7-d1d8b3cdc909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11929
87222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1192987222
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2129898821
Short name T1303
Test name
Test status
Simulation time 68667860 ps
CPU time 0.68 seconds
Started Jul 09 05:16:09 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206128 kb
Host smart-cec2b563-d586-4595-9a79-c8bba6b1d94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21298
98821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2129898821
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3323020522
Short name T2204
Test name
Test status
Simulation time 8612337143 ps
CPU time 21.88 seconds
Started Jul 09 05:16:06 PM PDT 24
Finished Jul 09 05:16:29 PM PDT 24
Peak memory 214520 kb
Host smart-625729ea-8964-4faf-9222-d70b451d09aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230
20522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3323020522
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2059776807
Short name T2231
Test name
Test status
Simulation time 179602076 ps
CPU time 0.9 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:09 PM PDT 24
Peak memory 206136 kb
Host smart-2ac9c2e1-3b63-4172-9a3d-b68f501ba321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597
76807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2059776807
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1539459157
Short name T723
Test name
Test status
Simulation time 221381347 ps
CPU time 0.94 seconds
Started Jul 09 05:16:05 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206016 kb
Host smart-69572855-9b84-4811-8026-02773209e8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15394
59157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1539459157
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3426533155
Short name T2654
Test name
Test status
Simulation time 175876555 ps
CPU time 0.79 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:16:13 PM PDT 24
Peak memory 206060 kb
Host smart-9cd83857-c0ee-43b9-9d41-e1bd07a43e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
33155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3426533155
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1842478755
Short name T534
Test name
Test status
Simulation time 179324431 ps
CPU time 0.82 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:09 PM PDT 24
Peak memory 206164 kb
Host smart-ec78881c-0694-4c1b-bc90-8ad9fe73a163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18424
78755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1842478755
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1996213265
Short name T880
Test name
Test status
Simulation time 184214890 ps
CPU time 0.86 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:10 PM PDT 24
Peak memory 206056 kb
Host smart-6933f650-0804-4a9b-b62e-9246589e770d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19962
13265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1996213265
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.4258601570
Short name T154
Test name
Test status
Simulation time 155167793 ps
CPU time 0.8 seconds
Started Jul 09 05:16:06 PM PDT 24
Finished Jul 09 05:16:08 PM PDT 24
Peak memory 206124 kb
Host smart-11ab8bcd-f797-487c-9764-b88022f67c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42586
01570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.4258601570
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2466563741
Short name T627
Test name
Test status
Simulation time 153118225 ps
CPU time 0.77 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:09 PM PDT 24
Peak memory 206148 kb
Host smart-d8d0d2cf-82b0-4260-8e4d-f30cb8e43675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24665
63741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2466563741
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3940019627
Short name T2485
Test name
Test status
Simulation time 197001370 ps
CPU time 0.89 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:10 PM PDT 24
Peak memory 206016 kb
Host smart-da9789d2-a23d-4118-a25b-8bc051fa0903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
19627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3940019627
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1676646259
Short name T2633
Test name
Test status
Simulation time 3596009147 ps
CPU time 34.41 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206344 kb
Host smart-015d9f9e-c559-4ffc-bb9f-cc15ac428a1a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1676646259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1676646259
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3145466791
Short name T2327
Test name
Test status
Simulation time 170800621 ps
CPU time 0.88 seconds
Started Jul 09 05:16:09 PM PDT 24
Finished Jul 09 05:16:10 PM PDT 24
Peak memory 206108 kb
Host smart-979377c6-4de1-46e4-bf15-d594fbedd139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
66791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3145466791
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.4191724776
Short name T1055
Test name
Test status
Simulation time 169612501 ps
CPU time 0.88 seconds
Started Jul 09 05:16:05 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 205992 kb
Host smart-530d760c-19db-422c-93d9-d8e5dd4495f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
24776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.4191724776
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2915672983
Short name T1377
Test name
Test status
Simulation time 1023568118 ps
CPU time 2.5 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206396 kb
Host smart-b8acc34d-ffdb-491a-9055-00ac3812b2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29156
72983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2915672983
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3256825012
Short name T1251
Test name
Test status
Simulation time 6094667624 ps
CPU time 53.07 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:17:02 PM PDT 24
Peak memory 206368 kb
Host smart-db7c69d7-9912-4738-a986-d634c921a92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32568
25012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3256825012
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3255598183
Short name T602
Test name
Test status
Simulation time 61152149 ps
CPU time 0.74 seconds
Started Jul 09 05:16:15 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 206180 kb
Host smart-a31ea3de-af58-4de7-9f65-1fd27fb76f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3255598183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3255598183
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3291755245
Short name T1393
Test name
Test status
Simulation time 4386324652 ps
CPU time 4.75 seconds
Started Jul 09 05:16:06 PM PDT 24
Finished Jul 09 05:16:12 PM PDT 24
Peak memory 206392 kb
Host smart-3d800d02-2666-4816-a8f7-18181c9ee68f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3291755245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3291755245
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.705148036
Short name T1212
Test name
Test status
Simulation time 13372791908 ps
CPU time 15.69 seconds
Started Jul 09 05:16:08 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206096 kb
Host smart-72d00007-ac33-4372-8c3d-94aba5667d21
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=705148036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.705148036
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1156611523
Short name T1396
Test name
Test status
Simulation time 23301047500 ps
CPU time 24.09 seconds
Started Jul 09 05:16:07 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206156 kb
Host smart-3de9c79b-6cf6-4161-9995-9c0b99975ad9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1156611523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1156611523
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2331785574
Short name T2286
Test name
Test status
Simulation time 192842805 ps
CPU time 0.82 seconds
Started Jul 09 05:16:09 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206136 kb
Host smart-8d0bdc0a-3fd6-42a8-ad76-b66a25948c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23317
85574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2331785574
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.212257060
Short name T2304
Test name
Test status
Simulation time 152277029 ps
CPU time 0.81 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:16:13 PM PDT 24
Peak memory 206060 kb
Host smart-c5be2099-cfa5-4c73-abb3-c46676718fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21225
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.212257060
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3998541331
Short name T596
Test name
Test status
Simulation time 200958206 ps
CPU time 0.88 seconds
Started Jul 09 05:16:07 PM PDT 24
Finished Jul 09 05:16:09 PM PDT 24
Peak memory 206124 kb
Host smart-80c5e01c-d413-4e72-9af9-df3bbc2e9671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39985
41331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3998541331
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3885784449
Short name T1831
Test name
Test status
Simulation time 550966442 ps
CPU time 1.55 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:16 PM PDT 24
Peak memory 206052 kb
Host smart-4b70026a-536b-439f-b741-072e89e7e523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38857
84449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3885784449
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1831341515
Short name T1600
Test name
Test status
Simulation time 22722575121 ps
CPU time 47.99 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:17:03 PM PDT 24
Peak memory 206328 kb
Host smart-79c795a5-8b1e-419c-a0d0-d611ac115d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
41515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1831341515
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3665906534
Short name T448
Test name
Test status
Simulation time 452728319 ps
CPU time 1.34 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:15 PM PDT 24
Peak memory 206068 kb
Host smart-920cb326-c5e6-4ee9-bb3d-fd4aa87d4023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659
06534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3665906534
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3476698809
Short name T1447
Test name
Test status
Simulation time 155602593 ps
CPU time 0.76 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:14 PM PDT 24
Peak memory 206096 kb
Host smart-86a08511-dbaa-4baa-8221-6bcf7baeb499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34766
98809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3476698809
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2179926423
Short name T1398
Test name
Test status
Simulation time 38540089 ps
CPU time 0.69 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:15 PM PDT 24
Peak memory 206052 kb
Host smart-b485a2e4-67fd-40b2-afe0-4f45e405fe02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21799
26423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2179926423
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1905668470
Short name T2323
Test name
Test status
Simulation time 834877253 ps
CPU time 2.04 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:16 PM PDT 24
Peak memory 206264 kb
Host smart-d3ecfa60-81ea-4897-b433-8a60f7c3291f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19056
68470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1905668470
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2232257724
Short name T1462
Test name
Test status
Simulation time 408885142 ps
CPU time 2.21 seconds
Started Jul 09 05:16:15 PM PDT 24
Finished Jul 09 05:16:18 PM PDT 24
Peak memory 206352 kb
Host smart-29baa661-5112-464d-a1fb-aa351ac6fcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
57724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2232257724
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.361461433
Short name T1435
Test name
Test status
Simulation time 186713187 ps
CPU time 0.85 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:16:12 PM PDT 24
Peak memory 206112 kb
Host smart-a0b8f863-5883-4f02-9ed2-ecac03570748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36146
1433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.361461433
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1661358481
Short name T995
Test name
Test status
Simulation time 147861794 ps
CPU time 0.79 seconds
Started Jul 09 05:16:10 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206020 kb
Host smart-106e710b-1cbd-498b-b126-72aad69dc4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16613
58481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1661358481
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2651064272
Short name T2309
Test name
Test status
Simulation time 235223583 ps
CPU time 0.95 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:16:13 PM PDT 24
Peak memory 206064 kb
Host smart-bf6c093e-a146-4e39-bb0d-e4c6ab3a37b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
64272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2651064272
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3106959239
Short name T1401
Test name
Test status
Simulation time 9831586625 ps
CPU time 282.68 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:20:56 PM PDT 24
Peak memory 206380 kb
Host smart-3ec5aadc-3a93-4872-8e57-b6b4988cd00d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3106959239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3106959239
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2827107942
Short name T1242
Test name
Test status
Simulation time 214848193 ps
CPU time 0.88 seconds
Started Jul 09 05:16:10 PM PDT 24
Finished Jul 09 05:16:11 PM PDT 24
Peak memory 206008 kb
Host smart-f4c4f100-4d48-4f91-8e72-2337d9afc1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28271
07942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2827107942
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.4199049451
Short name T737
Test name
Test status
Simulation time 23323592824 ps
CPU time 23.88 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206212 kb
Host smart-dfdd3bc4-da63-4f0e-8d11-8b46475ec5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41990
49451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.4199049451
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1174204793
Short name T335
Test name
Test status
Simulation time 3310940920 ps
CPU time 3.88 seconds
Started Jul 09 05:16:16 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 206192 kb
Host smart-fc3e98b7-86a4-45fb-bb49-050ec58bba31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11742
04793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1174204793
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.4122252106
Short name T1088
Test name
Test status
Simulation time 6483378838 ps
CPU time 177.79 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:19:10 PM PDT 24
Peak memory 206472 kb
Host smart-47f08d39-9dd3-4e8e-a9e4-7561fed12095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
52106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.4122252106
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2934507150
Short name T1694
Test name
Test status
Simulation time 5171247083 ps
CPU time 50.61 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:17:05 PM PDT 24
Peak memory 206232 kb
Host smart-6a1d36e0-9a1f-46ff-adcf-8eb100671bad
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2934507150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2934507150
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.400842561
Short name T1703
Test name
Test status
Simulation time 249570921 ps
CPU time 0.93 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:15 PM PDT 24
Peak memory 206144 kb
Host smart-d81df54f-e632-4f13-b61a-9ab32ba0f6c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=400842561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.400842561
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2816499334
Short name T406
Test name
Test status
Simulation time 204023979 ps
CPU time 0.93 seconds
Started Jul 09 05:16:15 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 206128 kb
Host smart-0ad8dc5f-07b4-4df3-a943-6d0b38e477c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28164
99334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2816499334
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1641490656
Short name T938
Test name
Test status
Simulation time 6725821327 ps
CPU time 66.13 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206328 kb
Host smart-cecf9a2d-5d77-4349-a361-0e91dc6a7afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16414
90656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1641490656
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2692579865
Short name T1514
Test name
Test status
Simulation time 3635494563 ps
CPU time 101.7 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206328 kb
Host smart-9300c383-e839-4fe3-b2ac-dda24b32e4a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2692579865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2692579865
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1442949744
Short name T1427
Test name
Test status
Simulation time 205948761 ps
CPU time 0.88 seconds
Started Jul 09 05:16:15 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 206084 kb
Host smart-e616c472-411c-49b7-89e7-81d430b3247e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1442949744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1442949744
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3838940053
Short name T2024
Test name
Test status
Simulation time 150221980 ps
CPU time 0.77 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:14 PM PDT 24
Peak memory 206164 kb
Host smart-21f4d1f5-c711-4fe0-a331-900a7225c8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
40053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3838940053
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1051511624
Short name T124
Test name
Test status
Simulation time 197697640 ps
CPU time 0.9 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:14 PM PDT 24
Peak memory 206120 kb
Host smart-92f41cdf-60df-4f72-baa2-d0b345b69d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
11624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1051511624
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.544355386
Short name T607
Test name
Test status
Simulation time 195582296 ps
CPU time 0.88 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:14 PM PDT 24
Peak memory 206088 kb
Host smart-dafc9b82-9e63-4578-b766-a15aec3b6ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54435
5386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.544355386
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.357555190
Short name T747
Test name
Test status
Simulation time 156606767 ps
CPU time 0.77 seconds
Started Jul 09 05:16:15 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 206104 kb
Host smart-4d1de8b5-e027-4f23-b3fe-732041bd0ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35755
5190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.357555190
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2285562307
Short name T1492
Test name
Test status
Simulation time 200112974 ps
CPU time 0.87 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:15 PM PDT 24
Peak memory 205992 kb
Host smart-2377ff68-b117-4aeb-908c-9a59e7bd33eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
62307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2285562307
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.819762940
Short name T573
Test name
Test status
Simulation time 153775472 ps
CPU time 0.79 seconds
Started Jul 09 05:16:11 PM PDT 24
Finished Jul 09 05:16:13 PM PDT 24
Peak memory 206160 kb
Host smart-997e98e3-150b-4fbb-89e1-7cda48714d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81976
2940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.819762940
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2111016815
Short name T1613
Test name
Test status
Simulation time 218335228 ps
CPU time 0.96 seconds
Started Jul 09 05:16:12 PM PDT 24
Finished Jul 09 05:16:14 PM PDT 24
Peak memory 206124 kb
Host smart-91d910ec-a3d8-4228-aa88-1a57b2f5e466
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2111016815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2111016815
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2229364395
Short name T2050
Test name
Test status
Simulation time 193922678 ps
CPU time 0.79 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:15 PM PDT 24
Peak memory 206156 kb
Host smart-ae9a8a75-4a98-4f37-8011-c6b962360f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22293
64395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2229364395
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3767246078
Short name T1667
Test name
Test status
Simulation time 110348021 ps
CPU time 0.75 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 206040 kb
Host smart-737d5614-7e86-489d-b943-c53facc97285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37672
46078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3767246078
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2244734473
Short name T2375
Test name
Test status
Simulation time 19143674580 ps
CPU time 44.19 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:17:03 PM PDT 24
Peak memory 206396 kb
Host smart-e5c8e95c-b0ba-44ad-8f61-3b863a20e6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22447
34473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2244734473
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1697035749
Short name T2442
Test name
Test status
Simulation time 159675607 ps
CPU time 0.87 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:18 PM PDT 24
Peak memory 206164 kb
Host smart-ea35afe2-aa25-48e2-b156-41fe355a63bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16970
35749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1697035749
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3184610784
Short name T385
Test name
Test status
Simulation time 224714049 ps
CPU time 0.92 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 206156 kb
Host smart-5afe1364-ad04-4dfb-a68a-840e6e8f6b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31846
10784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3184610784
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.685605271
Short name T1330
Test name
Test status
Simulation time 183120226 ps
CPU time 0.9 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:18 PM PDT 24
Peak memory 206132 kb
Host smart-b2690baa-272d-41df-b59f-dd3795338755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68560
5271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.685605271
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3556554984
Short name T1485
Test name
Test status
Simulation time 210645604 ps
CPU time 0.89 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:19 PM PDT 24
Peak memory 206068 kb
Host smart-00aade11-9dba-4291-a43f-f27120953590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35565
54984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3556554984
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.684062313
Short name T582
Test name
Test status
Simulation time 185747916 ps
CPU time 0.89 seconds
Started Jul 09 05:16:13 PM PDT 24
Finished Jul 09 05:16:16 PM PDT 24
Peak memory 206060 kb
Host smart-b9cd6d77-e84b-4543-9365-57f7596f3bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68406
2313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.684062313
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.164717647
Short name T555
Test name
Test status
Simulation time 173402797 ps
CPU time 0.82 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 206048 kb
Host smart-caad9264-32c5-4470-bdfd-757bae3eded9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16471
7647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.164717647
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3567816509
Short name T2324
Test name
Test status
Simulation time 148408105 ps
CPU time 0.75 seconds
Started Jul 09 05:16:15 PM PDT 24
Finished Jul 09 05:16:17 PM PDT 24
Peak memory 206136 kb
Host smart-09e05cfb-dc75-4a23-bd86-ca73040e94f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35678
16509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3567816509
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3770564319
Short name T2341
Test name
Test status
Simulation time 206295946 ps
CPU time 0.88 seconds
Started Jul 09 05:16:14 PM PDT 24
Finished Jul 09 05:16:16 PM PDT 24
Peak memory 206120 kb
Host smart-b3868216-26b0-4720-9db5-a2d471157d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37705
64319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3770564319
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1880801241
Short name T148
Test name
Test status
Simulation time 6542768725 ps
CPU time 60.76 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:17:19 PM PDT 24
Peak memory 206416 kb
Host smart-ad53e9c9-53c5-49da-a33e-df8b545c8706
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1880801241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1880801241
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1120900821
Short name T1803
Test name
Test status
Simulation time 233961104 ps
CPU time 0.98 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:21 PM PDT 24
Peak memory 206132 kb
Host smart-deeb754e-4c08-49d3-805e-bb63be27163d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11209
00821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1120900821
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2506235200
Short name T1038
Test name
Test status
Simulation time 186282907 ps
CPU time 0.82 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:19 PM PDT 24
Peak memory 206016 kb
Host smart-c34b20bd-3460-48c7-9d6b-554efe02be00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
35200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2506235200
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3529998408
Short name T914
Test name
Test status
Simulation time 852740610 ps
CPU time 2.2 seconds
Started Jul 09 05:16:16 PM PDT 24
Finished Jul 09 05:16:19 PM PDT 24
Peak memory 206264 kb
Host smart-30a63ba7-678e-4031-ac94-4e5a5ae47e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35299
98408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3529998408
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1825565235
Short name T1024
Test name
Test status
Simulation time 4288199243 ps
CPU time 124.49 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:18:22 PM PDT 24
Peak memory 206464 kb
Host smart-fb2a6dd5-ab6b-4269-90e7-b708f697b3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255
65235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1825565235
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3624659335
Short name T2273
Test name
Test status
Simulation time 36889285 ps
CPU time 0.69 seconds
Started Jul 09 05:16:25 PM PDT 24
Finished Jul 09 05:16:26 PM PDT 24
Peak memory 206120 kb
Host smart-a48fc930-577c-4b1f-b556-f27f03f4a523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3624659335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3624659335
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.549716019
Short name T2430
Test name
Test status
Simulation time 4079458292 ps
CPU time 4.46 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:23 PM PDT 24
Peak memory 206428 kb
Host smart-6d61d9dd-1af4-4933-b1de-2eeaf15763d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=549716019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.549716019
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.807536793
Short name T2614
Test name
Test status
Simulation time 13366806969 ps
CPU time 12.17 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206460 kb
Host smart-c4bd6ca6-9b1d-408e-b905-b769f5b70887
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=807536793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.807536793
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3927684365
Short name T1745
Test name
Test status
Simulation time 23370381346 ps
CPU time 22.71 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206432 kb
Host smart-d4d80d72-e94d-4648-85ab-dcc2d6989a51
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3927684365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3927684365
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1973390885
Short name T79
Test name
Test status
Simulation time 165021909 ps
CPU time 0.81 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:21 PM PDT 24
Peak memory 206132 kb
Host smart-9f817c10-fe95-4f0b-b6ad-083be205d0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19733
90885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1973390885
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2231243864
Short name T2057
Test name
Test status
Simulation time 155130243 ps
CPU time 0.83 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:29 PM PDT 24
Peak memory 206092 kb
Host smart-88dbef2c-b745-43be-b53d-515cfd695b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22312
43864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2231243864
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2172560436
Short name T2489
Test name
Test status
Simulation time 477985865 ps
CPU time 1.48 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:22 PM PDT 24
Peak memory 206068 kb
Host smart-d9c99afc-9f8a-4536-8f84-8405fd93d84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21725
60436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2172560436
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1324416830
Short name T238
Test name
Test status
Simulation time 259003070 ps
CPU time 0.92 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:22 PM PDT 24
Peak memory 206016 kb
Host smart-d93eb59b-0f84-42e7-b875-628d5dd2325d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13244
16830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1324416830
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3368567740
Short name T1124
Test name
Test status
Simulation time 21798393070 ps
CPU time 38.7 seconds
Started Jul 09 05:16:28 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206388 kb
Host smart-914531bb-e486-467f-ac37-d39f46789899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33685
67740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3368567740
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1041846699
Short name T2389
Test name
Test status
Simulation time 383425857 ps
CPU time 1.24 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:21 PM PDT 24
Peak memory 206068 kb
Host smart-628d0f7b-15c3-45c1-92e6-edc01656c1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
46699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1041846699
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2182919602
Short name T1312
Test name
Test status
Simulation time 142466085 ps
CPU time 0.78 seconds
Started Jul 09 05:16:21 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206128 kb
Host smart-d6942f8a-e008-436d-ab8f-8c320df5711f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21829
19602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2182919602
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.400225252
Short name T1631
Test name
Test status
Simulation time 43218834 ps
CPU time 0.68 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:16:23 PM PDT 24
Peak memory 206032 kb
Host smart-f67dbe3f-325f-49f6-b9b4-b38b2310fae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40022
5252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.400225252
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2842782396
Short name T2103
Test name
Test status
Simulation time 931919222 ps
CPU time 2.3 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206384 kb
Host smart-608eeca1-54d8-4934-8e7f-eac6bb6a8c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
82396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2842782396
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1795887480
Short name T1615
Test name
Test status
Simulation time 178758519 ps
CPU time 1.92 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:16:23 PM PDT 24
Peak memory 206388 kb
Host smart-5c65d5c1-58eb-48b6-98d7-af6bfe2739d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
87480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1795887480
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1310847695
Short name T480
Test name
Test status
Simulation time 196573390 ps
CPU time 0.94 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:21 PM PDT 24
Peak memory 206140 kb
Host smart-b4723782-0455-45da-b4b0-757db76f94b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108
47695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1310847695
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3987759992
Short name T443
Test name
Test status
Simulation time 146431760 ps
CPU time 0.77 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:21 PM PDT 24
Peak memory 206036 kb
Host smart-39ee01d8-2dcc-4b11-bda9-6a738e86e3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
59992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3987759992
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4052995408
Short name T1319
Test name
Test status
Simulation time 246718016 ps
CPU time 0.94 seconds
Started Jul 09 05:16:17 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 206080 kb
Host smart-a267dd26-8533-4772-9600-b441137b3864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40529
95408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4052995408
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.357977403
Short name T2388
Test name
Test status
Simulation time 7976243105 ps
CPU time 54.09 seconds
Started Jul 09 05:16:21 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206412 kb
Host smart-85c80b10-fafb-4031-8f77-0d7ea3ebcd97
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=357977403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.357977403
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3369698843
Short name T2446
Test name
Test status
Simulation time 205261396 ps
CPU time 0.85 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 206144 kb
Host smart-2282fbfd-ba48-40a0-8b10-8c60ea305432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33696
98843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3369698843
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2206267525
Short name T2702
Test name
Test status
Simulation time 23298285927 ps
CPU time 20.93 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:16:42 PM PDT 24
Peak memory 206120 kb
Host smart-e5c26bb2-54a2-4f97-8c56-c84892d33ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22062
67525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2206267525
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2882555661
Short name T575
Test name
Test status
Simulation time 3348081644 ps
CPU time 3.98 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 206112 kb
Host smart-17e3f447-e81b-4f6c-b6b7-0387bbb06691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
55661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2882555661
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2283769938
Short name T1440
Test name
Test status
Simulation time 7870110899 ps
CPU time 226.15 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:20:08 PM PDT 24
Peak memory 206420 kb
Host smart-71fc05d0-79b4-4b29-82f4-73cea87f8eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22837
69938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2283769938
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2642343532
Short name T1512
Test name
Test status
Simulation time 7618225992 ps
CPU time 56.85 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:17:19 PM PDT 24
Peak memory 206356 kb
Host smart-02eb1ed8-23fa-4723-9f14-86c21381f3b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2642343532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2642343532
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2602947954
Short name T1094
Test name
Test status
Simulation time 244580508 ps
CPU time 0.96 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:22 PM PDT 24
Peak memory 206012 kb
Host smart-8cfb601a-267c-4e35-bce0-f869849cf8d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2602947954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2602947954
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1697059481
Short name T799
Test name
Test status
Simulation time 251578034 ps
CPU time 0.89 seconds
Started Jul 09 05:16:19 PM PDT 24
Finished Jul 09 05:16:21 PM PDT 24
Peak memory 205996 kb
Host smart-d77b212a-3e9c-4d14-b0d8-c55cdf2d232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16970
59481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1697059481
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.1803453187
Short name T151
Test name
Test status
Simulation time 4813063503 ps
CPU time 35.36 seconds
Started Jul 09 05:16:18 PM PDT 24
Finished Jul 09 05:16:55 PM PDT 24
Peak memory 206372 kb
Host smart-fb21a68c-a6d6-41ac-8f49-6940f6c5db61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
53187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.1803453187
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.842187950
Short name T1698
Test name
Test status
Simulation time 7078156381 ps
CPU time 202.41 seconds
Started Jul 09 05:16:20 PM PDT 24
Finished Jul 09 05:19:44 PM PDT 24
Peak memory 206432 kb
Host smart-dfa74d99-c93e-4995-93b9-c3105d722622
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=842187950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.842187950
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.259369256
Short name T2474
Test name
Test status
Simulation time 150098042 ps
CPU time 0.8 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206020 kb
Host smart-73e69f3b-471e-470a-9c3f-df8b713edc5e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=259369256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.259369256
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.563884536
Short name T1376
Test name
Test status
Simulation time 151685520 ps
CPU time 0.78 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206120 kb
Host smart-c2743b7a-558d-45a2-8dcc-f31a61555681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56388
4536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.563884536
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1143383424
Short name T118
Test name
Test status
Simulation time 178576450 ps
CPU time 0.92 seconds
Started Jul 09 05:16:28 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 206056 kb
Host smart-d6e08d29-3705-4069-8251-5f4ec8c77acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11433
83424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1143383424
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1354770905
Short name T2425
Test name
Test status
Simulation time 157489781 ps
CPU time 0.82 seconds
Started Jul 09 05:16:23 PM PDT 24
Finished Jul 09 05:16:25 PM PDT 24
Peak memory 206152 kb
Host smart-cfa387d3-bd56-4481-a4f9-9443207a60e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13547
70905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1354770905
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1104109088
Short name T2120
Test name
Test status
Simulation time 187074149 ps
CPU time 0.85 seconds
Started Jul 09 05:16:24 PM PDT 24
Finished Jul 09 05:16:25 PM PDT 24
Peak memory 206160 kb
Host smart-5eb8fa78-e641-4ab1-ab5e-a68973c87688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
09088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1104109088
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2070762020
Short name T2234
Test name
Test status
Simulation time 190026479 ps
CPU time 0.86 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 205952 kb
Host smart-23c84cd6-4db6-4e91-886f-e497227476cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20707
62020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2070762020
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2456166481
Short name T370
Test name
Test status
Simulation time 160973805 ps
CPU time 0.85 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:30 PM PDT 24
Peak memory 206148 kb
Host smart-8a521dab-f2e1-4b38-b5d9-edd7728b88ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24561
66481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2456166481
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2425215547
Short name T1500
Test name
Test status
Simulation time 252590744 ps
CPU time 0.98 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:34 PM PDT 24
Peak memory 206128 kb
Host smart-f42c2c5e-a10b-46f0-a49f-e0b30ddec6b8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2425215547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2425215547
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.383273146
Short name T784
Test name
Test status
Simulation time 146272716 ps
CPU time 0.83 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206008 kb
Host smart-f1d5ed40-2f15-4ea9-8de0-d7a471d35d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38327
3146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.383273146
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1695196773
Short name T785
Test name
Test status
Simulation time 70788923 ps
CPU time 0.71 seconds
Started Jul 09 05:16:25 PM PDT 24
Finished Jul 09 05:16:27 PM PDT 24
Peak memory 206128 kb
Host smart-8a1825bf-cedc-4815-b1d0-efe847e9aac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16951
96773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1695196773
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1464405966
Short name T959
Test name
Test status
Simulation time 7621526559 ps
CPU time 16.55 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:17:00 PM PDT 24
Peak memory 206364 kb
Host smart-a469d415-8460-480c-8862-831c7675c25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14644
05966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1464405966
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3142893470
Short name T2396
Test name
Test status
Simulation time 255594878 ps
CPU time 0.91 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206052 kb
Host smart-732f6284-ef2b-4448-9f09-fbf145c30389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31428
93470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3142893470
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3704177187
Short name T1339
Test name
Test status
Simulation time 228365786 ps
CPU time 0.89 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206076 kb
Host smart-eb354b2a-7fef-4131-9169-0a16934f6bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041
77187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3704177187
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1477131780
Short name T1355
Test name
Test status
Simulation time 178211106 ps
CPU time 0.88 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 205996 kb
Host smart-a4702622-c74f-4cf2-9f92-69c2b4316f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
31780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1477131780
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.4284283153
Short name T2065
Test name
Test status
Simulation time 178730529 ps
CPU time 0.87 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206096 kb
Host smart-bc73ff2a-2bbf-4624-aea1-11617ff70e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42842
83153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.4284283153
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.47386084
Short name T1621
Test name
Test status
Simulation time 176009582 ps
CPU time 0.85 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 205764 kb
Host smart-0940ede5-61ed-4595-9d5f-4b2457acba04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47386
084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.47386084
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1376710248
Short name T1262
Test name
Test status
Simulation time 153809908 ps
CPU time 0.82 seconds
Started Jul 09 05:16:25 PM PDT 24
Finished Jul 09 05:16:27 PM PDT 24
Peak memory 206020 kb
Host smart-21bb2d25-a321-4c55-ac5e-2388c2603bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13767
10248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1376710248
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1605650500
Short name T1576
Test name
Test status
Simulation time 168765458 ps
CPU time 0.76 seconds
Started Jul 09 05:16:22 PM PDT 24
Finished Jul 09 05:16:24 PM PDT 24
Peak memory 206132 kb
Host smart-ec3636ba-e70d-4a19-b6d2-60f4eedc449d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16056
50500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1605650500
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.4068520235
Short name T2536
Test name
Test status
Simulation time 214766212 ps
CPU time 0.93 seconds
Started Jul 09 05:16:26 PM PDT 24
Finished Jul 09 05:16:27 PM PDT 24
Peak memory 206064 kb
Host smart-041d1b07-006a-4db2-b040-4b16ac33ae61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
20235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.4068520235
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1663719604
Short name T1184
Test name
Test status
Simulation time 4830029414 ps
CPU time 36.32 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206192 kb
Host smart-a8694e17-e01e-4fbb-a880-fbf160a55a2c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1663719604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1663719604
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1655442562
Short name T670
Test name
Test status
Simulation time 171884344 ps
CPU time 0.8 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206132 kb
Host smart-6ae5b3b6-4055-4d0e-999a-d09b94e686d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16554
42562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1655442562
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3049673238
Short name T1182
Test name
Test status
Simulation time 166379382 ps
CPU time 0.78 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 206140 kb
Host smart-82e6e511-34ff-4e27-908f-1a80193657d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30496
73238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3049673238
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.4198808675
Short name T1538
Test name
Test status
Simulation time 820609735 ps
CPU time 1.94 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206252 kb
Host smart-c3105ec4-83ef-4f21-abf8-c9c15cb300f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41988
08675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.4198808675
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.4198713374
Short name T2361
Test name
Test status
Simulation time 4906367566 ps
CPU time 34.78 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206244 kb
Host smart-0b15f673-a8e1-441c-821d-2c48c3993105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
13374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.4198713374
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3257786908
Short name T1318
Test name
Test status
Simulation time 46042454 ps
CPU time 0.72 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:34 PM PDT 24
Peak memory 206096 kb
Host smart-18ed489c-62c8-4e82-99a2-8481e92cc863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3257786908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3257786908
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1529089875
Short name T1236
Test name
Test status
Simulation time 4309423184 ps
CPU time 4.79 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 206432 kb
Host smart-a326c5a6-121c-473f-94f9-547741d2ece0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1529089875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1529089875
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.4018504945
Short name T1208
Test name
Test status
Simulation time 13443113316 ps
CPU time 13.52 seconds
Started Jul 09 05:16:25 PM PDT 24
Finished Jul 09 05:16:40 PM PDT 24
Peak memory 206000 kb
Host smart-f6d7c832-3327-42e3-9fe0-e09bcd34f181
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4018504945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.4018504945
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1019469480
Short name T2564
Test name
Test status
Simulation time 23394525225 ps
CPU time 25.04 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:59 PM PDT 24
Peak memory 206376 kb
Host smart-e3321ccc-3b83-4609-a53e-9c20e3eeb0bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1019469480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.1019469480
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1293029551
Short name T1814
Test name
Test status
Simulation time 147389960 ps
CPU time 0.85 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:30 PM PDT 24
Peak memory 206160 kb
Host smart-cefdfb91-2351-4482-b6c9-b773ad6efbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
29551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1293029551
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1897803922
Short name T1689
Test name
Test status
Simulation time 179541500 ps
CPU time 0.82 seconds
Started Jul 09 05:16:42 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206056 kb
Host smart-07972d1b-49cf-4ded-b8a0-d1bb95bfcfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18978
03922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1897803922
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.1600461864
Short name T169
Test name
Test status
Simulation time 442363155 ps
CPU time 1.51 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206052 kb
Host smart-8ff70a74-4cab-4ed4-b202-46a2532762f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16004
61864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.1600461864
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1394301
Short name T819
Test name
Test status
Simulation time 995777973 ps
CPU time 2.26 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206316 kb
Host smart-e4ba0f6f-2d07-480e-badc-e2e4b75b0eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13943
01 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1394301
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3844645882
Short name T1929
Test name
Test status
Simulation time 8285256336 ps
CPU time 16.45 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206404 kb
Host smart-0b6b208e-1007-4b83-b46a-c89e3a4f8379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38446
45882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3844645882
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2786118866
Short name T993
Test name
Test status
Simulation time 440876907 ps
CPU time 1.43 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206096 kb
Host smart-c38d667a-fd26-4601-b2d3-603f676b2a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27861
18866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2786118866
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3508366020
Short name T1945
Test name
Test status
Simulation time 144114532 ps
CPU time 0.77 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 205848 kb
Host smart-43f4b75f-3f74-4e2b-8523-c8b091d346a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35083
66020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3508366020
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3570357919
Short name T314
Test name
Test status
Simulation time 34761115 ps
CPU time 0.66 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206132 kb
Host smart-1fbc389a-e628-4af6-94d8-e73cf97d2918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
57919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3570357919
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3558336688
Short name T1972
Test name
Test status
Simulation time 778611973 ps
CPU time 1.98 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206308 kb
Host smart-fc478e6b-ec99-426b-ae84-1c5f5816bce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583
36688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3558336688
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2697114748
Short name T1900
Test name
Test status
Simulation time 286666580 ps
CPU time 1.97 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206068 kb
Host smart-a5fbbedc-decf-48a5-9e85-fb1a78f301f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26971
14748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2697114748
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2799036871
Short name T2292
Test name
Test status
Simulation time 234925329 ps
CPU time 0.94 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 205992 kb
Host smart-e56f56e9-8b9a-4018-8ff5-57810741bf4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27990
36871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2799036871
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1144267024
Short name T2392
Test name
Test status
Simulation time 145064926 ps
CPU time 0.74 seconds
Started Jul 09 05:19:40 PM PDT 24
Finished Jul 09 05:19:42 PM PDT 24
Peak memory 206048 kb
Host smart-63097831-f57a-4aa8-aee3-490a0382e379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11442
67024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1144267024
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3078408199
Short name T917
Test name
Test status
Simulation time 210640196 ps
CPU time 0.91 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206112 kb
Host smart-29b8bb91-69a3-4fa3-bf77-8d041c004e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30784
08199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3078408199
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.3278472917
Short name T1674
Test name
Test status
Simulation time 8786758236 ps
CPU time 249.77 seconds
Started Jul 09 05:16:25 PM PDT 24
Finished Jul 09 05:20:36 PM PDT 24
Peak memory 206416 kb
Host smart-6f3a8d39-92b4-42e6-8783-a71fd3cdca8c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3278472917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.3278472917
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2972585461
Short name T1424
Test name
Test status
Simulation time 163274403 ps
CPU time 0.77 seconds
Started Jul 09 05:16:26 PM PDT 24
Finished Jul 09 05:16:28 PM PDT 24
Peak memory 205960 kb
Host smart-50fb5d04-9730-40de-9d99-49e2b5bf4cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29725
85461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2972585461
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1198155676
Short name T1766
Test name
Test status
Simulation time 23279093185 ps
CPU time 23.83 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:52 PM PDT 24
Peak memory 206436 kb
Host smart-12b36065-499e-4be5-acc9-8f40ffd666a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11981
55676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1198155676
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1426250052
Short name T2576
Test name
Test status
Simulation time 3304437394 ps
CPU time 4.03 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206024 kb
Host smart-92f92d7c-4bcd-4420-8ae5-6e2894ca80a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
50052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1426250052
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3585561304
Short name T2150
Test name
Test status
Simulation time 11177531774 ps
CPU time 108.73 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206328 kb
Host smart-3f8f5830-6d37-4736-ad90-86ce481bf8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855
61304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3585561304
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.574375253
Short name T869
Test name
Test status
Simulation time 5272055598 ps
CPU time 49.05 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206096 kb
Host smart-eb914cb5-8530-423c-a72f-445316cc3570
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=574375253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.574375253
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2217850673
Short name T973
Test name
Test status
Simulation time 238774916 ps
CPU time 0.96 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206144 kb
Host smart-d6851db2-85ff-4c36-a068-ea0f4a3c63df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2217850673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2217850673
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.587874043
Short name T2543
Test name
Test status
Simulation time 195187290 ps
CPU time 0.85 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:16:37 PM PDT 24
Peak memory 206132 kb
Host smart-bcaadbc0-8bb0-47ae-9163-1825ff35e854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58787
4043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.587874043
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3306594845
Short name T404
Test name
Test status
Simulation time 5961392244 ps
CPU time 164.19 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:19:14 PM PDT 24
Peak memory 206476 kb
Host smart-b28850b7-8658-4e56-bd82-fba3863cf8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33065
94845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3306594845
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3991883209
Short name T706
Test name
Test status
Simulation time 5268762253 ps
CPU time 40 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206316 kb
Host smart-9d99251d-3c03-45dd-8d60-7fc5d4e0f332
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3991883209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3991883209
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.891520758
Short name T2335
Test name
Test status
Simulation time 157253340 ps
CPU time 0.84 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:38 PM PDT 24
Peak memory 206144 kb
Host smart-dccc381b-cd55-4f11-b176-8621c31c2545
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=891520758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.891520758
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2693346939
Short name T1547
Test name
Test status
Simulation time 172551803 ps
CPU time 0.82 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206164 kb
Host smart-1689ad55-ab26-4f23-be83-bbf2b34b05c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
46939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2693346939
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.253093527
Short name T1949
Test name
Test status
Simulation time 180805560 ps
CPU time 0.86 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 205988 kb
Host smart-08af5c9a-8b23-4fb2-9f82-e1d7e54d6d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309
3527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.253093527
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2837962336
Short name T312
Test name
Test status
Simulation time 164646263 ps
CPU time 0.83 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206128 kb
Host smart-259cd687-7ecf-4657-a045-4bf191ede886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28379
62336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2837962336
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.4268447763
Short name T2603
Test name
Test status
Simulation time 194252627 ps
CPU time 0.86 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:28 PM PDT 24
Peak memory 206112 kb
Host smart-f06628c1-75d0-4808-9773-65bfe970605f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42684
47763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.4268447763
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3442022857
Short name T873
Test name
Test status
Simulation time 173906392 ps
CPU time 0.83 seconds
Started Jul 09 05:16:28 PM PDT 24
Finished Jul 09 05:16:30 PM PDT 24
Peak memory 206164 kb
Host smart-6c119719-7eb1-40e9-a1cf-e700b00f9a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34420
22857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3442022857
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.432503183
Short name T432
Test name
Test status
Simulation time 217752552 ps
CPU time 0.98 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206108 kb
Host smart-e6c73b78-c21f-4a2b-aa9e-298e8935c6e3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=432503183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.432503183
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3466163989
Short name T2139
Test name
Test status
Simulation time 141128125 ps
CPU time 0.76 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206112 kb
Host smart-e292871f-bca2-4d85-898b-eef9deb25d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34661
63989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3466163989
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3119635087
Short name T2141
Test name
Test status
Simulation time 40852503 ps
CPU time 0.67 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206124 kb
Host smart-c29ca584-e847-4339-8240-2c2d3736a97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196
35087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3119635087
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4033445300
Short name T2665
Test name
Test status
Simulation time 10121332550 ps
CPU time 22.8 seconds
Started Jul 09 05:16:25 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206484 kb
Host smart-92fe2f42-8933-467c-a17e-4c455c73e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
45300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4033445300
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1772930476
Short name T2514
Test name
Test status
Simulation time 162552159 ps
CPU time 0.86 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:29 PM PDT 24
Peak memory 206156 kb
Host smart-baea90ec-c02e-4b95-b03c-291dc5d9c676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17729
30476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1772930476
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1921496692
Short name T345
Test name
Test status
Simulation time 235107641 ps
CPU time 0.9 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 206116 kb
Host smart-45ece654-08c3-4da8-8a80-6b2df3cde12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
96692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1921496692
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2814092080
Short name T998
Test name
Test status
Simulation time 220863629 ps
CPU time 0.88 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:38 PM PDT 24
Peak memory 206164 kb
Host smart-9d579864-90a3-48d0-a850-52cee5f8046b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
92080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2814092080
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3690418727
Short name T326
Test name
Test status
Simulation time 183116701 ps
CPU time 0.87 seconds
Started Jul 09 05:16:27 PM PDT 24
Finished Jul 09 05:16:29 PM PDT 24
Peak memory 206380 kb
Host smart-fd1f624f-5288-439d-b59c-6a4c76208b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904
18727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3690418727
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.113880041
Short name T412
Test name
Test status
Simulation time 155620393 ps
CPU time 0.81 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206116 kb
Host smart-c1161052-ec98-4cce-bee3-bcce931e9fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11388
0041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.113880041
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3184393206
Short name T109
Test name
Test status
Simulation time 152333833 ps
CPU time 0.79 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:33 PM PDT 24
Peak memory 206156 kb
Host smart-ad121906-31ef-46e2-806a-8a22d200a609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31843
93206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3184393206
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1489844304
Short name T1001
Test name
Test status
Simulation time 170512818 ps
CPU time 0.81 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206112 kb
Host smart-da29a9b2-beee-4eb2-af37-a23cdcf66f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14898
44304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1489844304
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2868723100
Short name T949
Test name
Test status
Simulation time 268038002 ps
CPU time 0.97 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 205992 kb
Host smart-1f164acb-5d88-4443-8d56-64b49401e0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687
23100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2868723100
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.1671507208
Short name T507
Test name
Test status
Simulation time 4584086289 ps
CPU time 130.06 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 206404 kb
Host smart-4483bc8a-4197-44b5-a6a8-6966ce12631e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1671507208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.1671507208
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.360876183
Short name T1765
Test name
Test status
Simulation time 184520495 ps
CPU time 0.85 seconds
Started Jul 09 05:16:37 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206016 kb
Host smart-1f3dda4d-51e3-4804-82c1-6452080033f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36087
6183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.360876183
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2430677105
Short name T384
Test name
Test status
Simulation time 178114394 ps
CPU time 0.88 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 206056 kb
Host smart-48e13598-f917-430a-9efe-6a062ede28ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24306
77105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2430677105
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2032852935
Short name T1085
Test name
Test status
Simulation time 1360597282 ps
CPU time 2.76 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206380 kb
Host smart-bd618303-694a-45a7-99d8-8c40fc0289c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20328
52935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2032852935
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3954833053
Short name T2620
Test name
Test status
Simulation time 4493875331 ps
CPU time 30.74 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:17:04 PM PDT 24
Peak memory 206408 kb
Host smart-2faea6d0-b7d8-495f-909f-5758dd5e1752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548
33053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3954833053
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3880233325
Short name T1002
Test name
Test status
Simulation time 39863696 ps
CPU time 0.67 seconds
Started Jul 09 05:12:15 PM PDT 24
Finished Jul 09 05:12:17 PM PDT 24
Peak memory 205984 kb
Host smart-b9aaa77e-3937-4cd3-aed6-fc1771c0e1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3880233325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3880233325
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1006569256
Short name T1385
Test name
Test status
Simulation time 3903084315 ps
CPU time 4.76 seconds
Started Jul 09 05:12:00 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206036 kb
Host smart-fb7cdc1f-630e-43c2-9e2a-81b5fa51d6d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1006569256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1006569256
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3349664943
Short name T1837
Test name
Test status
Simulation time 13358304104 ps
CPU time 13.04 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:15 PM PDT 24
Peak memory 206352 kb
Host smart-c21f1f18-df54-4d2a-b9b9-8eb50730c548
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3349664943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3349664943
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.667464599
Short name T895
Test name
Test status
Simulation time 23330410121 ps
CPU time 24.72 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206156 kb
Host smart-6af38e6d-dfa8-4e9f-9d88-7a1d394a108b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=667464599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.667464599
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.864679059
Short name T1767
Test name
Test status
Simulation time 194035378 ps
CPU time 0.86 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:04 PM PDT 24
Peak memory 206108 kb
Host smart-42a7fae9-fc65-4509-8ba6-6b5f3448dd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86467
9059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.864679059
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.763175024
Short name T85
Test name
Test status
Simulation time 126264399 ps
CPU time 0.8 seconds
Started Jul 09 05:11:58 PM PDT 24
Finished Jul 09 05:12:00 PM PDT 24
Peak memory 206152 kb
Host smart-2e2fca8a-8d3f-4941-8ebb-a596e290c469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76317
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.763175024
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2411346989
Short name T1317
Test name
Test status
Simulation time 159339001 ps
CPU time 0.76 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 206104 kb
Host smart-549d21c6-741f-4f88-b1fc-ab25e22ea287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24113
46989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2411346989
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2798706903
Short name T1464
Test name
Test status
Simulation time 327338465 ps
CPU time 1.06 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:07 PM PDT 24
Peak memory 206148 kb
Host smart-24beb7d8-c3f5-43c8-b421-fa87905264bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27987
06903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2798706903
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.365822391
Short name T1618
Test name
Test status
Simulation time 425183415 ps
CPU time 1.23 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:12:08 PM PDT 24
Peak memory 206164 kb
Host smart-45da143d-a9b8-4280-bc0d-b65d137e599d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36582
2391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.365822391
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.4056009359
Short name T2664
Test name
Test status
Simulation time 5956670684 ps
CPU time 11.06 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:16 PM PDT 24
Peak memory 206476 kb
Host smart-ae876ecc-7f07-461c-9609-c97bea8a029e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
09359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.4056009359
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.810865796
Short name T1812
Test name
Test status
Simulation time 476903999 ps
CPU time 1.41 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:12:08 PM PDT 24
Peak memory 206124 kb
Host smart-8bc51f61-3f9b-47d6-8a1c-e8b71dddbab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81086
5796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.810865796
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.3858534741
Short name T344
Test name
Test status
Simulation time 201257557 ps
CPU time 0.88 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206096 kb
Host smart-3a34cdff-eb85-4a12-882d-4a8c71e7a5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
34741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3858534741
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1066614357
Short name T240
Test name
Test status
Simulation time 57935494 ps
CPU time 0.68 seconds
Started Jul 09 05:12:06 PM PDT 24
Finished Jul 09 05:12:08 PM PDT 24
Peak memory 206008 kb
Host smart-006a66e1-6c35-426d-92e3-452910fbcc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10666
14357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1066614357
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3965426989
Short name T2236
Test name
Test status
Simulation time 855320561 ps
CPU time 1.98 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:12:08 PM PDT 24
Peak memory 206380 kb
Host smart-0f5d4655-f57c-4c5f-8d1a-a960cd29c597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39654
26989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3965426989
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3946450657
Short name T866
Test name
Test status
Simulation time 177758403 ps
CPU time 2.12 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206336 kb
Host smart-e9a926fd-3b5c-46e7-9812-047ff91e2dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39464
50657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3946450657
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.4032694210
Short name T920
Test name
Test status
Simulation time 101189851808 ps
CPU time 144.94 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:14:32 PM PDT 24
Peak memory 206384 kb
Host smart-1f6f8069-dc79-4a28-8d44-1c56a5ee2a86
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4032694210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.4032694210
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1670615500
Short name T925
Test name
Test status
Simulation time 116435041096 ps
CPU time 163.41 seconds
Started Jul 09 05:12:06 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 206380 kb
Host smart-958fdd3b-671c-4ecf-b42b-df03e73fe3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670615500 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1670615500
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.159306010
Short name T580
Test name
Test status
Simulation time 99154889738 ps
CPU time 162.9 seconds
Started Jul 09 05:12:06 PM PDT 24
Finished Jul 09 05:14:50 PM PDT 24
Peak memory 206252 kb
Host smart-98922a68-17a9-403c-a084-749a7bb2c9e1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=159306010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.159306010
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1201557913
Short name T2593
Test name
Test status
Simulation time 121319145855 ps
CPU time 160.42 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:14:45 PM PDT 24
Peak memory 206372 kb
Host smart-de882288-3496-4f6e-a328-ce987dbb824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201557913 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1201557913
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.1694652376
Short name T1026
Test name
Test status
Simulation time 106167982460 ps
CPU time 181.68 seconds
Started Jul 09 05:12:01 PM PDT 24
Finished Jul 09 05:15:03 PM PDT 24
Peak memory 206288 kb
Host smart-295c55d3-0065-45c8-80b1-745dbfbea1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
52376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.1694652376
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.7903584
Short name T2520
Test name
Test status
Simulation time 209692525 ps
CPU time 0.88 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:05 PM PDT 24
Peak memory 206084 kb
Host smart-2a9db7c7-58a8-4e4c-8429-9acaaf707a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79035
84 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.7903584
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.271644724
Short name T636
Test name
Test status
Simulation time 149360614 ps
CPU time 0.85 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:12:07 PM PDT 24
Peak memory 206116 kb
Host smart-e2cd433a-423b-4807-a4c4-aa161e69ac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27164
4724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.271644724
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.4179084363
Short name T2509
Test name
Test status
Simulation time 232210161 ps
CPU time 0.98 seconds
Started Jul 09 05:12:02 PM PDT 24
Finished Jul 09 05:12:05 PM PDT 24
Peak memory 206080 kb
Host smart-f9369000-8ae0-4403-8b49-f81d9186e186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41790
84363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.4179084363
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1378380546
Short name T1218
Test name
Test status
Simulation time 236047098 ps
CPU time 0.89 seconds
Started Jul 09 05:12:06 PM PDT 24
Finished Jul 09 05:12:08 PM PDT 24
Peak memory 206116 kb
Host smart-9590a14d-b414-432d-ba2c-3486ab9b04c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13783
80546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1378380546
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1039132388
Short name T2190
Test name
Test status
Simulation time 23317088657 ps
CPU time 23.57 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:29 PM PDT 24
Peak memory 206220 kb
Host smart-10d9356e-8fa6-4c8c-b69c-78b4b2aadb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391
32388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1039132388
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2730773793
Short name T1170
Test name
Test status
Simulation time 3335518643 ps
CPU time 3.59 seconds
Started Jul 09 05:12:06 PM PDT 24
Finished Jul 09 05:12:11 PM PDT 24
Peak memory 206196 kb
Host smart-7e824713-4cb8-405b-a0c3-122a77ef183e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
73793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2730773793
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2415395669
Short name T1110
Test name
Test status
Simulation time 13696542562 ps
CPU time 98.79 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:13:45 PM PDT 24
Peak memory 206448 kb
Host smart-42261c81-9c9d-4245-b72f-b1c5211a4252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24153
95669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2415395669
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1265453138
Short name T1681
Test name
Test status
Simulation time 5536976562 ps
CPU time 49.01 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:54 PM PDT 24
Peak memory 206244 kb
Host smart-3e28f9c6-9fee-4032-b0f2-2cba920ff5ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1265453138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1265453138
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3797444255
Short name T649
Test name
Test status
Simulation time 240829183 ps
CPU time 0.87 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206088 kb
Host smart-0468953e-b86d-4211-a29f-632f3c8f380a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3797444255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3797444255
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2448093893
Short name T2353
Test name
Test status
Simulation time 244290048 ps
CPU time 0.96 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:07 PM PDT 24
Peak memory 206152 kb
Host smart-7c7387e6-40c2-42e6-a33b-3e3eb8c3d05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24480
93893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2448093893
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3094517647
Short name T501
Test name
Test status
Simulation time 3919519842 ps
CPU time 30.02 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206352 kb
Host smart-73151d0b-83ed-498d-9e5c-1ef072291fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30945
17647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3094517647
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.4275330043
Short name T372
Test name
Test status
Simulation time 6265985978 ps
CPU time 175.72 seconds
Started Jul 09 05:12:03 PM PDT 24
Finished Jul 09 05:15:00 PM PDT 24
Peak memory 206328 kb
Host smart-89021c9f-687b-4a95-bbc8-4764c9d2b2b5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4275330043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.4275330043
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3547252461
Short name T522
Test name
Test status
Simulation time 154721268 ps
CPU time 0.78 seconds
Started Jul 09 05:12:04 PM PDT 24
Finished Jul 09 05:12:06 PM PDT 24
Peak memory 206004 kb
Host smart-5aa2ef9f-a97d-4d09-a983-6d8758c9d807
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3547252461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3547252461
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3117921820
Short name T969
Test name
Test status
Simulation time 146407624 ps
CPU time 0.87 seconds
Started Jul 09 05:12:11 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 206164 kb
Host smart-f302a8a5-3097-43a7-926f-e58d3e2531de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31179
21820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3117921820
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1649650764
Short name T120
Test name
Test status
Simulation time 193629474 ps
CPU time 0.92 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:10 PM PDT 24
Peak memory 205956 kb
Host smart-ec188850-6078-4f94-887b-2d82ca3404d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16496
50764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1649650764
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.813054254
Short name T1646
Test name
Test status
Simulation time 185107494 ps
CPU time 0.84 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206152 kb
Host smart-b4f7c940-ddb2-4e3b-a6dc-bc5b024d677f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81305
4254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.813054254
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2751325579
Short name T1445
Test name
Test status
Simulation time 211734282 ps
CPU time 0.85 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 205956 kb
Host smart-20dc1ac2-5832-4a6f-9f35-d98b4d443f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
25579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2751325579
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.170859086
Short name T1432
Test name
Test status
Simulation time 208462479 ps
CPU time 0.88 seconds
Started Jul 09 05:12:07 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206052 kb
Host smart-8cc190e6-bcdb-403f-857b-0b62cc7268c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17085
9086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.170859086
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2754395402
Short name T1071
Test name
Test status
Simulation time 181786067 ps
CPU time 0.82 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206116 kb
Host smart-19574cfe-321e-4098-bebd-6a497182df30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27543
95402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2754395402
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.113517784
Short name T2445
Test name
Test status
Simulation time 233623788 ps
CPU time 0.99 seconds
Started Jul 09 05:12:07 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206068 kb
Host smart-f445e412-9937-4490-802e-647d9b704865
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=113517784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.113517784
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.4120182277
Short name T1645
Test name
Test status
Simulation time 204119747 ps
CPU time 0.89 seconds
Started Jul 09 05:12:07 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206068 kb
Host smart-0bba7b38-59d2-4c9f-884e-baeb326b0d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41201
82277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.4120182277
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1852155182
Short name T812
Test name
Test status
Simulation time 155606764 ps
CPU time 0.79 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:12:11 PM PDT 24
Peak memory 206120 kb
Host smart-e9425241-6145-4492-9589-612296abe920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18521
55182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1852155182
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.4021018098
Short name T39
Test name
Test status
Simulation time 41230011 ps
CPU time 0.66 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:10 PM PDT 24
Peak memory 206060 kb
Host smart-4ff08c06-31a5-4fe4-b28d-e0708a69b6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
18098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.4021018098
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2600475424
Short name T276
Test name
Test status
Simulation time 17259405290 ps
CPU time 37.72 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206364 kb
Host smart-717f6310-acb8-4984-a4a4-41260e83d66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26004
75424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2600475424
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.852377659
Short name T921
Test name
Test status
Simulation time 186413263 ps
CPU time 0.87 seconds
Started Jul 09 05:12:05 PM PDT 24
Finished Jul 09 05:12:07 PM PDT 24
Peak memory 206016 kb
Host smart-91d6b9c4-c409-4431-8ec7-c85e2b6dd549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85237
7659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.852377659
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1463454446
Short name T1422
Test name
Test status
Simulation time 187104886 ps
CPU time 0.9 seconds
Started Jul 09 05:12:10 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 205960 kb
Host smart-6bcb7b0a-b717-4621-8ba6-1474332d0bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14634
54446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1463454446
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2463402192
Short name T2365
Test name
Test status
Simulation time 14041268419 ps
CPU time 87.7 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206448 kb
Host smart-8a176c0d-bac6-4d47-8a6c-a963b13a4a59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2463402192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2463402192
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.4127052575
Short name T2203
Test name
Test status
Simulation time 4237183721 ps
CPU time 113.86 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:14:03 PM PDT 24
Peak memory 206456 kb
Host smart-b13bfed8-e8f6-4611-a5dc-adbbd052423e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4127052575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.4127052575
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.1893734391
Short name T1200
Test name
Test status
Simulation time 8147251991 ps
CPU time 34.04 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206380 kb
Host smart-ccb85e1d-951e-4ac7-9bc2-6bceb39feea3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1893734391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1893734391
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2003580960
Short name T1480
Test name
Test status
Simulation time 208494093 ps
CPU time 0.86 seconds
Started Jul 09 05:12:10 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 205964 kb
Host smart-22a2259d-c25e-4d5b-9556-d710a0aae47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20035
80960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2003580960
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3282002596
Short name T1404
Test name
Test status
Simulation time 173226300 ps
CPU time 0.88 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 206124 kb
Host smart-a03d8c60-8a8c-4a7e-b24b-343c0acfab99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
02596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3282002596
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2236706632
Short name T964
Test name
Test status
Simulation time 192239668 ps
CPU time 0.85 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:10 PM PDT 24
Peak memory 206124 kb
Host smart-6dee9fdb-a437-469d-8ba6-00b9b79d7f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22367
06632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2236706632
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.4215708330
Short name T2600
Test name
Test status
Simulation time 179199530 ps
CPU time 0.86 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:12:11 PM PDT 24
Peak memory 206060 kb
Host smart-fd9ac95a-c479-46dd-9b2a-f4a7300fc07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42157
08330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.4215708330
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3594462000
Short name T207
Test name
Test status
Simulation time 263240295 ps
CPU time 1.07 seconds
Started Jul 09 05:12:13 PM PDT 24
Finished Jul 09 05:12:14 PM PDT 24
Peak memory 223952 kb
Host smart-75819e1b-82e2-431e-8cc9-300cc14ec2ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3594462000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3594462000
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.105054672
Short name T52
Test name
Test status
Simulation time 452176025 ps
CPU time 1.36 seconds
Started Jul 09 05:12:07 PM PDT 24
Finished Jul 09 05:12:09 PM PDT 24
Peak memory 206088 kb
Host smart-f9a68efd-45f5-42a5-ae00-3433f0c559bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505
4672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.105054672
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3885189921
Short name T707
Test name
Test status
Simulation time 218294534 ps
CPU time 0.93 seconds
Started Jul 09 05:12:11 PM PDT 24
Finished Jul 09 05:12:13 PM PDT 24
Peak memory 206068 kb
Host smart-0c5bfcf1-005c-40a3-bb0b-65fb1791c003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38851
89921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3885189921
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1305410132
Short name T681
Test name
Test status
Simulation time 158264928 ps
CPU time 0.84 seconds
Started Jul 09 05:12:08 PM PDT 24
Finished Jul 09 05:12:10 PM PDT 24
Peak memory 206124 kb
Host smart-d7662960-c88b-4112-9aca-fe47753d7a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13054
10132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1305410132
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.187268302
Short name T2628
Test name
Test status
Simulation time 157938761 ps
CPU time 0.8 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:12:10 PM PDT 24
Peak memory 206132 kb
Host smart-ad1ff0e6-7213-405b-9054-86b633b3af31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
8302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.187268302
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1042579178
Short name T33
Test name
Test status
Simulation time 317028590 ps
CPU time 1.08 seconds
Started Jul 09 05:12:09 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 206160 kb
Host smart-36f44968-ae90-4180-bf5a-0cd8a0ab3edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10425
79178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1042579178
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2962908843
Short name T2001
Test name
Test status
Simulation time 4026852721 ps
CPU time 37.7 seconds
Started Jul 09 05:12:11 PM PDT 24
Finished Jul 09 05:12:49 PM PDT 24
Peak memory 206392 kb
Host smart-6050afe7-462e-4279-ab15-dccfaff52fd7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2962908843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2962908843
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3008609215
Short name T2419
Test name
Test status
Simulation time 181620016 ps
CPU time 0.82 seconds
Started Jul 09 05:12:13 PM PDT 24
Finished Jul 09 05:12:15 PM PDT 24
Peak memory 206044 kb
Host smart-6812c7da-425b-4a7c-8c63-67a3a6bca80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30086
09215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3008609215
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.4108449788
Short name T1120
Test name
Test status
Simulation time 171789838 ps
CPU time 0.83 seconds
Started Jul 09 05:12:10 PM PDT 24
Finished Jul 09 05:12:12 PM PDT 24
Peak memory 205988 kb
Host smart-f9092568-d01d-4806-800b-31aba76c8684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084
49788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.4108449788
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.24697682
Short name T1254
Test name
Test status
Simulation time 555924250 ps
CPU time 1.48 seconds
Started Jul 09 05:12:15 PM PDT 24
Finished Jul 09 05:12:17 PM PDT 24
Peak memory 206064 kb
Host smart-551d25c6-cdc7-4f49-8c63-83aece8cb956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24697
682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.24697682
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2856610756
Short name T855
Test name
Test status
Simulation time 7158378544 ps
CPU time 189.31 seconds
Started Jul 09 05:12:13 PM PDT 24
Finished Jul 09 05:15:23 PM PDT 24
Peak memory 206272 kb
Host smart-04b40648-6904-45b3-b451-d6015ab75976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
10756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2856610756
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2327773680
Short name T2113
Test name
Test status
Simulation time 27120054890 ps
CPU time 674.92 seconds
Started Jul 09 05:12:14 PM PDT 24
Finished Jul 09 05:23:30 PM PDT 24
Peak memory 206448 kb
Host smart-579d342b-d08e-415b-9c8c-440294fc6962
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2327773680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2327773680
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.1569885543
Short name T1640
Test name
Test status
Simulation time 26892686 ps
CPU time 0.63 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 206132 kb
Host smart-306c5769-4ce7-42ff-85db-b306e6217f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1569885543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1569885543
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2187952411
Short name T2020
Test name
Test status
Simulation time 4013193778 ps
CPU time 5.03 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206440 kb
Host smart-35b412b2-0788-40b5-bacc-133033a25a39
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2187952411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2187952411
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.4239980657
Short name T2465
Test name
Test status
Simulation time 13454956907 ps
CPU time 14.2 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206356 kb
Host smart-257bef72-7e61-409d-b0d9-fae47f59933a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4239980657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.4239980657
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1310207220
Short name T14
Test name
Test status
Simulation time 23353666300 ps
CPU time 22.57 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206392 kb
Host smart-e2abef5c-966a-451c-a01d-979814412c5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1310207220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1310207220
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2337456235
Short name T2091
Test name
Test status
Simulation time 184311263 ps
CPU time 0.81 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206156 kb
Host smart-fa5de49a-ba4a-4dc4-8829-ac1ca92d736d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374
56235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2337456235
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.993222035
Short name T1867
Test name
Test status
Simulation time 150583432 ps
CPU time 0.79 seconds
Started Jul 09 05:16:29 PM PDT 24
Finished Jul 09 05:16:32 PM PDT 24
Peak memory 205996 kb
Host smart-7d186fb1-cf00-4cbb-ad78-18188f7e8f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99322
2035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.993222035
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.2872363873
Short name T159
Test name
Test status
Simulation time 442504383 ps
CPU time 1.4 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:34 PM PDT 24
Peak memory 206004 kb
Host smart-6bf98f97-7998-47ab-a95d-756d40dca41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723
63873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.2872363873
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.423064451
Short name T174
Test name
Test status
Simulation time 851566353 ps
CPU time 1.99 seconds
Started Jul 09 05:16:49 PM PDT 24
Finished Jul 09 05:16:52 PM PDT 24
Peak memory 206276 kb
Host smart-620160bf-7c4a-454c-b5af-0a010acc2518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
4451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.423064451
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2804781723
Short name T1325
Test name
Test status
Simulation time 16837737367 ps
CPU time 35.33 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:17:07 PM PDT 24
Peak memory 206464 kb
Host smart-61491fe0-dc71-4a33-888d-16b5dd19d85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28047
81723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2804781723
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2568840506
Short name T1986
Test name
Test status
Simulation time 453634628 ps
CPU time 1.35 seconds
Started Jul 09 05:16:32 PM PDT 24
Finished Jul 09 05:16:36 PM PDT 24
Peak memory 206120 kb
Host smart-82f75bdf-efb6-4a82-b53b-a2ccdc1ba387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688
40506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2568840506
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.229776198
Short name T2423
Test name
Test status
Simulation time 155027936 ps
CPU time 0.76 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:16:40 PM PDT 24
Peak memory 206020 kb
Host smart-0ab558a6-6517-4e81-9b39-66b1e1464d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22977
6198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.229776198
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3986289590
Short name T503
Test name
Test status
Simulation time 36361757 ps
CPU time 0.68 seconds
Started Jul 09 05:16:40 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206068 kb
Host smart-f5dab912-1df6-46d9-bdff-e0709d3eee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39862
89590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3986289590
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2903888403
Short name T601
Test name
Test status
Simulation time 941782612 ps
CPU time 2.17 seconds
Started Jul 09 05:16:31 PM PDT 24
Finished Jul 09 05:16:35 PM PDT 24
Peak memory 206304 kb
Host smart-4e764d93-456b-4b20-b1e4-ad82b7c29d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29038
88403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2903888403
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3238150165
Short name T1857
Test name
Test status
Simulation time 310631855 ps
CPU time 1.94 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206204 kb
Host smart-bbe8f9f4-9b40-433f-a163-e057ac8b013a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32381
50165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3238150165
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3760412658
Short name T2459
Test name
Test status
Simulation time 217140329 ps
CPU time 0.93 seconds
Started Jul 09 05:16:37 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206012 kb
Host smart-ab6096ce-3af4-40b8-a5e7-2294784f6573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37604
12658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3760412658
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2449384829
Short name T732
Test name
Test status
Simulation time 138040526 ps
CPU time 0.82 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 205988 kb
Host smart-6d2ef904-7d0a-4400-b4a4-78f1ae00d2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24493
84829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2449384829
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1992036871
Short name T1386
Test name
Test status
Simulation time 249476362 ps
CPU time 0.94 seconds
Started Jul 09 05:16:37 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206024 kb
Host smart-71ef22c2-6674-4f3e-a2a5-90fd70106f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19920
36871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1992036871
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.624175605
Short name T892
Test name
Test status
Simulation time 6052176630 ps
CPU time 44.46 seconds
Started Jul 09 05:16:30 PM PDT 24
Finished Jul 09 05:17:16 PM PDT 24
Peak memory 206324 kb
Host smart-9e918415-d488-4164-bf32-a5e35df01c54
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=624175605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.624175605
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3382888759
Short name T1293
Test name
Test status
Simulation time 183566526 ps
CPU time 0.86 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206160 kb
Host smart-85c6cf53-e415-4947-988c-86c5ecbd50cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33828
88759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3382888759
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.4058071611
Short name T1249
Test name
Test status
Simulation time 23321535810 ps
CPU time 31.45 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:17:09 PM PDT 24
Peak memory 206088 kb
Host smart-b7a2b05c-e0ae-4a4f-9985-f81fb314ab3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40580
71611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.4058071611
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1503482436
Short name T528
Test name
Test status
Simulation time 3282489084 ps
CPU time 4.66 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206184 kb
Host smart-9d333032-019f-4de2-af38-838d61e47b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15034
82436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1503482436
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.552095146
Short name T2672
Test name
Test status
Simulation time 11645322303 ps
CPU time 85.44 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 206460 kb
Host smart-96c040cd-f0cb-4c14-82df-52fb7b05bb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55209
5146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.552095146
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1008560614
Short name T2675
Test name
Test status
Simulation time 7322234614 ps
CPU time 207.31 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:20:07 PM PDT 24
Peak memory 206296 kb
Host smart-d70b0260-8c70-4912-9c66-25b6519f0818
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1008560614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1008560614
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.509161787
Short name T1198
Test name
Test status
Simulation time 283843186 ps
CPU time 0.92 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206136 kb
Host smart-e0dff2ed-49d7-4716-a014-4bad9dc41a19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=509161787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.509161787
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3502384003
Short name T927
Test name
Test status
Simulation time 229682571 ps
CPU time 0.94 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:37 PM PDT 24
Peak memory 206112 kb
Host smart-ee419faa-8e64-4462-8d58-639d14209ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
84003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3502384003
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1802978516
Short name T1390
Test name
Test status
Simulation time 4926490403 ps
CPU time 139.43 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:18:58 PM PDT 24
Peak memory 206252 kb
Host smart-c1841a8b-dd4e-4d52-ac62-915dc7818e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18029
78516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1802978516
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2151004250
Short name T885
Test name
Test status
Simulation time 5380396870 ps
CPU time 37.64 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:17:13 PM PDT 24
Peak memory 206444 kb
Host smart-9fcfb678-4bbc-457d-a825-88bdf27c9eb9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2151004250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2151004250
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1007394745
Short name T1388
Test name
Test status
Simulation time 156959498 ps
CPU time 0.79 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206136 kb
Host smart-b8286cfe-a4dc-4d47-8b00-4cfd223ed6e0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1007394745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1007394745
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1731443166
Short name T2104
Test name
Test status
Simulation time 166031725 ps
CPU time 0.81 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206064 kb
Host smart-a02b1940-181b-4887-a08c-1e16fdaaad4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17314
43166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1731443166
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1344431874
Short name T1380
Test name
Test status
Simulation time 191161339 ps
CPU time 0.86 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206156 kb
Host smart-e4fd8f72-2ee7-4860-a0ba-be73b7c817b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13444
31874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1344431874
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3307989533
Short name T807
Test name
Test status
Simulation time 170912617 ps
CPU time 0.82 seconds
Started Jul 09 05:16:37 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206068 kb
Host smart-8b5d940c-e614-4d89-b084-298882af3b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33079
89533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3307989533
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1014052444
Short name T418
Test name
Test status
Simulation time 176153071 ps
CPU time 0.9 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:16:40 PM PDT 24
Peak memory 206144 kb
Host smart-972d625a-0585-4a08-bc63-25543ad6a6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10140
52444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1014052444
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3828210048
Short name T1395
Test name
Test status
Simulation time 146839763 ps
CPU time 0.79 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:42 PM PDT 24
Peak memory 206028 kb
Host smart-9167b147-66d2-4dc0-89ac-5f0c1eb7e006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38282
10048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3828210048
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2358470892
Short name T1619
Test name
Test status
Simulation time 239205304 ps
CPU time 0.95 seconds
Started Jul 09 05:16:50 PM PDT 24
Finished Jul 09 05:16:52 PM PDT 24
Peak memory 206024 kb
Host smart-4c94b9f5-14fc-4efa-88bf-e4cd4ecc4538
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2358470892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2358470892
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3730550222
Short name T1953
Test name
Test status
Simulation time 181429804 ps
CPU time 0.8 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206004 kb
Host smart-cfc555e4-d222-413a-9a9f-f2befbf5caae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
50222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3730550222
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1281994019
Short name T41
Test name
Test status
Simulation time 63419327 ps
CPU time 0.68 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:16:37 PM PDT 24
Peak memory 206120 kb
Host smart-a88a206b-706b-414c-8d53-164bd16dd6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12819
94019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1281994019
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.109735094
Short name T252
Test name
Test status
Simulation time 16469887726 ps
CPU time 39.58 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:17:21 PM PDT 24
Peak memory 214536 kb
Host smart-c16edab8-761f-4cbb-b3b8-ba0f03a7442a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973
5094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.109735094
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2485320699
Short name T1276
Test name
Test status
Simulation time 169350209 ps
CPU time 0.88 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:37 PM PDT 24
Peak memory 206372 kb
Host smart-d9539eb3-1bca-45b4-af27-d7088e602b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24853
20699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2485320699
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4106555887
Short name T2214
Test name
Test status
Simulation time 236869353 ps
CPU time 0.93 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206140 kb
Host smart-3c2c0a52-b1e7-410e-b01a-94228aa83553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41065
55887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4106555887
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3630253325
Short name T1149
Test name
Test status
Simulation time 241387386 ps
CPU time 0.93 seconds
Started Jul 09 05:16:33 PM PDT 24
Finished Jul 09 05:16:37 PM PDT 24
Peak memory 206060 kb
Host smart-1336cc27-9f72-4cca-b733-e51703517bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36302
53325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3630253325
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1858151034
Short name T1695
Test name
Test status
Simulation time 182119036 ps
CPU time 0.83 seconds
Started Jul 09 05:16:34 PM PDT 24
Finished Jul 09 05:16:38 PM PDT 24
Peak memory 206112 kb
Host smart-11d3730f-a0f0-4007-ac2f-19900f8f1549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18581
51034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1858151034
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.890220530
Short name T677
Test name
Test status
Simulation time 168627407 ps
CPU time 0.78 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206120 kb
Host smart-a2ced988-5e9d-4e53-a099-4fd2044f1f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89022
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.890220530
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1647619131
Short name T2681
Test name
Test status
Simulation time 146431421 ps
CPU time 0.76 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:42 PM PDT 24
Peak memory 205952 kb
Host smart-203a3b6b-0e1c-425d-9f22-b090aee9ff6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
19131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1647619131
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2262108148
Short name T1880
Test name
Test status
Simulation time 169090656 ps
CPU time 0.85 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:42 PM PDT 24
Peak memory 206120 kb
Host smart-2fac5105-7c5b-4508-9191-90347d02ec70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22621
08148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2262108148
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3149848672
Short name T337
Test name
Test status
Simulation time 224363097 ps
CPU time 1.03 seconds
Started Jul 09 05:16:49 PM PDT 24
Finished Jul 09 05:16:51 PM PDT 24
Peak memory 206156 kb
Host smart-c5a5d336-9a81-45ad-8dcd-5e29161d6183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
48672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3149848672
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.327452946
Short name T212
Test name
Test status
Simulation time 6160289428 ps
CPU time 42.66 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206424 kb
Host smart-c736642e-e24d-43de-a50f-142719ad8aab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=327452946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.327452946
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1748609510
Short name T1730
Test name
Test status
Simulation time 182782847 ps
CPU time 0.84 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:42 PM PDT 24
Peak memory 206164 kb
Host smart-beca66e7-75f4-4870-bbe7-cb5c33090dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
09510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1748609510
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3825138364
Short name T2555
Test name
Test status
Simulation time 177824588 ps
CPU time 0.86 seconds
Started Jul 09 05:16:37 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206128 kb
Host smart-12483bac-d050-41cb-8afb-71e823faa21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38251
38364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3825138364
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.853979944
Short name T471
Test name
Test status
Simulation time 201031362 ps
CPU time 0.88 seconds
Started Jul 09 05:16:35 PM PDT 24
Finished Jul 09 05:16:39 PM PDT 24
Peak memory 206132 kb
Host smart-36de48a0-f138-41f0-a685-94091634f251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85397
9944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.853979944
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2149777689
Short name T2602
Test name
Test status
Simulation time 6022058585 ps
CPU time 57.73 seconds
Started Jul 09 05:16:41 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206368 kb
Host smart-8a4acec2-8d9c-4fb0-ab76-5ebf593fc4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21497
77689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2149777689
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3310825686
Short name T2302
Test name
Test status
Simulation time 70281617 ps
CPU time 0.72 seconds
Started Jul 09 05:16:48 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206172 kb
Host smart-12a84281-9b7f-4a35-90d7-0cd852eacc19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3310825686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3310825686
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3678485476
Short name T1207
Test name
Test status
Simulation time 3534773393 ps
CPU time 4.25 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:46 PM PDT 24
Peak memory 206164 kb
Host smart-bbab0d3e-a578-46c9-bdd8-f5d97814ad94
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3678485476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3678485476
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1908197187
Short name T791
Test name
Test status
Simulation time 13356187239 ps
CPU time 13.72 seconds
Started Jul 09 05:16:39 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206200 kb
Host smart-d7e12688-ccea-445c-b072-bc614959b530
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1908197187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1908197187
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3295850023
Short name T1206
Test name
Test status
Simulation time 23406730941 ps
CPU time 26.66 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:17:06 PM PDT 24
Peak memory 206340 kb
Host smart-3e584695-3936-4a62-8081-bbb5079050ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3295850023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3295850023
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.445853254
Short name T494
Test name
Test status
Simulation time 171184120 ps
CPU time 0.81 seconds
Started Jul 09 05:16:36 PM PDT 24
Finished Jul 09 05:16:41 PM PDT 24
Peak memory 206056 kb
Host smart-e3a968c9-000c-40f3-b0e0-fa1c3d9d70a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44585
3254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.445853254
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2454385686
Short name T705
Test name
Test status
Simulation time 165940768 ps
CPU time 0.81 seconds
Started Jul 09 05:16:39 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206068 kb
Host smart-04a3efb0-b58f-42a9-9a42-98c32c3c4b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24543
85686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2454385686
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.235213113
Short name T1726
Test name
Test status
Simulation time 566290735 ps
CPU time 1.56 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206356 kb
Host smart-7fb87dfd-5ab0-44bf-ba55-a7a5ca4374f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521
3113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.235213113
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.4286606357
Short name T157
Test name
Test status
Simulation time 1203480765 ps
CPU time 2.58 seconds
Started Jul 09 05:16:41 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206332 kb
Host smart-6145dfb5-7cd3-41b1-b0d5-47930f721698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42866
06357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.4286606357
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.550707277
Short name T2415
Test name
Test status
Simulation time 20103642343 ps
CPU time 40.64 seconds
Started Jul 09 05:16:42 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206348 kb
Host smart-96b5203a-adce-430d-8f69-b7b43e3b001f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55070
7277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.550707277
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3836803125
Short name T749
Test name
Test status
Simulation time 332335458 ps
CPU time 1.23 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206160 kb
Host smart-2210b9bd-168e-4ad2-bd40-49bd50146404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
03125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3836803125
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3816370078
Short name T666
Test name
Test status
Simulation time 148090726 ps
CPU time 0.8 seconds
Started Jul 09 05:16:39 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206108 kb
Host smart-eca2aa72-f389-43ed-b133-37731ea48032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38163
70078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3816370078
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3014072147
Short name T440
Test name
Test status
Simulation time 38637769 ps
CPU time 0.68 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206156 kb
Host smart-fd31e6c1-b447-4c23-b8e3-eb21e2d28af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
72147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3014072147
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.444938198
Short name T447
Test name
Test status
Simulation time 910451180 ps
CPU time 2.26 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:44 PM PDT 24
Peak memory 206396 kb
Host smart-519a49ba-8241-4e99-99c8-305af9951476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44493
8198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.444938198
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.217124455
Short name T399
Test name
Test status
Simulation time 243353402 ps
CPU time 1.6 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206292 kb
Host smart-efcf6617-bfe5-4435-8308-55326aaa8105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21712
4455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.217124455
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3177327378
Short name T1204
Test name
Test status
Simulation time 175965583 ps
CPU time 0.84 seconds
Started Jul 09 05:16:42 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206080 kb
Host smart-9a90a9b6-550b-4d5b-9ccc-8e3441991c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
27378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3177327378
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.665773589
Short name T2167
Test name
Test status
Simulation time 140678444 ps
CPU time 0.75 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:46 PM PDT 24
Peak memory 206044 kb
Host smart-4a4fe1ac-c53c-4ae4-9cb3-68dc7691af37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66577
3589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.665773589
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4887878
Short name T2434
Test name
Test status
Simulation time 239347034 ps
CPU time 0.89 seconds
Started Jul 09 05:16:44 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206048 kb
Host smart-934320dd-fff9-464d-bf5d-9fe17dfd054d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48878
78 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4887878
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.683395092
Short name T59
Test name
Test status
Simulation time 163824492 ps
CPU time 0.77 seconds
Started Jul 09 05:16:42 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206080 kb
Host smart-0d2b4d39-29e1-4b8e-bd08-588fb78d14a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68339
5092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.683395092
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.657157046
Short name T1301
Test name
Test status
Simulation time 23292240866 ps
CPU time 22.9 seconds
Started Jul 09 05:16:38 PM PDT 24
Finished Jul 09 05:17:05 PM PDT 24
Peak memory 206212 kb
Host smart-c76ed178-a8e4-49e9-95be-fce46ea43821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65715
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.657157046
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2145055020
Short name T832
Test name
Test status
Simulation time 3342008570 ps
CPU time 4.06 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206120 kb
Host smart-179926c8-817b-463c-9964-f1f301fd0730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
55020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2145055020
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2578734226
Short name T1616
Test name
Test status
Simulation time 6568107059 ps
CPU time 61.33 seconds
Started Jul 09 05:16:37 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206336 kb
Host smart-42e18042-be07-4dbf-a389-5206bff64a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
34226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2578734226
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1346178532
Short name T599
Test name
Test status
Simulation time 4252485618 ps
CPU time 31.71 seconds
Started Jul 09 05:16:42 PM PDT 24
Finished Jul 09 05:17:16 PM PDT 24
Peak memory 206324 kb
Host smart-b9c5fd5b-17e1-44e1-af80-8aeb7e277c7f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1346178532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1346178532
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2098465625
Short name T2508
Test name
Test status
Simulation time 243087315 ps
CPU time 0.98 seconds
Started Jul 09 05:16:44 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206032 kb
Host smart-20897c22-e85e-4b93-b103-b87cefd7f9aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2098465625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2098465625
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2664530856
Short name T1876
Test name
Test status
Simulation time 191802152 ps
CPU time 0.95 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:46 PM PDT 24
Peak memory 206068 kb
Host smart-15fd83fa-bc8a-4745-a1d0-fcb285163119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645
30856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2664530856
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3293055879
Short name T401
Test name
Test status
Simulation time 3052632272 ps
CPU time 21.25 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206424 kb
Host smart-5741d16a-f35f-4d8b-abae-aa48432331cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32930
55879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3293055879
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1463598388
Short name T411
Test name
Test status
Simulation time 5382010897 ps
CPU time 38.39 seconds
Started Jul 09 05:16:44 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206332 kb
Host smart-b72e86ce-a7fe-47a9-8230-f112d2cbb1b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1463598388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1463598388
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3324110966
Short name T387
Test name
Test status
Simulation time 175983899 ps
CPU time 0.79 seconds
Started Jul 09 05:16:44 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206104 kb
Host smart-3e534eec-f1ad-4443-9f25-54fd02e8013e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3324110966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3324110966
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1517333441
Short name T1682
Test name
Test status
Simulation time 153019186 ps
CPU time 0.78 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206104 kb
Host smart-40891774-9d1e-48ba-9d71-808738fafc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15173
33441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1517333441
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1624994147
Short name T2618
Test name
Test status
Simulation time 203121136 ps
CPU time 0.94 seconds
Started Jul 09 05:16:41 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206088 kb
Host smart-cf159cba-e621-494c-b1a5-d6bdc1ac3bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
94147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1624994147
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.606696947
Short name T2198
Test name
Test status
Simulation time 178803557 ps
CPU time 0.87 seconds
Started Jul 09 05:16:44 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206048 kb
Host smart-bdf08114-ecf0-45ea-9bf4-2c1667e9a4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60669
6947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.606696947
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3353102563
Short name T317
Test name
Test status
Simulation time 145662214 ps
CPU time 0.76 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:46 PM PDT 24
Peak memory 206004 kb
Host smart-b79f419a-0c1c-4042-b367-277506ce6ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
02563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3353102563
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.733021745
Short name T574
Test name
Test status
Simulation time 190236087 ps
CPU time 0.87 seconds
Started Jul 09 05:16:42 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206028 kb
Host smart-50ca5a53-1716-4d8d-9c4e-e9eb0afccb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73302
1745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.733021745
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.4165558772
Short name T2133
Test name
Test status
Simulation time 152112061 ps
CPU time 0.85 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:46 PM PDT 24
Peak memory 206160 kb
Host smart-c5f1193c-c05f-4bc2-a2c1-c49a6b660eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655
58772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.4165558772
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1685463201
Short name T2339
Test name
Test status
Simulation time 295649267 ps
CPU time 1.05 seconds
Started Jul 09 05:16:50 PM PDT 24
Finished Jul 09 05:16:51 PM PDT 24
Peak memory 206124 kb
Host smart-883296bf-4a06-44ad-979f-247effb4c623
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1685463201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1685463201
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2809154152
Short name T1202
Test name
Test status
Simulation time 150438599 ps
CPU time 0.79 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:46 PM PDT 24
Peak memory 206140 kb
Host smart-96b481cc-76e4-4a35-bca5-6f05fedfc2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28091
54152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2809154152
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1099587740
Short name T2064
Test name
Test status
Simulation time 48076156 ps
CPU time 0.7 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206124 kb
Host smart-a9a9676f-5d8c-4215-9846-563b02a65b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10995
87740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1099587740
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3946836744
Short name T2470
Test name
Test status
Simulation time 22248270286 ps
CPU time 50 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206444 kb
Host smart-3bca5fb7-602f-472b-9269-c17edce82905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39468
36744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3946836744
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4049682665
Short name T651
Test name
Test status
Simulation time 157893682 ps
CPU time 0.78 seconds
Started Jul 09 05:16:41 PM PDT 24
Finished Jul 09 05:16:45 PM PDT 24
Peak memory 206064 kb
Host smart-80577405-367d-40aa-98bc-0f45be9cd0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40496
82665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4049682665
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.136836405
Short name T600
Test name
Test status
Simulation time 194380286 ps
CPU time 0.85 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206048 kb
Host smart-2b65eb18-2cb1-4314-a77a-8acc7e5f190e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13683
6405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.136836405
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1913942245
Short name T472
Test name
Test status
Simulation time 170055697 ps
CPU time 0.85 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206056 kb
Host smart-8bcea1b7-f2a6-401d-b08f-e6fece89721b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139
42245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1913942245
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2221960351
Short name T2241
Test name
Test status
Simulation time 179464599 ps
CPU time 0.86 seconds
Started Jul 09 05:16:43 PM PDT 24
Finished Jul 09 05:16:47 PM PDT 24
Peak memory 206112 kb
Host smart-8839d0ef-f41c-4de7-bd85-8d7b06c293a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22219
60351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2221960351
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2176822146
Short name T777
Test name
Test status
Simulation time 198905301 ps
CPU time 0.85 seconds
Started Jul 09 05:16:39 PM PDT 24
Finished Jul 09 05:16:43 PM PDT 24
Peak memory 206116 kb
Host smart-15d67e4a-8188-42e5-888c-875b1fe86604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
22146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2176822146
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3920390609
Short name T1238
Test name
Test status
Simulation time 157029278 ps
CPU time 0.82 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206124 kb
Host smart-94b79a7d-9e2f-4be3-bf65-a8a76adb25ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39203
90609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3920390609
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3948049229
Short name T877
Test name
Test status
Simulation time 188966085 ps
CPU time 0.81 seconds
Started Jul 09 05:16:44 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206148 kb
Host smart-04b3d64f-ecd4-45d6-86e9-baabd73178f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
49229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3948049229
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2250139919
Short name T442
Test name
Test status
Simulation time 206114585 ps
CPU time 0.97 seconds
Started Jul 09 05:16:48 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206144 kb
Host smart-c25d2891-bb31-45f4-b76b-aa3a18e10a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22501
39919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2250139919
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1060933556
Short name T1225
Test name
Test status
Simulation time 6210942321 ps
CPU time 59.33 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206408 kb
Host smart-35937b7a-1212-499c-83ba-182c9c498c97
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1060933556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1060933556
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1151042898
Short name T1764
Test name
Test status
Simulation time 163588822 ps
CPU time 0.82 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206148 kb
Host smart-594ca4df-6914-4f1e-a047-021b656e2fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11510
42898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1151042898
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2744831190
Short name T22
Test name
Test status
Simulation time 173238638 ps
CPU time 0.75 seconds
Started Jul 09 05:16:47 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 205208 kb
Host smart-0cd87523-cd98-415b-931e-b20dd443dd72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27448
31190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2744831190
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2151137091
Short name T728
Test name
Test status
Simulation time 944903107 ps
CPU time 2.08 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206372 kb
Host smart-cc5015a9-1776-4647-8e95-0d6893b88b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21511
37091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2151137091
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2961071471
Short name T1806
Test name
Test status
Simulation time 4157233146 ps
CPU time 33.74 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:17:21 PM PDT 24
Peak memory 206420 kb
Host smart-cdd2ffd1-c569-4bbd-8794-8190656001a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29610
71471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2961071471
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3487240630
Short name T467
Test name
Test status
Simulation time 38733147 ps
CPU time 0.64 seconds
Started Jul 09 05:16:53 PM PDT 24
Finished Jul 09 05:16:55 PM PDT 24
Peak memory 206088 kb
Host smart-ae1921fc-b671-42bd-865d-0f02770e45b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3487240630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3487240630
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.900041474
Short name T1753
Test name
Test status
Simulation time 3769633877 ps
CPU time 4.79 seconds
Started Jul 09 05:16:47 PM PDT 24
Finished Jul 09 05:16:53 PM PDT 24
Peak memory 206352 kb
Host smart-6ca352b8-4b91-4961-8be1-6ae09079d057
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=900041474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.900041474
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3702981473
Short name T2033
Test name
Test status
Simulation time 13348485527 ps
CPU time 12.56 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:17:00 PM PDT 24
Peak memory 206032 kb
Host smart-951c771e-c7ba-44fe-a952-33475ffc6f51
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3702981473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3702981473
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.158953090
Short name T2037
Test name
Test status
Simulation time 23398905934 ps
CPU time 22.55 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:17:10 PM PDT 24
Peak memory 206380 kb
Host smart-707f0533-698b-4bf9-aa17-a604843e259f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=158953090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.158953090
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1203324444
Short name T1439
Test name
Test status
Simulation time 153641623 ps
CPU time 0.77 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206060 kb
Host smart-65bb0497-b77f-411d-a7b0-dc276ff6bb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12033
24444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1203324444
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2306109736
Short name T1025
Test name
Test status
Simulation time 161597159 ps
CPU time 0.8 seconds
Started Jul 09 05:16:48 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206140 kb
Host smart-1a5a7348-1090-4a50-9ca9-59b5635d6dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23061
09736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2306109736
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.327770813
Short name T2043
Test name
Test status
Simulation time 353212312 ps
CPU time 1.22 seconds
Started Jul 09 05:16:49 PM PDT 24
Finished Jul 09 05:16:51 PM PDT 24
Peak memory 206104 kb
Host smart-31498bbd-1d43-4e6d-9b3b-f44b9912d327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32777
0813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.327770813
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3005368340
Short name T1004
Test name
Test status
Simulation time 644168558 ps
CPU time 1.52 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206120 kb
Host smart-0c2a4738-fa8b-4f44-b16b-a3763aac1ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30053
68340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3005368340
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1218033231
Short name T1057
Test name
Test status
Simulation time 19228038947 ps
CPU time 35.67 seconds
Started Jul 09 05:16:50 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206464 kb
Host smart-3a5e57e5-0b7e-4055-9128-296e7e2a5c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
33231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1218033231
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3283241038
Short name T852
Test name
Test status
Simulation time 379782586 ps
CPU time 1.18 seconds
Started Jul 09 05:16:47 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 205224 kb
Host smart-1be6790f-ed93-4a2f-9d4a-4204d57fd694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32832
41038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3283241038
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1969887025
Short name T374
Test name
Test status
Simulation time 212331281 ps
CPU time 0.88 seconds
Started Jul 09 05:16:45 PM PDT 24
Finished Jul 09 05:16:48 PM PDT 24
Peak memory 206160 kb
Host smart-dc14b941-44a6-4c20-a2ca-60905c2adca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
87025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1969887025
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2674036000
Short name T935
Test name
Test status
Simulation time 53040763 ps
CPU time 0.65 seconds
Started Jul 09 05:16:46 PM PDT 24
Finished Jul 09 05:16:49 PM PDT 24
Peak memory 206140 kb
Host smart-31b1bf91-fc0f-43cf-a686-6c727265df0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26740
36000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2674036000
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1154687690
Short name T2701
Test name
Test status
Simulation time 881443706 ps
CPU time 2.37 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:16:54 PM PDT 24
Peak memory 206264 kb
Host smart-66585ffc-2e26-4aae-997e-364f1c8b0c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11546
87690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1154687690
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1492940776
Short name T2466
Test name
Test status
Simulation time 348723578 ps
CPU time 2.18 seconds
Started Jul 09 05:16:52 PM PDT 24
Finished Jul 09 05:16:55 PM PDT 24
Peak memory 206320 kb
Host smart-b71c5e07-b262-4747-8831-82ed9e95f989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14929
40776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1492940776
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1156341555
Short name T111
Test name
Test status
Simulation time 285840501 ps
CPU time 0.92 seconds
Started Jul 09 05:16:49 PM PDT 24
Finished Jul 09 05:16:51 PM PDT 24
Peak memory 206052 kb
Host smart-8d765501-1c0a-4be2-88d8-56c1ca9ec223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11563
41555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1156341555
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.560533311
Short name T2709
Test name
Test status
Simulation time 145638493 ps
CPU time 0.8 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206104 kb
Host smart-ceb173a8-17d8-4b0d-831d-b19290c15c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56053
3311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.560533311
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1500276135
Short name T775
Test name
Test status
Simulation time 229094762 ps
CPU time 0.94 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:16:53 PM PDT 24
Peak memory 206128 kb
Host smart-daf7cadb-3b2b-4495-8f08-8cfa87e51474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
76135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1500276135
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3553796270
Short name T1841
Test name
Test status
Simulation time 182016544 ps
CPU time 0.82 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:16:52 PM PDT 24
Peak memory 206124 kb
Host smart-da996b03-1421-4dca-b9e6-299b2d81f244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
96270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3553796270
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.786811162
Short name T2235
Test name
Test status
Simulation time 23341431661 ps
CPU time 21.5 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:17:13 PM PDT 24
Peak memory 206168 kb
Host smart-5d5d6c3d-8ce5-45b3-b6ec-5c355f69d3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78681
1162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.786811162
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1231738130
Short name T1044
Test name
Test status
Simulation time 3327302282 ps
CPU time 3.92 seconds
Started Jul 09 05:16:50 PM PDT 24
Finished Jul 09 05:16:55 PM PDT 24
Peak memory 206172 kb
Host smart-2a2664a0-a7b6-42b9-a8a0-243d18d8dbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12317
38130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1231738130
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3014788218
Short name T922
Test name
Test status
Simulation time 8733161513 ps
CPU time 235 seconds
Started Jul 09 05:16:52 PM PDT 24
Finished Jul 09 05:20:48 PM PDT 24
Peak memory 206332 kb
Host smart-d905186c-f921-45d1-b36b-30bef0e205bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
88218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3014788218
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2492738284
Short name T1028
Test name
Test status
Simulation time 4531152947 ps
CPU time 32.6 seconds
Started Jul 09 05:16:52 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206392 kb
Host smart-0097bf84-e441-4797-bff1-c7c4e9f1f32a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2492738284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2492738284
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3430460437
Short name T1246
Test name
Test status
Simulation time 279273045 ps
CPU time 0.97 seconds
Started Jul 09 05:16:50 PM PDT 24
Finished Jul 09 05:16:52 PM PDT 24
Peak memory 206100 kb
Host smart-7f441758-850a-4e13-9441-e919b09e46a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3430460437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3430460437
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.262482044
Short name T2516
Test name
Test status
Simulation time 203188390 ps
CPU time 0.88 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:16:52 PM PDT 24
Peak memory 206164 kb
Host smart-2a1fd1ab-42f6-48e5-965e-52fcbbd962b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26248
2044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.262482044
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2159046234
Short name T1579
Test name
Test status
Simulation time 2792825564 ps
CPU time 74.02 seconds
Started Jul 09 05:16:50 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 206280 kb
Host smart-50c3149b-c2e2-4f66-9116-f61978302f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21590
46234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2159046234
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3008212498
Short name T1146
Test name
Test status
Simulation time 4922125765 ps
CPU time 47.94 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206304 kb
Host smart-62e3ec73-7fe4-48cc-a090-fcfa7edb5038
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3008212498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3008212498
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.303628937
Short name T1250
Test name
Test status
Simulation time 192371127 ps
CPU time 0.86 seconds
Started Jul 09 05:16:51 PM PDT 24
Finished Jul 09 05:16:53 PM PDT 24
Peak memory 206060 kb
Host smart-2d9568f1-b44c-4f79-9406-0b679e176a54
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=303628937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.303628937
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1707159209
Short name T2615
Test name
Test status
Simulation time 158168047 ps
CPU time 0.77 seconds
Started Jul 09 05:16:52 PM PDT 24
Finished Jul 09 05:16:53 PM PDT 24
Peak memory 206160 kb
Host smart-fd1ab61b-0f1a-46d5-8427-03556e0421ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071
59209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1707159209
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.223044708
Short name T128
Test name
Test status
Simulation time 233926344 ps
CPU time 0.87 seconds
Started Jul 09 05:16:48 PM PDT 24
Finished Jul 09 05:16:50 PM PDT 24
Peak memory 206092 kb
Host smart-823dab4e-7051-48cf-85c3-4a47b601b93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304
4708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.223044708
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1866586071
Short name T1872
Test name
Test status
Simulation time 187048980 ps
CPU time 0.89 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206048 kb
Host smart-0cd56440-613e-4ed8-b8f3-efbb0fc3fd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18665
86071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1866586071
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.4036791296
Short name T349
Test name
Test status
Simulation time 245239819 ps
CPU time 0.88 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 205972 kb
Host smart-4cd5f29f-c9a0-465f-a3e8-8210f4774516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40367
91296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.4036791296
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.4135905106
Short name T1609
Test name
Test status
Simulation time 229944516 ps
CPU time 0.83 seconds
Started Jul 09 05:16:52 PM PDT 24
Finished Jul 09 05:16:53 PM PDT 24
Peak memory 206120 kb
Host smart-a624b4b6-9c6d-450f-957f-4ef90ec3a1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359
05106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.4135905106
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2797012291
Short name T165
Test name
Test status
Simulation time 154528997 ps
CPU time 0.79 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206160 kb
Host smart-c44db0dc-e0d6-4042-9a4e-326de557b324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
12291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2797012291
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3129125257
Short name T947
Test name
Test status
Simulation time 255347175 ps
CPU time 1.06 seconds
Started Jul 09 05:16:53 PM PDT 24
Finished Jul 09 05:16:54 PM PDT 24
Peak memory 205992 kb
Host smart-49d0810c-10a3-4091-bfee-03cf2d8a9fc3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3129125257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3129125257
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.918111659
Short name T1906
Test name
Test status
Simulation time 154960462 ps
CPU time 0.8 seconds
Started Jul 09 05:16:53 PM PDT 24
Finished Jul 09 05:16:55 PM PDT 24
Peak memory 206056 kb
Host smart-832f4dbd-d5a2-4b15-8338-4313481b3aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91811
1659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.918111659
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1996017054
Short name T2639
Test name
Test status
Simulation time 41581586 ps
CPU time 0.67 seconds
Started Jul 09 05:16:53 PM PDT 24
Finished Jul 09 05:16:54 PM PDT 24
Peak memory 206012 kb
Host smart-39d7c270-8b75-40b8-bace-74bc69d1e1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19960
17054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1996017054
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2366074479
Short name T2036
Test name
Test status
Simulation time 6797405003 ps
CPU time 16.85 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206468 kb
Host smart-9372b18c-09cd-437c-a284-8af9212357c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23660
74479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2366074479
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3361421727
Short name T1502
Test name
Test status
Simulation time 178456794 ps
CPU time 0.84 seconds
Started Jul 09 05:16:55 PM PDT 24
Finished Jul 09 05:16:57 PM PDT 24
Peak memory 206068 kb
Host smart-cc8707ac-68e4-41f5-8744-14cacdf7e804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
21727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3361421727
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3341494491
Short name T1504
Test name
Test status
Simulation time 212883441 ps
CPU time 0.87 seconds
Started Jul 09 05:16:57 PM PDT 24
Finished Jul 09 05:16:58 PM PDT 24
Peak memory 206160 kb
Host smart-6ab85b89-2e02-4bd0-a51b-af4ec9b97979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33414
94491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3341494491
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2215672188
Short name T2421
Test name
Test status
Simulation time 184915408 ps
CPU time 0.88 seconds
Started Jul 09 05:16:55 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206116 kb
Host smart-d7e86210-af8c-4995-925d-f101061bb33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156
72188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2215672188
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.51348828
Short name T1924
Test name
Test status
Simulation time 175021126 ps
CPU time 0.83 seconds
Started Jul 09 05:16:56 PM PDT 24
Finished Jul 09 05:16:57 PM PDT 24
Peak memory 206140 kb
Host smart-4bd66a95-5855-4e5a-91b2-184e310aee20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51348
828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.51348828
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3695235424
Short name T2314
Test name
Test status
Simulation time 247693237 ps
CPU time 0.96 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206060 kb
Host smart-b99a9a45-2325-440a-af51-8570963ee230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36952
35424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3695235424
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2922080147
Short name T2557
Test name
Test status
Simulation time 158941432 ps
CPU time 0.82 seconds
Started Jul 09 05:17:00 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206056 kb
Host smart-92f4825c-3e35-4f2d-bb72-106d69554b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29220
80147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2922080147
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2565044602
Short name T644
Test name
Test status
Simulation time 306664762 ps
CPU time 1.02 seconds
Started Jul 09 05:16:56 PM PDT 24
Finished Jul 09 05:16:58 PM PDT 24
Peak memory 205992 kb
Host smart-d0a1e485-d5dd-4fb5-a413-9f910757766f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
44602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2565044602
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1887558497
Short name T1451
Test name
Test status
Simulation time 5641157467 ps
CPU time 52.77 seconds
Started Jul 09 05:16:53 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206180 kb
Host smart-9f090124-f943-4238-8d78-3e98c2409e1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1887558497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1887558497
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1042172178
Short name T1008
Test name
Test status
Simulation time 187773551 ps
CPU time 0.84 seconds
Started Jul 09 05:16:54 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 206164 kb
Host smart-1e277199-df45-45d7-9e45-18916644c0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10421
72178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1042172178
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.874887724
Short name T1747
Test name
Test status
Simulation time 213272692 ps
CPU time 0.9 seconds
Started Jul 09 05:16:55 PM PDT 24
Finished Jul 09 05:16:57 PM PDT 24
Peak memory 206136 kb
Host smart-e939ee11-4b7e-483b-83e4-fbee24ddcdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87488
7724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.874887724
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1457035725
Short name T2136
Test name
Test status
Simulation time 465249638 ps
CPU time 1.38 seconds
Started Jul 09 05:16:53 PM PDT 24
Finished Jul 09 05:16:55 PM PDT 24
Peak memory 206140 kb
Host smart-e4ed3b15-99b4-4d48-a28c-a77e1fe1b19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14570
35725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1457035725
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3044359834
Short name T1553
Test name
Test status
Simulation time 7725389964 ps
CPU time 71.64 seconds
Started Jul 09 05:16:55 PM PDT 24
Finished Jul 09 05:18:08 PM PDT 24
Peak memory 206416 kb
Host smart-c22689ab-7171-4a0a-98f1-912f797b0c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30443
59834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3044359834
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.1809453816
Short name T2411
Test name
Test status
Simulation time 60706830 ps
CPU time 0.73 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 206124 kb
Host smart-fbbf64e5-964c-41b1-9ea3-f55104d1e361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1809453816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.1809453816
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1662031323
Short name T1032
Test name
Test status
Simulation time 3898622946 ps
CPU time 4.52 seconds
Started Jul 09 05:16:55 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206388 kb
Host smart-89305824-2e67-4b2a-9588-9cffdc67064c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1662031323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1662031323
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2479564336
Short name T2594
Test name
Test status
Simulation time 13368187223 ps
CPU time 15.54 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:15 PM PDT 24
Peak memory 206300 kb
Host smart-12ee0842-3d79-4e6e-903c-6151c86ab130
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2479564336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2479564336
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.387962577
Short name T1997
Test name
Test status
Simulation time 23372198921 ps
CPU time 30.11 seconds
Started Jul 09 05:17:00 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206172 kb
Host smart-89fa1d79-63f2-4216-8257-7d4bb49d22b3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387962577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.387962577
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.804808847
Short name T1153
Test name
Test status
Simulation time 205934962 ps
CPU time 0.83 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206052 kb
Host smart-5dde7d18-2c13-4e25-8ffe-1b79b7973b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80480
8847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.804808847
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3703089719
Short name T621
Test name
Test status
Simulation time 180835011 ps
CPU time 0.79 seconds
Started Jul 09 05:16:58 PM PDT 24
Finished Jul 09 05:17:00 PM PDT 24
Peak memory 206124 kb
Host smart-448c4e58-c725-4c31-9f69-0c43d6b97fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37030
89719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3703089719
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2195970058
Short name T1591
Test name
Test status
Simulation time 540263087 ps
CPU time 1.59 seconds
Started Jul 09 05:17:01 PM PDT 24
Finished Jul 09 05:17:04 PM PDT 24
Peak memory 206308 kb
Host smart-b8fa853b-0bb4-4c2f-ad90-99e64ff68f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
70058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2195970058
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.938453752
Short name T180
Test name
Test status
Simulation time 1014879335 ps
CPU time 2.21 seconds
Started Jul 09 05:16:55 PM PDT 24
Finished Jul 09 05:16:59 PM PDT 24
Peak memory 206296 kb
Host smart-78a86598-c07e-4313-b19d-f271ce608642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93845
3752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.938453752
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3911483127
Short name T1405
Test name
Test status
Simulation time 11331102971 ps
CPU time 24.9 seconds
Started Jul 09 05:17:01 PM PDT 24
Finished Jul 09 05:17:27 PM PDT 24
Peak memory 206420 kb
Host smart-401ba839-178f-4c5d-a5cf-423dd8148486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
83127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3911483127
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1648294421
Short name T1899
Test name
Test status
Simulation time 463222272 ps
CPU time 1.4 seconds
Started Jul 09 05:16:58 PM PDT 24
Finished Jul 09 05:17:00 PM PDT 24
Peak memory 206064 kb
Host smart-923d5bed-574a-44e1-918a-5527d2a146f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16482
94421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1648294421
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.634012139
Short name T825
Test name
Test status
Simulation time 140898830 ps
CPU time 0.79 seconds
Started Jul 09 05:17:01 PM PDT 24
Finished Jul 09 05:17:03 PM PDT 24
Peak memory 206108 kb
Host smart-f24572a9-093e-4f0c-a88b-f0a134a4cb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63401
2139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.634012139
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2444159383
Short name T727
Test name
Test status
Simulation time 30864607 ps
CPU time 0.68 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:00 PM PDT 24
Peak memory 206116 kb
Host smart-9fd6e450-3af3-4a85-a7b7-2eb8aebea81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24441
59383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2444159383
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2913653123
Short name T896
Test name
Test status
Simulation time 721290022 ps
CPU time 1.87 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206348 kb
Host smart-000e0cc5-36bc-4233-98a4-c9f24c3a139e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136
53123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2913653123
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3697559225
Short name T1138
Test name
Test status
Simulation time 164219167 ps
CPU time 1.57 seconds
Started Jul 09 05:17:03 PM PDT 24
Finished Jul 09 05:17:05 PM PDT 24
Peak memory 206388 kb
Host smart-28e8b5d8-bf9d-460d-be7e-91d18fbb353d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
59225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3697559225
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1961767912
Short name T1228
Test name
Test status
Simulation time 159483694 ps
CPU time 0.81 seconds
Started Jul 09 05:17:00 PM PDT 24
Finished Jul 09 05:17:02 PM PDT 24
Peak memory 206136 kb
Host smart-771f1666-e755-4339-98c8-395733dc7af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19617
67912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1961767912
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3334086260
Short name T2207
Test name
Test status
Simulation time 146643868 ps
CPU time 0.79 seconds
Started Jul 09 05:16:57 PM PDT 24
Finished Jul 09 05:16:58 PM PDT 24
Peak memory 206140 kb
Host smart-c9c9f48f-0ab3-4fb2-96fe-de5b9ca27a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
86260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3334086260
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3425823133
Short name T2206
Test name
Test status
Simulation time 175563565 ps
CPU time 0.89 seconds
Started Jul 09 05:17:00 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206120 kb
Host smart-b7b29c59-2519-41f9-9f30-9cf4d55ac2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34258
23133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3425823133
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.221318334
Short name T1105
Test name
Test status
Simulation time 171820137 ps
CPU time 0.82 seconds
Started Jul 09 05:17:00 PM PDT 24
Finished Jul 09 05:17:02 PM PDT 24
Peak memory 206092 kb
Host smart-bda0b044-5f92-4c1d-a007-f3586a10e4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22131
8334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.221318334
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1771411690
Short name T882
Test name
Test status
Simulation time 23383829463 ps
CPU time 25.04 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206120 kb
Host smart-8422d1f0-232d-415f-b3af-eacad9b4b71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
11690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1771411690
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.63791858
Short name T1020
Test name
Test status
Simulation time 3293607490 ps
CPU time 3.73 seconds
Started Jul 09 05:17:01 PM PDT 24
Finished Jul 09 05:17:06 PM PDT 24
Peak memory 206124 kb
Host smart-826b06b1-04ca-4682-bb68-17d172b4041b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63791
858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.63791858
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.4274615411
Short name T2630
Test name
Test status
Simulation time 12822539792 ps
CPU time 357.63 seconds
Started Jul 09 05:17:03 PM PDT 24
Finished Jul 09 05:23:01 PM PDT 24
Peak memory 206504 kb
Host smart-24219f0f-4975-4277-92a1-9f22713d5bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
15411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.4274615411
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.822396126
Short name T383
Test name
Test status
Simulation time 4599110820 ps
CPU time 43.27 seconds
Started Jul 09 05:16:57 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206360 kb
Host smart-485886c0-365a-434a-916e-11bb383c7194
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=822396126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.822396126
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.364068386
Short name T1505
Test name
Test status
Simulation time 244545265 ps
CPU time 0.91 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:17:01 PM PDT 24
Peak memory 206140 kb
Host smart-c4d44b6b-3f7d-4fd2-87d3-05cf87637612
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=364068386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.364068386
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3475088919
Short name T2192
Test name
Test status
Simulation time 193247658 ps
CPU time 0.92 seconds
Started Jul 09 05:17:01 PM PDT 24
Finished Jul 09 05:17:03 PM PDT 24
Peak memory 206108 kb
Host smart-4259bb6a-4436-49c0-89ae-a598753bd9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34750
88919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3475088919
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.519413317
Short name T2562
Test name
Test status
Simulation time 4532574391 ps
CPU time 127.4 seconds
Started Jul 09 05:16:59 PM PDT 24
Finished Jul 09 05:19:08 PM PDT 24
Peak memory 206372 kb
Host smart-91d8c802-b917-4ff6-97e4-fa895b10ef2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51941
3317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.519413317
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1900192893
Short name T2200
Test name
Test status
Simulation time 5569701922 ps
CPU time 41.25 seconds
Started Jul 09 05:16:57 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 206376 kb
Host smart-2ed611d7-410e-4b91-b14c-fa5b313810e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1900192893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1900192893
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2003440160
Short name T2188
Test name
Test status
Simulation time 159392594 ps
CPU time 0.81 seconds
Started Jul 09 05:16:58 PM PDT 24
Finished Jul 09 05:16:59 PM PDT 24
Peak memory 206132 kb
Host smart-da81cdd4-2825-4cb7-9444-17bbf3393699
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2003440160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2003440160
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.926763690
Short name T2362
Test name
Test status
Simulation time 141597934 ps
CPU time 0.76 seconds
Started Jul 09 05:17:06 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206068 kb
Host smart-e68e56f6-a1c0-4df8-8f8c-1757abd03ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92676
3690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.926763690
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2072061193
Short name T123
Test name
Test status
Simulation time 191135652 ps
CPU time 0.9 seconds
Started Jul 09 05:17:02 PM PDT 24
Finished Jul 09 05:17:04 PM PDT 24
Peak memory 206160 kb
Host smart-42ac2688-b7c5-412e-bf7b-38e67a2fd2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
61193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2072061193
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3817754881
Short name T2497
Test name
Test status
Simulation time 179541647 ps
CPU time 0.83 seconds
Started Jul 09 05:17:05 PM PDT 24
Finished Jul 09 05:17:06 PM PDT 24
Peak memory 206124 kb
Host smart-8db09d1c-e3f9-4d13-82a4-965864c915d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38177
54881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3817754881
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.298875284
Short name T1501
Test name
Test status
Simulation time 171186651 ps
CPU time 0.86 seconds
Started Jul 09 05:17:03 PM PDT 24
Finished Jul 09 05:17:05 PM PDT 24
Peak memory 206080 kb
Host smart-80843330-a603-403d-89d3-860fb74c6227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29887
5284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.298875284
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.46766518
Short name T101
Test name
Test status
Simulation time 190160631 ps
CPU time 0.83 seconds
Started Jul 09 05:17:04 PM PDT 24
Finished Jul 09 05:17:05 PM PDT 24
Peak memory 206148 kb
Host smart-b27772e0-4312-41f1-9dd2-f821da7a6de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46766
518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.46766518
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.854963728
Short name T2660
Test name
Test status
Simulation time 165162041 ps
CPU time 0.91 seconds
Started Jul 09 05:17:03 PM PDT 24
Finished Jul 09 05:17:04 PM PDT 24
Peak memory 206160 kb
Host smart-c059c956-caa7-473a-9c77-014c7c5a09b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85496
3728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.854963728
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1017471608
Short name T648
Test name
Test status
Simulation time 296875244 ps
CPU time 1.16 seconds
Started Jul 09 05:17:02 PM PDT 24
Finished Jul 09 05:17:04 PM PDT 24
Peak memory 206104 kb
Host smart-b733abd2-cfa4-467c-be05-579739cd8357
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1017471608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1017471608
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.987967323
Short name T2416
Test name
Test status
Simulation time 184506141 ps
CPU time 0.88 seconds
Started Jul 09 05:17:04 PM PDT 24
Finished Jul 09 05:17:05 PM PDT 24
Peak memory 206132 kb
Host smart-141af813-3202-42e0-9221-6797c9e25126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98796
7323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.987967323
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1828572957
Short name T25
Test name
Test status
Simulation time 70091823 ps
CPU time 0.68 seconds
Started Jul 09 05:17:03 PM PDT 24
Finished Jul 09 05:17:04 PM PDT 24
Peak memory 205988 kb
Host smart-0f952753-4d72-4483-957c-c489e289d732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18285
72957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1828572957
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.30162404
Short name T1296
Test name
Test status
Simulation time 15773974354 ps
CPU time 36.33 seconds
Started Jul 09 05:17:01 PM PDT 24
Finished Jul 09 05:17:38 PM PDT 24
Peak memory 206412 kb
Host smart-e6ce683d-2572-4cfc-bd3e-9efa364ad0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30162
404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.30162404
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3260522507
Short name T1990
Test name
Test status
Simulation time 179493862 ps
CPU time 0.81 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206060 kb
Host smart-afc77d48-e5b8-4870-a11e-5b49726619d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32605
22507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3260522507
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.4115609416
Short name T2075
Test name
Test status
Simulation time 199570451 ps
CPU time 0.88 seconds
Started Jul 09 05:17:04 PM PDT 24
Finished Jul 09 05:17:06 PM PDT 24
Peak memory 206016 kb
Host smart-2cbe1f65-313b-4468-b6e2-300274f878d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156
09416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.4115609416
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3626593776
Short name T1709
Test name
Test status
Simulation time 167590784 ps
CPU time 0.82 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 206052 kb
Host smart-4fb4c6eb-b154-4ef8-8782-736fb17d8a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36265
93776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3626593776
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3862458615
Short name T1873
Test name
Test status
Simulation time 169515303 ps
CPU time 0.93 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 205996 kb
Host smart-2cae2903-2ed6-4c8a-94e9-ec446228b2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
58615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3862458615
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1339599385
Short name T1838
Test name
Test status
Simulation time 168969035 ps
CPU time 0.82 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:17:09 PM PDT 24
Peak memory 206080 kb
Host smart-1017aaa1-9a69-40bb-8180-f0229cf8d8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
99385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1339599385
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2340197457
Short name T1033
Test name
Test status
Simulation time 158301504 ps
CPU time 0.78 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206140 kb
Host smart-1319c740-4afe-441a-99b9-832b39ca7f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401
97457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2340197457
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3995548972
Short name T1779
Test name
Test status
Simulation time 156061037 ps
CPU time 0.82 seconds
Started Jul 09 05:17:12 PM PDT 24
Finished Jul 09 05:17:14 PM PDT 24
Peak memory 206144 kb
Host smart-e40ffef8-ac8e-40af-884e-d72f30576e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
48972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3995548972
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1759478890
Short name T1326
Test name
Test status
Simulation time 259491766 ps
CPU time 1 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:17:09 PM PDT 24
Peak memory 206112 kb
Host smart-f78c24b5-bb60-44ba-8fa8-7ce09b260bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17594
78890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1759478890
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1199149671
Short name T2568
Test name
Test status
Simulation time 3444698736 ps
CPU time 93.49 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:18:41 PM PDT 24
Peak memory 206352 kb
Host smart-16869b2e-f86a-4439-a4b2-448e37f88469
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1199149671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1199149671
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3134298229
Short name T813
Test name
Test status
Simulation time 170069587 ps
CPU time 0.88 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 206092 kb
Host smart-136fee50-f5cc-4f81-871a-704c970bfb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31342
98229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3134298229
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3905005400
Short name T1305
Test name
Test status
Simulation time 189896295 ps
CPU time 0.87 seconds
Started Jul 09 05:17:05 PM PDT 24
Finished Jul 09 05:17:06 PM PDT 24
Peak memory 206024 kb
Host smart-8fc941ee-245b-4f04-8d1f-1ea0c95e4779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050
05400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3905005400
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1847970364
Short name T2496
Test name
Test status
Simulation time 747510083 ps
CPU time 1.88 seconds
Started Jul 09 05:17:08 PM PDT 24
Finished Jul 09 05:17:10 PM PDT 24
Peak memory 206188 kb
Host smart-f1d54c05-8cd7-4cb4-8b03-545c54dff304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18479
70364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1847970364
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1502067368
Short name T1482
Test name
Test status
Simulation time 5030760668 ps
CPU time 136.29 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:19:24 PM PDT 24
Peak memory 206500 kb
Host smart-7adf5be5-a87b-4ec3-b389-98e4588c05e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15020
67368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1502067368
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2026722154
Short name T2372
Test name
Test status
Simulation time 85627085 ps
CPU time 0.71 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206160 kb
Host smart-46a04918-7c9e-454c-a98d-39a1b7b972ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2026722154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2026722154
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.4090655347
Short name T1544
Test name
Test status
Simulation time 4003148686 ps
CPU time 5.58 seconds
Started Jul 09 05:17:08 PM PDT 24
Finished Jul 09 05:17:15 PM PDT 24
Peak memory 206160 kb
Host smart-13a32bda-f1d3-4dde-87de-f1494efe90ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4090655347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.4090655347
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.573754476
Short name T1460
Test name
Test status
Simulation time 13381964860 ps
CPU time 15.19 seconds
Started Jul 09 05:17:06 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206088 kb
Host smart-e9a7f777-b35b-430e-804b-d12a645c0f0c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=573754476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.573754476
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3691970998
Short name T1786
Test name
Test status
Simulation time 23416750325 ps
CPU time 24.78 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206332 kb
Host smart-3eb4af86-15e2-4806-8cd6-9c395c91d05c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3691970998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3691970998
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1289848678
Short name T1955
Test name
Test status
Simulation time 146092995 ps
CPU time 0.83 seconds
Started Jul 09 05:17:08 PM PDT 24
Finished Jul 09 05:17:10 PM PDT 24
Peak memory 206136 kb
Host smart-bb710e87-aaad-4d31-86e7-2d2d1e3e20e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
48678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1289848678
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.221218087
Short name T787
Test name
Test status
Simulation time 147130818 ps
CPU time 0.8 seconds
Started Jul 09 05:17:07 PM PDT 24
Finished Jul 09 05:17:09 PM PDT 24
Peak memory 206016 kb
Host smart-66dc76d7-274d-4bee-874e-ea8778aa8874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22121
8087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.221218087
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1415502968
Short name T1611
Test name
Test status
Simulation time 191536311 ps
CPU time 0.97 seconds
Started Jul 09 05:17:08 PM PDT 24
Finished Jul 09 05:17:10 PM PDT 24
Peak memory 206128 kb
Host smart-a617542c-6019-4a19-a9ea-4c4965fe8633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155
02968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1415502968
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1095298727
Short name T742
Test name
Test status
Simulation time 317662639 ps
CPU time 1.03 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206048 kb
Host smart-72b12376-058a-4aac-b311-b9453f5c607c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
98727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1095298727
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2153035130
Short name T940
Test name
Test status
Simulation time 20064296451 ps
CPU time 35.76 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206456 kb
Host smart-aab2733b-81cb-4175-accc-e19cfdc0408d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
35130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2153035130
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3527037918
Short name T1596
Test name
Test status
Simulation time 479958802 ps
CPU time 1.4 seconds
Started Jul 09 05:17:06 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206148 kb
Host smart-105a7ab7-9dde-41b1-8960-38d2144aa773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
37918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3527037918
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.216721250
Short name T746
Test name
Test status
Simulation time 143034436 ps
CPU time 0.76 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206164 kb
Host smart-5817419e-f7c4-4c5c-bdbe-6deb73809980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21672
1250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.216721250
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.399684368
Short name T1168
Test name
Test status
Simulation time 44341345 ps
CPU time 0.72 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:17:14 PM PDT 24
Peak memory 206056 kb
Host smart-b7f6fcb6-7f87-4d15-a665-15040b6e5c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39968
4368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.399684368
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2644656597
Short name T2030
Test name
Test status
Simulation time 917835816 ps
CPU time 2.2 seconds
Started Jul 09 05:17:05 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206312 kb
Host smart-d979e5f8-989c-4eb7-ae8f-e1359fa92a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
56597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2644656597
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2266334534
Short name T2495
Test name
Test status
Simulation time 406794639 ps
CPU time 2.29 seconds
Started Jul 09 05:17:06 PM PDT 24
Finished Jul 09 05:17:08 PM PDT 24
Peak memory 206304 kb
Host smart-74175ff4-c3e1-43b4-965b-661c40874fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
34534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2266334534
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.622037556
Short name T1090
Test name
Test status
Simulation time 199686289 ps
CPU time 0.88 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206116 kb
Host smart-47cd6564-bb47-4b76-a8d0-3d028239cced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62203
7556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.622037556
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2317731403
Short name T1159
Test name
Test status
Simulation time 152396658 ps
CPU time 0.79 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206136 kb
Host smart-3f16b025-0996-4248-bba6-6743c2eaf284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23177
31403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2317731403
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2167231004
Short name T1288
Test name
Test status
Simulation time 178930171 ps
CPU time 0.86 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:17:15 PM PDT 24
Peak memory 206048 kb
Host smart-3882ba02-1608-410a-85f5-23455a98a715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21672
31004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2167231004
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2923068823
Short name T814
Test name
Test status
Simulation time 216141990 ps
CPU time 0.85 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206160 kb
Host smart-06a39e17-c14c-460e-838b-0f8f63ddd37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
68823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2923068823
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1428081226
Short name T2184
Test name
Test status
Simulation time 23348638973 ps
CPU time 23.59 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206204 kb
Host smart-3cc00165-451f-4a8b-bd63-726c7780fe2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14280
81226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1428081226
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1834441453
Short name T1036
Test name
Test status
Simulation time 3340328101 ps
CPU time 4.03 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206128 kb
Host smart-5a0bf6a3-b347-4010-8ee0-c1ed56ab6f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344
41453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1834441453
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3484724595
Short name T2643
Test name
Test status
Simulation time 5131586840 ps
CPU time 137.66 seconds
Started Jul 09 05:17:11 PM PDT 24
Finished Jul 09 05:19:30 PM PDT 24
Peak memory 206384 kb
Host smart-74ddbd71-e204-4d28-8d2b-215b55151803
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3484724595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3484724595
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1376373163
Short name T715
Test name
Test status
Simulation time 291357748 ps
CPU time 0.95 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 206092 kb
Host smart-4b1c8a1e-73a1-4eb9-a689-67f7e8a414c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1376373163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1376373163
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2428825694
Short name T1042
Test name
Test status
Simulation time 193997854 ps
CPU time 0.88 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 205996 kb
Host smart-a90e670b-a296-4129-afd3-effde9300bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24288
25694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2428825694
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.969141449
Short name T2671
Test name
Test status
Simulation time 6290032703 ps
CPU time 44.19 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 206328 kb
Host smart-0d4c54eb-aac0-49fe-adcb-6abd1567a910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96914
1449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.969141449
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.567883230
Short name T2517
Test name
Test status
Simulation time 4075401319 ps
CPU time 115.17 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206656 kb
Host smart-332f5b08-4334-4ac1-a80d-4eeabb8c804a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=567883230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.567883230
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3513454501
Short name T1546
Test name
Test status
Simulation time 161592895 ps
CPU time 0.86 seconds
Started Jul 09 05:17:14 PM PDT 24
Finished Jul 09 05:17:16 PM PDT 24
Peak memory 206140 kb
Host smart-ec0f02f3-6811-489c-9586-6273ecd7c5bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3513454501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3513454501
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1689347790
Short name T2604
Test name
Test status
Simulation time 139920858 ps
CPU time 0.79 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206068 kb
Host smart-92ac914a-3e00-42d8-b0e3-b8f4cc233bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
47790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1689347790
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.222669925
Short name T131
Test name
Test status
Simulation time 199826254 ps
CPU time 0.86 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206116 kb
Host smart-910eca4a-b9fc-40cd-8c38-b6f30843a919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22266
9925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.222669925
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2158272234
Short name T2157
Test name
Test status
Simulation time 175709073 ps
CPU time 0.82 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206128 kb
Host smart-745bc7e5-dbde-4377-aace-78e404bdc1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
72234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2158272234
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2942727838
Short name T2548
Test name
Test status
Simulation time 242872967 ps
CPU time 0.89 seconds
Started Jul 09 05:17:11 PM PDT 24
Finished Jul 09 05:17:13 PM PDT 24
Peak memory 206148 kb
Host smart-2aa292a0-29af-41de-948a-1bf270ecd3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
27838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2942727838
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3394095106
Short name T441
Test name
Test status
Simulation time 141292333 ps
CPU time 0.77 seconds
Started Jul 09 05:17:14 PM PDT 24
Finished Jul 09 05:17:16 PM PDT 24
Peak memory 206136 kb
Host smart-079869bc-02bc-4625-98f1-54c0a992596c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33940
95106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3394095106
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2998540167
Short name T686
Test name
Test status
Simulation time 159825919 ps
CPU time 0.85 seconds
Started Jul 09 05:17:12 PM PDT 24
Finished Jul 09 05:17:14 PM PDT 24
Peak memory 206124 kb
Host smart-a2217a6c-e5a7-4297-97a5-c961917db931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
40167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2998540167
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1201253099
Short name T1125
Test name
Test status
Simulation time 229093366 ps
CPU time 0.92 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:19 PM PDT 24
Peak memory 206100 kb
Host smart-e691f40d-6230-4965-8f99-866e29676503
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1201253099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1201253099
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3356953254
Short name T2453
Test name
Test status
Simulation time 148697361 ps
CPU time 0.74 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 205964 kb
Host smart-5671d162-8a7d-46d6-815f-c700bef19c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33569
53254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3356953254
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1627928523
Short name T1710
Test name
Test status
Simulation time 47765947 ps
CPU time 0.69 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 206144 kb
Host smart-6e143c0b-d95a-4815-bc77-076cfd166094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279
28523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1627928523
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.808762028
Short name T243
Test name
Test status
Simulation time 19275530448 ps
CPU time 41.1 seconds
Started Jul 09 05:17:11 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206476 kb
Host smart-d14cd7f8-804d-401b-8879-f0b4beeccf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80876
2028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.808762028
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2596427800
Short name T285
Test name
Test status
Simulation time 164877723 ps
CPU time 0.86 seconds
Started Jul 09 05:17:11 PM PDT 24
Finished Jul 09 05:17:13 PM PDT 24
Peak memory 206056 kb
Host smart-960e5f91-5249-40f0-a8b0-4a59ab9a5b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25964
27800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2596427800
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.367795540
Short name T323
Test name
Test status
Simulation time 225878361 ps
CPU time 0.94 seconds
Started Jul 09 05:17:09 PM PDT 24
Finished Jul 09 05:17:11 PM PDT 24
Peak memory 206020 kb
Host smart-54d0af00-7ff0-454b-976e-54b37ef2937b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36779
5540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.367795540
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2474223275
Short name T831
Test name
Test status
Simulation time 228591558 ps
CPU time 0.96 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206128 kb
Host smart-047bc6e4-74cd-417f-aa48-fb432170ab43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24742
23275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2474223275
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2414232121
Short name T2629
Test name
Test status
Simulation time 226575738 ps
CPU time 0.93 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 206164 kb
Host smart-5e2ecef8-b3a7-4291-8b9f-575006631fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24142
32121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2414232121
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2873327950
Short name T90
Test name
Test status
Simulation time 133501137 ps
CPU time 0.8 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 205956 kb
Host smart-bf2597a8-4d65-4748-8828-c5b9a7cf4771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28733
27950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2873327950
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1886180962
Short name T800
Test name
Test status
Simulation time 210915966 ps
CPU time 0.85 seconds
Started Jul 09 05:17:10 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 205988 kb
Host smart-88b17071-79bd-4f91-af3a-cbaf004dcfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18861
80962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1886180962
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.90038695
Short name T98
Test name
Test status
Simulation time 172975541 ps
CPU time 0.84 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206124 kb
Host smart-3d489945-1374-46c6-ac2b-15a16c941ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90038
695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.90038695
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3662806567
Short name T1572
Test name
Test status
Simulation time 217636014 ps
CPU time 0.89 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 205960 kb
Host smart-4d7bb2db-158a-48a5-97b5-1ba073bd7394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36628
06567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3662806567
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3663231712
Short name T2705
Test name
Test status
Simulation time 6494469728 ps
CPU time 60.81 seconds
Started Jul 09 05:17:11 PM PDT 24
Finished Jul 09 05:18:13 PM PDT 24
Peak memory 206404 kb
Host smart-2f7615dd-0bcd-4ca4-8c3a-5cb633ea928c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3663231712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3663231712
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.484123932
Short name T1794
Test name
Test status
Simulation time 154950298 ps
CPU time 0.77 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:17:14 PM PDT 24
Peak memory 206144 kb
Host smart-87a290d7-4047-443e-ad70-75697b28d5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48412
3932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.484123932
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2420214240
Short name T512
Test name
Test status
Simulation time 158896509 ps
CPU time 0.79 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:19 PM PDT 24
Peak memory 205960 kb
Host smart-c9a4f929-9b89-4238-80f3-c8a658b398f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
14240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2420214240
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.594245444
Short name T577
Test name
Test status
Simulation time 388758212 ps
CPU time 1.27 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206164 kb
Host smart-8aac40b0-a882-483c-b703-8dff6fc23b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59424
5444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.594245444
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.420336061
Short name T1329
Test name
Test status
Simulation time 3955534461 ps
CPU time 107.96 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:19:07 PM PDT 24
Peak memory 206272 kb
Host smart-6619516b-4b67-4d9e-af0e-86e4a8f848f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
6061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.420336061
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.374592487
Short name T1045
Test name
Test status
Simulation time 39145026 ps
CPU time 0.71 seconds
Started Jul 09 05:17:19 PM PDT 24
Finished Jul 09 05:17:21 PM PDT 24
Peak memory 206024 kb
Host smart-f7eccf48-06d1-4f57-9fe1-72564219dbf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=374592487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.374592487
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.469983033
Short name T858
Test name
Test status
Simulation time 4119540837 ps
CPU time 6.14 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206400 kb
Host smart-e441e270-96af-49ad-8ce7-0c173fe03291
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=469983033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.469983033
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3724344044
Short name T2145
Test name
Test status
Simulation time 13312633091 ps
CPU time 16.7 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206184 kb
Host smart-49fa1fe4-00ae-44a5-948e-3c45a29a1934
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3724344044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3724344044
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.634680564
Short name T1515
Test name
Test status
Simulation time 23378948685 ps
CPU time 22.94 seconds
Started Jul 09 05:17:16 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206172 kb
Host smart-366a7a25-4a7c-4805-8f18-1b2b325a5678
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=634680564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.634680564
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3409538096
Short name T1577
Test name
Test status
Simulation time 180503388 ps
CPU time 0.83 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206132 kb
Host smart-3c153e76-b27b-472c-8899-bb66459248a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34095
38096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3409538096
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2111319264
Short name T981
Test name
Test status
Simulation time 155904167 ps
CPU time 0.82 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206008 kb
Host smart-a8b5b260-c49b-44f1-8ca0-1548485f31dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21113
19264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2111319264
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3538311507
Short name T1417
Test name
Test status
Simulation time 391833104 ps
CPU time 1.39 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206064 kb
Host smart-72c56846-c684-43fa-9325-a9bbc55d45f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35383
11507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3538311507
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.4019522238
Short name T1826
Test name
Test status
Simulation time 1225096589 ps
CPU time 2.61 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:19 PM PDT 24
Peak memory 206276 kb
Host smart-09a52ecc-d2db-40d9-a6f0-934fd9b8aa17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
22238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.4019522238
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3604227051
Short name T1926
Test name
Test status
Simulation time 6234857708 ps
CPU time 12.19 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206408 kb
Host smart-f7138a35-880c-4336-b44a-5c9355ab2933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042
27051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3604227051
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1006840840
Short name T979
Test name
Test status
Simulation time 341863396 ps
CPU time 1.14 seconds
Started Jul 09 05:17:16 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206060 kb
Host smart-86700961-ca16-45c4-8cf8-40fcc8da8d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10068
40840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1006840840
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.253347110
Short name T2502
Test name
Test status
Simulation time 157234504 ps
CPU time 0.77 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:17:15 PM PDT 24
Peak memory 206104 kb
Host smart-204620cf-920d-425f-8bb3-74929899a7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.253347110
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2811406229
Short name T2642
Test name
Test status
Simulation time 33183224 ps
CPU time 0.67 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206152 kb
Host smart-cf31c19f-8580-4896-816b-4282be71f4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
06229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2811406229
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3681909807
Short name T496
Test name
Test status
Simulation time 913860069 ps
CPU time 2.25 seconds
Started Jul 09 05:17:14 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206348 kb
Host smart-ff16be71-9cd4-48d1-987e-5fef0d419b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819
09807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3681909807
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.133960212
Short name T1437
Test name
Test status
Simulation time 306624537 ps
CPU time 1.95 seconds
Started Jul 09 05:17:11 PM PDT 24
Finished Jul 09 05:17:14 PM PDT 24
Peak memory 206292 kb
Host smart-bc2ba321-6888-4975-be8c-1a08788d14fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13396
0212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.133960212
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3100696813
Short name T112
Test name
Test status
Simulation time 170341239 ps
CPU time 0.86 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206148 kb
Host smart-abc90553-6226-4c40-9b1c-89bb2f38e452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006
96813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3100696813
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3688052468
Short name T2226
Test name
Test status
Simulation time 151810326 ps
CPU time 0.77 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:17:17 PM PDT 24
Peak memory 206012 kb
Host smart-d308ae82-5ded-45fd-beb0-1ed1fa1bddf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
52468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3688052468
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2500520396
Short name T931
Test name
Test status
Simulation time 190025139 ps
CPU time 0.94 seconds
Started Jul 09 05:17:16 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206144 kb
Host smart-efd77d72-d59c-4b8d-8882-7753ff936c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25005
20396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2500520396
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.1688270727
Short name T1522
Test name
Test status
Simulation time 7489950723 ps
CPU time 53.82 seconds
Started Jul 09 05:17:15 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206352 kb
Host smart-ed0cb731-31e5-4063-bcb2-70dc807b10cb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1688270727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1688270727
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2373916820
Short name T943
Test name
Test status
Simulation time 231642887 ps
CPU time 0.88 seconds
Started Jul 09 05:17:14 PM PDT 24
Finished Jul 09 05:17:16 PM PDT 24
Peak memory 205992 kb
Host smart-5f1a4a4e-108d-446b-a80b-19339b56a924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23739
16820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2373916820
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1322999076
Short name T354
Test name
Test status
Simulation time 23353321558 ps
CPU time 24.45 seconds
Started Jul 09 05:17:13 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 206108 kb
Host smart-1a9fc1c8-806b-45eb-aa1c-81812c0fb62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13229
99076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1322999076
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1310927917
Short name T2645
Test name
Test status
Simulation time 3339497497 ps
CPU time 3.96 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206108 kb
Host smart-bfce7532-9cd0-4e08-854b-d791f5fbccff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13109
27917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1310927917
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.569886456
Short name T695
Test name
Test status
Simulation time 11647729293 ps
CPU time 315.9 seconds
Started Jul 09 05:17:19 PM PDT 24
Finished Jul 09 05:22:36 PM PDT 24
Peak memory 206508 kb
Host smart-0796d3a8-cb21-4578-933c-5fbf4600f15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56988
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.569886456
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3700092714
Short name T790
Test name
Test status
Simulation time 4155507541 ps
CPU time 31.18 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206300 kb
Host smart-5958b0f1-1828-4191-8ffa-e5dcb6f5a1fa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3700092714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3700092714
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2751456486
Short name T986
Test name
Test status
Simulation time 239361814 ps
CPU time 0.93 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 205980 kb
Host smart-437a7183-06b9-4c16-9939-3dd7d4f214bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2751456486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2751456486
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3522290532
Short name T1031
Test name
Test status
Simulation time 185664616 ps
CPU time 0.89 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206124 kb
Host smart-2e7bbeab-77d7-4a28-9925-6da3ed373ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
90532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3522290532
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3433799485
Short name T1541
Test name
Test status
Simulation time 5083230625 ps
CPU time 133 seconds
Started Jul 09 05:17:20 PM PDT 24
Finished Jul 09 05:19:34 PM PDT 24
Peak memory 206256 kb
Host smart-d4c118bb-e27e-4d97-9bf5-a3a862e32cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34337
99485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3433799485
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2509112719
Short name T1433
Test name
Test status
Simulation time 7245252860 ps
CPU time 65.41 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206360 kb
Host smart-dcae08fc-60f5-4e8a-b587-bcc0f217d92c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2509112719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2509112719
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1330631816
Short name T510
Test name
Test status
Simulation time 154103617 ps
CPU time 0.8 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206108 kb
Host smart-5a0f5586-7d93-45ff-8bc1-33ebf790ace0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1330631816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1330631816
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4270078475
Short name T1925
Test name
Test status
Simulation time 178158486 ps
CPU time 0.82 seconds
Started Jul 09 05:17:25 PM PDT 24
Finished Jul 09 05:17:27 PM PDT 24
Peak memory 205740 kb
Host smart-84237827-656c-4e3b-9534-640a2e091d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
78475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4270078475
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2182744198
Short name T1761
Test name
Test status
Simulation time 204292931 ps
CPU time 0.91 seconds
Started Jul 09 05:17:20 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 205992 kb
Host smart-f0c3dc8d-af38-4d4c-b079-a332d54bd883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
44198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2182744198
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.235063596
Short name T788
Test name
Test status
Simulation time 172279376 ps
CPU time 0.95 seconds
Started Jul 09 05:17:22 PM PDT 24
Finished Jul 09 05:17:24 PM PDT 24
Peak memory 206088 kb
Host smart-2afc9504-e371-4d93-9ffc-5d5f95ad2ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.235063596
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2913420150
Short name T748
Test name
Test status
Simulation time 185568009 ps
CPU time 0.81 seconds
Started Jul 09 05:17:20 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206020 kb
Host smart-230f956e-9224-45e2-bc00-c3eac492b653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
20150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2913420150
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.4233258022
Short name T1060
Test name
Test status
Simulation time 183111341 ps
CPU time 0.8 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206108 kb
Host smart-40d4647c-3096-4eab-860a-19e01e3b0618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42332
58022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.4233258022
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1950327730
Short name T1334
Test name
Test status
Simulation time 157888743 ps
CPU time 0.78 seconds
Started Jul 09 05:17:19 PM PDT 24
Finished Jul 09 05:17:21 PM PDT 24
Peak memory 206060 kb
Host smart-0eed5a5d-b740-420a-b968-521230799327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
27730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1950327730
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1502905470
Short name T1922
Test name
Test status
Simulation time 216551511 ps
CPU time 0.97 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 205968 kb
Host smart-e9114c1e-506d-4878-8e16-873c0895c4c3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1502905470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1502905470
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1383606788
Short name T1372
Test name
Test status
Simulation time 141565096 ps
CPU time 0.8 seconds
Started Jul 09 05:17:16 PM PDT 24
Finished Jul 09 05:17:18 PM PDT 24
Peak memory 206108 kb
Host smart-315f6e1d-f060-4be9-b1a0-344ee0d2a3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13836
06788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1383606788
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2739276655
Short name T2331
Test name
Test status
Simulation time 100469314 ps
CPU time 0.75 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:21 PM PDT 24
Peak memory 206364 kb
Host smart-e3cb86a6-02a5-48bc-87d9-e764b535b9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27392
76655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2739276655
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.562658704
Short name T2237
Test name
Test status
Simulation time 12618948163 ps
CPU time 30.95 seconds
Started Jul 09 05:17:22 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206424 kb
Host smart-60425c8f-b73b-4b66-b6e7-2f84d6250834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56265
8704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.562658704
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.671966338
Short name T1789
Test name
Test status
Simulation time 155304524 ps
CPU time 0.84 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206148 kb
Host smart-66538a4d-7e67-4938-8f05-ae096fe60806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67196
6338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.671966338
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3344364580
Short name T1161
Test name
Test status
Simulation time 229875110 ps
CPU time 0.89 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206036 kb
Host smart-d8fa6ef2-70f8-4a60-836e-dbca669e7038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33443
64580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3344364580
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2739053202
Short name T392
Test name
Test status
Simulation time 168629131 ps
CPU time 0.84 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:21 PM PDT 24
Peak memory 206152 kb
Host smart-f3e75381-8557-4fe5-9792-95552a2636b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390
53202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2739053202
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2598579408
Short name T1139
Test name
Test status
Simulation time 174193820 ps
CPU time 0.85 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 206004 kb
Host smart-35bc1b0d-447d-4ad9-8892-2bf793560360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25985
79408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2598579408
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1378825846
Short name T2553
Test name
Test status
Simulation time 160381206 ps
CPU time 0.81 seconds
Started Jul 09 05:17:20 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206160 kb
Host smart-707fbf47-29d0-4d27-aaf9-1a7f1a89733a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13788
25846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1378825846
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3937154325
Short name T2009
Test name
Test status
Simulation time 149652197 ps
CPU time 0.77 seconds
Started Jul 09 05:17:24 PM PDT 24
Finished Jul 09 05:17:27 PM PDT 24
Peak memory 206060 kb
Host smart-5edecea7-cb8f-4ca2-a82a-4c74d0cd345d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39371
54325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3937154325
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1094448872
Short name T675
Test name
Test status
Simulation time 153122472 ps
CPU time 0.8 seconds
Started Jul 09 05:17:18 PM PDT 24
Finished Jul 09 05:17:20 PM PDT 24
Peak memory 206048 kb
Host smart-19843709-a0bd-42d8-a1d2-1f2d0b99d0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
48872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1094448872
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1882041445
Short name T339
Test name
Test status
Simulation time 198387284 ps
CPU time 0.91 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:23 PM PDT 24
Peak memory 206092 kb
Host smart-de148820-79e6-43fd-af74-cf59da9c1b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
41445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1882041445
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1811500277
Short name T1570
Test name
Test status
Simulation time 3705245906 ps
CPU time 102.45 seconds
Started Jul 09 05:17:17 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 206412 kb
Host smart-bb8c1b94-be67-4110-8c59-3d720704f2f0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1811500277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1811500277
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.868277133
Short name T2558
Test name
Test status
Simulation time 156735431 ps
CPU time 0.84 seconds
Started Jul 09 05:17:25 PM PDT 24
Finished Jul 09 05:17:27 PM PDT 24
Peak memory 205744 kb
Host smart-a8141fbe-bb5e-4c15-9192-1b896bcc3738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86827
7133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.868277133
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2800795474
Short name T1494
Test name
Test status
Simulation time 186132670 ps
CPU time 0.86 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:24 PM PDT 24
Peak memory 206128 kb
Host smart-5f8c0bc7-1147-493f-ac90-c4641edda22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28007
95474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2800795474
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.409460625
Short name T961
Test name
Test status
Simulation time 527119950 ps
CPU time 1.38 seconds
Started Jul 09 05:17:19 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206132 kb
Host smart-54eda631-897f-4eae-a2c5-58076a42a224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40946
0625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.409460625
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2325418965
Short name T2077
Test name
Test status
Simulation time 2798644217 ps
CPU time 78.13 seconds
Started Jul 09 05:17:22 PM PDT 24
Finished Jul 09 05:18:41 PM PDT 24
Peak memory 206440 kb
Host smart-d20f66a7-f879-40d9-a518-30ce25c191a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23254
18965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2325418965
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2784710131
Short name T2584
Test name
Test status
Simulation time 50678189 ps
CPU time 0.68 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:17:30 PM PDT 24
Peak memory 206192 kb
Host smart-c5395d10-a682-4152-9e55-77a85e542cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2784710131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2784710131
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3348673225
Short name T9
Test name
Test status
Simulation time 3865612603 ps
CPU time 4.24 seconds
Started Jul 09 05:17:19 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206308 kb
Host smart-9f061a77-32e2-4fcb-af5e-50d6bbea804e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3348673225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3348673225
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4085030524
Short name T2179
Test name
Test status
Simulation time 13384852879 ps
CPU time 13.77 seconds
Started Jul 09 05:17:25 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206236 kb
Host smart-ddea2b69-ec44-48a8-997b-4447ebb7062d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4085030524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4085030524
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3973725881
Short name T2132
Test name
Test status
Simulation time 23381531230 ps
CPU time 21.09 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206304 kb
Host smart-55329c5d-cb4b-47a5-b267-4e02b3afc961
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3973725881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3973725881
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.940455424
Short name T393
Test name
Test status
Simulation time 159471398 ps
CPU time 0.84 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:23 PM PDT 24
Peak memory 206156 kb
Host smart-a116c0e3-b704-4739-8601-3337a5284bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94045
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.940455424
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.956942356
Short name T1365
Test name
Test status
Simulation time 139719583 ps
CPU time 0.79 seconds
Started Jul 09 05:17:24 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206124 kb
Host smart-c218cde3-08e8-42f0-897b-06546a2f372b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95694
2356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.956942356
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2089945439
Short name T1603
Test name
Test status
Simulation time 372397346 ps
CPU time 1.29 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206004 kb
Host smart-40c1d549-04ae-43a7-8f55-3d7d18772bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20899
45439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2089945439
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3684311187
Short name T2550
Test name
Test status
Simulation time 1166999972 ps
CPU time 2.83 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:30 PM PDT 24
Peak memory 206388 kb
Host smart-0fba8edb-7d98-4948-9c2d-01b02f31d719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36843
11187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3684311187
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.710377702
Short name T1023
Test name
Test status
Simulation time 361024577 ps
CPU time 1.14 seconds
Started Jul 09 05:17:22 PM PDT 24
Finished Jul 09 05:17:24 PM PDT 24
Peak memory 206160 kb
Host smart-9d84ec5c-541a-46b3-ae0d-9ece903a4aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71037
7702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.710377702
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.385780201
Short name T835
Test name
Test status
Simulation time 163165103 ps
CPU time 0.77 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:23 PM PDT 24
Peak memory 206116 kb
Host smart-d5b1521c-e54d-4dcd-a719-ea559193041d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.385780201
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.196571264
Short name T1738
Test name
Test status
Simulation time 36894146 ps
CPU time 0.64 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206128 kb
Host smart-671e3c70-edaa-4116-bfe1-41c75932c535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19657
1264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.196571264
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.523078741
Short name T1412
Test name
Test status
Simulation time 1049978293 ps
CPU time 2.21 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206308 kb
Host smart-098f6d6e-6eb4-4827-9780-5c1b5ef873e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52307
8741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.523078741
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4199443000
Short name T1076
Test name
Test status
Simulation time 264984701 ps
CPU time 1.84 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206204 kb
Host smart-ebf83190-5878-4882-a6a0-d0fc6ee45e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41994
43000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4199443000
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1430749432
Short name T1186
Test name
Test status
Simulation time 182862020 ps
CPU time 0.85 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:23 PM PDT 24
Peak memory 206144 kb
Host smart-659305a2-249f-404c-a75a-34a5306fb997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14307
49432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1430749432
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2220073856
Short name T2427
Test name
Test status
Simulation time 151771429 ps
CPU time 0.78 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:17:23 PM PDT 24
Peak memory 206140 kb
Host smart-4acffaf8-7e6b-485f-ae8f-e2ef931f912a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22200
73856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2220073856
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1067191321
Short name T1154
Test name
Test status
Simulation time 191559743 ps
CPU time 0.86 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206160 kb
Host smart-616e3cfb-0c89-4844-a43d-80d62f381f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10671
91321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1067191321
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1937887175
Short name T1533
Test name
Test status
Simulation time 181656300 ps
CPU time 0.81 seconds
Started Jul 09 05:17:24 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206160 kb
Host smart-7d3813ca-d4b2-405b-a251-e39d0cbd4e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378
87175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1937887175
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.671843966
Short name T20
Test name
Test status
Simulation time 23348658364 ps
CPU time 22.32 seconds
Started Jul 09 05:17:25 PM PDT 24
Finished Jul 09 05:17:49 PM PDT 24
Peak memory 206080 kb
Host smart-86312c2a-4015-45f1-8ad0-d6cff4d7062f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67184
3966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.671843966
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.59537080
Short name T2217
Test name
Test status
Simulation time 3336516829 ps
CPU time 4.12 seconds
Started Jul 09 05:17:24 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206196 kb
Host smart-926995a6-0470-47ce-b1b6-d2d970bf4d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59537
080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.59537080
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3955383383
Short name T415
Test name
Test status
Simulation time 11572986378 ps
CPU time 329.72 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:22:52 PM PDT 24
Peak memory 206412 kb
Host smart-f9402590-6aae-4000-adb2-d2e94087dd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
83383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3955383383
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2331857575
Short name T996
Test name
Test status
Simulation time 5919629613 ps
CPU time 164.07 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:20:07 PM PDT 24
Peak memory 206232 kb
Host smart-1b4309ff-b2ea-4d48-a51a-484894ae0df0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2331857575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2331857575
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3012080551
Short name T990
Test name
Test status
Simulation time 235337197 ps
CPU time 0.91 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206036 kb
Host smart-baf80b7f-7d46-4b4f-b1f3-61f1ac2e1ac1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3012080551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3012080551
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.896226884
Short name T2393
Test name
Test status
Simulation time 196590376 ps
CPU time 0.89 seconds
Started Jul 09 05:17:20 PM PDT 24
Finished Jul 09 05:17:22 PM PDT 24
Peak memory 206112 kb
Host smart-126371d3-1930-4175-a56b-7831631ee3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89622
6884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.896226884
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.818992802
Short name T2359
Test name
Test status
Simulation time 5261822129 ps
CPU time 153.25 seconds
Started Jul 09 05:17:24 PM PDT 24
Finished Jul 09 05:19:59 PM PDT 24
Peak memory 206424 kb
Host smart-8ffbd1b3-c727-40af-a1c9-958a30271bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81899
2802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.818992802
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3678468352
Short name T2518
Test name
Test status
Simulation time 4392062416 ps
CPU time 122.58 seconds
Started Jul 09 05:17:21 PM PDT 24
Finished Jul 09 05:19:25 PM PDT 24
Peak memory 206396 kb
Host smart-bb5c93f1-b736-445d-99a3-f187554e01e9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3678468352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3678468352
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.166908778
Short name T352
Test name
Test status
Simulation time 175411865 ps
CPU time 0.85 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206120 kb
Host smart-787864f3-4855-43ed-a971-665ed823e7eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=166908778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.166908778
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2337375587
Short name T946
Test name
Test status
Simulation time 211183324 ps
CPU time 0.83 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206120 kb
Host smart-4ffd0d67-4151-44e4-9d80-180fdcd80991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
75587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2337375587
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2042039477
Short name T138
Test name
Test status
Simulation time 227689377 ps
CPU time 0.95 seconds
Started Jul 09 05:17:25 PM PDT 24
Finished Jul 09 05:17:28 PM PDT 24
Peak memory 206016 kb
Host smart-16efc82c-8217-4267-8030-49fb601c3a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20420
39477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2042039477
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1567622583
Short name T2578
Test name
Test status
Simulation time 162299451 ps
CPU time 0.87 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206108 kb
Host smart-b4f6892f-972a-4fb3-9958-e0d4ddb79c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15676
22583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1567622583
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3719570170
Short name T1012
Test name
Test status
Simulation time 192017702 ps
CPU time 0.83 seconds
Started Jul 09 05:17:22 PM PDT 24
Finished Jul 09 05:17:24 PM PDT 24
Peak memory 206056 kb
Host smart-09e10da7-90bb-4f8c-8b65-c04441050f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195
70170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3719570170
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.4057919167
Short name T667
Test name
Test status
Simulation time 183651494 ps
CPU time 0.84 seconds
Started Jul 09 05:17:23 PM PDT 24
Finished Jul 09 05:17:25 PM PDT 24
Peak memory 206068 kb
Host smart-1c7193b7-ec8b-4427-a9c7-7e2b7c4f622c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40579
19167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.4057919167
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3670296292
Short name T2254
Test name
Test status
Simulation time 177610941 ps
CPU time 0.77 seconds
Started Jul 09 05:17:24 PM PDT 24
Finished Jul 09 05:17:26 PM PDT 24
Peak memory 206164 kb
Host smart-b988d34c-5eb6-445b-96fd-033354109e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
96292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3670296292
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1199162069
Short name T2261
Test name
Test status
Simulation time 251373374 ps
CPU time 1.13 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206104 kb
Host smart-c72bc75f-b10d-44dd-950c-73d598caeb87
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1199162069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1199162069
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3808513820
Short name T1244
Test name
Test status
Simulation time 144724288 ps
CPU time 0.81 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206120 kb
Host smart-cecc7675-e07c-49d4-b14b-364fa3640602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38085
13820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3808513820
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3701832161
Short name T1882
Test name
Test status
Simulation time 113799693 ps
CPU time 0.75 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 205996 kb
Host smart-39dbeb0e-8e56-498e-935d-122f783c8faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
32161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3701832161
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2694407883
Short name T902
Test name
Test status
Simulation time 20389546211 ps
CPU time 47.74 seconds
Started Jul 09 05:17:28 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206476 kb
Host smart-3e003d6e-c019-411a-8d3a-53665014921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26944
07883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2694407883
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.41575659
Short name T474
Test name
Test status
Simulation time 195038927 ps
CPU time 0.87 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206056 kb
Host smart-d663cc99-09fe-4cfe-be58-d304ae1f0895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.41575659
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3104171570
Short name T2417
Test name
Test status
Simulation time 152480520 ps
CPU time 0.81 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:28 PM PDT 24
Peak memory 206064 kb
Host smart-0f7678b7-e601-4217-a244-d78998400236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31041
71570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3104171570
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.182512496
Short name T1352
Test name
Test status
Simulation time 279647297 ps
CPU time 1.02 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206116 kb
Host smart-b7eaae90-a036-41aa-a011-aff78f8045f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18251
2496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.182512496
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3881326641
Short name T778
Test name
Test status
Simulation time 180667474 ps
CPU time 0.87 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:17:30 PM PDT 24
Peak memory 206088 kb
Host smart-43798617-d693-4af7-9557-94ca2f5d78a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
26641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3881326641
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.330884642
Short name T2420
Test name
Test status
Simulation time 176974836 ps
CPU time 0.86 seconds
Started Jul 09 05:17:28 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206028 kb
Host smart-059c1861-e3c4-49dd-a9ca-957b5caa4b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33088
4642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.330884642
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2818096174
Short name T840
Test name
Test status
Simulation time 153015536 ps
CPU time 0.74 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206056 kb
Host smart-c849bd12-8d36-4b5e-86aa-b72fe9273160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
96174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2818096174
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.829959553
Short name T531
Test name
Test status
Simulation time 243942636 ps
CPU time 0.87 seconds
Started Jul 09 05:17:25 PM PDT 24
Finished Jul 09 05:17:27 PM PDT 24
Peak memory 206068 kb
Host smart-cddb35d0-dca4-49a8-9e9a-dddb550e0290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82995
9553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.829959553
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1900441992
Short name T2300
Test name
Test status
Simulation time 247393967 ps
CPU time 1.07 seconds
Started Jul 09 05:17:28 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206024 kb
Host smart-7a1da90e-39d1-414f-9597-13c6d082feb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004
41992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1900441992
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.240836715
Short name T1714
Test name
Test status
Simulation time 4971040848 ps
CPU time 35.23 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206464 kb
Host smart-a3b3c68b-b92f-4c81-865d-ed5f5e37d936
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=240836715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.240836715
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.467597413
Short name T955
Test name
Test status
Simulation time 216561109 ps
CPU time 0.93 seconds
Started Jul 09 05:17:28 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206144 kb
Host smart-3f6573c4-ba5f-4e3a-8a5e-090a35cecab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46759
7413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.467597413
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1967678458
Short name T2168
Test name
Test status
Simulation time 178580734 ps
CPU time 0.84 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206116 kb
Host smart-7b4817be-272b-4468-b0f8-e439e9f40ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19676
78458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1967678458
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.459562205
Short name T2156
Test name
Test status
Simulation time 764209010 ps
CPU time 2.08 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206312 kb
Host smart-2daa6a58-0fb6-416d-b1a8-02bb56ad2c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45956
2205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.459562205
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.622709582
Short name T857
Test name
Test status
Simulation time 4805276129 ps
CPU time 32.91 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:18:02 PM PDT 24
Peak memory 206280 kb
Host smart-4f1a0bb2-7c83-410c-b457-291eee7ece79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62270
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.622709582
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.540704397
Short name T2440
Test name
Test status
Simulation time 44187325 ps
CPU time 0.69 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206136 kb
Host smart-71dd8e22-b979-4ebc-8fd3-24d134656e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=540704397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.540704397
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.670671590
Short name T1612
Test name
Test status
Simulation time 4211893562 ps
CPU time 5.8 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 206316 kb
Host smart-82ead734-5416-4ffa-900c-7c164d46ea1f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=670671590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.670671590
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3808099006
Short name T1937
Test name
Test status
Simulation time 13384663056 ps
CPU time 13.63 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206164 kb
Host smart-2414624f-481c-4d72-b1f8-99d4a9f94d0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3808099006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3808099006
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3376665862
Short name T11
Test name
Test status
Simulation time 23386719807 ps
CPU time 24.57 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206100 kb
Host smart-52a77ba2-822d-4f0d-a752-d07e84ce6fe2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3376665862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3376665862
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2636460234
Short name T1969
Test name
Test status
Simulation time 144206104 ps
CPU time 0.79 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:28 PM PDT 24
Peak memory 206120 kb
Host smart-d22fa354-dd29-4773-9253-55952cddabf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26364
60234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2636460234
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3857609125
Short name T1444
Test name
Test status
Simulation time 149659153 ps
CPU time 0.79 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:17:30 PM PDT 24
Peak memory 206056 kb
Host smart-a0503889-855e-47c3-b013-3dbcc0c129f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576
09125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3857609125
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3877157644
Short name T176
Test name
Test status
Simulation time 240156424 ps
CPU time 1.04 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 205952 kb
Host smart-4102ef30-5764-4ecc-86bb-44a5dd2c693c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38771
57644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3877157644
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.709185683
Short name T762
Test name
Test status
Simulation time 679708603 ps
CPU time 1.78 seconds
Started Jul 09 05:17:28 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 206344 kb
Host smart-17842ba7-1858-47c4-9dff-04e9930f9686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70918
5683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.709185683
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.55625551
Short name T95
Test name
Test status
Simulation time 6916567724 ps
CPU time 13.92 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206380 kb
Host smart-a63a6544-fac3-4ce3-8d8b-d7af3552ab25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55625
551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.55625551
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.741443172
Short name T81
Test name
Test status
Simulation time 325927226 ps
CPU time 1.19 seconds
Started Jul 09 05:17:27 PM PDT 24
Finished Jul 09 05:17:30 PM PDT 24
Peak memory 206160 kb
Host smart-6fd4fb64-2354-447f-a881-05eb679a9d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74144
3172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.741443172
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.578980832
Short name T561
Test name
Test status
Simulation time 145547931 ps
CPU time 0.81 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206104 kb
Host smart-7e8d9d76-103e-48c9-b44f-bb5a8f6d86ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57898
0832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.578980832
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2542007436
Short name T2500
Test name
Test status
Simulation time 58867408 ps
CPU time 0.71 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:29 PM PDT 24
Peak memory 206116 kb
Host smart-a50dd10e-90c4-4647-874a-70f8dab6d55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
07436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2542007436
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.4140950128
Short name T554
Test name
Test status
Simulation time 853068558 ps
CPU time 2.05 seconds
Started Jul 09 05:17:30 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 206360 kb
Host smart-6f77794b-1d99-486a-868c-c20c4a28baaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
50128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.4140950128
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3004515085
Short name T665
Test name
Test status
Simulation time 184905544 ps
CPU time 2.32 seconds
Started Jul 09 05:17:26 PM PDT 24
Finished Jul 09 05:17:30 PM PDT 24
Peak memory 206372 kb
Host smart-c7df9721-624c-4c1f-b797-a7c590cb462b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30045
15085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3004515085
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3782076049
Short name T2659
Test name
Test status
Simulation time 166584448 ps
CPU time 0.82 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 206100 kb
Host smart-0d96eec5-e2a7-450a-b5b0-fd450968911a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37820
76049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3782076049
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3380807540
Short name T1910
Test name
Test status
Simulation time 136502167 ps
CPU time 0.81 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 206368 kb
Host smart-16693a91-7e23-4c49-a7e9-a3c36cc9db74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33808
07540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3380807540
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2920884807
Short name T360
Test name
Test status
Simulation time 232053527 ps
CPU time 1 seconds
Started Jul 09 05:17:30 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 205992 kb
Host smart-89b05a1b-6421-45d0-aaa4-c693f82fdde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
84807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2920884807
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1600075490
Short name T1988
Test name
Test status
Simulation time 188111767 ps
CPU time 0.83 seconds
Started Jul 09 05:17:36 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206112 kb
Host smart-28ab9258-f798-41da-b6d8-1718c5fcf57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16000
75490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1600075490
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1532169814
Short name T1363
Test name
Test status
Simulation time 23350100962 ps
CPU time 27 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206184 kb
Host smart-b9b0023f-faa5-473e-8e78-5296d545653a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15321
69814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1532169814
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.231868335
Short name T1670
Test name
Test status
Simulation time 3261936727 ps
CPU time 4.32 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206204 kb
Host smart-64d25170-491e-4b5c-b5c8-81da8dc2a118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
8335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.231868335
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.932497246
Short name T2099
Test name
Test status
Simulation time 7474124619 ps
CPU time 72.94 seconds
Started Jul 09 05:17:30 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206460 kb
Host smart-32bfb927-fb29-456e-b313-57108eede373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93249
7246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.932497246
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1769321739
Short name T2224
Test name
Test status
Simulation time 5127133003 ps
CPU time 48.8 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:18:23 PM PDT 24
Peak memory 206188 kb
Host smart-b8b91b0f-502c-4af0-9265-cbc0711ca060
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1769321739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1769321739
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3954438529
Short name T824
Test name
Test status
Simulation time 252804915 ps
CPU time 0.95 seconds
Started Jul 09 05:17:32 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 206140 kb
Host smart-9405eab0-7714-4bd8-a568-4e6e98ed8893
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3954438529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3954438529
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.884344478
Short name T1167
Test name
Test status
Simulation time 207697830 ps
CPU time 0.9 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206084 kb
Host smart-d439a5ec-054c-471a-aab5-016bd6627d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88434
4478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.884344478
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.42171701
Short name T2035
Test name
Test status
Simulation time 7100755908 ps
CPU time 203.41 seconds
Started Jul 09 05:17:32 PM PDT 24
Finished Jul 09 05:20:57 PM PDT 24
Peak memory 206436 kb
Host smart-3c08c93a-f423-4557-bce9-bbaab91f7df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42171
701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.42171701
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.4036427523
Short name T2601
Test name
Test status
Simulation time 3238475619 ps
CPU time 22.32 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 206376 kb
Host smart-dc186919-9ecb-4e54-a65b-2e58995dff5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4036427523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.4036427523
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.4070051910
Short name T2546
Test name
Test status
Simulation time 164853382 ps
CPU time 0.85 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 206124 kb
Host smart-9bbd8f5f-a263-4687-a200-f6424beeefb9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4070051910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.4070051910
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.876738550
Short name T1638
Test name
Test status
Simulation time 138000852 ps
CPU time 0.79 seconds
Started Jul 09 05:17:32 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 206152 kb
Host smart-c9c43303-f088-4999-b493-d8754eaea826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87673
8550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.876738550
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2279894671
Short name T142
Test name
Test status
Simulation time 246674144 ps
CPU time 0.94 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 206128 kb
Host smart-0b0ba331-0078-46d7-af7f-139217a7c1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22798
94671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2279894671
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3332256036
Short name T100
Test name
Test status
Simulation time 180665116 ps
CPU time 0.81 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 206116 kb
Host smart-c723057b-b013-4d0a-b223-519892eb62bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
56036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3332256036
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.4083814627
Short name T2
Test name
Test status
Simulation time 169235922 ps
CPU time 0.85 seconds
Started Jul 09 05:17:29 PM PDT 24
Finished Jul 09 05:17:32 PM PDT 24
Peak memory 206092 kb
Host smart-c0e0c354-4487-4100-b2f2-0cfb51c0de97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
14627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.4083814627
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3662242097
Short name T2397
Test name
Test status
Simulation time 147475261 ps
CPU time 0.89 seconds
Started Jul 09 05:17:36 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206112 kb
Host smart-4c3125e1-91a5-4016-abcb-077ada6c9423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36622
42097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3662242097
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2819999993
Short name T2225
Test name
Test status
Simulation time 200078089 ps
CPU time 0.87 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 205924 kb
Host smart-5c8a3942-bf02-4ccd-b415-3cb9e3964ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28199
99993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2819999993
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3362533582
Short name T490
Test name
Test status
Simulation time 196437648 ps
CPU time 0.95 seconds
Started Jul 09 05:17:32 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206036 kb
Host smart-f49295f2-25db-4856-96d6-5bc7a0e45350
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3362533582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3362533582
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1567299230
Short name T2107
Test name
Test status
Simulation time 144826915 ps
CPU time 0.77 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 206128 kb
Host smart-31ecf654-6b8e-43dd-af53-6a4ea25bf1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15672
99230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1567299230
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3110288282
Short name T2637
Test name
Test status
Simulation time 54930497 ps
CPU time 0.64 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 206124 kb
Host smart-c4c401ae-ed88-40ba-be39-0406434ce6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31102
88282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3110288282
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2096655652
Short name T1641
Test name
Test status
Simulation time 9968449793 ps
CPU time 24.8 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 206476 kb
Host smart-9c3e8c65-9039-4e4d-9f50-d9c08a761e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20966
55652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2096655652
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.702593829
Short name T519
Test name
Test status
Simulation time 191459954 ps
CPU time 0.89 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206084 kb
Host smart-9d9aed4a-de90-4298-8a2d-cf3640a2e012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70259
3829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.702593829
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.876184959
Short name T1740
Test name
Test status
Simulation time 317324825 ps
CPU time 1.15 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:17:36 PM PDT 24
Peak memory 206144 kb
Host smart-06f97f67-4252-4603-964a-6cab0fcaf6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87618
4959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.876184959
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2430932570
Short name T2537
Test name
Test status
Simulation time 161612296 ps
CPU time 0.79 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206076 kb
Host smart-57db9291-5065-4d0d-af21-5c8baae6cd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24309
32570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2430932570
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2049569092
Short name T987
Test name
Test status
Simulation time 196319387 ps
CPU time 0.82 seconds
Started Jul 09 05:17:30 PM PDT 24
Finished Jul 09 05:17:33 PM PDT 24
Peak memory 206160 kb
Host smart-1263ad4c-50cb-44f7-8f7c-600eea4d0559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495
69092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2049569092
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2858974174
Short name T2034
Test name
Test status
Simulation time 184608424 ps
CPU time 0.84 seconds
Started Jul 09 05:17:34 PM PDT 24
Finished Jul 09 05:17:36 PM PDT 24
Peak memory 206120 kb
Host smart-5b070219-7016-4896-9e3f-9cf9c50132c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28589
74174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2858974174
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3532708968
Short name T2638
Test name
Test status
Simulation time 150787783 ps
CPU time 0.81 seconds
Started Jul 09 05:17:34 PM PDT 24
Finished Jul 09 05:17:36 PM PDT 24
Peak memory 206064 kb
Host smart-e1f41d4c-08a2-423b-9818-4571f9ab514a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
08968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3532708968
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.769209797
Short name T942
Test name
Test status
Simulation time 146146480 ps
CPU time 0.78 seconds
Started Jul 09 05:17:34 PM PDT 24
Finished Jul 09 05:17:36 PM PDT 24
Peak memory 206108 kb
Host smart-0ec731f5-6368-4930-9bae-817057b8b501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76920
9797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.769209797
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1277829075
Short name T1708
Test name
Test status
Simulation time 214834433 ps
CPU time 1.01 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206112 kb
Host smart-8ff52d0c-f63f-43c2-9078-eae765d0baae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12778
29075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1277829075
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.76013518
Short name T1526
Test name
Test status
Simulation time 4495886176 ps
CPU time 126.5 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:19:42 PM PDT 24
Peak memory 206360 kb
Host smart-b3a3f2ff-8201-4cd2-b1cb-ee77cbead696
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=76013518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.76013518
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2442013224
Short name T633
Test name
Test status
Simulation time 162021585 ps
CPU time 0.83 seconds
Started Jul 09 05:17:37 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 206116 kb
Host smart-c3736e70-f956-41b4-a26a-679a35323086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24420
13224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2442013224
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2550018907
Short name T1177
Test name
Test status
Simulation time 155598939 ps
CPU time 0.9 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:17:35 PM PDT 24
Peak memory 206372 kb
Host smart-461c2f76-1759-4ec2-af1c-8767058aae25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25500
18907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2550018907
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2585948440
Short name T1333
Test name
Test status
Simulation time 991745292 ps
CPU time 2.24 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:17:38 PM PDT 24
Peak memory 206376 kb
Host smart-0c883187-b49d-4e76-9ad7-3473e39591f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25859
48440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2585948440
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1612631062
Short name T908
Test name
Test status
Simulation time 4487143460 ps
CPU time 120.86 seconds
Started Jul 09 05:17:32 PM PDT 24
Finished Jul 09 05:19:34 PM PDT 24
Peak memory 206420 kb
Host smart-315cb9c8-a40c-4705-a63f-aa0db75d86ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16126
31062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1612631062
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1373878727
Short name T2428
Test name
Test status
Simulation time 36204371 ps
CPU time 0.73 seconds
Started Jul 09 05:17:43 PM PDT 24
Finished Jul 09 05:17:44 PM PDT 24
Peak memory 206092 kb
Host smart-6d29a222-7f51-4baa-b19e-16266dcf353d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1373878727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1373878727
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2649518605
Short name T2171
Test name
Test status
Simulation time 3567255368 ps
CPU time 4.5 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 206068 kb
Host smart-514c1e2a-e2c8-47e8-9f54-8f43e0f1fb3e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2649518605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2649518605
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.112178938
Short name T2019
Test name
Test status
Simulation time 13316085899 ps
CPU time 12.95 seconds
Started Jul 09 05:17:37 PM PDT 24
Finished Jul 09 05:17:50 PM PDT 24
Peak memory 206208 kb
Host smart-7fc2e9f8-6fea-450b-8bfd-514be800b69f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=112178938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.112178938
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2408531457
Short name T1991
Test name
Test status
Simulation time 23360866165 ps
CPU time 29.11 seconds
Started Jul 09 05:17:33 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206340 kb
Host smart-0fbeffe8-0363-4bac-b200-45516bdce378
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2408531457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.2408531457
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1254881788
Short name T1707
Test name
Test status
Simulation time 159684419 ps
CPU time 0.82 seconds
Started Jul 09 05:17:34 PM PDT 24
Finished Jul 09 05:17:36 PM PDT 24
Peak memory 206156 kb
Host smart-0fb7707d-411e-4989-9b2d-b7c4a88ee10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
81788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1254881788
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.4197175367
Short name T794
Test name
Test status
Simulation time 146849041 ps
CPU time 0.82 seconds
Started Jul 09 05:17:35 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206084 kb
Host smart-62f5cda9-d27f-472a-aa5d-8590a0e8336f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41971
75367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.4197175367
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.223760796
Short name T1853
Test name
Test status
Simulation time 485261954 ps
CPU time 1.6 seconds
Started Jul 09 05:17:31 PM PDT 24
Finished Jul 09 05:17:34 PM PDT 24
Peak memory 206036 kb
Host smart-4d7616e5-4ad4-4447-9683-109302771192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22376
0796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.223760796
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.814526260
Short name T2112
Test name
Test status
Simulation time 461779975 ps
CPU time 1.37 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206148 kb
Host smart-40e29540-8e9d-440b-92b2-58737b65aad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81452
6260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.814526260
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1286476204
Short name T1062
Test name
Test status
Simulation time 7884241799 ps
CPU time 16.64 seconds
Started Jul 09 05:17:40 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 206436 kb
Host smart-aeea2cee-dde4-45da-b6c4-fd31e561f806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12864
76204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1286476204
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2236321429
Short name T1736
Test name
Test status
Simulation time 473408415 ps
CPU time 1.44 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206096 kb
Host smart-b3031e67-0298-4fb7-9ef0-e0b4d40dd229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22363
21429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2236321429
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2747691667
Short name T518
Test name
Test status
Simulation time 154434406 ps
CPU time 0.79 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206132 kb
Host smart-4974702d-b4b4-4e4f-b795-13ecad2b023a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27476
91667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2747691667
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3169296464
Short name T1893
Test name
Test status
Simulation time 71202384 ps
CPU time 0.71 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 206048 kb
Host smart-32f542cb-77c0-4383-984c-799dba503fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
96464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3169296464
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3107309001
Short name T2102
Test name
Test status
Simulation time 841397214 ps
CPU time 1.98 seconds
Started Jul 09 05:17:37 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206412 kb
Host smart-8a88c9e1-6160-41a7-b54e-3ccaf6c6d84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31073
09001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3107309001
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1059448273
Short name T2351
Test name
Test status
Simulation time 185074602 ps
CPU time 1.27 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206208 kb
Host smart-0d778aa5-9fa0-4b8c-84ba-b6bc283c5eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10594
48273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1059448273
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2477991454
Short name T2544
Test name
Test status
Simulation time 202165452 ps
CPU time 0.86 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206056 kb
Host smart-33f21e74-904e-4356-a221-a16b50b2dd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
91454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2477991454
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2952206785
Short name T1111
Test name
Test status
Simulation time 181936300 ps
CPU time 0.84 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206116 kb
Host smart-69c164a9-e1ac-45fd-9983-a4fb31fd7615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29522
06785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2952206785
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2165080161
Short name T2082
Test name
Test status
Simulation time 225946613 ps
CPU time 0.94 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 206016 kb
Host smart-379f96d7-ed5f-4a60-ad44-3464113f059f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
80161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2165080161
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.333157849
Short name T2334
Test name
Test status
Simulation time 4999202707 ps
CPU time 134.53 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:19:54 PM PDT 24
Peak memory 206424 kb
Host smart-191bc9bf-f7f4-453e-b579-d77efd4731c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=333157849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.333157849
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.4236479025
Short name T479
Test name
Test status
Simulation time 189620369 ps
CPU time 0.89 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 205992 kb
Host smart-9acf642b-1582-4612-b1cc-cd84e07a669f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
79025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4236479025
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1766414468
Short name T1558
Test name
Test status
Simulation time 23304748162 ps
CPU time 26.92 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206128 kb
Host smart-6da25754-a7ca-409e-8706-f281f5dbcc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17664
14468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1766414468
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.498446870
Short name T1428
Test name
Test status
Simulation time 3342637035 ps
CPU time 4.65 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:17:45 PM PDT 24
Peak memory 206192 kb
Host smart-a2b78277-a73f-4629-b82e-054011a3e4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49844
6870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.498446870
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3845631268
Short name T915
Test name
Test status
Simulation time 7290305172 ps
CPU time 210.41 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:21:11 PM PDT 24
Peak memory 206408 kb
Host smart-07544b2c-1f3c-454a-b6bc-b54bfdc104c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38456
31268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3845631268
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.757741921
Short name T1344
Test name
Test status
Simulation time 5086528442 ps
CPU time 36.98 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:18:31 PM PDT 24
Peak memory 206232 kb
Host smart-d8d92ad2-6498-4473-a27d-82c9434bc7a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=757741921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.757741921
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.4036510598
Short name T1754
Test name
Test status
Simulation time 247854853 ps
CPU time 0.99 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206092 kb
Host smart-3d489d7e-6e7d-4054-9b42-505264b4eabf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4036510598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.4036510598
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1567855159
Short name T2380
Test name
Test status
Simulation time 224372687 ps
CPU time 0.96 seconds
Started Jul 09 05:17:38 PM PDT 24
Finished Jul 09 05:17:40 PM PDT 24
Peak memory 206112 kb
Host smart-801dbec9-874f-40b6-a4ca-3dd2cb0b86b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
55159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1567855159
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2565999179
Short name T1818
Test name
Test status
Simulation time 6912111544 ps
CPU time 62.96 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206468 kb
Host smart-fe8b00ae-9777-477a-b358-971f5113b845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25659
99179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2565999179
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.772157058
Short name T698
Test name
Test status
Simulation time 4987189155 ps
CPU time 137.44 seconds
Started Jul 09 05:17:41 PM PDT 24
Finished Jul 09 05:19:59 PM PDT 24
Peak memory 206400 kb
Host smart-52cbcc33-7309-4963-9330-f153e8fffa46
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=772157058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.772157058
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3662874291
Short name T2683
Test name
Test status
Simulation time 149533548 ps
CPU time 0.84 seconds
Started Jul 09 05:17:39 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206124 kb
Host smart-0be672dc-6acc-468a-a4cb-a78105930097
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3662874291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3662874291
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3913794001
Short name T2276
Test name
Test status
Simulation time 149704253 ps
CPU time 0.81 seconds
Started Jul 09 05:17:40 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206164 kb
Host smart-80f37a7f-d63d-4c84-afe9-18ef5d3c22ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39137
94001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3913794001
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1990722471
Short name T134
Test name
Test status
Simulation time 242439330 ps
CPU time 0.93 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206004 kb
Host smart-c9519de5-f790-481c-9183-7e6857d0fa8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
22471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1990722471
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2730929931
Short name T646
Test name
Test status
Simulation time 175903682 ps
CPU time 0.87 seconds
Started Jul 09 05:17:41 PM PDT 24
Finished Jul 09 05:17:43 PM PDT 24
Peak memory 205988 kb
Host smart-eddba5fc-44e5-43d4-9d20-7057950f879f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
29931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2730929931
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.221939723
Short name T509
Test name
Test status
Simulation time 213406961 ps
CPU time 0.87 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206160 kb
Host smart-ca533d83-f9ab-457c-bb93-ec78ee4ff5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22193
9723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.221939723
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2821682889
Short name T2051
Test name
Test status
Simulation time 154601982 ps
CPU time 0.85 seconds
Started Jul 09 05:17:44 PM PDT 24
Finished Jul 09 05:17:46 PM PDT 24
Peak memory 206164 kb
Host smart-7786e5d4-ed95-44e6-a343-31557eb7c0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28216
82889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2821682889
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2808938434
Short name T1503
Test name
Test status
Simulation time 176754023 ps
CPU time 0.86 seconds
Started Jul 09 05:17:43 PM PDT 24
Finished Jul 09 05:17:44 PM PDT 24
Peak memory 206164 kb
Host smart-8b753250-e203-4154-9907-d38f394361f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28089
38434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2808938434
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2681135320
Short name T2130
Test name
Test status
Simulation time 229081861 ps
CPU time 1.02 seconds
Started Jul 09 05:17:45 PM PDT 24
Finished Jul 09 05:17:46 PM PDT 24
Peak memory 206088 kb
Host smart-8e49aa36-0f1c-4d6c-9325-c8835e8d0e11
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2681135320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2681135320
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3288196284
Short name T1810
Test name
Test status
Simulation time 136230472 ps
CPU time 0.74 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206004 kb
Host smart-26bdd8de-b5f2-4faf-85eb-c1abdf1ef323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881
96284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3288196284
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1094550376
Short name T2155
Test name
Test status
Simulation time 39220063 ps
CPU time 0.67 seconds
Started Jul 09 05:17:41 PM PDT 24
Finished Jul 09 05:17:43 PM PDT 24
Peak memory 206108 kb
Host smart-cd3a0c6d-4c82-4f69-a662-2a2c3a0af1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10945
50376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1094550376
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.447540506
Short name T1860
Test name
Test status
Simulation time 19598986535 ps
CPU time 43.32 seconds
Started Jul 09 05:17:44 PM PDT 24
Finished Jul 09 05:18:28 PM PDT 24
Peak memory 206472 kb
Host smart-c0df870b-9c2d-4ec3-8bb9-3d98acc573c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44754
0506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.447540506
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1656336816
Short name T1302
Test name
Test status
Simulation time 193715325 ps
CPU time 0.87 seconds
Started Jul 09 05:17:43 PM PDT 24
Finished Jul 09 05:17:45 PM PDT 24
Peak memory 206140 kb
Host smart-9247d149-d9f9-4942-87d9-1565b8e65bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16563
36816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1656336816
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.669225489
Short name T499
Test name
Test status
Simulation time 245120365 ps
CPU time 0.9 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 205996 kb
Host smart-21c6eca3-545b-467c-89bc-0a84795c3783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66922
5489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.669225489
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2311270384
Short name T1310
Test name
Test status
Simulation time 166715200 ps
CPU time 0.85 seconds
Started Jul 09 05:17:46 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206096 kb
Host smart-4509588c-0fa0-451c-a47f-57bfcbae6fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23112
70384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2311270384
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1795030088
Short name T2387
Test name
Test status
Simulation time 142446742 ps
CPU time 0.9 seconds
Started Jul 09 05:17:44 PM PDT 24
Finished Jul 09 05:17:45 PM PDT 24
Peak memory 206020 kb
Host smart-ca03bcd1-1463-4945-9af4-9aba4eebf4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17950
30088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1795030088
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1785028970
Short name T1272
Test name
Test status
Simulation time 200082204 ps
CPU time 0.83 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206000 kb
Host smart-e627a4d6-b563-4b22-bcc4-8117b2dca5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
28970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1785028970
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.959297137
Short name T1672
Test name
Test status
Simulation time 181497966 ps
CPU time 0.8 seconds
Started Jul 09 05:17:45 PM PDT 24
Finished Jul 09 05:17:47 PM PDT 24
Peak memory 206088 kb
Host smart-8e247830-142d-4453-b37b-3ac6b6a4be1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95929
7137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.959297137
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1729360786
Short name T2493
Test name
Test status
Simulation time 153961724 ps
CPU time 0.78 seconds
Started Jul 09 05:17:41 PM PDT 24
Finished Jul 09 05:17:43 PM PDT 24
Peak memory 206064 kb
Host smart-1e412f53-9cad-4689-a89c-195604116720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17293
60786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1729360786
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1690629485
Short name T423
Test name
Test status
Simulation time 294272295 ps
CPU time 1.05 seconds
Started Jul 09 05:17:43 PM PDT 24
Finished Jul 09 05:17:45 PM PDT 24
Peak memory 206148 kb
Host smart-db999ac7-bd9e-487c-b7bc-1984bb7c1da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
29485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1690629485
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1835205320
Short name T1971
Test name
Test status
Simulation time 3631338758 ps
CPU time 97.61 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:19:29 PM PDT 24
Peak memory 206284 kb
Host smart-fecf198f-aa0a-4ba1-a18e-06b613148336
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1835205320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1835205320
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.69807003
Short name T468
Test name
Test status
Simulation time 180098314 ps
CPU time 0.87 seconds
Started Jul 09 05:17:42 PM PDT 24
Finished Jul 09 05:17:43 PM PDT 24
Peak memory 206060 kb
Host smart-341eed08-bcf2-4319-8b1b-da2962cb72b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69807
003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.69807003
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.630334140
Short name T2541
Test name
Test status
Simulation time 180952269 ps
CPU time 0.89 seconds
Started Jul 09 05:17:42 PM PDT 24
Finished Jul 09 05:17:43 PM PDT 24
Peak memory 206120 kb
Host smart-0c8ef677-65a0-4c54-8f68-7aa9af191994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63033
4140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.630334140
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2736670495
Short name T2657
Test name
Test status
Simulation time 935308989 ps
CPU time 2.22 seconds
Started Jul 09 05:17:45 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 206292 kb
Host smart-c1280962-516c-42bc-8446-3feedc2e85d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
70495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2736670495
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3883737821
Short name T2041
Test name
Test status
Simulation time 4961419563 ps
CPU time 44.41 seconds
Started Jul 09 05:17:42 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206412 kb
Host smart-1092f3d1-0856-4f61-a839-f0265a9b6ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38837
37821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3883737821
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1437107002
Short name T1294
Test name
Test status
Simulation time 35789944 ps
CPU time 0.68 seconds
Started Jul 09 05:17:55 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 206080 kb
Host smart-e88e08ec-d152-47c0-b2f4-67d53a75c419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1437107002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1437107002
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.982483229
Short name T2258
Test name
Test status
Simulation time 3923495992 ps
CPU time 4.77 seconds
Started Jul 09 05:17:44 PM PDT 24
Finished Jul 09 05:17:49 PM PDT 24
Peak memory 206356 kb
Host smart-284eb35a-f2cd-44d9-8660-15d70cdc029e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=982483229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.982483229
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1232893894
Short name T2144
Test name
Test status
Simulation time 13328837058 ps
CPU time 12.33 seconds
Started Jul 09 05:17:42 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206176 kb
Host smart-96975337-66ab-4ffd-b1ba-49fe547b96ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1232893894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1232893894
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.741799910
Short name T1324
Test name
Test status
Simulation time 23413247510 ps
CPU time 29.86 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:18:19 PM PDT 24
Peak memory 206036 kb
Host smart-3b6c5b81-7a5d-44ea-a1ba-e79c49277d6c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=741799910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.741799910
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1559165052
Short name T1191
Test name
Test status
Simulation time 167225745 ps
CPU time 0.77 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206108 kb
Host smart-c3d5be3f-7d02-4d1b-ae82-cdb060ebeaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591
65052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1559165052
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3060817584
Short name T647
Test name
Test status
Simulation time 202887286 ps
CPU time 0.81 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:50 PM PDT 24
Peak memory 205952 kb
Host smart-6cde9649-cd9d-457c-afbc-a685d390166f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608
17584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3060817584
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1266903832
Short name T1802
Test name
Test status
Simulation time 543782472 ps
CPU time 1.62 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 206356 kb
Host smart-64b0c66d-f85e-4594-bb18-baf270f3fa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12669
03832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1266903832
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2260282744
Short name T106
Test name
Test status
Simulation time 676572569 ps
CPU time 1.63 seconds
Started Jul 09 05:17:45 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 206308 kb
Host smart-9559d7c0-aa58-46d7-b143-f63bcfb05166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602
82744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2260282744
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1131357906
Short name T1261
Test name
Test status
Simulation time 10726739766 ps
CPU time 22.99 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:18:16 PM PDT 24
Peak memory 206416 kb
Host smart-b6fb3059-1046-4680-8c6f-871f5a46c16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
57906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1131357906
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.162827292
Short name T1851
Test name
Test status
Simulation time 537997001 ps
CPU time 1.43 seconds
Started Jul 09 05:17:47 PM PDT 24
Finished Jul 09 05:17:49 PM PDT 24
Peak memory 206068 kb
Host smart-0d38cc60-6f9e-4ba8-8d72-839250a33bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16282
7292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.162827292
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2257721237
Short name T653
Test name
Test status
Simulation time 148022359 ps
CPU time 0.77 seconds
Started Jul 09 05:17:48 PM PDT 24
Finished Jul 09 05:17:49 PM PDT 24
Peak memory 206020 kb
Host smart-1519c2bc-9572-4e1d-9a51-085f3f5f71c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22577
21237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2257721237
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1738757962
Short name T1895
Test name
Test status
Simulation time 49541306 ps
CPU time 0.72 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 206072 kb
Host smart-91d6888e-ff97-42c8-8bed-f59985c424e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17387
57962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1738757962
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.791086423
Short name T1106
Test name
Test status
Simulation time 845173305 ps
CPU time 2.11 seconds
Started Jul 09 05:17:51 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206256 kb
Host smart-34b561ec-f704-4df7-9f23-13f0b092597a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79108
6423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.791086423
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3319238550
Short name T2492
Test name
Test status
Simulation time 182954954 ps
CPU time 2.15 seconds
Started Jul 09 05:17:46 PM PDT 24
Finished Jul 09 05:17:49 PM PDT 24
Peak memory 206308 kb
Host smart-fcf9298c-3463-4b4d-877e-f167a9673312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33192
38550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3319238550
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3893545757
Short name T1406
Test name
Test status
Simulation time 179275052 ps
CPU time 0.9 seconds
Started Jul 09 05:17:45 PM PDT 24
Finished Jul 09 05:17:46 PM PDT 24
Peak memory 206024 kb
Host smart-f45be7a8-3a96-4121-9380-cd45431e9690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38935
45757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3893545757
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3765767508
Short name T811
Test name
Test status
Simulation time 145851751 ps
CPU time 0.76 seconds
Started Jul 09 05:17:51 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 205988 kb
Host smart-84e00639-5d03-42ea-8c8a-b616d490d55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
67508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3765767508
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.4041545465
Short name T2084
Test name
Test status
Simulation time 250155145 ps
CPU time 0.89 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 205952 kb
Host smart-42f25034-62f7-441b-8cc6-63db2f796c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40415
45465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.4041545465
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.1548602953
Short name T661
Test name
Test status
Simulation time 7331301563 ps
CPU time 206.79 seconds
Started Jul 09 05:17:46 PM PDT 24
Finished Jul 09 05:21:14 PM PDT 24
Peak memory 206424 kb
Host smart-ed7ead6d-f898-4eb4-a122-3cb1c79ddfec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1548602953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1548602953
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3284734225
Short name T806
Test name
Test status
Simulation time 231124471 ps
CPU time 0.85 seconds
Started Jul 09 05:17:46 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 206024 kb
Host smart-9bb2ed90-ffde-4259-8852-b6892cb172b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32847
34225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3284734225
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3408919123
Short name T1699
Test name
Test status
Simulation time 23270623174 ps
CPU time 25.57 seconds
Started Jul 09 05:17:48 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206052 kb
Host smart-dde02726-114c-479d-8f58-fb51b2df155a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
19123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3408919123
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3606474052
Short name T2268
Test name
Test status
Simulation time 3332936888 ps
CPU time 3.85 seconds
Started Jul 09 05:17:51 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206204 kb
Host smart-c782bc21-3879-4337-a039-0a478d17938f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36064
74052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3606474052
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.3473145992
Short name T2463
Test name
Test status
Simulation time 7441857896 ps
CPU time 69.04 seconds
Started Jul 09 05:17:46 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206484 kb
Host smart-98cac073-b47b-48ed-8b5b-b9759b01a9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
45992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.3473145992
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2025906500
Short name T400
Test name
Test status
Simulation time 4742635266 ps
CPU time 131.52 seconds
Started Jul 09 05:17:45 PM PDT 24
Finished Jul 09 05:19:58 PM PDT 24
Peak memory 206436 kb
Host smart-53e7e6ab-40c2-43cf-8cdc-9897acc67e10
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2025906500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2025906500
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2048103416
Short name T1274
Test name
Test status
Simulation time 241466813 ps
CPU time 0.89 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206136 kb
Host smart-d70d60b4-7e6e-461a-aef8-468fceb98125
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2048103416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2048103416
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2428653957
Short name T934
Test name
Test status
Simulation time 192442638 ps
CPU time 0.86 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206160 kb
Host smart-863f4358-07ae-49d0-898f-375e82f34b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24286
53957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2428653957
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.4172037197
Short name T1122
Test name
Test status
Simulation time 6190678851 ps
CPU time 174.32 seconds
Started Jul 09 05:17:51 PM PDT 24
Finished Jul 09 05:20:47 PM PDT 24
Peak memory 206424 kb
Host smart-21b6eca6-53a8-47a4-afcd-67bba25b7316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
37197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.4172037197
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3146706055
Short name T470
Test name
Test status
Simulation time 5990570448 ps
CPU time 176.1 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:21:47 PM PDT 24
Peak memory 206304 kb
Host smart-16a14565-2180-44a1-95dc-7393ca4acb8b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3146706055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3146706055
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.4293439341
Short name T2523
Test name
Test status
Simulation time 158893313 ps
CPU time 0.79 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 205932 kb
Host smart-aab759fb-67f3-488e-b0ec-6e54e9856e9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4293439341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.4293439341
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.418771960
Short name T1418
Test name
Test status
Simulation time 146707797 ps
CPU time 0.75 seconds
Started Jul 09 05:17:46 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 206156 kb
Host smart-8581235d-b89b-47b3-9d7c-3aeba0bd47cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41877
1960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.418771960
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1305797233
Short name T122
Test name
Test status
Simulation time 281165579 ps
CPU time 0.91 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 205992 kb
Host smart-61691aa3-2f41-4646-8eb2-f401e9440a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
97233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1305797233
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.51852113
Short name T2522
Test name
Test status
Simulation time 201300957 ps
CPU time 0.85 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:50 PM PDT 24
Peak memory 206124 kb
Host smart-7bf6945b-e630-40ec-9ffe-972144bdcd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51852
113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.51852113
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2842503377
Short name T1010
Test name
Test status
Simulation time 228356145 ps
CPU time 0.89 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:04 PM PDT 24
Peak memory 206088 kb
Host smart-888ea882-f3a4-448a-9a25-0401ddbdbe4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
03377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2842503377
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2406314267
Short name T1593
Test name
Test status
Simulation time 201885369 ps
CPU time 0.84 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 206060 kb
Host smart-18dba4fa-3666-4fac-a9c5-7a1295f2ead9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
14267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2406314267
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3581866257
Short name T2072
Test name
Test status
Simulation time 160693816 ps
CPU time 0.91 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206132 kb
Host smart-e2490f1d-8406-4b52-a87c-12dd6636b373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35818
66257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3581866257
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.957157581
Short name T2682
Test name
Test status
Simulation time 257377566 ps
CPU time 0.96 seconds
Started Jul 09 05:20:18 PM PDT 24
Finished Jul 09 05:20:20 PM PDT 24
Peak memory 206128 kb
Host smart-3506e514-c38d-4441-acd9-4059d42c1414
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=957157581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.957157581
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3389208649
Short name T461
Test name
Test status
Simulation time 137545548 ps
CPU time 0.8 seconds
Started Jul 09 05:17:51 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 206148 kb
Host smart-7071b9de-bc83-471f-b5e0-6a75bec9c193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33892
08649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3389208649
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4042797161
Short name T2655
Test name
Test status
Simulation time 35830041 ps
CPU time 0.68 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206080 kb
Host smart-9d7ae7ba-a427-4c0d-8f06-f30316428591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40427
97161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4042797161
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2051593264
Short name T2097
Test name
Test status
Simulation time 7799309413 ps
CPU time 18.66 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:18:13 PM PDT 24
Peak memory 206388 kb
Host smart-753c7b08-b215-47c9-94d0-b7c31e8644d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515
93264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2051593264
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.868488305
Short name T663
Test name
Test status
Simulation time 162047887 ps
CPU time 0.8 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206128 kb
Host smart-a59aa61b-85dc-4e25-b22b-790fe637055b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86848
8305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.868488305
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3227176353
Short name T1107
Test name
Test status
Simulation time 229804657 ps
CPU time 0.86 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206108 kb
Host smart-90117dc3-6058-4261-bebf-9ad61d1f244c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271
76353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3227176353
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1711728503
Short name T1473
Test name
Test status
Simulation time 217406179 ps
CPU time 0.89 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206160 kb
Host smart-c546b3b3-24ed-4002-b334-ef0375cd8f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17117
28503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1711728503
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3546186537
Short name T1644
Test name
Test status
Simulation time 185853700 ps
CPU time 0.87 seconds
Started Jul 09 05:17:51 PM PDT 24
Finished Jul 09 05:17:53 PM PDT 24
Peak memory 206060 kb
Host smart-6315e737-0183-44b2-8ac7-989d9bd5408d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
86537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3546186537
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1901248779
Short name T970
Test name
Test status
Simulation time 196556739 ps
CPU time 0.89 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206076 kb
Host smart-920463ca-0d9e-4141-9268-a2783edfba75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012
48779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1901248779
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1659426727
Short name T373
Test name
Test status
Simulation time 150096359 ps
CPU time 0.75 seconds
Started Jul 09 05:17:49 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 206064 kb
Host smart-4d49b407-5df9-43eb-bda3-bfa1c77c5c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16594
26727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1659426727
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1520367091
Short name T420
Test name
Test status
Simulation time 155661404 ps
CPU time 0.79 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206048 kb
Host smart-b6e594fa-5655-4815-9a28-f8ead10c3ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15203
67091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1520367091
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1380957933
Short name T829
Test name
Test status
Simulation time 228549209 ps
CPU time 0.91 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206040 kb
Host smart-a330dad2-eb34-44d1-ac2b-921b1e27440c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13809
57933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1380957933
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2356919109
Short name T1128
Test name
Test status
Simulation time 3641687507 ps
CPU time 24.88 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:18:20 PM PDT 24
Peak memory 206284 kb
Host smart-dc307115-2eb7-420e-99dc-64888b274218
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2356919109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2356919109
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3308719589
Short name T720
Test name
Test status
Simulation time 172354893 ps
CPU time 0.82 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:52 PM PDT 24
Peak memory 206060 kb
Host smart-10229ba5-b129-40a5-a961-3944fc4aa522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33087
19589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3308719589
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1722234108
Short name T1476
Test name
Test status
Simulation time 173398409 ps
CPU time 0.85 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206132 kb
Host smart-83d3ffba-ef90-4ced-a3e1-a25ab8ee8199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17222
34108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1722234108
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.2087291334
Short name T483
Test name
Test status
Simulation time 1096447790 ps
CPU time 2.53 seconds
Started Jul 09 05:17:50 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206292 kb
Host smart-0b2b6cde-dcef-4196-8204-2804a1120358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20872
91334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.2087291334
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1919011009
Short name T532
Test name
Test status
Simulation time 3105653198 ps
CPU time 22.24 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:18:16 PM PDT 24
Peak memory 206448 kb
Host smart-10b2903f-e720-46ad-a17b-73a3514d9b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
11009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1919011009
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1240154202
Short name T2347
Test name
Test status
Simulation time 38079456 ps
CPU time 0.71 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:12:40 PM PDT 24
Peak memory 206180 kb
Host smart-af69cb3c-abb4-44ef-a212-b4d7a7711907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1240154202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1240154202
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.356609827
Short name T1923
Test name
Test status
Simulation time 4378477996 ps
CPU time 4.84 seconds
Started Jul 09 05:12:13 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206380 kb
Host smart-00af55ac-d89c-4073-9d91-df5fe32132d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=356609827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.356609827
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.543722118
Short name T16
Test name
Test status
Simulation time 13354312378 ps
CPU time 13.61 seconds
Started Jul 09 05:12:13 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206460 kb
Host smart-2bf524e9-c823-4b23-87a1-2b906d05980d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=543722118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.543722118
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3370494158
Short name T187
Test name
Test status
Simulation time 23322258242 ps
CPU time 23.58 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:12:43 PM PDT 24
Peak memory 206176 kb
Host smart-c28664a0-189a-4d5e-b5c6-2beba44b3f41
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3370494158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3370494158
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2597886693
Short name T687
Test name
Test status
Simulation time 152170154 ps
CPU time 0.84 seconds
Started Jul 09 05:12:12 PM PDT 24
Finished Jul 09 05:12:13 PM PDT 24
Peak memory 206088 kb
Host smart-f5feb11a-81f8-4b19-8f1c-0e1844e48d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25978
86693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2597886693
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3975638441
Short name T56
Test name
Test status
Simulation time 177940455 ps
CPU time 0.81 seconds
Started Jul 09 05:12:11 PM PDT 24
Finished Jul 09 05:12:13 PM PDT 24
Peak memory 205992 kb
Host smart-71363200-b677-4f5b-a1ab-54782222b87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39756
38441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3975638441
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.15574368
Short name T62
Test name
Test status
Simulation time 157467179 ps
CPU time 0.78 seconds
Started Jul 09 05:12:14 PM PDT 24
Finished Jul 09 05:12:15 PM PDT 24
Peak memory 206136 kb
Host smart-7b1db91f-8153-4a14-b66d-a30013dab4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15574
368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.15574368
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.284254333
Short name T576
Test name
Test status
Simulation time 178171306 ps
CPU time 0.77 seconds
Started Jul 09 05:12:14 PM PDT 24
Finished Jul 09 05:12:16 PM PDT 24
Peak memory 206108 kb
Host smart-fa84fd2a-9430-4007-b19a-0593680e2b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
4333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.284254333
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3562101647
Short name T2249
Test name
Test status
Simulation time 995391454 ps
CPU time 2.38 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:12:21 PM PDT 24
Peak memory 206380 kb
Host smart-f72f9f2b-ef2a-452c-bf6e-a9f4e2527ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35621
01647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3562101647
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2097424813
Short name T1286
Test name
Test status
Simulation time 22138573216 ps
CPU time 40.86 seconds
Started Jul 09 05:12:15 PM PDT 24
Finished Jul 09 05:12:57 PM PDT 24
Peak memory 206372 kb
Host smart-9ef948b1-f2f9-461c-9d5e-9865c404f099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20974
24813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2097424813
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3363442793
Short name T497
Test name
Test status
Simulation time 342621527 ps
CPU time 1.16 seconds
Started Jul 09 05:12:16 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206104 kb
Host smart-e30a0c58-ece1-4bbb-9323-ffadc01e8853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33634
42793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3363442793
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3232423975
Short name T1029
Test name
Test status
Simulation time 154674492 ps
CPU time 0.82 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:12:19 PM PDT 24
Peak memory 206148 kb
Host smart-860d56b3-53d6-408e-903a-6be8d5182c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324
23975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3232423975
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1221435145
Short name T821
Test name
Test status
Simulation time 30839492 ps
CPU time 0.68 seconds
Started Jul 09 05:12:17 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206060 kb
Host smart-33c1b4c5-a26d-4644-aca2-24959cb0e529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12214
35145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1221435145
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.1126269675
Short name T680
Test name
Test status
Simulation time 866027545 ps
CPU time 2.42 seconds
Started Jul 09 05:12:15 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206356 kb
Host smart-e1672c46-a453-42fe-add9-e7d5eb4880f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11262
69675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1126269675
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2177813953
Short name T1663
Test name
Test status
Simulation time 362705709 ps
CPU time 2.23 seconds
Started Jul 09 05:12:17 PM PDT 24
Finished Jul 09 05:12:20 PM PDT 24
Peak memory 206396 kb
Host smart-e99fccc1-50a0-4403-b0e4-73ee58b287a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21778
13953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2177813953
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2575215477
Short name T2288
Test name
Test status
Simulation time 98189329258 ps
CPU time 127.52 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:14:26 PM PDT 24
Peak memory 206396 kb
Host smart-35420c7d-9616-47d6-83fe-8b5546962c57
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2575215477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2575215477
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2058333531
Short name T594
Test name
Test status
Simulation time 83298518140 ps
CPU time 132.7 seconds
Started Jul 09 05:12:17 PM PDT 24
Finished Jul 09 05:14:31 PM PDT 24
Peak memory 206420 kb
Host smart-14cfea94-2bc2-47b2-8bb6-76460aa1d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058333531 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2058333531
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1184018160
Short name T2031
Test name
Test status
Simulation time 116112493585 ps
CPU time 162.25 seconds
Started Jul 09 05:12:15 PM PDT 24
Finished Jul 09 05:14:58 PM PDT 24
Peak memory 206392 kb
Host smart-d510cc4b-7eed-4b27-88b1-de8056aa5ac1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1184018160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1184018160
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.910500849
Short name T435
Test name
Test status
Simulation time 93289752585 ps
CPU time 127.77 seconds
Started Jul 09 05:12:16 PM PDT 24
Finished Jul 09 05:14:24 PM PDT 24
Peak memory 206388 kb
Host smart-4bf5ac0c-eedd-4a73-8ecf-9fb2f8d3e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910500849 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.910500849
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1696944908
Short name T2193
Test name
Test status
Simulation time 119184786382 ps
CPU time 161.77 seconds
Started Jul 09 05:12:14 PM PDT 24
Finished Jul 09 05:14:57 PM PDT 24
Peak memory 206320 kb
Host smart-1ba54017-2648-450b-92b9-3d000512f0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
44908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1696944908
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3263424753
Short name T2088
Test name
Test status
Simulation time 290867087 ps
CPU time 0.94 seconds
Started Jul 09 05:12:16 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206064 kb
Host smart-2412647c-ff77-49d6-9f2d-4471b9c3a7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32634
24753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3263424753
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2937469566
Short name T2378
Test name
Test status
Simulation time 142738092 ps
CPU time 0.8 seconds
Started Jul 09 05:12:16 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206020 kb
Host smart-63f9b1bf-87c2-4c81-b66c-5ecfaac974ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29374
69566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2937469566
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1156364153
Short name T645
Test name
Test status
Simulation time 234186067 ps
CPU time 0.91 seconds
Started Jul 09 05:12:16 PM PDT 24
Finished Jul 09 05:12:18 PM PDT 24
Peak memory 206144 kb
Host smart-4ad6c162-b5e7-4c1e-ba90-4c27044c2c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11563
64153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1156364153
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.114308226
Short name T1495
Test name
Test status
Simulation time 184702239 ps
CPU time 0.85 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:12:20 PM PDT 24
Peak memory 206068 kb
Host smart-932eada3-abcc-45ee-8aee-453e2d0a4fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11430
8226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.114308226
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.2901893368
Short name T2549
Test name
Test status
Simulation time 23294066078 ps
CPU time 23.51 seconds
Started Jul 09 05:12:17 PM PDT 24
Finished Jul 09 05:12:41 PM PDT 24
Peak memory 206224 kb
Host smart-abd7722c-96b6-4f73-aa27-363bbb66d693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018
93368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2901893368
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3641204074
Short name T209
Test name
Test status
Simulation time 3272157797 ps
CPU time 4.71 seconds
Started Jul 09 05:12:19 PM PDT 24
Finished Jul 09 05:12:25 PM PDT 24
Peak memory 206072 kb
Host smart-82d739ff-c2a4-46f1-8f5d-e964571d0625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36412
04074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3641204074
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3177544091
Short name T1551
Test name
Test status
Simulation time 12500497810 ps
CPU time 338.43 seconds
Started Jul 09 05:12:21 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206404 kb
Host smart-46b79e83-b7b6-43fd-895c-eb09efc65180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31775
44091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3177544091
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.917832974
Short name T2556
Test name
Test status
Simulation time 4301115336 ps
CPU time 31.64 seconds
Started Jul 09 05:12:20 PM PDT 24
Finished Jul 09 05:12:52 PM PDT 24
Peak memory 206360 kb
Host smart-616f5912-4903-4dea-94b1-d39f9039ac1a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=917832974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.917832974
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.4293691976
Short name T770
Test name
Test status
Simulation time 239640494 ps
CPU time 1.01 seconds
Started Jul 09 05:12:22 PM PDT 24
Finished Jul 09 05:12:23 PM PDT 24
Peak memory 205972 kb
Host smart-6d93e40c-3790-49b5-b93f-2a1a81deb1d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4293691976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.4293691976
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.882341972
Short name T2003
Test name
Test status
Simulation time 201136357 ps
CPU time 0.9 seconds
Started Jul 09 05:12:21 PM PDT 24
Finished Jul 09 05:12:23 PM PDT 24
Peak memory 206112 kb
Host smart-ea8e3b3f-33c4-4382-a2ff-f2f32a2d617d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88234
1972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.882341972
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3137413504
Short name T2333
Test name
Test status
Simulation time 3957688905 ps
CPU time 35.88 seconds
Started Jul 09 05:12:19 PM PDT 24
Finished Jul 09 05:12:55 PM PDT 24
Peak memory 206264 kb
Host smart-cdc221d7-af9d-4b3f-babb-78d6cdec7e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31374
13504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3137413504
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2542679234
Short name T2201
Test name
Test status
Simulation time 5363916916 ps
CPU time 143.36 seconds
Started Jul 09 05:12:19 PM PDT 24
Finished Jul 09 05:14:43 PM PDT 24
Peak memory 206228 kb
Host smart-6368b9a9-6a3f-4293-a8b9-b0481931e970
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2542679234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2542679234
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1732576235
Short name T894
Test name
Test status
Simulation time 158318733 ps
CPU time 0.87 seconds
Started Jul 09 05:12:20 PM PDT 24
Finished Jul 09 05:12:22 PM PDT 24
Peak memory 206088 kb
Host smart-df340bd6-50ad-4e4f-a346-ce1fc5a8554e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1732576235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1732576235
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1356274653
Short name T537
Test name
Test status
Simulation time 143393401 ps
CPU time 0.77 seconds
Started Jul 09 05:14:21 PM PDT 24
Finished Jul 09 05:14:24 PM PDT 24
Peak memory 206152 kb
Host smart-1db78d0d-6ec1-4fa6-aaf1-1bc4ec78e4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13562
74653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1356274653
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2115076960
Short name T117
Test name
Test status
Simulation time 186305792 ps
CPU time 0.86 seconds
Started Jul 09 05:12:19 PM PDT 24
Finished Jul 09 05:12:21 PM PDT 24
Peak memory 206068 kb
Host smart-8e11254e-58fd-4bf0-8ce2-2e8628747962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21150
76960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2115076960
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1353406203
Short name T1633
Test name
Test status
Simulation time 164881854 ps
CPU time 0.84 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:12:20 PM PDT 24
Peak memory 206148 kb
Host smart-f3127c77-10d4-462e-80bd-9b1eb673d070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13534
06203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1353406203
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3075610199
Short name T2399
Test name
Test status
Simulation time 191477655 ps
CPU time 0.89 seconds
Started Jul 09 05:12:20 PM PDT 24
Finished Jul 09 05:12:22 PM PDT 24
Peak memory 206112 kb
Host smart-51c2a16d-c8e4-4073-a8ab-f223334caf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30756
10199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3075610199
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.184282015
Short name T643
Test name
Test status
Simulation time 162308273 ps
CPU time 0.81 seconds
Started Jul 09 05:12:21 PM PDT 24
Finished Jul 09 05:12:23 PM PDT 24
Peak memory 206128 kb
Host smart-f47c3baf-fa8e-41b6-9a52-b4c84f7cc0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428
2015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.184282015
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2364572865
Short name T398
Test name
Test status
Simulation time 189021533 ps
CPU time 0.85 seconds
Started Jul 09 05:12:21 PM PDT 24
Finished Jul 09 05:12:23 PM PDT 24
Peak memory 206056 kb
Host smart-57d7fc43-cad0-487b-b0ff-2ba725f53b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
72865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2364572865
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.4034219234
Short name T382
Test name
Test status
Simulation time 229992432 ps
CPU time 0.93 seconds
Started Jul 09 05:12:18 PM PDT 24
Finished Jul 09 05:12:20 PM PDT 24
Peak memory 206036 kb
Host smart-31851d70-cff1-4ad3-9615-b727fcb61893
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4034219234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.4034219234
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2023013439
Short name T741
Test name
Test status
Simulation time 196032494 ps
CPU time 0.87 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:12:30 PM PDT 24
Peak memory 206160 kb
Host smart-5a1733fe-5986-4439-a224-baccdfc4937e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
13439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2023013439
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3061457901
Short name T1039
Test name
Test status
Simulation time 161986756 ps
CPU time 0.79 seconds
Started Jul 09 05:12:23 PM PDT 24
Finished Jul 09 05:12:25 PM PDT 24
Peak memory 205992 kb
Host smart-69110fb0-467a-4d07-823e-9dbd902a09da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614
57901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3061457901
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1841186739
Short name T2177
Test name
Test status
Simulation time 15501562199 ps
CPU time 31.15 seconds
Started Jul 09 05:12:28 PM PDT 24
Finished Jul 09 05:13:00 PM PDT 24
Peak memory 206424 kb
Host smart-b1b08560-9e89-4042-a4fa-86dcc68175ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18411
86739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1841186739
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4123727366
Short name T1357
Test name
Test status
Simulation time 182326210 ps
CPU time 0.89 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:12:30 PM PDT 24
Peak memory 206064 kb
Host smart-73af2c34-75f7-4d2e-bac2-42b6f0896624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237
27366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4123727366
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1457685803
Short name T1653
Test name
Test status
Simulation time 274347828 ps
CPU time 1 seconds
Started Jul 09 05:12:26 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206056 kb
Host smart-353792b8-2ad2-48c6-8a78-c314ad2691b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14576
85803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1457685803
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3645371245
Short name T177
Test name
Test status
Simulation time 9472805845 ps
CPU time 160.19 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 206416 kb
Host smart-5505dcdd-1d80-44c5-b74d-64956b880003
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3645371245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3645371245
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1055997756
Short name T1309
Test name
Test status
Simulation time 13225090394 ps
CPU time 71.56 seconds
Started Jul 09 05:12:26 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206376 kb
Host smart-889899ec-bb46-45f4-83e1-1e822d86eebc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1055997756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1055997756
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1709824428
Short name T779
Test name
Test status
Simulation time 13358419738 ps
CPU time 98.74 seconds
Started Jul 09 05:12:23 PM PDT 24
Finished Jul 09 05:14:03 PM PDT 24
Peak memory 206636 kb
Host smart-c0c7a6bf-f67b-4b3a-b645-bcc065143bcd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1709824428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1709824428
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2095447920
Short name T1901
Test name
Test status
Simulation time 233607190 ps
CPU time 1 seconds
Started Jul 09 05:12:24 PM PDT 24
Finished Jul 09 05:12:27 PM PDT 24
Peak memory 206160 kb
Host smart-4d063b3f-2324-495a-9408-f4eed61c1634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20954
47920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2095447920
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1371262030
Short name T1486
Test name
Test status
Simulation time 223212491 ps
CPU time 0.85 seconds
Started Jul 09 05:12:24 PM PDT 24
Finished Jul 09 05:12:27 PM PDT 24
Peak memory 206112 kb
Host smart-9ee8865b-b3fc-4c8d-9f12-7710222b6e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13712
62030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1371262030
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4097176265
Short name T2626
Test name
Test status
Simulation time 185215262 ps
CPU time 0.86 seconds
Started Jul 09 05:12:24 PM PDT 24
Finished Jul 09 05:12:26 PM PDT 24
Peak memory 205996 kb
Host smart-de64c5cd-3ed4-4b8d-9c3c-40f35525fe22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40971
76265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4097176265
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.778965479
Short name T74
Test name
Test status
Simulation time 171680259 ps
CPU time 0.77 seconds
Started Jul 09 05:12:25 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206128 kb
Host smart-44769b4c-7203-4ae8-b6b1-de6ed91d2dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77896
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.778965479
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1224711483
Short name T192
Test name
Test status
Simulation time 260140314 ps
CPU time 1.09 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:32 PM PDT 24
Peak memory 223996 kb
Host smart-065e7bb2-edde-45f7-879d-720eea1b08aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1224711483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1224711483
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1674456852
Short name T51
Test name
Test status
Simulation time 439060389 ps
CPU time 1.32 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:12:30 PM PDT 24
Peak memory 206064 kb
Host smart-cac850b0-1e02-4f3d-86ac-9e2e94f7ea24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744
56852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1674456852
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1937794255
Short name T181
Test name
Test status
Simulation time 329044073 ps
CPU time 1.03 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:12:30 PM PDT 24
Peak memory 206060 kb
Host smart-c48bfe9c-f37e-4de4-a936-ea77fab5122c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
94255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1937794255
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1380984550
Short name T1022
Test name
Test status
Simulation time 148738296 ps
CPU time 0.79 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:12:30 PM PDT 24
Peak memory 206124 kb
Host smart-62a863ad-d563-4419-aa02-a04324cb3055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13809
84550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1380984550
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.151253789
Short name T2695
Test name
Test status
Simulation time 159900419 ps
CPU time 0.82 seconds
Started Jul 09 05:12:26 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206060 kb
Host smart-5fe02baf-414f-4cd0-90df-74228f7b3e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
3789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.151253789
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1179466005
Short name T2056
Test name
Test status
Simulation time 255405838 ps
CPU time 1 seconds
Started Jul 09 05:12:25 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206116 kb
Host smart-e849167a-fd89-4124-8243-9bacf8805880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11794
66005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1179466005
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.579037203
Short name T2011
Test name
Test status
Simulation time 3753939636 ps
CPU time 106.28 seconds
Started Jul 09 05:12:25 PM PDT 24
Finished Jul 09 05:14:13 PM PDT 24
Peak memory 206376 kb
Host smart-f80343a3-bda5-434b-b60c-cb28989a029e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=579037203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.579037203
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.890620475
Short name T1537
Test name
Test status
Simulation time 152253594 ps
CPU time 0.77 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:12:30 PM PDT 24
Peak memory 206068 kb
Host smart-e31beaf2-0baa-4971-8509-d3d64e756d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89062
0475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.890620475
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.16877298
Short name T2153
Test name
Test status
Simulation time 158235848 ps
CPU time 0.82 seconds
Started Jul 09 05:12:25 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 206124 kb
Host smart-322177ee-35fd-449f-8f3e-f412f2e02397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.16877298
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.3160333758
Short name T795
Test name
Test status
Simulation time 1126868475 ps
CPU time 2.71 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:33 PM PDT 24
Peak memory 206404 kb
Host smart-604ca5c2-fcd3-47f7-83b8-873542a6a515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
33758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3160333758
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.969928883
Short name T900
Test name
Test status
Simulation time 4394324303 ps
CPU time 124.3 seconds
Started Jul 09 05:12:29 PM PDT 24
Finished Jul 09 05:14:34 PM PDT 24
Peak memory 206460 kb
Host smart-dad09a48-7270-46b2-8685-b78b0f0f721f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96992
8883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.969928883
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3609206019
Short name T168
Test name
Test status
Simulation time 12160828283 ps
CPU time 109.51 seconds
Started Jul 09 05:12:27 PM PDT 24
Finished Jul 09 05:14:19 PM PDT 24
Peak memory 206376 kb
Host smart-c09264da-bb29-4930-9b09-7ecffd534001
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3609206019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3609206019
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3388049720
Short name T1772
Test name
Test status
Simulation time 71637382 ps
CPU time 0.72 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:59 PM PDT 24
Peak memory 206148 kb
Host smart-56849e14-bcff-4ea6-8bfd-fed676296539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3388049720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3388049720
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.374021673
Short name T2110
Test name
Test status
Simulation time 4396702071 ps
CPU time 5.07 seconds
Started Jul 09 05:17:56 PM PDT 24
Finished Jul 09 05:18:02 PM PDT 24
Peak memory 206328 kb
Host smart-3cd56d01-cc89-4063-b3e8-dcda06318b8a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=374021673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.374021673
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3659831222
Short name T2125
Test name
Test status
Simulation time 13514701454 ps
CPU time 13.55 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:18:08 PM PDT 24
Peak memory 206400 kb
Host smart-ebed1d6f-f33a-4fde-8fb4-62c9a72909cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3659831222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3659831222
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2660542481
Short name T1118
Test name
Test status
Simulation time 23402125130 ps
CPU time 21.9 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206336 kb
Host smart-a9c9ee29-0ebb-45e3-a39b-acde8d168fdb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2660542481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2660542481
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1073856764
Short name T610
Test name
Test status
Simulation time 183675191 ps
CPU time 0.82 seconds
Started Jul 09 05:17:55 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 206064 kb
Host smart-296be4ba-2f8b-49f7-9493-e56f38bd906d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
56764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1073856764
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.363922418
Short name T669
Test name
Test status
Simulation time 146837209 ps
CPU time 0.75 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206152 kb
Host smart-8b3525ba-aeca-47e9-beb3-6a8dc4673554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36392
2418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.363922418
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1355921338
Short name T2284
Test name
Test status
Simulation time 434761137 ps
CPU time 1.35 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 206128 kb
Host smart-d9b6b209-c80e-461e-b46e-9afc822d1381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13559
21338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1355921338
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1543195019
Short name T1752
Test name
Test status
Simulation time 912238418 ps
CPU time 2.08 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206428 kb
Host smart-be3ba2c2-5402-47c4-958b-e5e4795dec83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15431
95019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1543195019
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3961725880
Short name T1702
Test name
Test status
Simulation time 16701548436 ps
CPU time 32.86 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206344 kb
Host smart-3bbcb673-822d-42ef-826c-d3f35caf0b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
25880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3961725880
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.439763308
Short name T2076
Test name
Test status
Simulation time 342764089 ps
CPU time 1.19 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 206068 kb
Host smart-c24c0645-83ca-4b93-a8c2-635503eb8141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43976
3308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.439763308
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2430251536
Short name T2585
Test name
Test status
Simulation time 135320361 ps
CPU time 0.75 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206052 kb
Host smart-3ca2f9f4-3155-432a-84a9-a54fd3b5838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
51536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2430251536
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2757961533
Short name T318
Test name
Test status
Simulation time 37007468 ps
CPU time 0.73 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 206136 kb
Host smart-ca1c283d-e72d-4244-b762-c1f4eccd11cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
61533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2757961533
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.962992340
Short name T547
Test name
Test status
Simulation time 766183913 ps
CPU time 1.95 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206192 kb
Host smart-5d7a8e7e-561b-4714-9de3-12967c68fa9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96299
2340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.962992340
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3281572441
Short name T2599
Test name
Test status
Simulation time 313013580 ps
CPU time 2.22 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206180 kb
Host smart-ca3396ca-c11a-4764-8493-d76353e64d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32815
72441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3281572441
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2089888808
Short name T1185
Test name
Test status
Simulation time 243841322 ps
CPU time 0.89 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:17:55 PM PDT 24
Peak memory 206048 kb
Host smart-d14446d4-fe21-45bb-8fb6-b52aeafe25a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
88808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2089888808
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3599245850
Short name T2577
Test name
Test status
Simulation time 215802418 ps
CPU time 0.85 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206140 kb
Host smart-b9783524-cbbe-4929-95a0-f81a372f503a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35992
45850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3599245850
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2574949335
Short name T1351
Test name
Test status
Simulation time 167137843 ps
CPU time 0.85 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:56 PM PDT 24
Peak memory 206136 kb
Host smart-28cbec86-dbca-44a1-9905-2f75af12682b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25749
49335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2574949335
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2351335006
Short name T704
Test name
Test status
Simulation time 6476958472 ps
CPU time 59 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:18:55 PM PDT 24
Peak memory 206488 kb
Host smart-b59b67bc-823b-4df8-a8e1-d9ac747362ca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2351335006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2351335006
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1583019797
Short name T583
Test name
Test status
Simulation time 172209600 ps
CPU time 0.91 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206144 kb
Host smart-4308a18c-5043-4d31-85be-855f74efbdb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15830
19797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1583019797
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2979592559
Short name T1729
Test name
Test status
Simulation time 23344728061 ps
CPU time 24.9 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206112 kb
Host smart-69d353af-b00c-49db-84d7-9b3a8d5380f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
92559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2979592559
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3906049252
Short name T2597
Test name
Test status
Simulation time 3325225514 ps
CPU time 3.62 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:59 PM PDT 24
Peak memory 206192 kb
Host smart-a4eb973d-6620-4049-b421-3813f60811e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
49252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3906049252
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1822512562
Short name T450
Test name
Test status
Simulation time 8297295040 ps
CPU time 61.37 seconds
Started Jul 09 05:17:56 PM PDT 24
Finished Jul 09 05:18:58 PM PDT 24
Peak memory 206348 kb
Host smart-33ca829d-94df-454b-a1ea-4dec288f132f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225
12562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1822512562
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.4053015910
Short name T1430
Test name
Test status
Simulation time 4657215301 ps
CPU time 32.46 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206356 kb
Host smart-8216525e-5b56-45d4-9ff4-a53c4b2a93ac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4053015910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.4053015910
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3469744395
Short name T2563
Test name
Test status
Simulation time 256105180 ps
CPU time 0.95 seconds
Started Jul 09 05:17:55 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 205940 kb
Host smart-1bccaa09-cc8a-4c80-8017-5cfecbe28604
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3469744395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3469744395
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.303957989
Short name T929
Test name
Test status
Simulation time 202734198 ps
CPU time 0.87 seconds
Started Jul 09 05:17:52 PM PDT 24
Finished Jul 09 05:17:54 PM PDT 24
Peak memory 206104 kb
Host smart-5709b877-a807-496e-9545-b6c955eb4d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395
7989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.303957989
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.3766187334
Short name T431
Test name
Test status
Simulation time 4000563790 ps
CPU time 31.45 seconds
Started Jul 09 05:17:53 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206404 kb
Host smart-6e2affc9-754a-4e50-8b0c-ed2b4f51231f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37661
87334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.3766187334
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1591150414
Short name T2318
Test name
Test status
Simulation time 3165277701 ps
CPU time 22.12 seconds
Started Jul 09 05:17:55 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206304 kb
Host smart-d6ecfefb-722b-4c3f-9031-df795c19147c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1591150414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1591150414
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.705191148
Short name T567
Test name
Test status
Simulation time 161556136 ps
CPU time 0.84 seconds
Started Jul 09 05:17:54 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 205968 kb
Host smart-2f06eb46-a186-45e0-863e-e952bf48f5f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=705191148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.705191148
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3450812640
Short name T1776
Test name
Test status
Simulation time 207120210 ps
CPU time 0.9 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206028 kb
Host smart-9764cc77-52e4-44f2-95d3-3ef58097fe44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34508
12640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3450812640
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3587241038
Short name T129
Test name
Test status
Simulation time 204801027 ps
CPU time 1.01 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:59 PM PDT 24
Peak memory 206024 kb
Host smart-384dcf60-d6fe-40c3-b6ae-14eb336a822e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35872
41038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3587241038
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1060648557
Short name T834
Test name
Test status
Simulation time 160436070 ps
CPU time 0.83 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206008 kb
Host smart-edc21ac0-4689-47a8-bab2-37f9f5736ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606
48557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1060648557
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1670462517
Short name T2109
Test name
Test status
Simulation time 204264279 ps
CPU time 0.86 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:59 PM PDT 24
Peak memory 206160 kb
Host smart-f0a1acb8-61dd-4723-9767-a0e2d40c05f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
62517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1670462517
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.61537898
Short name T1967
Test name
Test status
Simulation time 145904992 ps
CPU time 0.77 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206064 kb
Host smart-80392d45-cbd1-4bc6-8d23-e14e81730102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61537
898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.61537898
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.326987048
Short name T2117
Test name
Test status
Simulation time 184990297 ps
CPU time 0.76 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206056 kb
Host smart-b486f726-7135-45fe-80f1-eda5addd5091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32698
7048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.326987048
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2442089255
Short name T2242
Test name
Test status
Simulation time 235647990 ps
CPU time 0.99 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206092 kb
Host smart-0a5a2589-0078-421f-aa51-ba468fc51f15
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2442089255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2442089255
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2504414250
Short name T511
Test name
Test status
Simulation time 149903032 ps
CPU time 0.89 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206116 kb
Host smart-76cff218-729e-4faf-ac76-3da8176464a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25044
14250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2504414250
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.235411904
Short name T27
Test name
Test status
Simulation time 41655127 ps
CPU time 0.66 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206104 kb
Host smart-0d30b280-24f5-4a66-883a-b243323da6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
1904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.235411904
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1428666289
Short name T1141
Test name
Test status
Simulation time 16665156804 ps
CPU time 36.52 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206312 kb
Host smart-2aa06a6e-b661-4d88-b952-e394968bebc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14286
66289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1428666289
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2813029651
Short name T971
Test name
Test status
Simulation time 159360990 ps
CPU time 0.8 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206056 kb
Host smart-76d3f8b6-9b5b-48e8-8cce-ff31ee336b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28130
29651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2813029651
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.355184394
Short name T1858
Test name
Test status
Simulation time 190961856 ps
CPU time 0.84 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206052 kb
Host smart-cdfe739c-24a9-4d4f-a62a-ddc76c74caaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
4394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.355184394
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2885898538
Short name T886
Test name
Test status
Simulation time 214496791 ps
CPU time 0.91 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:04 PM PDT 24
Peak memory 206152 kb
Host smart-b7c80a66-b987-4bd2-849c-e95b895a1182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
98538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2885898538
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2324495298
Short name T2174
Test name
Test status
Simulation time 177495113 ps
CPU time 0.83 seconds
Started Jul 09 05:18:00 PM PDT 24
Finished Jul 09 05:18:02 PM PDT 24
Peak memory 205964 kb
Host smart-17c9b164-ba6a-4686-9126-161b3f180786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244
95298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2324495298
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2451662904
Short name T1221
Test name
Test status
Simulation time 215776315 ps
CPU time 0.88 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206144 kb
Host smart-d5ec1b56-5ae8-4a3a-a995-b3df5b99f1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24516
62904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2451662904
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3664043522
Short name T1101
Test name
Test status
Simulation time 167957834 ps
CPU time 0.85 seconds
Started Jul 09 05:17:56 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206060 kb
Host smart-b6445331-7ebc-498e-829e-35eec52dd5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36640
43522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3664043522
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1835525
Short name T533
Test name
Test status
Simulation time 191372138 ps
CPU time 0.84 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206136 kb
Host smart-d64f92c4-3afc-4067-b816-474e26d1a02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18355
25 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1835525
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3830603507
Short name T616
Test name
Test status
Simulation time 236810590 ps
CPU time 1.01 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206128 kb
Host smart-b2a85d62-0743-4c32-b8ef-8457e1ba6e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
03507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3830603507
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.393643610
Short name T1890
Test name
Test status
Simulation time 4806345284 ps
CPU time 44.46 seconds
Started Jul 09 05:17:55 PM PDT 24
Finished Jul 09 05:18:41 PM PDT 24
Peak memory 206388 kb
Host smart-0dda924c-2b5a-456f-a8b0-ca9730499b11
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=393643610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.393643610
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.570237419
Short name T1914
Test name
Test status
Simulation time 200255631 ps
CPU time 0.82 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206052 kb
Host smart-995a3cf8-9324-4434-ac5b-cafe61503614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57023
7419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.570237419
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.178052992
Short name T584
Test name
Test status
Simulation time 184953771 ps
CPU time 0.79 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:00 PM PDT 24
Peak memory 206136 kb
Host smart-39b608b2-2e82-4d70-832b-a791d9772d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17805
2992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.178052992
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.1277076498
Short name T1651
Test name
Test status
Simulation time 1238334928 ps
CPU time 2.93 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206396 kb
Host smart-50a1a2b5-6049-4f79-b0fe-f0516d49fd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12770
76498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.1277076498
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.77032668
Short name T716
Test name
Test status
Simulation time 6549606783 ps
CPU time 47.47 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:18:46 PM PDT 24
Peak memory 206340 kb
Host smart-96281b04-a474-42a3-954b-ddbd160e3c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77032
668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.77032668
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.4100749962
Short name T1332
Test name
Test status
Simulation time 62711997 ps
CPU time 0.72 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206128 kb
Host smart-7fbf7693-90da-4efd-a655-7dd197272893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4100749962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.4100749962
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.4284212126
Short name T2016
Test name
Test status
Simulation time 4025226446 ps
CPU time 5.31 seconds
Started Jul 09 05:18:00 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206376 kb
Host smart-4fd64fa8-0ffd-422f-9fd6-7af56f268166
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4284212126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.4284212126
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3290467172
Short name T1136
Test name
Test status
Simulation time 13350163670 ps
CPU time 13.88 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206248 kb
Host smart-b9391ae3-4e7b-4364-9ae4-c98ec4ed2fcd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3290467172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3290467172
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1891530809
Short name T1413
Test name
Test status
Simulation time 23341767142 ps
CPU time 22.57 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:23 PM PDT 24
Peak memory 206144 kb
Host smart-74266387-d814-4fac-8c9e-e2656a16b27d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1891530809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1891530809
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.406227568
Short name T477
Test name
Test status
Simulation time 182993793 ps
CPU time 0.83 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:59 PM PDT 24
Peak memory 206160 kb
Host smart-0fb3a0ec-0583-4418-abfe-c299fb6b8912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40622
7568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.406227568
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2616401145
Short name T609
Test name
Test status
Simulation time 145614173 ps
CPU time 0.74 seconds
Started Jul 09 05:17:57 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206152 kb
Host smart-7b618c80-f3a1-42a4-9e85-cb9f983b9290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
01145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2616401145
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3179130191
Short name T1562
Test name
Test status
Simulation time 239774789 ps
CPU time 0.99 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206056 kb
Host smart-dfd785c6-6454-475e-bae4-cc4f16552a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31791
30191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3179130191
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3096245047
Short name T1842
Test name
Test status
Simulation time 771171475 ps
CPU time 1.91 seconds
Started Jul 09 05:17:55 PM PDT 24
Finished Jul 09 05:17:58 PM PDT 24
Peak memory 206308 kb
Host smart-670cb13e-f8c4-4cb8-90a5-4ff89d0fdefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
45047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3096245047
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.166732352
Short name T1287
Test name
Test status
Simulation time 15798598940 ps
CPU time 32.73 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206352 kb
Host smart-350b6124-db28-4df3-b465-7bc6d3130d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16673
2352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.166732352
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2532170490
Short name T2134
Test name
Test status
Simulation time 385580183 ps
CPU time 1.35 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206128 kb
Host smart-ea8f0b42-b0ef-4f5d-8d66-f5741831b221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
70490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2532170490
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3213644292
Short name T1891
Test name
Test status
Simulation time 166849478 ps
CPU time 0.8 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206152 kb
Host smart-dadf03ed-1ffd-419f-a3ed-9b90c3e88d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32136
44292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3213644292
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.4199900116
Short name T2116
Test name
Test status
Simulation time 73128732 ps
CPU time 0.68 seconds
Started Jul 09 05:17:58 PM PDT 24
Finished Jul 09 05:17:59 PM PDT 24
Peak memory 205984 kb
Host smart-6bd385af-b17e-4e77-a7f4-baba67415104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41999
00116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.4199900116
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1581470365
Short name T1364
Test name
Test status
Simulation time 919791010 ps
CPU time 2.19 seconds
Started Jul 09 05:18:03 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206376 kb
Host smart-92835487-ba54-451d-93ae-142ef421dbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
70365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1581470365
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2633816313
Short name T595
Test name
Test status
Simulation time 155536248 ps
CPU time 1.37 seconds
Started Jul 09 05:18:03 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 206304 kb
Host smart-152bfca5-c29b-423b-9031-f705a531cadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
16313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2633816313
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3162734269
Short name T514
Test name
Test status
Simulation time 230241280 ps
CPU time 0.93 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:08 PM PDT 24
Peak memory 206104 kb
Host smart-72ca6245-12ef-4d09-9710-ae5cca77ead3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31627
34269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3162734269
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2480585924
Short name T1348
Test name
Test status
Simulation time 202357460 ps
CPU time 0.93 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:04 PM PDT 24
Peak memory 206012 kb
Host smart-7f07b361-792f-4fea-8110-131a8596b83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24805
85924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2480585924
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.77409867
Short name T1190
Test name
Test status
Simulation time 186346456 ps
CPU time 0.84 seconds
Started Jul 09 05:18:01 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206056 kb
Host smart-6229faea-ec6f-4fad-b3d9-11e200328d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77409
867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.77409867
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2125788557
Short name T690
Test name
Test status
Simulation time 303854901 ps
CPU time 0.98 seconds
Started Jul 09 05:18:01 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206064 kb
Host smart-e09b2791-66ce-4992-a1a0-010ef14488b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21257
88557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2125788557
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2345745318
Short name T1935
Test name
Test status
Simulation time 23396777050 ps
CPU time 28.87 seconds
Started Jul 09 05:18:05 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206104 kb
Host smart-f459367b-130b-41af-a8b4-f8f923257d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23457
45318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2345745318
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2474449200
Short name T1073
Test name
Test status
Simulation time 3346822330 ps
CPU time 3.83 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206228 kb
Host smart-9240e599-c50e-4e84-adfa-f372c3b20307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24744
49200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2474449200
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2552074479
Short name T455
Test name
Test status
Simulation time 11277942981 ps
CPU time 83.84 seconds
Started Jul 09 05:18:04 PM PDT 24
Finished Jul 09 05:19:28 PM PDT 24
Peak memory 206284 kb
Host smart-4d9f54a7-474a-420d-b21b-e7095f1a6ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
74479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2552074479
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2940236205
Short name T1341
Test name
Test status
Simulation time 3219527479 ps
CPU time 23.27 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206400 kb
Host smart-74bd0d55-9359-48ca-a15c-0fc3ff06a023
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2940236205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2940236205
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1989415271
Short name T2169
Test name
Test status
Simulation time 247467590 ps
CPU time 1 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206140 kb
Host smart-83fcd868-8eca-4e10-b86a-1f4a3e17f284
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1989415271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1989415271
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.564793095
Short name T1065
Test name
Test status
Simulation time 199328642 ps
CPU time 0.9 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206132 kb
Host smart-6c0d50fd-f4db-4fc2-8772-6b8b1eb63349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56479
3095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.564793095
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3794296765
Short name T1771
Test name
Test status
Simulation time 6825214509 ps
CPU time 65.01 seconds
Started Jul 09 05:18:03 PM PDT 24
Finished Jul 09 05:19:09 PM PDT 24
Peak memory 206412 kb
Host smart-cc820551-13ae-407d-854e-e048b0363174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37942
96765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3794296765
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3370117680
Short name T1397
Test name
Test status
Simulation time 5523082228 ps
CPU time 49.62 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206232 kb
Host smart-95b9039c-ffc0-4ec8-80bc-754b4af6315b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3370117680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3370117680
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.800789308
Short name T1374
Test name
Test status
Simulation time 182516744 ps
CPU time 0.81 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:01 PM PDT 24
Peak memory 206396 kb
Host smart-273f8a50-b55a-4671-b479-45a325414088
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=800789308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.800789308
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2946839079
Short name T557
Test name
Test status
Simulation time 175521793 ps
CPU time 0.83 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:04 PM PDT 24
Peak memory 206020 kb
Host smart-03fc7fd9-12e2-434a-a9a3-04114b324ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29468
39079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2946839079
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1981363
Short name T1718
Test name
Test status
Simulation time 198147592 ps
CPU time 0.85 seconds
Started Jul 09 05:18:05 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206040 kb
Host smart-ac6f5d39-25d5-4c4c-bdb4-cc67a9ea9c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19813
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1981363
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.855067685
Short name T572
Test name
Test status
Simulation time 162064681 ps
CPU time 0.86 seconds
Started Jul 09 05:18:01 PM PDT 24
Finished Jul 09 05:18:02 PM PDT 24
Peak memory 206156 kb
Host smart-9b87aebb-85be-4127-bb22-7f03da6ede4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85506
7685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.855067685
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2288746676
Short name T2264
Test name
Test status
Simulation time 170746273 ps
CPU time 0.86 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:04 PM PDT 24
Peak memory 205988 kb
Host smart-d6ee40b2-c4a7-4ee4-93ab-675a0456b61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
46676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2288746676
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2957008989
Short name T322
Test name
Test status
Simulation time 204621268 ps
CPU time 0.93 seconds
Started Jul 09 05:18:02 PM PDT 24
Finished Jul 09 05:18:04 PM PDT 24
Peak memory 206144 kb
Host smart-66f589c6-8526-4c1b-a21f-45d293924fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570
08989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2957008989
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.827614731
Short name T1461
Test name
Test status
Simulation time 157304548 ps
CPU time 0.78 seconds
Started Jul 09 05:18:03 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 206084 kb
Host smart-93128bee-0448-42f3-9db1-bb7bd5ef16c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82761
4731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.827614731
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1242496906
Short name T1361
Test name
Test status
Simulation time 244941883 ps
CPU time 0.98 seconds
Started Jul 09 05:17:59 PM PDT 24
Finished Jul 09 05:18:02 PM PDT 24
Peak memory 205992 kb
Host smart-cf8d91cb-346d-44d1-8496-f756de3d931e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1242496906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1242496906
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1104797285
Short name T1235
Test name
Test status
Simulation time 157154812 ps
CPU time 0.76 seconds
Started Jul 09 05:18:04 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 205964 kb
Host smart-2af71492-dd7f-4266-9b3a-d871579d48a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11047
97285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1104797285
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3745031286
Short name T1741
Test name
Test status
Simulation time 49572347 ps
CPU time 0.68 seconds
Started Jul 09 05:18:04 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 205952 kb
Host smart-13e3c462-91fc-40d7-b9eb-83bb513b4aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37450
31286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3745031286
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.6342170
Short name T88
Test name
Test status
Simulation time 21552397961 ps
CPU time 47.88 seconds
Started Jul 09 05:18:01 PM PDT 24
Finished Jul 09 05:18:50 PM PDT 24
Peak memory 206460 kb
Host smart-ba7e3d2b-f184-42db-afc8-77243adb22a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63421
70 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.6342170
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1014529167
Short name T2216
Test name
Test status
Simulation time 172142204 ps
CPU time 0.93 seconds
Started Jul 09 05:18:03 PM PDT 24
Finished Jul 09 05:18:05 PM PDT 24
Peak memory 206148 kb
Host smart-4ed88ae8-5cfc-41d7-aa79-42e012570749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
29167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1014529167
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3081944838
Short name T459
Test name
Test status
Simulation time 204519082 ps
CPU time 0.94 seconds
Started Jul 09 05:18:00 PM PDT 24
Finished Jul 09 05:18:02 PM PDT 24
Peak memory 206128 kb
Host smart-0e2e6f78-26fd-4607-ad62-3d1afee6903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30819
44838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3081944838
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3901078114
Short name T1273
Test name
Test status
Simulation time 211772511 ps
CPU time 0.91 seconds
Started Jul 09 05:18:01 PM PDT 24
Finished Jul 09 05:18:03 PM PDT 24
Peak memory 206052 kb
Host smart-f3b7e108-ffb5-4275-8616-289df06ee3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39010
78114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3901078114
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1153689686
Short name T1787
Test name
Test status
Simulation time 159696063 ps
CPU time 0.84 seconds
Started Jul 09 05:18:05 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206044 kb
Host smart-d4513fe3-11a4-4731-9cbd-c57428ec0c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
89686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1153689686
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.959014557
Short name T860
Test name
Test status
Simulation time 136515790 ps
CPU time 0.76 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206148 kb
Host smart-7b17f8cc-b151-4a71-bf39-39313ceb3a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95901
4557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.959014557
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.762166812
Short name T2297
Test name
Test status
Simulation time 190306468 ps
CPU time 0.86 seconds
Started Jul 09 05:18:05 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206156 kb
Host smart-638377e0-c7a0-4183-b00d-8991388501c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76216
6812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.762166812
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3310451164
Short name T1531
Test name
Test status
Simulation time 155680800 ps
CPU time 0.81 seconds
Started Jul 09 05:18:04 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206160 kb
Host smart-b10eb0b1-0aea-4c34-a536-62b641d4f76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33104
51164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3310451164
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.130652872
Short name T997
Test name
Test status
Simulation time 249014083 ps
CPU time 1.01 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206064 kb
Host smart-61401c4c-23d6-449f-8ace-9ef76ea43b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065
2872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.130652872
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.305025255
Short name T2220
Test name
Test status
Simulation time 5998831875 ps
CPU time 169.13 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:20:56 PM PDT 24
Peak memory 206412 kb
Host smart-270106fa-0e00-4195-ba20-689ec32d0c6a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=305025255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.305025255
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3483142702
Short name T1861
Test name
Test status
Simulation time 164079032 ps
CPU time 0.79 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206020 kb
Host smart-f084466f-a8bf-4bc7-989e-568024546531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34831
42702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3483142702
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1901386634
Short name T313
Test name
Test status
Simulation time 156826647 ps
CPU time 0.79 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206048 kb
Host smart-32e64f04-411a-4ba0-bfdc-319cb1b4519c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19013
86634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1901386634
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.263506406
Short name T2646
Test name
Test status
Simulation time 611473954 ps
CPU time 1.51 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206128 kb
Host smart-2c123c45-6c93-4775-9470-5415e6c33fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26350
6406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.263506406
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2489456547
Short name T1680
Test name
Test status
Simulation time 5680093087 ps
CPU time 156.28 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:20:44 PM PDT 24
Peak memory 206464 kb
Host smart-31c592e6-c85d-4dfa-97ff-c53c00e5dc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24894
56547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2489456547
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1090557720
Short name T1668
Test name
Test status
Simulation time 33730634 ps
CPU time 0.68 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206092 kb
Host smart-423413f8-81dc-40bc-963f-bd18b233e3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1090557720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1090557720
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2691319984
Short name T224
Test name
Test status
Simulation time 3869837406 ps
CPU time 4.78 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206320 kb
Host smart-41776535-8ec1-4c6a-bf09-5c80ff8a73a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2691319984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2691319984
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3448672373
Short name T717
Test name
Test status
Simulation time 13387999699 ps
CPU time 12.21 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:20 PM PDT 24
Peak memory 206292 kb
Host smart-07a369ca-3fc6-4ab8-b7a1-be375d5ef358
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3448672373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3448672373
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3089645104
Short name T1313
Test name
Test status
Simulation time 23297008519 ps
CPU time 23.09 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:30 PM PDT 24
Peak memory 206156 kb
Host smart-afb3d09a-a0f6-4fe0-bc5f-7f7e73c5e774
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3089645104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3089645104
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2286620438
Short name T1983
Test name
Test status
Simulation time 166622624 ps
CPU time 0.84 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206068 kb
Host smart-7483f530-6ef8-47c8-8e3a-272b9c5ee9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22866
20438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2286620438
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2791588414
Short name T1804
Test name
Test status
Simulation time 159231968 ps
CPU time 0.85 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206008 kb
Host smart-5c10056f-9c26-4269-8592-fc27cd5dc539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
88414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2791588414
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.822063141
Short name T960
Test name
Test status
Simulation time 238841642 ps
CPU time 1.04 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:08 PM PDT 24
Peak memory 206148 kb
Host smart-d6cc21a4-a31d-4e69-a875-23069cfe4c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82206
3141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.822063141
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3670478868
Short name T1932
Test name
Test status
Simulation time 1012209574 ps
CPU time 2.37 seconds
Started Jul 09 05:18:04 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206288 kb
Host smart-bff7a90f-8244-4ee6-856f-95e95e410b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36704
78868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3670478868
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.697161585
Short name T1839
Test name
Test status
Simulation time 7091675153 ps
CPU time 13.66 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206372 kb
Host smart-6299e574-961a-4a7f-96a4-decdbf902c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69716
1585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.697161585
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3477853441
Short name T2367
Test name
Test status
Simulation time 384404430 ps
CPU time 1.28 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206068 kb
Host smart-620afcdf-7aff-4b11-a5bc-a5721a3091c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
53441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3477853441
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1497143150
Short name T2640
Test name
Test status
Simulation time 149271976 ps
CPU time 0.81 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206160 kb
Host smart-64baf0c7-6119-4aad-beb0-d3396d1bd611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14971
43150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1497143150
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1560283626
Short name T570
Test name
Test status
Simulation time 38662815 ps
CPU time 0.65 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206080 kb
Host smart-338b0d74-b0b8-4d09-ae64-e746086d9754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15602
83626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1560283626
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2822450254
Short name T2026
Test name
Test status
Simulation time 967173311 ps
CPU time 2.3 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206320 kb
Host smart-7877e3b5-8471-4e7c-a61b-6c6593d4a030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224
50254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2822450254
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3834440220
Short name T1687
Test name
Test status
Simulation time 269036811 ps
CPU time 1.67 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206284 kb
Host smart-89c50736-cb7e-4fd8-acd3-4ec6744d1730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38344
40220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3834440220
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.416673155
Short name T867
Test name
Test status
Simulation time 209612739 ps
CPU time 0.87 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206016 kb
Host smart-6f160877-b41e-40cb-9871-276704f30531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
3155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.416673155
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.587364817
Short name T2661
Test name
Test status
Simulation time 224711619 ps
CPU time 0.84 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206112 kb
Host smart-7cc0b92e-a251-439a-adf2-8d0b463c77cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58736
4817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.587364817
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2731582868
Short name T1691
Test name
Test status
Simulation time 170177245 ps
CPU time 0.85 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206004 kb
Host smart-ec4f1bfe-dda5-4e06-af6b-fc2b474a22fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
82868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2731582868
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3207542943
Short name T366
Test name
Test status
Simulation time 179467021 ps
CPU time 0.87 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206128 kb
Host smart-b7f40f9d-17e2-40cf-b31c-6835ef43d41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32075
42943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3207542943
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.4065536731
Short name T1493
Test name
Test status
Simulation time 23337857556 ps
CPU time 23.2 seconds
Started Jul 09 05:18:05 PM PDT 24
Finished Jul 09 05:18:29 PM PDT 24
Peak memory 206176 kb
Host smart-90cd9192-945d-4284-b83f-6fceb1e42389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655
36731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.4065536731
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1707273577
Short name T2038
Test name
Test status
Simulation time 3299692401 ps
CPU time 3.92 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206124 kb
Host smart-6d8177f9-5d78-42a8-b49f-219f667e6148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17072
73577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1707273577
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.311065424
Short name T1192
Test name
Test status
Simulation time 10835446614 ps
CPU time 110.56 seconds
Started Jul 09 05:18:05 PM PDT 24
Finished Jul 09 05:19:56 PM PDT 24
Peak memory 206484 kb
Host smart-659a190b-23f8-4c87-ac36-f781409cb6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31106
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.311065424
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2853745543
Short name T1634
Test name
Test status
Simulation time 4508925127 ps
CPU time 44.3 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206388 kb
Host smart-f8147d27-fa8d-46b1-933a-09ae947ed83b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2853745543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2853745543
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.3501283139
Short name T810
Test name
Test status
Simulation time 261483933 ps
CPU time 0.98 seconds
Started Jul 09 05:18:04 PM PDT 24
Finished Jul 09 05:18:06 PM PDT 24
Peak memory 206124 kb
Host smart-e8cebfc8-99e5-4962-9d86-1ae4f8be9b18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3501283139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.3501283139
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3011376187
Short name T1733
Test name
Test status
Simulation time 190037865 ps
CPU time 0.9 seconds
Started Jul 09 05:18:06 PM PDT 24
Finished Jul 09 05:18:07 PM PDT 24
Peak memory 206060 kb
Host smart-132b89e5-8966-492e-937c-72e45ee6367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
76187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3011376187
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.128744248
Short name T495
Test name
Test status
Simulation time 5822057718 ps
CPU time 55.54 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:19:07 PM PDT 24
Peak memory 206404 kb
Host smart-d1d4b89a-606f-4acf-886d-4a55012a36b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12874
4248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.128744248
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.974538253
Short name T2123
Test name
Test status
Simulation time 3200525993 ps
CPU time 29.12 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:39 PM PDT 24
Peak memory 206396 kb
Host smart-8327d4ee-e40a-405c-9c4c-bf6bca732bbb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=974538253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.974538253
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3938434114
Short name T315
Test name
Test status
Simulation time 160606335 ps
CPU time 0.84 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206108 kb
Host smart-2a9aa746-79ec-40f8-a187-57aef30e426f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3938434114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3938434114
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.545960614
Short name T1183
Test name
Test status
Simulation time 203765515 ps
CPU time 0.91 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:11 PM PDT 24
Peak memory 206060 kb
Host smart-a620175f-980a-42c5-818d-f98db7cd4a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54596
0614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.545960614
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4115130119
Short name T2023
Test name
Test status
Simulation time 246020346 ps
CPU time 0.89 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206088 kb
Host smart-6c3c5790-f207-4a0f-9b46-6171e25b6316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
30119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4115130119
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1567328773
Short name T2454
Test name
Test status
Simulation time 221494460 ps
CPU time 0.88 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:15 PM PDT 24
Peak memory 206120 kb
Host smart-39cd7936-b422-42c8-a45c-290b439076b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
28773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1567328773
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2513889456
Short name T2438
Test name
Test status
Simulation time 143642544 ps
CPU time 0.85 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206024 kb
Host smart-e1acad2d-ef6a-41da-86dd-fcdefa369c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25138
89456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2513889456
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1815106879
Short name T1335
Test name
Test status
Simulation time 172161167 ps
CPU time 0.84 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206016 kb
Host smart-477563e4-bff9-40a0-905c-0c3c801a57db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18151
06879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1815106879
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.4211664867
Short name T744
Test name
Test status
Simulation time 175293975 ps
CPU time 0.86 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206380 kb
Host smart-2bf1acfd-cc20-4443-9e9f-711ba672e223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116
64867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.4211664867
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3394795964
Short name T2368
Test name
Test status
Simulation time 230614670 ps
CPU time 0.99 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:10 PM PDT 24
Peak memory 206104 kb
Host smart-4881a028-199f-4311-9edd-008a332199e1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3394795964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3394795964
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.264480652
Short name T1791
Test name
Test status
Simulation time 175153223 ps
CPU time 0.77 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206052 kb
Host smart-839c599c-4c49-4740-94ec-74f3e2c562b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448
0652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.264480652
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3695485841
Short name T389
Test name
Test status
Simulation time 45317281 ps
CPU time 0.66 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206132 kb
Host smart-0d64183e-6271-46d4-9226-17f1b8f7db6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
85841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3695485841
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.832993971
Short name T2078
Test name
Test status
Simulation time 22266639140 ps
CPU time 50.37 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 214672 kb
Host smart-69ba3eba-c1ee-4803-b34f-023340acb94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83299
3971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.832993971
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2493877666
Short name T2619
Test name
Test status
Simulation time 220948865 ps
CPU time 0.87 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:18:13 PM PDT 24
Peak memory 206132 kb
Host smart-763b0e71-b40a-4ffd-910f-6aca00298b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
77666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2493877666
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2974981478
Short name T1656
Test name
Test status
Simulation time 180797525 ps
CPU time 0.85 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206120 kb
Host smart-ec9090de-8a02-418e-87c0-c1053456a872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
81478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2974981478
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.1482352969
Short name T21
Test name
Test status
Simulation time 159986394 ps
CPU time 0.87 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206120 kb
Host smart-c05311e9-d7fd-4d32-8af4-47e98b70b0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823
52969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.1482352969
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2616768737
Short name T475
Test name
Test status
Simulation time 193302436 ps
CPU time 0.82 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206168 kb
Host smart-89b7575b-1408-4b70-a97e-47620234836a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167
68737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2616768737
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2184661228
Short name T3
Test name
Test status
Simulation time 152656740 ps
CPU time 0.78 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206140 kb
Host smart-ee788a02-48fe-45d0-a40f-ed077aed3abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
61228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2184661228
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1009742303
Short name T1833
Test name
Test status
Simulation time 143437513 ps
CPU time 0.8 seconds
Started Jul 09 05:18:12 PM PDT 24
Finished Jul 09 05:18:15 PM PDT 24
Peak memory 206160 kb
Host smart-8b560d0a-a24a-4d61-9c72-577fb86edfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10097
42303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1009742303
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2164449828
Short name T2462
Test name
Test status
Simulation time 150407757 ps
CPU time 0.78 seconds
Started Jul 09 05:18:07 PM PDT 24
Finished Jul 09 05:18:09 PM PDT 24
Peak memory 206156 kb
Host smart-7610a119-63f2-4acb-b187-653cbd52a8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
49828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2164449828
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1981804827
Short name T342
Test name
Test status
Simulation time 223795029 ps
CPU time 0.91 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:18:13 PM PDT 24
Peak memory 206144 kb
Host smart-5b1a8c48-0f8b-4c8a-9b68-e843b2632307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19818
04827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1981804827
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1026525629
Short name T146
Test name
Test status
Simulation time 5671811275 ps
CPU time 162.09 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:20:54 PM PDT 24
Peak memory 206460 kb
Host smart-f1c8aab7-55ba-40fe-b250-d88435ab7120
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1026525629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1026525629
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2172556330
Short name T1443
Test name
Test status
Simulation time 185759361 ps
CPU time 0.81 seconds
Started Jul 09 05:18:12 PM PDT 24
Finished Jul 09 05:18:15 PM PDT 24
Peak memory 206108 kb
Host smart-4d0a9516-d53d-4220-95e7-398e9a7102fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21725
56330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2172556330
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3850336891
Short name T1617
Test name
Test status
Simulation time 187191011 ps
CPU time 0.86 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:18:12 PM PDT 24
Peak memory 206080 kb
Host smart-7bad6969-06a8-449f-add4-1bcaad7abef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
36891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3850336891
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2073556866
Short name T23
Test name
Test status
Simulation time 1386381165 ps
CPU time 2.73 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:16 PM PDT 24
Peak memory 206252 kb
Host smart-e98ee1ef-24a7-4827-83c6-ee7516dcd6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
56866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2073556866
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3866992225
Short name T2400
Test name
Test status
Simulation time 5501424742 ps
CPU time 54.26 seconds
Started Jul 09 05:18:09 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206316 kb
Host smart-d4f68cad-b370-46fe-b55f-a84af17b24ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
92225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3866992225
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2331368707
Short name T2613
Test name
Test status
Simulation time 47787028 ps
CPU time 0.71 seconds
Started Jul 09 05:18:19 PM PDT 24
Finished Jul 09 05:18:20 PM PDT 24
Peak memory 206192 kb
Host smart-7a0fcfb4-3fdd-4538-9917-6e0c832f1428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2331368707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2331368707
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3927845419
Short name T2267
Test name
Test status
Simulation time 3781537987 ps
CPU time 5.26 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206688 kb
Host smart-ea9b4802-e6b2-4cc7-bc4d-ac0d10990bb8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3927845419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3927845419
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1102160063
Short name T1665
Test name
Test status
Simulation time 13483842467 ps
CPU time 13.93 seconds
Started Jul 09 05:18:08 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206340 kb
Host smart-9f5f1c39-352b-4dae-af7f-2d01028c8b3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1102160063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1102160063
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3426768062
Short name T975
Test name
Test status
Simulation time 23354909757 ps
CPU time 25.99 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:39 PM PDT 24
Peak memory 206060 kb
Host smart-c00bb810-c0a6-4a45-92b3-449cd9c615c6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3426768062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3426768062
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.4140959022
Short name T1545
Test name
Test status
Simulation time 189340289 ps
CPU time 0.88 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206112 kb
Host smart-d0fe00f8-e7ca-4192-8473-09d287bb32cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
59022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.4140959022
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.791519667
Short name T2018
Test name
Test status
Simulation time 183172467 ps
CPU time 0.83 seconds
Started Jul 09 05:18:15 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206164 kb
Host smart-88f76fa5-b54e-4794-a579-9866b1e98eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79151
9667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.791519667
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3031566747
Short name T444
Test name
Test status
Simulation time 252718210 ps
CPU time 0.95 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206088 kb
Host smart-38f8fd40-b9bf-45ae-b866-840a1b003a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30315
66747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3031566747
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.188653254
Short name T1059
Test name
Test status
Simulation time 1340562049 ps
CPU time 3.22 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:19 PM PDT 24
Peak memory 206328 kb
Host smart-be4efee4-f1e7-4f43-b711-d468db8f78ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
3254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.188653254
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2628520868
Short name T2263
Test name
Test status
Simulation time 6339342361 ps
CPU time 13.66 seconds
Started Jul 09 05:18:12 PM PDT 24
Finished Jul 09 05:18:28 PM PDT 24
Peak memory 206284 kb
Host smart-24a043ea-2c20-4cdf-81d7-28b485831508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26285
20868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2628520868
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3890006379
Short name T2461
Test name
Test status
Simulation time 342974454 ps
CPU time 1.25 seconds
Started Jul 09 05:18:15 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206148 kb
Host smart-18fdcf36-7541-4435-8517-04231a74bc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
06379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3890006379
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.332322496
Short name T724
Test name
Test status
Simulation time 136716340 ps
CPU time 0.74 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:15 PM PDT 24
Peak memory 206068 kb
Host smart-8782a5f1-71a4-4097-9be8-b904d37e9352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33232
2496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.332322496
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.4149576947
Short name T1113
Test name
Test status
Simulation time 42120914 ps
CPU time 0.69 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206100 kb
Host smart-11c48c81-5400-497c-82bb-9e41c2b761c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41495
76947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.4149576947
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2235393876
Short name T1807
Test name
Test status
Simulation time 917027864 ps
CPU time 2.17 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206344 kb
Host smart-1ab46e37-e31b-4af5-9c5e-7e958896e532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22353
93876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2235393876
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.896660806
Short name T2332
Test name
Test status
Simulation time 182717933 ps
CPU time 1.99 seconds
Started Jul 09 05:18:13 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206372 kb
Host smart-9ceb0301-5b16-4def-a847-ce52b26f822b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89666
0806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.896660806
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.716016304
Short name T540
Test name
Test status
Simulation time 220950865 ps
CPU time 0.91 seconds
Started Jul 09 05:18:12 PM PDT 24
Finished Jul 09 05:18:15 PM PDT 24
Peak memory 206156 kb
Host smart-2d0f8d86-54d4-4a97-a588-8557b93e0d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71601
6304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.716016304
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1871335922
Short name T2424
Test name
Test status
Simulation time 156776995 ps
CPU time 0.81 seconds
Started Jul 09 05:18:10 PM PDT 24
Finished Jul 09 05:18:13 PM PDT 24
Peak memory 206012 kb
Host smart-e206f4e8-22a7-4e83-a44c-1bd32496bc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18713
35922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1871335922
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1754823513
Short name T761
Test name
Test status
Simulation time 261307423 ps
CPU time 0.96 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:18:14 PM PDT 24
Peak memory 206024 kb
Host smart-c75b2ecf-9559-43f2-87c1-07c57e8f2adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
23513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1754823513
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3125987678
Short name T2484
Test name
Test status
Simulation time 8359469380 ps
CPU time 82.81 seconds
Started Jul 09 05:18:17 PM PDT 24
Finished Jul 09 05:19:41 PM PDT 24
Peak memory 206432 kb
Host smart-f07f146f-7b5f-4265-adc7-02aca5d9dc5c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3125987678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3125987678
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1993844683
Short name T2515
Test name
Test status
Simulation time 220091490 ps
CPU time 0.83 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206120 kb
Host smart-72b09019-1fde-4304-9086-06b236ef20a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19938
44683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1993844683
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2857337861
Short name T1354
Test name
Test status
Simulation time 23349630918 ps
CPU time 26.96 seconds
Started Jul 09 05:18:13 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206120 kb
Host smart-ae4cfaa4-102a-4dbe-8adf-458b2b9021e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28573
37861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2857337861
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1753194485
Short name T664
Test name
Test status
Simulation time 3292658639 ps
CPU time 3.75 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:20 PM PDT 24
Peak memory 206152 kb
Host smart-3656985a-60ac-4512-ae31-9d3707b6d72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
94485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1753194485
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.4029426143
Short name T1506
Test name
Test status
Simulation time 9365246138 ps
CPU time 85.84 seconds
Started Jul 09 05:18:11 PM PDT 24
Finished Jul 09 05:19:40 PM PDT 24
Peak memory 206468 kb
Host smart-a4312b7b-65ac-4438-9bf3-eed594287209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40294
26143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.4029426143
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.4021803478
Short name T1554
Test name
Test status
Simulation time 7851767413 ps
CPU time 58.75 seconds
Started Jul 09 05:18:12 PM PDT 24
Finished Jul 09 05:19:14 PM PDT 24
Peak memory 206384 kb
Host smart-b650cbea-fd31-4b91-933d-703d832c6f81
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4021803478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.4021803478
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.4262675406
Short name T1193
Test name
Test status
Simulation time 242165954 ps
CPU time 0.9 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206124 kb
Host smart-a9a597d1-77cc-4a0e-a575-57e375048097
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4262675406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.4262675406
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1519216797
Short name T1420
Test name
Test status
Simulation time 259294476 ps
CPU time 0.91 seconds
Started Jul 09 05:18:14 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206108 kb
Host smart-cf3cfa75-8a6e-48eb-bd25-289f0bcd9b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
16797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1519216797
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2195143167
Short name T2429
Test name
Test status
Simulation time 4594122089 ps
CPU time 44.69 seconds
Started Jul 09 05:18:12 PM PDT 24
Finished Jul 09 05:18:59 PM PDT 24
Peak memory 206424 kb
Host smart-3066aa07-d98c-4a3b-8d8b-12d5f9b845c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21951
43167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2195143167
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3617644148
Short name T694
Test name
Test status
Simulation time 3828407957 ps
CPU time 27.98 seconds
Started Jul 09 05:18:13 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206344 kb
Host smart-19a32412-0b0b-4a2d-929d-bf3f2d00758c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3617644148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3617644148
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1139215458
Short name T1035
Test name
Test status
Simulation time 180575289 ps
CPU time 0.84 seconds
Started Jul 09 05:18:23 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206140 kb
Host smart-9dcc550e-0fb4-45c8-a4f0-4c1c04068887
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1139215458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1139215458
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3559685702
Short name T553
Test name
Test status
Simulation time 161032816 ps
CPU time 0.85 seconds
Started Jul 09 05:18:24 PM PDT 24
Finished Jul 09 05:18:26 PM PDT 24
Peak memory 206096 kb
Host smart-4d0cc865-8233-4b8c-b2f6-910fcd90b3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
85702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3559685702
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1377027231
Short name T1829
Test name
Test status
Simulation time 207749296 ps
CPU time 0.88 seconds
Started Jul 09 05:18:15 PM PDT 24
Finished Jul 09 05:18:17 PM PDT 24
Peak memory 206128 kb
Host smart-022cee2a-0659-47c7-8878-54128661245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
27231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1377027231
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1673407484
Short name T1732
Test name
Test status
Simulation time 184871959 ps
CPU time 0.85 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:46 PM PDT 24
Peak memory 206100 kb
Host smart-c508c69b-3b3d-4643-ba38-d75810ae317a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
07484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1673407484
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2306303043
Short name T1724
Test name
Test status
Simulation time 175442126 ps
CPU time 0.87 seconds
Started Jul 09 05:18:22 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206116 kb
Host smart-9ff9147e-c6e9-44e0-9dbd-a1333ae6709c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063
03043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2306303043
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3809093181
Short name T2677
Test name
Test status
Simulation time 173737844 ps
CPU time 0.81 seconds
Started Jul 09 05:18:30 PM PDT 24
Finished Jul 09 05:18:32 PM PDT 24
Peak memory 206012 kb
Host smart-39d980fc-e6ee-46ba-9590-ca8ad16d8921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090
93181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3809093181
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2597567083
Short name T24
Test name
Test status
Simulation time 153132420 ps
CPU time 0.81 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:31 PM PDT 24
Peak memory 206084 kb
Host smart-171c13a0-86a7-40ab-9dfe-43924482bef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25975
67083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2597567083
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3717047236
Short name T1661
Test name
Test status
Simulation time 267076872 ps
CPU time 1 seconds
Started Jul 09 05:18:23 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206136 kb
Host smart-63a839fc-f917-400d-8d96-45c6224b1afc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3717047236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3717047236
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1596612299
Short name T37
Test name
Test status
Simulation time 148412080 ps
CPU time 0.81 seconds
Started Jul 09 05:18:22 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206156 kb
Host smart-af3c0992-42bb-47dc-b537-9a5c96d6885c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15966
12299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1596612299
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1578719536
Short name T1928
Test name
Test status
Simulation time 26853068 ps
CPU time 0.66 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:32 PM PDT 24
Peak memory 206136 kb
Host smart-46336786-5756-40ec-9573-594957eb2063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
19536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1578719536
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.593687200
Short name T251
Test name
Test status
Simulation time 6114969378 ps
CPU time 15.06 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:18:41 PM PDT 24
Peak memory 206368 kb
Host smart-07293622-0506-4b78-9af6-cd99482726ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59368
7200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.593687200
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.4052883903
Short name T402
Test name
Test status
Simulation time 174374180 ps
CPU time 0.83 seconds
Started Jul 09 05:18:23 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206156 kb
Host smart-ccb1e4fc-5916-4055-bd03-17bf1b4ca73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
83903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.4052883903
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.332429414
Short name T548
Test name
Test status
Simulation time 217140365 ps
CPU time 0.91 seconds
Started Jul 09 05:18:30 PM PDT 24
Finished Jul 09 05:18:32 PM PDT 24
Peak memory 206120 kb
Host smart-fdbd110b-179b-4cf4-8bd6-dd69c2682594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
9414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.332429414
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1478169601
Short name T1487
Test name
Test status
Simulation time 258403635 ps
CPU time 0.9 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206020 kb
Host smart-0f3b2f02-32ae-42b1-b6ec-024207b526a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
69601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1478169601
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3862368043
Short name T1199
Test name
Test status
Simulation time 223041212 ps
CPU time 0.87 seconds
Started Jul 09 05:18:16 PM PDT 24
Finished Jul 09 05:18:18 PM PDT 24
Peak memory 206148 kb
Host smart-edf96d3b-a6e7-4e79-90d3-a8effda6f863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38623
68043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3862368043
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1385712554
Short name T1951
Test name
Test status
Simulation time 159429104 ps
CPU time 0.81 seconds
Started Jul 09 05:18:38 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206100 kb
Host smart-f29075df-eeef-4341-83a5-63d9e1ce3696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857
12554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1385712554
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3460735199
Short name T1394
Test name
Test status
Simulation time 147678662 ps
CPU time 0.75 seconds
Started Jul 09 05:18:27 PM PDT 24
Finished Jul 09 05:18:28 PM PDT 24
Peak memory 206128 kb
Host smart-af201538-3338-4508-b87f-9ecbfe84b89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
35199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3460735199
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2088675788
Short name T1353
Test name
Test status
Simulation time 171303947 ps
CPU time 0.83 seconds
Started Jul 09 05:18:23 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206064 kb
Host smart-2c52f1cc-93a0-4e38-acd4-8608ac14493f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886
75788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2088675788
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1984646549
Short name T793
Test name
Test status
Simulation time 221055107 ps
CPU time 0.94 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:31 PM PDT 24
Peak memory 206160 kb
Host smart-41721d0d-d2a4-436e-a52f-f2491c03961a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846
46549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1984646549
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2403929595
Short name T2700
Test name
Test status
Simulation time 4776084147 ps
CPU time 34.41 seconds
Started Jul 09 05:18:38 PM PDT 24
Finished Jul 09 05:19:14 PM PDT 24
Peak memory 206224 kb
Host smart-1f763111-b078-4471-8e93-8940cfc522dd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2403929595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2403929595
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1376034350
Short name T2395
Test name
Test status
Simulation time 174781487 ps
CPU time 0.82 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206060 kb
Host smart-e7d11971-39c6-4ec1-9a36-5b922a917977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
34350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1376034350
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.314997656
Short name T462
Test name
Test status
Simulation time 168815280 ps
CPU time 0.78 seconds
Started Jul 09 05:18:22 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206112 kb
Host smart-7fb4c90b-c102-4abf-970a-8c5ff17dc625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31499
7656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.314997656
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3140821208
Short name T246
Test name
Test status
Simulation time 1122387409 ps
CPU time 2.44 seconds
Started Jul 09 05:18:35 PM PDT 24
Finished Jul 09 05:18:39 PM PDT 24
Peak memory 206356 kb
Host smart-b0b5765f-7392-43e4-9788-4e8fc69a962e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31408
21208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3140821208
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.9399527
Short name T2199
Test name
Test status
Simulation time 7228347942 ps
CPU time 201.18 seconds
Started Jul 09 05:18:22 PM PDT 24
Finished Jul 09 05:21:44 PM PDT 24
Peak memory 206356 kb
Host smart-e61ed6cb-b3f0-474b-8b88-534a7cd5efdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93995
27 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.9399527
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.437668393
Short name T1129
Test name
Test status
Simulation time 44447520 ps
CPU time 0.7 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 206048 kb
Host smart-74498e6d-e1aa-4683-9ed0-85ad93a5a6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=437668393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.437668393
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2920207559
Short name T1581
Test name
Test status
Simulation time 3368145103 ps
CPU time 4.1 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 206108 kb
Host smart-ca4bdae5-1d87-4a43-91f5-fd9fdb259b8f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2920207559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2920207559
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3522964840
Short name T1299
Test name
Test status
Simulation time 13362927879 ps
CPU time 15.17 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206120 kb
Host smart-4e836e8f-2008-41c7-9c63-6cb047254deb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3522964840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3522964840
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.97225051
Short name T2281
Test name
Test status
Simulation time 23377848828 ps
CPU time 27.14 seconds
Started Jul 09 05:18:41 PM PDT 24
Finished Jul 09 05:19:10 PM PDT 24
Peak memory 206152 kb
Host smart-add5dc7e-f727-4a40-899a-59c3e6bc3e93
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=97225051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.97225051
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.776824292
Short name T1797
Test name
Test status
Simulation time 209345029 ps
CPU time 0.9 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 205992 kb
Host smart-529d8157-adff-4bd7-b18b-4439ec529e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77682
4292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.776824292
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.534510381
Short name T1530
Test name
Test status
Simulation time 140157089 ps
CPU time 0.78 seconds
Started Jul 09 05:18:22 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206368 kb
Host smart-edafa76a-bded-44e2-b06c-cd64e2fd27c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53451
0381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.534510381
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2889348196
Short name T992
Test name
Test status
Simulation time 485289250 ps
CPU time 1.56 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206016 kb
Host smart-f748623b-ba4b-4414-8559-5b71761d62a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
48196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2889348196
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1510389640
Short name T2004
Test name
Test status
Simulation time 1365296425 ps
CPU time 3 seconds
Started Jul 09 05:18:21 PM PDT 24
Finished Jul 09 05:18:24 PM PDT 24
Peak memory 206224 kb
Host smart-ab03126c-f1be-45df-9184-daec139d1500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15103
89640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1510389640
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2614758214
Short name T2342
Test name
Test status
Simulation time 19929282838 ps
CPU time 37.48 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:19:11 PM PDT 24
Peak memory 206352 kb
Host smart-07591324-a8c1-4ca0-a27f-51fd9436c637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26147
58214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2614758214
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1108538423
Short name T419
Test name
Test status
Simulation time 507897875 ps
CPU time 1.58 seconds
Started Jul 09 05:18:34 PM PDT 24
Finished Jul 09 05:18:37 PM PDT 24
Peak memory 206116 kb
Host smart-55280dc7-af5e-422f-8134-6b2f2f6ca120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11085
38423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1108538423
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.164689924
Short name T44
Test name
Test status
Simulation time 134383373 ps
CPU time 0.76 seconds
Started Jul 09 05:18:23 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206140 kb
Host smart-8cb1d927-8447-468b-9ec2-7b1bef70366d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16468
9924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.164689924
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1103169791
Short name T853
Test name
Test status
Simulation time 65318058 ps
CPU time 0.71 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:47 PM PDT 24
Peak memory 206104 kb
Host smart-b00a0750-1e18-49ca-a48a-d2bcac727aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031
69791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1103169791
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2733164060
Short name T1632
Test name
Test status
Simulation time 731397719 ps
CPU time 1.77 seconds
Started Jul 09 05:18:23 PM PDT 24
Finished Jul 09 05:18:26 PM PDT 24
Peak memory 206396 kb
Host smart-07fa5127-6bd2-43ad-a965-be7b47902ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
64060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2733164060
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4130787281
Short name T183
Test name
Test status
Simulation time 280564054 ps
CPU time 2.23 seconds
Started Jul 09 05:18:22 PM PDT 24
Finished Jul 09 05:18:25 PM PDT 24
Peak memory 206404 kb
Host smart-adc36925-85e9-4647-9dec-0b935622db73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
87281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4130787281
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.133010332
Short name T951
Test name
Test status
Simulation time 162559702 ps
CPU time 0.79 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:18:30 PM PDT 24
Peak memory 206148 kb
Host smart-1825e631-707d-4453-a4e7-da7cc16f348f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13301
0332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.133010332
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.591103623
Short name T1527
Test name
Test status
Simulation time 135242361 ps
CPU time 0.75 seconds
Started Jul 09 05:18:27 PM PDT 24
Finished Jul 09 05:18:28 PM PDT 24
Peak memory 206056 kb
Host smart-86df516f-3e0b-4a9a-aaa0-e1cbb438ef08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59110
3623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.591103623
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1691621883
Short name T726
Test name
Test status
Simulation time 162914805 ps
CPU time 0.8 seconds
Started Jul 09 05:18:21 PM PDT 24
Finished Jul 09 05:18:22 PM PDT 24
Peak memory 206056 kb
Host smart-a0ac8a05-a025-48dc-b16c-dd30d7975eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16916
21883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1691621883
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1565777929
Short name T658
Test name
Test status
Simulation time 7305084736 ps
CPU time 67.28 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:19:33 PM PDT 24
Peak memory 206372 kb
Host smart-57d2e14c-53dd-441f-a8d1-ded415bb5c82
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1565777929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1565777929
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1360542956
Short name T1210
Test name
Test status
Simulation time 179646525 ps
CPU time 0.84 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:30 PM PDT 24
Peak memory 206152 kb
Host smart-179b9bc1-cd2b-4805-a185-5d3194f8b0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
42956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1360542956
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2491341961
Short name T319
Test name
Test status
Simulation time 23279436637 ps
CPU time 24.55 seconds
Started Jul 09 05:18:26 PM PDT 24
Finished Jul 09 05:18:51 PM PDT 24
Peak memory 206088 kb
Host smart-e226a717-43e0-433d-8f36-0c1d64ae9033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24913
41961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2491341961
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1500076644
Short name T870
Test name
Test status
Simulation time 3283930899 ps
CPU time 3.84 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:18:38 PM PDT 24
Peak memory 206176 kb
Host smart-3e2a94d2-be35-4123-8c2e-b587683fb0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15000
76644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1500076644
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.621367939
Short name T1490
Test name
Test status
Simulation time 7849191967 ps
CPU time 206.94 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:22:05 PM PDT 24
Peak memory 206324 kb
Host smart-c5787b2e-2ac7-4be4-9fbb-3d7457ee0c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62136
7939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.621367939
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2380922929
Short name T1189
Test name
Test status
Simulation time 5009025942 ps
CPU time 43.45 seconds
Started Jul 09 05:18:41 PM PDT 24
Finished Jul 09 05:19:26 PM PDT 24
Peak memory 206240 kb
Host smart-abb4a151-c85b-468d-9fa6-3182331cf8c0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2380922929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2380922929
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1149956966
Short name T2521
Test name
Test status
Simulation time 242125999 ps
CPU time 0.94 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:18:26 PM PDT 24
Peak memory 206088 kb
Host smart-43eeade5-bd1d-4b04-bb0d-942b2a8e0051
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1149956966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1149956966
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1630194271
Short name T1446
Test name
Test status
Simulation time 251594161 ps
CPU time 0.98 seconds
Started Jul 09 05:18:24 PM PDT 24
Finished Jul 09 05:18:26 PM PDT 24
Peak memory 206068 kb
Host smart-5413f3b4-9018-4aa6-ab35-b38fe22a26e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16301
94271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1630194271
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3865697336
Short name T1498
Test name
Test status
Simulation time 5300923632 ps
CPU time 153.88 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:21:00 PM PDT 24
Peak memory 206288 kb
Host smart-e1cd1e12-d6db-403e-88a3-93989f983bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38656
97336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3865697336
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.4237167580
Short name T1849
Test name
Test status
Simulation time 6854653915 ps
CPU time 188.65 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:21:37 PM PDT 24
Peak memory 206284 kb
Host smart-86b9151a-b1fb-4280-9401-16f763b4f739
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4237167580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.4237167580
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3211478384
Short name T2403
Test name
Test status
Simulation time 161446511 ps
CPU time 0.79 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 205980 kb
Host smart-530f906a-71ca-48af-84c2-d3322eb4cb20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3211478384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3211478384
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.290408523
Short name T999
Test name
Test status
Simulation time 222883339 ps
CPU time 0.92 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206068 kb
Host smart-faf9d923-e3f5-46d4-b72e-696902e5d927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29040
8523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.290408523
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1815409085
Short name T125
Test name
Test status
Simulation time 247798097 ps
CPU time 0.9 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:47 PM PDT 24
Peak memory 206136 kb
Host smart-4ba5dfbf-ea5c-47a9-b12f-5c802eb1e342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18154
09085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1815409085
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3034726810
Short name T623
Test name
Test status
Simulation time 183187926 ps
CPU time 0.82 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206132 kb
Host smart-6bc114cf-85b0-4676-af47-35d95267d649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30347
26810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3034726810
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2377859893
Short name T2313
Test name
Test status
Simulation time 209447771 ps
CPU time 0.85 seconds
Started Jul 09 05:18:26 PM PDT 24
Finished Jul 09 05:18:28 PM PDT 24
Peak memory 206160 kb
Host smart-f58f7720-b832-47f9-8d64-c1113f2ce378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
59893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2377859893
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3025574202
Short name T848
Test name
Test status
Simulation time 151028089 ps
CPU time 0.75 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206112 kb
Host smart-defb5536-5ca9-4e79-9c82-ff20dc852cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30255
74202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3025574202
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1566600879
Short name T2086
Test name
Test status
Simulation time 169720534 ps
CPU time 0.79 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 206116 kb
Host smart-4f729a5c-4d75-47b3-b069-16ef1f1852a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15666
00879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1566600879
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1413931374
Short name T980
Test name
Test status
Simulation time 242256693 ps
CPU time 0.97 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:18:29 PM PDT 24
Peak memory 205984 kb
Host smart-a410527c-cf08-4280-b84f-16e8f65e3b4f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1413931374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1413931374
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1648929693
Short name T189
Test name
Test status
Simulation time 169791883 ps
CPU time 0.81 seconds
Started Jul 09 05:18:25 PM PDT 24
Finished Jul 09 05:18:27 PM PDT 24
Peak memory 206136 kb
Host smart-e5aa3f2b-b87d-4410-9922-1f320a4a761f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16489
29693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1648929693
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3372926112
Short name T2194
Test name
Test status
Simulation time 33372518 ps
CPU time 0.7 seconds
Started Jul 09 05:18:26 PM PDT 24
Finished Jul 09 05:18:28 PM PDT 24
Peak memory 206044 kb
Host smart-ecc44ab3-115b-4e3f-a3b9-1f25a0c448eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33729
26112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3372926112
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1289845490
Short name T287
Test name
Test status
Simulation time 192026730 ps
CPU time 0.84 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:47 PM PDT 24
Peak memory 206140 kb
Host smart-1a0f3d61-a305-456f-8584-3e8965678141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
45490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1289845490
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1956776961
Short name T2658
Test name
Test status
Simulation time 180216377 ps
CPU time 0.87 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:18:30 PM PDT 24
Peak memory 206136 kb
Host smart-493d1878-ba04-4fa7-b474-4730589e8da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567
76961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1956776961
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2899717776
Short name T1731
Test name
Test status
Simulation time 228373917 ps
CPU time 0.88 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:18:30 PM PDT 24
Peak memory 206112 kb
Host smart-173c5f71-e257-480b-bd76-85850e4861a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28997
17776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2899717776
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1883742299
Short name T1260
Test name
Test status
Simulation time 170557833 ps
CPU time 0.82 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206064 kb
Host smart-139c4c77-44d2-4b66-b1c9-6abb73331108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837
42299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1883742299
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.197784353
Short name T911
Test name
Test status
Simulation time 148443298 ps
CPU time 0.81 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 206016 kb
Host smart-dbbbf5cf-dfae-48d4-a5f6-ea1e76487f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19778
4353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.197784353
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3748176078
Short name T1604
Test name
Test status
Simulation time 160349769 ps
CPU time 0.82 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 206144 kb
Host smart-86611ede-1e37-4e48-bc63-7a0a61c35887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37481
76078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3748176078
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1155008850
Short name T1362
Test name
Test status
Simulation time 169636843 ps
CPU time 0.8 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206112 kb
Host smart-3672ca05-4b06-4ffe-ae60-f1a5ded4114b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11550
08850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1155008850
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4158631431
Short name T2394
Test name
Test status
Simulation time 234142180 ps
CPU time 0.97 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206112 kb
Host smart-17245933-0e27-493b-a982-0e245b623620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41586
31431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4158631431
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3154007157
Short name T654
Test name
Test status
Simulation time 4330485222 ps
CPU time 117.22 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:20:27 PM PDT 24
Peak memory 206444 kb
Host smart-2e10ab29-ce9b-40a8-9d4e-b803674fbc7b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3154007157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3154007157
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2268450042
Short name T1509
Test name
Test status
Simulation time 158532476 ps
CPU time 0.77 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206124 kb
Host smart-951b2df0-f48c-442e-a334-0bd3e59309b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22684
50042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2268450042
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.269400437
Short name T1463
Test name
Test status
Simulation time 171494496 ps
CPU time 0.78 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206132 kb
Host smart-bed5a3cf-03e4-4953-a12f-b38e41e3ad66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26940
0437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.269400437
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1992999903
Short name T1675
Test name
Test status
Simulation time 966969491 ps
CPU time 2.14 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 206312 kb
Host smart-109fd5d4-b64b-4882-bf70-1a309ff3fb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
99903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1992999903
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2305056272
Short name T919
Test name
Test status
Simulation time 3482833469 ps
CPU time 25.77 seconds
Started Jul 09 05:18:38 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206348 kb
Host smart-be6d63e0-f4cf-4c71-9afd-11a374d15209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
56272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2305056272
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3468944288
Short name T1686
Test name
Test status
Simulation time 51492481 ps
CPU time 0.7 seconds
Started Jul 09 05:18:32 PM PDT 24
Finished Jul 09 05:18:34 PM PDT 24
Peak memory 206092 kb
Host smart-dff867b6-5ead-4fec-b3c0-8962a7476523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3468944288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3468944288
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.601281541
Short name T988
Test name
Test status
Simulation time 3803444727 ps
CPU time 4.37 seconds
Started Jul 09 05:18:32 PM PDT 24
Finished Jul 09 05:18:37 PM PDT 24
Peak memory 206348 kb
Host smart-d8c8a55f-25a2-481f-8b87-1898c2e3c4e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=601281541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.601281541
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3833279605
Short name T429
Test name
Test status
Simulation time 13361480241 ps
CPU time 12.67 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206160 kb
Host smart-f2866f75-8c4a-4ec7-89d9-e14ab772a643
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3833279605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3833279605
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.731649467
Short name T1677
Test name
Test status
Simulation time 23361497583 ps
CPU time 26.73 seconds
Started Jul 09 05:18:27 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206136 kb
Host smart-9be5bb84-81b2-4a4b-b7d8-5535f82a84fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=731649467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.731649467
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.845007848
Short name T592
Test name
Test status
Simulation time 196633731 ps
CPU time 0.81 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206128 kb
Host smart-8a723ffd-2b97-4936-a047-2dd43ee634a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84500
7848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.845007848
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3714670022
Short name T2221
Test name
Test status
Simulation time 158829949 ps
CPU time 0.81 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206152 kb
Host smart-213781b9-9a21-4a59-a4ce-9bb89212f647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37146
70022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3714670022
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2546355331
Short name T1763
Test name
Test status
Simulation time 225229860 ps
CPU time 0.9 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206060 kb
Host smart-0fa2e868-7027-4bcc-86c0-cfec28d245af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25463
55331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2546355331
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3690822044
Short name T1516
Test name
Test status
Simulation time 682128101 ps
CPU time 1.59 seconds
Started Jul 09 05:18:30 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 206372 kb
Host smart-a1cac349-fd7b-4a4c-9a59-21942d2a654e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36908
22044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3690822044
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1093219408
Short name T1586
Test name
Test status
Simulation time 10926402291 ps
CPU time 19.62 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:19:11 PM PDT 24
Peak memory 206360 kb
Host smart-f7cdaca9-255c-468d-bff7-fc17da83405d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
19408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1093219408
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2380953685
Short name T2444
Test name
Test status
Simulation time 463385556 ps
CPU time 1.48 seconds
Started Jul 09 05:18:41 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 206052 kb
Host smart-e4acacb4-e831-46aa-96ee-aaebf54599ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23809
53685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2380953685
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3081348215
Short name T2650
Test name
Test status
Simulation time 142837682 ps
CPU time 0.74 seconds
Started Jul 09 05:18:32 PM PDT 24
Finished Jul 09 05:18:34 PM PDT 24
Peak memory 206124 kb
Host smart-8d749550-df0f-418b-8313-0fa3a50432db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30813
48215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3081348215
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.408551083
Short name T2211
Test name
Test status
Simulation time 68523174 ps
CPU time 0.68 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:31 PM PDT 24
Peak memory 206124 kb
Host smart-2ad2bbb1-baaf-47ce-be75-67f564117b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40855
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.408551083
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2795026405
Short name T2094
Test name
Test status
Simulation time 893776097 ps
CPU time 2.1 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:32 PM PDT 24
Peak memory 206360 kb
Host smart-83257ea8-f7cc-4d49-b795-8a678bff60a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27950
26405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2795026405
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2426047500
Short name T2464
Test name
Test status
Simulation time 211289888 ps
CPU time 1.44 seconds
Started Jul 09 05:18:39 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206252 kb
Host smart-3257baf9-45ac-4e34-94d4-28c9565242a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
47500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2426047500
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2277730799
Short name T736
Test name
Test status
Simulation time 217990487 ps
CPU time 0.88 seconds
Started Jul 09 05:18:28 PM PDT 24
Finished Jul 09 05:18:29 PM PDT 24
Peak memory 206128 kb
Host smart-b12f0068-515c-4b8e-b03c-d8828554c5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
30799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2277730799
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3059351770
Short name T2512
Test name
Test status
Simulation time 152677479 ps
CPU time 0.78 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:33 PM PDT 24
Peak memory 206116 kb
Host smart-a26fdf80-d3b5-4593-9ee5-e00256c35c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30593
51770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3059351770
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2139268924
Short name T445
Test name
Test status
Simulation time 167240839 ps
CPU time 0.87 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:47 PM PDT 24
Peak memory 206128 kb
Host smart-df0f1b90-8620-4567-aafd-e2ac354cf18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21392
68924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2139268924
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.4134149153
Short name T1706
Test name
Test status
Simulation time 8138323686 ps
CPU time 60.43 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:19:30 PM PDT 24
Peak memory 206388 kb
Host smart-1f28811b-e1a9-421c-802e-c2f7fee9f585
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4134149153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.4134149153
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1989278170
Short name T1567
Test name
Test status
Simulation time 164618730 ps
CPU time 0.78 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:18:39 PM PDT 24
Peak memory 206152 kb
Host smart-7a3264cc-36a6-4dc2-89c4-b4dee28181aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
78170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1989278170
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3570434931
Short name T28
Test name
Test status
Simulation time 23299343390 ps
CPU time 24.79 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:57 PM PDT 24
Peak memory 206128 kb
Host smart-a1d06b62-c7a8-4aab-9ad0-343eb8d145b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
34931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3570434931
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.785739586
Short name T2358
Test name
Test status
Simulation time 3290367548 ps
CPU time 4.18 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:51 PM PDT 24
Peak memory 206176 kb
Host smart-8605a5c3-b5d7-4e58-ad48-f55103dd49f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78573
9586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.785739586
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2736199596
Short name T2060
Test name
Test status
Simulation time 8809204177 ps
CPU time 62.56 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:19:34 PM PDT 24
Peak memory 206468 kb
Host smart-bf83b012-3c9a-411c-b996-64cd173615c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27361
99596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2736199596
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2122626297
Short name T2029
Test name
Test status
Simulation time 3850578896 ps
CPU time 108.41 seconds
Started Jul 09 05:18:32 PM PDT 24
Finished Jul 09 05:20:22 PM PDT 24
Peak memory 206336 kb
Host smart-58f5297d-3a98-43b1-b145-78baf4d1aca0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2122626297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2122626297
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3736230598
Short name T2436
Test name
Test status
Simulation time 255971547 ps
CPU time 0.88 seconds
Started Jul 09 05:18:29 PM PDT 24
Finished Jul 09 05:18:31 PM PDT 24
Peak memory 206108 kb
Host smart-bc50951b-4bb3-409a-9175-23104c789105
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3736230598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3736230598
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2825402381
Short name T2685
Test name
Test status
Simulation time 190235764 ps
CPU time 0.88 seconds
Started Jul 09 05:18:51 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206136 kb
Host smart-6f5fe982-75ba-49fe-838e-f55d07154f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28254
02381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2825402381
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.1515291506
Short name T2189
Test name
Test status
Simulation time 6209818326 ps
CPU time 170.43 seconds
Started Jul 09 05:18:39 PM PDT 24
Finished Jul 09 05:21:31 PM PDT 24
Peak memory 206412 kb
Host smart-97a539fe-5a3c-4ecf-a10b-f18f12dc047f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15152
91506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.1515291506
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.219643117
Short name T2377
Test name
Test status
Simulation time 4582984730 ps
CPU time 32 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206452 kb
Host smart-ff970591-6128-4bd1-8ebc-16fe7fb63889
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=219643117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.219643117
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1596395362
Short name T329
Test name
Test status
Simulation time 158904963 ps
CPU time 0.75 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206112 kb
Host smart-5a20185e-6fc8-478f-be20-0434a33e3c2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1596395362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1596395362
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.4116241566
Short name T247
Test name
Test status
Simulation time 143052653 ps
CPU time 0.77 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206060 kb
Host smart-b3a03917-22f0-48f0-88ef-b1111f9ae544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41162
41566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.4116241566
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3915454282
Short name T2481
Test name
Test status
Simulation time 201907849 ps
CPU time 0.87 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:18:38 PM PDT 24
Peak memory 206156 kb
Host smart-257121d7-18d1-4101-a1cb-fd27353494ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
54282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3915454282
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1472785360
Short name T1387
Test name
Test status
Simulation time 209074988 ps
CPU time 0.89 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:18:34 PM PDT 24
Peak memory 206052 kb
Host smart-72f193e7-ba49-420d-9f2b-27c729531529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14727
85360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1472785360
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.217037109
Short name T1046
Test name
Test status
Simulation time 182530029 ps
CPU time 0.81 seconds
Started Jul 09 05:18:35 PM PDT 24
Finished Jul 09 05:18:37 PM PDT 24
Peak memory 205968 kb
Host smart-37284b7e-c1de-4b51-b273-386d6d8a9568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21703
7109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.217037109
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.228579868
Short name T376
Test name
Test status
Simulation time 169860799 ps
CPU time 0.82 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 205992 kb
Host smart-b7246468-8628-437e-aaa7-1bb3dd4f54b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
9868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.228579868
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1665359593
Short name T703
Test name
Test status
Simulation time 220504375 ps
CPU time 0.84 seconds
Started Jul 09 05:18:32 PM PDT 24
Finished Jul 09 05:18:34 PM PDT 24
Peak memory 206052 kb
Host smart-680f3ef0-946d-467c-9ff3-6a0085e4483b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16653
59593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1665359593
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.941115468
Short name T1316
Test name
Test status
Simulation time 243670498 ps
CPU time 0.95 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:18:50 PM PDT 24
Peak memory 205980 kb
Host smart-6bddeb02-c6b9-4cc5-a5c1-7cc848773f5e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=941115468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.941115468
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3357175643
Short name T932
Test name
Test status
Simulation time 172953698 ps
CPU time 0.78 seconds
Started Jul 09 05:18:34 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206056 kb
Host smart-bb4cb74a-3599-487b-a0d5-8f993570afe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33571
75643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3357175643
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1502610812
Short name T709
Test name
Test status
Simulation time 32014231 ps
CPU time 0.65 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206056 kb
Host smart-83c8158f-f6dd-4b86-8d2a-343a84cd6204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15026
10812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1502610812
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3991157815
Short name T1411
Test name
Test status
Simulation time 18709212937 ps
CPU time 43.28 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:19:23 PM PDT 24
Peak memory 206452 kb
Host smart-4a207bc8-562f-440f-81ea-cc66607821b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39911
57815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3991157815
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3796366570
Short name T1196
Test name
Test status
Simulation time 179409769 ps
CPU time 0.9 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206132 kb
Host smart-2c4e90e4-9d19-4046-8f6f-5dfd4571fc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963
66570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3796366570
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2891819230
Short name T1279
Test name
Test status
Simulation time 196926626 ps
CPU time 0.84 seconds
Started Jul 09 05:18:35 PM PDT 24
Finished Jul 09 05:18:37 PM PDT 24
Peak memory 206040 kb
Host smart-06bd08e5-79ca-4809-ad1e-04ef57932ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28918
19230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2891819230
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2916963929
Short name T2647
Test name
Test status
Simulation time 196135177 ps
CPU time 0.82 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:18:38 PM PDT 24
Peak memory 206096 kb
Host smart-e6fc6846-af24-47e2-b6dd-4b8118433e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
63929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2916963929
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.579359859
Short name T1548
Test name
Test status
Simulation time 151724913 ps
CPU time 0.77 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 205960 kb
Host smart-d814e5c5-89e0-4257-9e16-4362bf5b84b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57935
9859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.579359859
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.111699205
Short name T2560
Test name
Test status
Simulation time 169274329 ps
CPU time 0.83 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206068 kb
Host smart-52454751-1ca4-45c4-9ddc-1678803e170a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11169
9205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.111699205
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3340615065
Short name T2666
Test name
Test status
Simulation time 149421851 ps
CPU time 0.75 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 205996 kb
Host smart-7c1b7fe9-4f04-4b56-8ce3-4532926543dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33406
15065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3340615065
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1092347765
Short name T2208
Test name
Test status
Simulation time 143573976 ps
CPU time 0.76 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206132 kb
Host smart-efd1e7ac-5c77-47d9-9af6-25cbbe9be1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
47765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1092347765
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3430243085
Short name T904
Test name
Test status
Simulation time 218250586 ps
CPU time 0.93 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206092 kb
Host smart-c56ea6b9-0809-412f-875c-2d352a66b794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34302
43085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3430243085
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.431383633
Short name T2712
Test name
Test status
Simulation time 5704507817 ps
CPU time 159.41 seconds
Started Jul 09 05:18:31 PM PDT 24
Finished Jul 09 05:21:11 PM PDT 24
Peak memory 206380 kb
Host smart-db72e328-697c-4362-8f2c-08b1c702a6c6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=431383633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.431383633
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1272634872
Short name T1879
Test name
Test status
Simulation time 197660947 ps
CPU time 0.87 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206160 kb
Host smart-88035472-ba6f-481b-94a5-d6e5e9b6c7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
34872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1272634872
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.159010454
Short name T353
Test name
Test status
Simulation time 187017304 ps
CPU time 0.78 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206132 kb
Host smart-aeb4ec53-e40c-4bea-9f06-7a5cd385ea68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.159010454
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.1237759019
Short name T452
Test name
Test status
Simulation time 1036232098 ps
CPU time 2.17 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206380 kb
Host smart-6bb9b656-9806-4eb4-b489-a7de71767883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12377
59019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.1237759019
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1237123202
Short name T963
Test name
Test status
Simulation time 2821210418 ps
CPU time 75.74 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:19:59 PM PDT 24
Peak memory 206392 kb
Host smart-9cc27eff-a1e0-41ac-8228-99923480c9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
23202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1237123202
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2337523582
Short name T2694
Test name
Test status
Simulation time 93310395 ps
CPU time 0.73 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:18:51 PM PDT 24
Peak memory 206148 kb
Host smart-47f902c0-e2d3-4b7c-afec-e24ddf95bf4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2337523582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2337523582
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.370450657
Short name T569
Test name
Test status
Simulation time 3780850092 ps
CPU time 4.51 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206048 kb
Host smart-a0a3d414-b13c-4ba2-93bc-03a0a1711868
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=370450657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.370450657
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.828279813
Short name T2127
Test name
Test status
Simulation time 23348432018 ps
CPU time 22.8 seconds
Started Jul 09 05:18:33 PM PDT 24
Finished Jul 09 05:18:57 PM PDT 24
Peak memory 206288 kb
Host smart-23df8634-0a6c-4a2a-840b-6018721d6084
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=828279813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.828279813
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3648794040
Short name T2524
Test name
Test status
Simulation time 176434246 ps
CPU time 0.88 seconds
Started Jul 09 05:18:32 PM PDT 24
Finished Jul 09 05:18:34 PM PDT 24
Peak memory 206048 kb
Host smart-d36a8a3d-4a0a-4b52-bb48-3cb9e656892c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36487
94040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3648794040
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1320355437
Short name T983
Test name
Test status
Simulation time 183948302 ps
CPU time 0.81 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206160 kb
Host smart-6f006312-3395-4b04-8aa9-2d5b38b8a339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13203
55437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1320355437
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.2038655726
Short name T1874
Test name
Test status
Simulation time 536152258 ps
CPU time 1.64 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:18:39 PM PDT 24
Peak memory 206348 kb
Host smart-2ebd56b8-49df-47ee-9457-09e17f25626a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
55726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.2038655726
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.464284961
Short name T792
Test name
Test status
Simulation time 331618104 ps
CPU time 0.96 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206128 kb
Host smart-867c51fb-7af9-4b3a-95cb-e0d04d7441e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46428
4961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.464284961
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2186708575
Short name T2320
Test name
Test status
Simulation time 9256984683 ps
CPU time 18.16 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:18:57 PM PDT 24
Peak memory 206396 kb
Host smart-57aad31b-9e04-428e-8f2f-2e17c93ff808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
08575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2186708575
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2702836598
Short name T1566
Test name
Test status
Simulation time 444365695 ps
CPU time 1.26 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:47 PM PDT 24
Peak memory 205956 kb
Host smart-38747641-5908-4a4a-b819-be0228f1e66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27028
36598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2702836598
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3322848864
Short name T2587
Test name
Test status
Simulation time 157718965 ps
CPU time 0.83 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206016 kb
Host smart-aebe286e-d208-48ba-85e9-b24eadeff134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
48864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3322848864
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2153900204
Short name T954
Test name
Test status
Simulation time 86986694 ps
CPU time 0.69 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 205948 kb
Host smart-b3e7139e-42f0-47b5-9435-46f7485b111a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
00204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2153900204
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.969804329
Short name T1172
Test name
Test status
Simulation time 939845931 ps
CPU time 2.14 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206320 kb
Host smart-1dcac6a3-527d-4793-9c88-544f2dab6550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96980
4329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.969804329
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.536942614
Short name T520
Test name
Test status
Simulation time 323780753 ps
CPU time 2.26 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:18:40 PM PDT 24
Peak memory 206240 kb
Host smart-a35d081a-0d7f-45ac-859c-6f3a1ba1d4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53694
2614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.536942614
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1072293257
Short name T1970
Test name
Test status
Simulation time 247776083 ps
CPU time 0.94 seconds
Started Jul 09 05:18:38 PM PDT 24
Finished Jul 09 05:18:41 PM PDT 24
Peak memory 206064 kb
Host smart-ba328069-c3c5-4ab1-ad36-63a38532f3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722
93257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1072293257
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.495709454
Short name T2014
Test name
Test status
Simulation time 143065445 ps
CPU time 0.8 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 205944 kb
Host smart-5c9472e1-2cdb-47da-a0a5-60d0f924a76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49570
9454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.495709454
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.515011449
Short name T1856
Test name
Test status
Simulation time 217292259 ps
CPU time 0.93 seconds
Started Jul 09 05:18:50 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 205988 kb
Host smart-4e20b024-edd5-49d8-a8b1-2134c015430f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51501
1449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.515011449
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.905229571
Short name T2180
Test name
Test status
Simulation time 222386005 ps
CPU time 0.91 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206372 kb
Host smart-a0d99692-5f3d-4f1d-8b6e-899f3b543643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90522
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.905229571
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.392718413
Short name T1304
Test name
Test status
Simulation time 23344595545 ps
CPU time 21.68 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:19:12 PM PDT 24
Peak memory 206144 kb
Host smart-7ade85db-aee4-4cec-911a-92d7823304e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39271
8413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.392718413
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.44545749
Short name T674
Test name
Test status
Simulation time 3339550921 ps
CPU time 3.73 seconds
Started Jul 09 05:18:37 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206124 kb
Host smart-abb6ab0e-9d88-47b3-9b7a-1290c4a7e405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44545
749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.44545749
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1398152503
Short name T2680
Test name
Test status
Simulation time 13641327794 ps
CPU time 373.86 seconds
Started Jul 09 05:18:36 PM PDT 24
Finished Jul 09 05:24:52 PM PDT 24
Peak memory 206380 kb
Host smart-da68d1b3-f288-432b-b1b6-1059039fe19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13981
52503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1398152503
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2968328254
Short name T816
Test name
Test status
Simulation time 6957154712 ps
CPU time 49.28 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:19:36 PM PDT 24
Peak memory 206244 kb
Host smart-b02ad7c2-4e0c-478e-90ad-7693e7d6de77
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2968328254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2968328254
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3002981783
Short name T2163
Test name
Test status
Simulation time 248087599 ps
CPU time 0.94 seconds
Started Jul 09 05:18:51 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206020 kb
Host smart-c623d3aa-a645-4dcc-b0fc-f4ab349eaeb8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3002981783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3002981783
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1417710818
Short name T456
Test name
Test status
Simulation time 184684677 ps
CPU time 0.88 seconds
Started Jul 09 05:18:39 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206132 kb
Host smart-02c0edfb-000c-411b-a2e2-d7431a50f6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14177
10818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1417710818
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2349082884
Short name T760
Test name
Test status
Simulation time 4393931069 ps
CPU time 39.17 seconds
Started Jul 09 05:18:38 PM PDT 24
Finished Jul 09 05:19:19 PM PDT 24
Peak memory 206404 kb
Host smart-64699007-40ab-4992-8157-796abe8747c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23490
82884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2349082884
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1132403754
Short name T2260
Test name
Test status
Simulation time 6556810533 ps
CPU time 58.74 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:19:44 PM PDT 24
Peak memory 206188 kb
Host smart-cdc3906b-6a65-4659-a162-ad2e6abc6ca5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1132403754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1132403754
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2890313876
Short name T2571
Test name
Test status
Simulation time 158514550 ps
CPU time 0.91 seconds
Started Jul 09 05:18:34 PM PDT 24
Finished Jul 09 05:18:36 PM PDT 24
Peak memory 206032 kb
Host smart-f6f00ffb-b257-4a15-b0b0-a7f0c79a2092
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2890313876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2890313876
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3593527642
Short name T2227
Test name
Test status
Simulation time 168685778 ps
CPU time 0.78 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:46 PM PDT 24
Peak memory 205956 kb
Host smart-92d04ba9-9dfc-4f9d-a066-5c8d4a272688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35935
27642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3593527642
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1512265623
Short name T2183
Test name
Test status
Simulation time 186737899 ps
CPU time 0.93 seconds
Started Jul 09 05:18:34 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206140 kb
Host smart-c15bd107-4f94-426d-bc87-12294ec3553a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15122
65623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1512265623
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3735707080
Short name T1176
Test name
Test status
Simulation time 173586600 ps
CPU time 0.81 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:49 PM PDT 24
Peak memory 205760 kb
Host smart-2399285c-405a-4991-82a0-152f704a6074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357
07080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3735707080
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.275832882
Short name T30
Test name
Test status
Simulation time 168143517 ps
CPU time 0.76 seconds
Started Jul 09 05:18:39 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206136 kb
Host smart-9c289329-b34e-49dc-8c65-93ab344c1a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583
2882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.275832882
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2322425296
Short name T424
Test name
Test status
Simulation time 161232716 ps
CPU time 0.76 seconds
Started Jul 09 05:18:34 PM PDT 24
Finished Jul 09 05:18:35 PM PDT 24
Peak memory 206060 kb
Host smart-f16740aa-17a8-4f0f-a382-8917d6f816ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23224
25296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2322425296
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2939907505
Short name T560
Test name
Test status
Simulation time 163766248 ps
CPU time 0.81 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206068 kb
Host smart-dd416519-1f1b-4ad0-bb50-9f14c246628f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29399
07505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2939907505
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3193992883
Short name T2062
Test name
Test status
Simulation time 189594435 ps
CPU time 0.87 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206096 kb
Host smart-666cdf8c-2360-4dd8-91b8-1312e6da1871
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3193992883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3193992883
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.305864373
Short name T1948
Test name
Test status
Simulation time 140170131 ps
CPU time 0.75 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206060 kb
Host smart-76c4dcbf-65b8-4337-bde9-f2a87203060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30586
4373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.305864373
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3989775322
Short name T2028
Test name
Test status
Simulation time 101008781 ps
CPU time 0.71 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206060 kb
Host smart-903d4fb5-ab33-4011-a626-5b8a78a6b8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
75322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3989775322
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.184431497
Short name T1255
Test name
Test status
Simulation time 13214710660 ps
CPU time 34.92 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:19:24 PM PDT 24
Peak memory 206728 kb
Host smart-a58d5950-8d08-4286-8888-d7f0c6e6886a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
1497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.184431497
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.220168608
Short name T905
Test name
Test status
Simulation time 189635635 ps
CPU time 0.87 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:49 PM PDT 24
Peak memory 206068 kb
Host smart-d18c1ee9-a531-4eed-9b72-378fdb954bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22016
8608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.220168608
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2884642238
Short name T1704
Test name
Test status
Simulation time 252265960 ps
CPU time 0.87 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:49 PM PDT 24
Peak memory 205820 kb
Host smart-9a5fbd69-5f41-4037-9d93-2b02b31674a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28846
42238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2884642238
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1594102471
Short name T375
Test name
Test status
Simulation time 199313989 ps
CPU time 0.84 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206124 kb
Host smart-cd511043-231c-4cd3-be06-def2e4791706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
02471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1594102471
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.555535704
Short name T1608
Test name
Test status
Simulation time 187549025 ps
CPU time 0.82 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:18:50 PM PDT 24
Peak memory 205964 kb
Host smart-9188566c-f9b4-41cf-b012-07171cdbd29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55553
5704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.555535704
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1339237833
Short name T2269
Test name
Test status
Simulation time 171243496 ps
CPU time 0.84 seconds
Started Jul 09 05:18:41 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206108 kb
Host smart-763aebf7-af3e-4674-96ff-af05dff1d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13392
37833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1339237833
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.4052296576
Short name T1620
Test name
Test status
Simulation time 152783901 ps
CPU time 0.78 seconds
Started Jul 09 05:18:50 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206064 kb
Host smart-be3d5725-6fbd-4d5d-aa12-34a6da5af333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40522
96576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.4052296576
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4173428553
Short name T1647
Test name
Test status
Simulation time 201562453 ps
CPU time 0.81 seconds
Started Jul 09 05:18:43 PM PDT 24
Finished Jul 09 05:18:46 PM PDT 24
Peak memory 206160 kb
Host smart-90598da3-7685-41c9-9183-2cba58f91801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
28553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4173428553
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3412419982
Short name T1392
Test name
Test status
Simulation time 256203292 ps
CPU time 0.95 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206112 kb
Host smart-42a1449a-9907-41ca-99f2-d6e50e38fe6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34124
19982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3412419982
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.2881190080
Short name T1865
Test name
Test status
Simulation time 6084658618 ps
CPU time 169.36 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:21:39 PM PDT 24
Peak memory 206356 kb
Host smart-1f7fa6a4-8008-4f23-a4cf-b35d119ab86f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2881190080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2881190080
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.238098152
Short name T2401
Test name
Test status
Simulation time 179993351 ps
CPU time 0.79 seconds
Started Jul 09 05:18:41 PM PDT 24
Finished Jul 09 05:18:44 PM PDT 24
Peak memory 206148 kb
Host smart-3c9217c5-cdd3-424e-b0a0-bfbde43e45e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23809
8152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.238098152
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.259717894
Short name T363
Test name
Test status
Simulation time 166399126 ps
CPU time 0.82 seconds
Started Jul 09 05:18:41 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206088 kb
Host smart-a30ba7a1-d736-4c9e-85f2-96691f255c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971
7894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.259717894
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2828414555
Short name T2294
Test name
Test status
Simulation time 1187282358 ps
CPU time 2.46 seconds
Started Jul 09 05:18:39 PM PDT 24
Finished Jul 09 05:18:43 PM PDT 24
Peak memory 206356 kb
Host smart-1c98f3fa-9767-492e-877b-b062605e97ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28284
14555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2828414555
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.525103966
Short name T463
Test name
Test status
Simulation time 5085016315 ps
CPU time 35.32 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:19:22 PM PDT 24
Peak memory 206476 kb
Host smart-d8ab143d-e9b2-4c43-8d47-0395919a748a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52510
3966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.525103966
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.185241059
Short name T1722
Test name
Test status
Simulation time 45702764 ps
CPU time 0.7 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:18:57 PM PDT 24
Peak memory 206092 kb
Host smart-1e9dc44a-e14d-4fd1-b677-cc7d161a4d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=185241059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.185241059
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2368902628
Short name T1470
Test name
Test status
Simulation time 4187914403 ps
CPU time 5.47 seconds
Started Jul 09 05:18:42 PM PDT 24
Finished Jul 09 05:18:49 PM PDT 24
Peak memory 206232 kb
Host smart-0c2c578d-4303-4c9b-8cf0-723688c070c4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2368902628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2368902628
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3410749512
Short name T516
Test name
Test status
Simulation time 13373267001 ps
CPU time 13 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206432 kb
Host smart-13359709-152e-4683-a430-8d91114473d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3410749512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3410749512
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3343805187
Short name T1952
Test name
Test status
Simulation time 23383006516 ps
CPU time 29.31 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:19:20 PM PDT 24
Peak memory 206100 kb
Host smart-003555e7-585f-42ab-ac77-184b7de05ad3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3343805187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.3343805187
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.269327364
Short name T2027
Test name
Test status
Simulation time 189620801 ps
CPU time 0.83 seconds
Started Jul 09 05:18:39 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206024 kb
Host smart-23a943ec-6baa-41d9-8ab3-5c329335fcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932
7364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.269327364
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.518587594
Short name T1905
Test name
Test status
Simulation time 171806477 ps
CPU time 0.78 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:18:51 PM PDT 24
Peak memory 206128 kb
Host smart-891cd373-34ca-4c3f-9bf7-bccb5e70c515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51858
7594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.518587594
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.943068655
Short name T155
Test name
Test status
Simulation time 564669935 ps
CPU time 1.61 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206232 kb
Host smart-c13a6e8d-7759-4ff0-a014-a72fa1ea28f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94306
8655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.943068655
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1993356039
Short name T179
Test name
Test status
Simulation time 1480969347 ps
CPU time 3.24 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:45 PM PDT 24
Peak memory 206396 kb
Host smart-5689493e-8b4f-4c4e-8295-377362287942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19933
56039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1993356039
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3381709292
Short name T847
Test name
Test status
Simulation time 14909212532 ps
CPU time 32.63 seconds
Started Jul 09 05:18:50 PM PDT 24
Finished Jul 09 05:19:25 PM PDT 24
Peak memory 206412 kb
Host smart-f7a3177e-ea73-4634-a25f-4035a5415ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817
09292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3381709292
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3086909824
Short name T1359
Test name
Test status
Simulation time 411874419 ps
CPU time 1.3 seconds
Started Jul 09 05:18:38 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206056 kb
Host smart-ba893543-bcf3-452f-86fe-b8307b54dbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30869
09824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3086909824
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3733647832
Short name T1214
Test name
Test status
Simulation time 132661005 ps
CPU time 0.75 seconds
Started Jul 09 05:18:40 PM PDT 24
Finished Jul 09 05:18:42 PM PDT 24
Peak memory 206112 kb
Host smart-d413ca83-504d-4e63-811a-a3f18a83e963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37336
47832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3733647832
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2856355197
Short name T581
Test name
Test status
Simulation time 48023772 ps
CPU time 0.68 seconds
Started Jul 09 05:18:53 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 205952 kb
Host smart-7585e551-261c-4fa2-8636-1adc17f43566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28563
55197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2856355197
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2493370681
Short name T380
Test name
Test status
Simulation time 1010827647 ps
CPU time 2.2 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206312 kb
Host smart-e90fe4d1-9d5d-41d5-bbf3-d0dd60ce66c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24933
70681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2493370681
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3994034217
Short name T2469
Test name
Test status
Simulation time 175131006 ps
CPU time 1.62 seconds
Started Jul 09 05:18:55 PM PDT 24
Finished Jul 09 05:18:58 PM PDT 24
Peak memory 206256 kb
Host smart-b0dab864-f829-46ef-a510-0f6d0c0e91ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39940
34217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3994034217
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2176706624
Short name T1751
Test name
Test status
Simulation time 146521155 ps
CPU time 0.77 seconds
Started Jul 09 05:20:25 PM PDT 24
Finished Jul 09 05:20:26 PM PDT 24
Peak memory 206124 kb
Host smart-e8f271e5-0de9-4ef2-b50d-1b38a2c44fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21767
06624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2176706624
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1053591368
Short name T2552
Test name
Test status
Simulation time 184329659 ps
CPU time 0.86 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206048 kb
Host smart-b1f64af6-8081-4982-aea4-b6df3d1d827a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10535
91368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1053591368
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1831800749
Short name T2046
Test name
Test status
Simulation time 178316046 ps
CPU time 0.85 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206016 kb
Host smart-857c6ca9-41be-46cc-9e51-d34db94ab2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18318
00749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1831800749
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1953441150
Short name T346
Test name
Test status
Simulation time 23266843542 ps
CPU time 22.38 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:19:11 PM PDT 24
Peak memory 206116 kb
Host smart-847b131b-b30e-4db1-bdd7-d5abe6065ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19534
41150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1953441150
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.475207874
Short name T2381
Test name
Test status
Simulation time 3290038736 ps
CPU time 3.93 seconds
Started Jul 09 05:18:50 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206156 kb
Host smart-59f63cc7-f8da-4b6b-a16a-92c03cda389b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47520
7874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.475207874
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1416968873
Short name T1713
Test name
Test status
Simulation time 7014731123 ps
CPU time 185.34 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:21:57 PM PDT 24
Peak memory 206316 kb
Host smart-b3b1fedb-46a4-4b88-b35b-c1d3681e7336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14169
68873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1416968873
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2298211566
Short name T918
Test name
Test status
Simulation time 4907730430 ps
CPU time 135.24 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:21:04 PM PDT 24
Peak memory 206400 kb
Host smart-3297e574-2709-4490-88fa-993e1a8b3689
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2298211566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2298211566
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1999644364
Short name T1421
Test name
Test status
Simulation time 232572800 ps
CPU time 0.93 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206140 kb
Host smart-b7f41716-6fb5-4dc1-9c93-a732aca8f63b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1999644364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1999644364
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.167663118
Short name T1649
Test name
Test status
Simulation time 201468172 ps
CPU time 0.89 seconds
Started Jul 09 05:18:51 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206084 kb
Host smart-9cd077c3-a42f-4205-b0b0-fc33ae16bcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.167663118
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.740600440
Short name T765
Test name
Test status
Simulation time 5402488511 ps
CPU time 52.17 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:19:40 PM PDT 24
Peak memory 206436 kb
Host smart-987c3490-c96d-447c-b3c4-77b1ef79adfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74060
0440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.740600440
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1906981956
Short name T1715
Test name
Test status
Simulation time 5258201219 ps
CPU time 145.05 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:21:14 PM PDT 24
Peak memory 206336 kb
Host smart-c33acbe6-3707-4c75-9d1b-f2019089660b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1906981956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1906981956
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2629034499
Short name T856
Test name
Test status
Simulation time 190435142 ps
CPU time 0.82 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206140 kb
Host smart-5088d21a-0a10-46d3-8122-1a9ae9c3bdaa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2629034499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2629034499
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.207815701
Short name T2182
Test name
Test status
Simulation time 142092687 ps
CPU time 0.76 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:18:51 PM PDT 24
Peak memory 206164 kb
Host smart-5ec7d6d4-f35c-4aa2-80c2-2fd4bffa9e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
5701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.207815701
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2563563446
Short name T139
Test name
Test status
Simulation time 213941049 ps
CPU time 0.88 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:50 PM PDT 24
Peak memory 206160 kb
Host smart-6e188478-4fb4-4026-94fa-2586c2bc80a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
63446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2563563446
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1945448259
Short name T2525
Test name
Test status
Simulation time 246684753 ps
CPU time 0.91 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:49 PM PDT 24
Peak memory 206052 kb
Host smart-113a7187-3019-472c-8045-2aaa35b19dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
48259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1945448259
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3284034996
Short name T1780
Test name
Test status
Simulation time 164716554 ps
CPU time 0.86 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206000 kb
Host smart-03567328-27d6-4b0c-a805-92de48f0eaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
34996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3284034996
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4220123792
Short name T1610
Test name
Test status
Simulation time 211573522 ps
CPU time 0.92 seconds
Started Jul 09 05:18:50 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206088 kb
Host smart-12f04f35-3dff-49db-8c3c-de6d38098542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
23792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4220123792
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.771309900
Short name T668
Test name
Test status
Simulation time 158538803 ps
CPU time 0.79 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206004 kb
Host smart-b460a069-c73e-4a62-81a4-bca4ced23995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77130
9900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.771309900
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.435209694
Short name T1868
Test name
Test status
Simulation time 218359292 ps
CPU time 0.92 seconds
Started Jul 09 05:18:50 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206068 kb
Host smart-1224748c-7810-49e4-8579-c8f145820326
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=435209694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.435209694
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3559617919
Short name T683
Test name
Test status
Simulation time 146107498 ps
CPU time 0.79 seconds
Started Jul 09 05:18:44 PM PDT 24
Finished Jul 09 05:18:47 PM PDT 24
Peak memory 206160 kb
Host smart-0b5ffa37-3308-4ee5-b60b-8a07ae966e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
17919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3559617919
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3951260301
Short name T2529
Test name
Test status
Simulation time 39344399 ps
CPU time 0.66 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206156 kb
Host smart-16dd5540-432c-46e3-870e-bc6e991e1f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39512
60301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3951260301
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.4176772721
Short name T603
Test name
Test status
Simulation time 14950729122 ps
CPU time 39.05 seconds
Started Jul 09 05:18:55 PM PDT 24
Finished Jul 09 05:19:35 PM PDT 24
Peak memory 206480 kb
Host smart-c01a7c00-7747-4f90-b405-731c308fdaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41767
72721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.4176772721
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1206285696
Short name T2176
Test name
Test status
Simulation time 184689637 ps
CPU time 0.86 seconds
Started Jul 09 05:18:45 PM PDT 24
Finished Jul 09 05:18:48 PM PDT 24
Peak memory 206020 kb
Host smart-b256eeff-f840-4df3-8430-656a65600f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
85696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1206285696
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1732382154
Short name T210
Test name
Test status
Simulation time 265074461 ps
CPU time 0.9 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:18:58 PM PDT 24
Peak memory 206144 kb
Host smart-d3d0e9fb-8dcb-448b-aede-505577796c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17323
82154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1732382154
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1481878157
Short name T368
Test name
Test status
Simulation time 180538587 ps
CPU time 0.83 seconds
Started Jul 09 05:18:51 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206124 kb
Host smart-b416e4ed-c851-4512-b25c-81062d6ec80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14818
78157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1481878157
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.455303060
Short name T1728
Test name
Test status
Simulation time 155718663 ps
CPU time 0.81 seconds
Started Jul 09 05:18:51 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206140 kb
Host smart-5083915c-cce5-491c-9815-a06e91a332bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45530
3060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.455303060
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.4214879510
Short name T71
Test name
Test status
Simulation time 154806084 ps
CPU time 0.8 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206156 kb
Host smart-06221857-9601-4103-a3f3-8294f4c9b152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42148
79510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.4214879510
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1938854586
Short name T2090
Test name
Test status
Simulation time 153061717 ps
CPU time 0.8 seconds
Started Jul 09 05:18:55 PM PDT 24
Finished Jul 09 05:18:57 PM PDT 24
Peak memory 206060 kb
Host smart-701026e4-c61d-4de0-9147-a73cf0c61e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19388
54586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1938854586
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3485659856
Short name T1678
Test name
Test status
Simulation time 148162135 ps
CPU time 0.79 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:55 PM PDT 24
Peak memory 206108 kb
Host smart-28f7c242-9df2-43bb-9cc1-0a855650b769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
59856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3485659856
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.882975809
Short name T924
Test name
Test status
Simulation time 224861667 ps
CPU time 0.95 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:18:59 PM PDT 24
Peak memory 206128 kb
Host smart-153adc8e-0a12-4772-a647-b32e58a8f7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88297
5809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.882975809
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2051688935
Short name T730
Test name
Test status
Simulation time 6042794218 ps
CPU time 168.23 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:21:39 PM PDT 24
Peak memory 206376 kb
Host smart-b2d6b7e9-af9d-411c-8363-c595fa779906
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2051688935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2051688935
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4148784334
Short name T2053
Test name
Test status
Simulation time 205669491 ps
CPU time 0.86 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 206028 kb
Host smart-e8ef1f79-3c85-4b90-93a9-8228cde87f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
84334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4148784334
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2821247036
Short name T2580
Test name
Test status
Simulation time 183287173 ps
CPU time 0.83 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:18:59 PM PDT 24
Peak memory 206148 kb
Host smart-01e3e61b-2a8d-47c1-b496-1522dcc39f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28212
47036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2821247036
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.2967734045
Short name T2173
Test name
Test status
Simulation time 713982812 ps
CPU time 1.67 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:18:53 PM PDT 24
Peak memory 206340 kb
Host smart-abbdf11c-e94c-469b-88f4-ab83354ba382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29677
34045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.2967734045
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2598158897
Short name T1097
Test name
Test status
Simulation time 7112665486 ps
CPU time 69.88 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:20:02 PM PDT 24
Peak memory 206460 kb
Host smart-65e4da28-5ca8-428a-8942-bcf9c41b3458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
58897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2598158897
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.4108223963
Short name T1845
Test name
Test status
Simulation time 54280818 ps
CPU time 0.68 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:03 PM PDT 24
Peak memory 206160 kb
Host smart-4a8a4417-4da2-4399-87c8-25ea1a146df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4108223963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.4108223963
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2576902252
Short name T2186
Test name
Test status
Simulation time 13415616930 ps
CPU time 15.49 seconds
Started Jul 09 05:18:59 PM PDT 24
Finished Jul 09 05:19:16 PM PDT 24
Peak memory 206324 kb
Host smart-d3b55bec-fa84-4d21-8ed5-220255ae2ced
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2576902252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2576902252
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3143246540
Short name T691
Test name
Test status
Simulation time 23348974817 ps
CPU time 30.38 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:19:21 PM PDT 24
Peak memory 206052 kb
Host smart-3a4ea30a-0a59-499f-a76a-b96d2eefec9b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3143246540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3143246540
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2218879109
Short name T530
Test name
Test status
Simulation time 184346796 ps
CPU time 0.78 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:18:50 PM PDT 24
Peak memory 206052 kb
Host smart-7a5981c5-de97-4a95-a747-942c324dda2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188
79109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2218879109
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4074388922
Short name T1264
Test name
Test status
Simulation time 213294588 ps
CPU time 0.84 seconds
Started Jul 09 05:18:51 PM PDT 24
Finished Jul 09 05:18:54 PM PDT 24
Peak memory 206164 kb
Host smart-e294f85e-3444-4009-86af-087f22d25479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40743
88922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4074388922
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2955890339
Short name T178
Test name
Test status
Simulation time 314919224 ps
CPU time 1.17 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206160 kb
Host smart-91d7902e-2b91-40b6-ac3e-6a004caad54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29558
90339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2955890339
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1943591107
Short name T166
Test name
Test status
Simulation time 746974287 ps
CPU time 2.02 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 206272 kb
Host smart-672545fb-fbdf-47f4-80bf-8ef08ba36a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19435
91107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1943591107
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2519456998
Short name T2708
Test name
Test status
Simulation time 10742275432 ps
CPU time 20.9 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:23 PM PDT 24
Peak memory 206320 kb
Host smart-2427a1e1-4e20-4b9c-b61a-aa1b841e481b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25194
56998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2519456998
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1435756139
Short name T958
Test name
Test status
Simulation time 410405114 ps
CPU time 1.25 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206152 kb
Host smart-347c601f-6c2a-4876-9926-a9a63317c374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14357
56139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1435756139
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3454122178
Short name T1041
Test name
Test status
Simulation time 146225106 ps
CPU time 0.77 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206164 kb
Host smart-2e1969e2-041f-4601-90b4-6d9f0393bce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34541
22178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3454122178
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3500310702
Short name T2595
Test name
Test status
Simulation time 48573153 ps
CPU time 0.71 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206156 kb
Host smart-01b6f05c-d001-4670-894c-a294cda20168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35003
10702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3500310702
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.42212819
Short name T1263
Test name
Test status
Simulation time 983183133 ps
CPU time 2.27 seconds
Started Jul 09 05:18:47 PM PDT 24
Finished Jul 09 05:18:52 PM PDT 24
Peak memory 206340 kb
Host smart-4f48a43e-9843-45a5-a2a8-8a562fc39fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42212
819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.42212819
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1172424200
Short name T2621
Test name
Test status
Simulation time 257842299 ps
CPU time 1.8 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206260 kb
Host smart-ca5969c9-25cc-49b8-a69c-867e3f318011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11724
24200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1172424200
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3284233861
Short name T1957
Test name
Test status
Simulation time 182217780 ps
CPU time 0.84 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 205960 kb
Host smart-ef4dd524-0c0a-44d3-abd3-e30a3f681ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32842
33861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3284233861
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4071645473
Short name T1510
Test name
Test status
Simulation time 161788280 ps
CPU time 0.79 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206100 kb
Host smart-13cb6880-9852-4fe5-b469-8dd91c445ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
45473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4071645473
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3180910471
Short name T1690
Test name
Test status
Simulation time 170611798 ps
CPU time 0.83 seconds
Started Jul 09 05:18:46 PM PDT 24
Finished Jul 09 05:18:49 PM PDT 24
Peak memory 206052 kb
Host smart-1209a636-ffd2-4543-a7eb-7a213872f08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31809
10471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3180910471
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.362474934
Short name T219
Test name
Test status
Simulation time 9830319561 ps
CPU time 93.36 seconds
Started Jul 09 05:18:49 PM PDT 24
Finished Jul 09 05:20:25 PM PDT 24
Peak memory 206448 kb
Host smart-297e7415-47c0-4e65-afe3-79f3b81a808d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=362474934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.362474934
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3932900477
Short name T1737
Test name
Test status
Simulation time 206597954 ps
CPU time 0.86 seconds
Started Jul 09 05:18:53 PM PDT 24
Finished Jul 09 05:18:55 PM PDT 24
Peak memory 206116 kb
Host smart-3c6a4887-16d0-4f73-908f-4c92a3eb5ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39329
00477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3932900477
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3194190384
Short name T1854
Test name
Test status
Simulation time 23313304049 ps
CPU time 24.71 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:19:22 PM PDT 24
Peak memory 206080 kb
Host smart-2666fe0c-21e0-4da8-9ab8-d04b4a69817d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941
90384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3194190384
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.782001499
Short name T2612
Test name
Test status
Simulation time 3305306362 ps
CPU time 3.71 seconds
Started Jul 09 05:18:55 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206104 kb
Host smart-321587c6-3f86-4ba0-96ce-8dbf2401426d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78200
1499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.782001499
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2195190839
Short name T1043
Test name
Test status
Simulation time 11630238869 ps
CPU time 110.11 seconds
Started Jul 09 05:18:48 PM PDT 24
Finished Jul 09 05:20:40 PM PDT 24
Peak memory 206468 kb
Host smart-c4868352-665f-4830-ae9a-6b37a2cc33f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21951
90839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2195190839
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3402787030
Short name T1283
Test name
Test status
Simulation time 4870298503 ps
CPU time 48.29 seconds
Started Jul 09 05:18:55 PM PDT 24
Finished Jul 09 05:19:44 PM PDT 24
Peak memory 206360 kb
Host smart-495c2ac7-6ae5-4781-b0c1-0d9eb09666d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3402787030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3402787030
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3079016840
Short name T1563
Test name
Test status
Simulation time 248168885 ps
CPU time 0.91 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206020 kb
Host smart-4b1511d8-4520-4a4e-adfb-6e4a0b808d48
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3079016840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3079016840
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3330700236
Short name T2374
Test name
Test status
Simulation time 193286114 ps
CPU time 0.91 seconds
Started Jul 09 05:18:59 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 205996 kb
Host smart-bfb121c5-38c1-4651-b98d-d9c1a535e65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
00236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3330700236
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3981938297
Short name T2250
Test name
Test status
Simulation time 4240231057 ps
CPU time 40.56 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:19:37 PM PDT 24
Peak memory 206244 kb
Host smart-d6f30208-5692-4290-894a-c08c5dc7d692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39819
38297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3981938297
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2186025319
Short name T2346
Test name
Test status
Simulation time 7756013581 ps
CPU time 218.83 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:22:36 PM PDT 24
Peak memory 206324 kb
Host smart-49a4d3a6-7953-489d-b9ef-883f2b4b87e9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2186025319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2186025319
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.547298341
Short name T861
Test name
Test status
Simulation time 190531041 ps
CPU time 0.82 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:03 PM PDT 24
Peak memory 206044 kb
Host smart-f31413d3-032e-4541-8eca-a2f6dfe38363
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=547298341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.547298341
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2154185007
Short name T1400
Test name
Test status
Simulation time 142815458 ps
CPU time 0.81 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206060 kb
Host smart-4c24c6c9-fefb-4033-8a37-9b562d049c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541
85007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2154185007
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.877916361
Short name T2087
Test name
Test status
Simulation time 194612065 ps
CPU time 0.9 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 205992 kb
Host smart-c232e7d0-425f-461d-b874-1f03984e5fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87791
6361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.877916361
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.481252389
Short name T2325
Test name
Test status
Simulation time 234446325 ps
CPU time 0.94 seconds
Started Jul 09 05:18:52 PM PDT 24
Finished Jul 09 05:18:55 PM PDT 24
Peak memory 206140 kb
Host smart-ceba4156-b28a-4272-ae79-8cb2ce39029b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48125
2389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.481252389
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2384455300
Short name T851
Test name
Test status
Simulation time 154114014 ps
CPU time 0.75 seconds
Started Jul 09 05:19:04 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206112 kb
Host smart-61c7e36c-3bb4-4325-b8e3-4f4f19fb538e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23844
55300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2384455300
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.335180676
Short name T1930
Test name
Test status
Simulation time 161703006 ps
CPU time 0.77 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206096 kb
Host smart-5f69f82f-c4d3-451f-a371-b9c6b1837d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
0676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.335180676
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2639050014
Short name T1358
Test name
Test status
Simulation time 140677049 ps
CPU time 0.81 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:03 PM PDT 24
Peak memory 206008 kb
Host smart-d6bceee5-4518-486b-9efc-4b7d505e1d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
50014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2639050014
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1391459692
Short name T433
Test name
Test status
Simulation time 237293942 ps
CPU time 1 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:18:58 PM PDT 24
Peak memory 205988 kb
Host smart-72c15b58-e1ee-4f62-8029-14e4d00ef0ac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1391459692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1391459692
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1280280809
Short name T1438
Test name
Test status
Simulation time 140086920 ps
CPU time 0.8 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206160 kb
Host smart-92821763-cd13-4396-b592-fe3b56e0cd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
80809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1280280809
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1523038839
Short name T2271
Test name
Test status
Simulation time 44451161 ps
CPU time 0.66 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:03 PM PDT 24
Peak memory 206016 kb
Host smart-ad4c3f26-928f-4fad-87d2-9199e712c76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15230
38839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1523038839
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.4091958615
Short name T2191
Test name
Test status
Simulation time 16002879270 ps
CPU time 34.35 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:19:38 PM PDT 24
Peak memory 206396 kb
Host smart-09482ab0-8138-4176-b17e-c1f0aa98e6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40919
58615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.4091958615
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1914717099
Short name T484
Test name
Test status
Simulation time 183146091 ps
CPU time 0.83 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:18:59 PM PDT 24
Peak memory 206016 kb
Host smart-20f120a4-6543-4488-9f39-85fda5fafb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19147
17099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1914717099
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1464654494
Short name T1327
Test name
Test status
Simulation time 233808623 ps
CPU time 0.91 seconds
Started Jul 09 05:19:04 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206060 kb
Host smart-1edce13a-aa78-4a62-b9e8-184a4bee8f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14646
54494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1464654494
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3668988434
Short name T2006
Test name
Test status
Simulation time 175068289 ps
CPU time 0.85 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206132 kb
Host smart-3e5b3d01-6db6-472b-a249-a677ad200863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36689
88434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3668988434
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3703660735
Short name T502
Test name
Test status
Simulation time 179030758 ps
CPU time 0.84 seconds
Started Jul 09 05:18:54 PM PDT 24
Finished Jul 09 05:18:56 PM PDT 24
Peak memory 206084 kb
Host smart-91e12a6a-6601-45a3-8b4f-9755174fe3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
60735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3703660735
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2107936666
Short name T1660
Test name
Test status
Simulation time 134353209 ps
CPU time 0.76 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:01 PM PDT 24
Peak memory 206012 kb
Host smart-b64de37f-2d7b-4cc4-a19e-c650afc4e267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21079
36666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2107936666
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3315706331
Short name T2391
Test name
Test status
Simulation time 173640076 ps
CPU time 0.81 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206108 kb
Host smart-f94ef084-2e23-4980-b3d1-f4738146c20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33157
06331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3315706331
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2533952658
Short name T1075
Test name
Test status
Simulation time 148439397 ps
CPU time 0.8 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206116 kb
Host smart-ba20491a-36d1-4cbd-912e-9922c6d4b9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
52658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2533952658
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1948580898
Short name T2670
Test name
Test status
Simulation time 209460098 ps
CPU time 0.94 seconds
Started Jul 09 05:19:08 PM PDT 24
Finished Jul 09 05:19:10 PM PDT 24
Peak memory 206136 kb
Host smart-88000dea-4749-483d-92f4-66333467d7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19485
80898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1948580898
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1179289902
Short name T930
Test name
Test status
Simulation time 5075153137 ps
CPU time 140.15 seconds
Started Jul 09 05:18:52 PM PDT 24
Finished Jul 09 05:21:14 PM PDT 24
Peak memory 206308 kb
Host smart-1b21e682-cacb-4711-9b0e-85dc468dc1b5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1179289902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1179289902
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2365525712
Short name T144
Test name
Test status
Simulation time 188647230 ps
CPU time 0.87 seconds
Started Jul 09 05:18:56 PM PDT 24
Finished Jul 09 05:18:58 PM PDT 24
Peak memory 205996 kb
Host smart-b4635bc5-0be5-4856-b8ca-50eb2a28eb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23655
25712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2365525712
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3979096579
Short name T2307
Test name
Test status
Simulation time 195315879 ps
CPU time 0.87 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:19:00 PM PDT 24
Peak memory 206136 kb
Host smart-d09eb13d-ef24-483f-9650-3af03601e38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39790
96579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3979096579
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1241374302
Short name T449
Test name
Test status
Simulation time 921555333 ps
CPU time 1.99 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206408 kb
Host smart-2a3b09ab-ab45-40af-b1de-31228e1c969b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
74302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1241374302
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3069302391
Short name T593
Test name
Test status
Simulation time 7390218679 ps
CPU time 77.14 seconds
Started Jul 09 05:18:58 PM PDT 24
Finished Jul 09 05:20:17 PM PDT 24
Peak memory 206324 kb
Host smart-641cb1f0-96df-430f-961c-58faaf44dd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30693
02391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3069302391
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1689892739
Short name T713
Test name
Test status
Simulation time 39849965 ps
CPU time 0.68 seconds
Started Jul 09 05:19:14 PM PDT 24
Finished Jul 09 05:19:16 PM PDT 24
Peak memory 206176 kb
Host smart-81af84d6-91dc-4c2a-94ec-68b18f4c3d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1689892739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1689892739
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3672569570
Short name T2296
Test name
Test status
Simulation time 4340319769 ps
CPU time 5.59 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:10 PM PDT 24
Peak memory 206432 kb
Host smart-678ce439-b054-4229-bc39-51cda4408e4d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3672569570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3672569570
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3368283608
Short name T907
Test name
Test status
Simulation time 13379494864 ps
CPU time 12.81 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:15 PM PDT 24
Peak memory 206088 kb
Host smart-6f6ffeb8-7f9d-4529-8f86-990a2b67e854
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3368283608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3368283608
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3026353295
Short name T1903
Test name
Test status
Simulation time 23381642530 ps
CPU time 23.13 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:19:27 PM PDT 24
Peak memory 206688 kb
Host smart-2d5e43b5-b35e-4e2c-89ee-4b339486a86c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026353295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3026353295
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.77494632
Short name T1300
Test name
Test status
Simulation time 149356476 ps
CPU time 0.82 seconds
Started Jul 09 05:18:57 PM PDT 24
Finished Jul 09 05:18:59 PM PDT 24
Peak memory 206136 kb
Host smart-a80c3328-2730-49c3-8b74-9071768d19be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77494
632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.77494632
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1106320462
Short name T409
Test name
Test status
Simulation time 168729191 ps
CPU time 0.77 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206132 kb
Host smart-7eb57eeb-ae22-401d-87c4-a9a4d572165e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11063
20462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1106320462
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1722757977
Short name T173
Test name
Test status
Simulation time 506563499 ps
CPU time 1.61 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206288 kb
Host smart-e80affe2-fd15-4a15-b9e5-1e3bbd5f215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
57977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1722757977
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3606336432
Short name T939
Test name
Test status
Simulation time 368160180 ps
CPU time 1.07 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206064 kb
Host smart-cba600c0-7c4f-4c75-bfcc-ef5e17076f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36063
36432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3606336432
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1988652993
Short name T486
Test name
Test status
Simulation time 10038740916 ps
CPU time 20 seconds
Started Jul 09 05:19:08 PM PDT 24
Finished Jul 09 05:19:29 PM PDT 24
Peak memory 206352 kb
Host smart-4c52bdfe-9b8c-42d3-a710-7e60c9b2d08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19886
52993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1988652993
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.461679215
Short name T2354
Test name
Test status
Simulation time 470461774 ps
CPU time 1.41 seconds
Started Jul 09 05:19:07 PM PDT 24
Finished Jul 09 05:19:09 PM PDT 24
Peak memory 206160 kb
Host smart-67ee2851-bf18-4771-9113-fd9079fdbca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46167
9215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.461679215
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.4041759485
Short name T1685
Test name
Test status
Simulation time 139750714 ps
CPU time 0.71 seconds
Started Jul 09 05:19:05 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206132 kb
Host smart-195ffde9-ed06-4260-bb20-ef596bca7f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40417
59485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.4041759485
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3785116221
Short name T2540
Test name
Test status
Simulation time 39775780 ps
CPU time 0.67 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:04 PM PDT 24
Peak memory 206148 kb
Host smart-1f40d8ce-5290-4e13-a2f4-72e0d53dfd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
16221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3785116221
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3209388485
Short name T147
Test name
Test status
Simulation time 996199694 ps
CPU time 2.32 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206404 kb
Host smart-a1e13687-b45e-4b4a-89e8-ce1be191ab52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32093
88485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3209388485
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3846046209
Short name T184
Test name
Test status
Simulation time 274820033 ps
CPU time 1.7 seconds
Started Jul 09 05:18:59 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206356 kb
Host smart-2a1722a2-81b6-4606-8f45-6d9a11dd0fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38460
46209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3846046209
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3941911919
Short name T1219
Test name
Test status
Simulation time 192254813 ps
CPU time 0.83 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206148 kb
Host smart-14d760c8-76fd-4423-9ec9-f74c9fd4af18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39419
11919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3941911919
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1114619186
Short name T891
Test name
Test status
Simulation time 145172791 ps
CPU time 0.77 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206152 kb
Host smart-8c7b88ee-2b1d-4809-8c8a-cc0e4cc951a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11146
19186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1114619186
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.88655859
Short name T632
Test name
Test status
Simulation time 189509501 ps
CPU time 0.86 seconds
Started Jul 09 05:19:00 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 206124 kb
Host smart-10f7fc21-f86f-4bce-b47a-d9c863eda6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88655
859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.88655859
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3838836251
Short name T1281
Test name
Test status
Simulation time 171403142 ps
CPU time 0.9 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:04 PM PDT 24
Peak memory 206088 kb
Host smart-af2c6888-0aaa-4317-8040-2d02558212f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
36251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3838836251
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.334932102
Short name T2574
Test name
Test status
Simulation time 23339921784 ps
CPU time 30.25 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:19:34 PM PDT 24
Peak memory 206120 kb
Host smart-32eea001-b33f-46fd-9bdd-240b08265f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493
2102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.334932102
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.872829474
Short name T671
Test name
Test status
Simulation time 3326323356 ps
CPU time 3.53 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206172 kb
Host smart-be536ebe-c05e-451e-8b10-78be0923b4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87282
9474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.872829474
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1578301666
Short name T1442
Test name
Test status
Simulation time 10399908994 ps
CPU time 288.34 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:23:51 PM PDT 24
Peak memory 206360 kb
Host smart-40d0a378-b524-4205-98d3-6d7e9458254b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15783
01666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1578301666
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1032616961
Short name T1850
Test name
Test status
Simulation time 5478995156 ps
CPU time 57.92 seconds
Started Jul 09 05:18:59 PM PDT 24
Finished Jul 09 05:19:59 PM PDT 24
Peak memory 206304 kb
Host smart-e6939f7d-de0a-4c90-8d36-cb94b8d59c47
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1032616961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1032616961
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2872764350
Short name T1756
Test name
Test status
Simulation time 236348134 ps
CPU time 0.93 seconds
Started Jul 09 05:19:06 PM PDT 24
Finished Jul 09 05:19:07 PM PDT 24
Peak memory 206124 kb
Host smart-3dfe662f-e904-4d3f-9214-43658d5b979b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2872764350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2872764350
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1079549083
Short name T1597
Test name
Test status
Simulation time 206508684 ps
CPU time 0.91 seconds
Started Jul 09 05:19:04 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206068 kb
Host smart-5fa25d36-1950-424e-b768-b02bfb56714e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10795
49083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1079549083
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3606239380
Short name T1881
Test name
Test status
Simulation time 4984807080 ps
CPU time 34 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:38 PM PDT 24
Peak memory 206316 kb
Host smart-a67376ab-fecd-4b7d-aaa9-c69075b4359d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36062
39380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3606239380
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.886533436
Short name T2404
Test name
Test status
Simulation time 3054878198 ps
CPU time 80.23 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:20:24 PM PDT 24
Peak memory 206240 kb
Host smart-493fd1d5-7b73-43f2-a7ac-065c1501060c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=886533436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.886533436
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1311577512
Short name T822
Test name
Test status
Simulation time 152173844 ps
CPU time 0.8 seconds
Started Jul 09 05:18:59 PM PDT 24
Finished Jul 09 05:19:02 PM PDT 24
Peak memory 205968 kb
Host smart-dfcecf01-48f8-4354-a2b7-9d663a1c6fb5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1311577512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1311577512
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3031105778
Short name T1098
Test name
Test status
Simulation time 150222632 ps
CPU time 0.81 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:03 PM PDT 24
Peak memory 206164 kb
Host smart-7a1c2688-b1dc-400b-b12d-060a71e91153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
05778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3031105778
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2073698781
Short name T143
Test name
Test status
Simulation time 235024945 ps
CPU time 0.95 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206100 kb
Host smart-7f29c01f-a959-4f2a-a040-461a6604ea42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20736
98781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2073698781
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2806902525
Short name T2255
Test name
Test status
Simulation time 222971582 ps
CPU time 0.87 seconds
Started Jul 09 05:19:04 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206152 kb
Host smart-40ded2b9-ccc8-4bd6-88a1-98b659a1fa4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
02525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2806902525
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1396833603
Short name T1529
Test name
Test status
Simulation time 183806263 ps
CPU time 0.88 seconds
Started Jul 09 05:19:02 PM PDT 24
Finished Jul 09 05:19:04 PM PDT 24
Peak memory 206064 kb
Host smart-7e463eda-5dbc-48d8-99fd-a0c0234f9cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968
33603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1396833603
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4097536585
Short name T1345
Test name
Test status
Simulation time 205525421 ps
CPU time 0.92 seconds
Started Jul 09 05:19:01 PM PDT 24
Finished Jul 09 05:19:04 PM PDT 24
Peak memory 206136 kb
Host smart-81029649-4c23-4a8a-93c5-f9606c73e17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40975
36585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4097536585
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3437827869
Short name T1744
Test name
Test status
Simulation time 155955193 ps
CPU time 0.78 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206108 kb
Host smart-6e949276-98f7-4655-adad-10c79fdba8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34378
27869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3437827869
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.326660105
Short name T2247
Test name
Test status
Simulation time 302964888 ps
CPU time 1.07 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206036 kb
Host smart-798ed451-8d04-484b-80a5-9d61147c339b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=326660105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.326660105
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3555560648
Short name T1622
Test name
Test status
Simulation time 179276800 ps
CPU time 0.85 seconds
Started Jul 09 05:19:07 PM PDT 24
Finished Jul 09 05:19:08 PM PDT 24
Peak memory 206160 kb
Host smart-6c98a9e4-5633-447a-95b9-5bde4835a20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35555
60648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3555560648
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1950150139
Short name T2274
Test name
Test status
Simulation time 56296844 ps
CPU time 0.71 seconds
Started Jul 09 05:19:05 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206052 kb
Host smart-a4d06f1c-313e-4197-b7d2-b578d4ac5fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19501
50139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1950150139
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.417707093
Short name T1092
Test name
Test status
Simulation time 5959525108 ps
CPU time 14.29 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:19 PM PDT 24
Peak memory 206336 kb
Host smart-84f0b2d6-df69-4b13-a01b-d0202f4d9044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41770
7093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.417707093
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1136128702
Short name T2219
Test name
Test status
Simulation time 208346166 ps
CPU time 0.9 seconds
Started Jul 09 05:19:07 PM PDT 24
Finished Jul 09 05:19:09 PM PDT 24
Peak memory 206160 kb
Host smart-87e78d56-27e1-4253-843f-71aec9e07d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
28702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1136128702
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1172703270
Short name T521
Test name
Test status
Simulation time 265780627 ps
CPU time 0.96 seconds
Started Jul 09 05:19:04 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206052 kb
Host smart-73632e5b-01c7-4b5c-9d59-561bcd38e92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11727
03270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1172703270
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3883758369
Short name T1100
Test name
Test status
Simulation time 226541286 ps
CPU time 0.88 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206052 kb
Host smart-b704232b-9b8d-47ab-850d-b7b7b8c2865b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38837
58369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3883758369
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3954485160
Short name T1371
Test name
Test status
Simulation time 163850701 ps
CPU time 0.83 seconds
Started Jul 09 05:19:09 PM PDT 24
Finished Jul 09 05:19:11 PM PDT 24
Peak memory 206144 kb
Host smart-b6b3fe2c-eb23-4925-b9a2-9aec3e49e963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39544
85160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3954485160
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2040262228
Short name T2431
Test name
Test status
Simulation time 161236995 ps
CPU time 0.8 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 205988 kb
Host smart-2359587e-ba96-4a49-84f0-56d60d8104e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
62228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2040262228
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1741150678
Short name T2688
Test name
Test status
Simulation time 171285205 ps
CPU time 0.79 seconds
Started Jul 09 05:19:04 PM PDT 24
Finished Jul 09 05:19:06 PM PDT 24
Peak memory 206116 kb
Host smart-6aae24c1-3b41-4693-8a41-288d8ee8ac6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17411
50678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1741150678
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3402639127
Short name T1048
Test name
Test status
Simulation time 147648853 ps
CPU time 0.84 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206144 kb
Host smart-26ec7d71-346a-4fde-974f-ec6562455a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
39127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3402639127
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3147682092
Short name T2154
Test name
Test status
Simulation time 240177986 ps
CPU time 0.96 seconds
Started Jul 09 05:19:09 PM PDT 24
Finished Jul 09 05:19:11 PM PDT 24
Peak memory 206144 kb
Host smart-dd5852fa-fedc-48e8-ae70-006049ec14da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31476
82092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3147682092
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3642396575
Short name T1648
Test name
Test status
Simulation time 6301496780 ps
CPU time 55.46 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:20:00 PM PDT 24
Peak memory 206456 kb
Host smart-cad68453-fc82-44f4-a6f8-52ea16434c3f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3642396575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3642396575
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2832356307
Short name T591
Test name
Test status
Simulation time 151579652 ps
CPU time 0.83 seconds
Started Jul 09 05:19:03 PM PDT 24
Finished Jul 09 05:19:05 PM PDT 24
Peak memory 206112 kb
Host smart-ad7f1810-59a1-49d2-b6d0-99b5e1dff182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
56307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2832356307
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.329225739
Short name T2506
Test name
Test status
Simulation time 188253082 ps
CPU time 0.81 seconds
Started Jul 09 05:19:09 PM PDT 24
Finished Jul 09 05:19:11 PM PDT 24
Peak memory 206156 kb
Host smart-06f24579-8097-4a29-9eb8-0e20bd1c3399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922
5739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.329225739
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2915728908
Short name T473
Test name
Test status
Simulation time 487490868 ps
CPU time 1.28 seconds
Started Jul 09 05:19:07 PM PDT 24
Finished Jul 09 05:19:09 PM PDT 24
Peak memory 206136 kb
Host smart-e87a0a6c-820d-4282-817c-2d16329005ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29157
28908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2915728908
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1043013493
Short name T2673
Test name
Test status
Simulation time 4933750420 ps
CPU time 136.07 seconds
Started Jul 09 05:19:09 PM PDT 24
Finished Jul 09 05:21:26 PM PDT 24
Peak memory 206448 kb
Host smart-e86ff2c0-51ff-4eca-8301-503fac059b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10430
13493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1043013493
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.680738973
Short name T2279
Test name
Test status
Simulation time 65395985 ps
CPU time 0.69 seconds
Started Jul 09 05:12:39 PM PDT 24
Finished Jul 09 05:12:41 PM PDT 24
Peak memory 206060 kb
Host smart-d852ace9-769c-484a-b4e5-e07feb8459b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=680738973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.680738973
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1610480459
Short name T1005
Test name
Test status
Simulation time 4004180345 ps
CPU time 5.59 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206200 kb
Host smart-7897a14e-0b49-4a20-9a57-294c3c02c515
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1610480459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1610480459
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2131468224
Short name T1284
Test name
Test status
Simulation time 13343489298 ps
CPU time 16.56 seconds
Started Jul 09 05:12:28 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206212 kb
Host smart-5578ac6d-fe15-4046-8f0b-6fc8fcd7e5c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2131468224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2131468224
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2972718116
Short name T1887
Test name
Test status
Simulation time 23536003208 ps
CPU time 25.1 seconds
Started Jul 09 05:12:29 PM PDT 24
Finished Jul 09 05:12:55 PM PDT 24
Peak memory 206364 kb
Host smart-47837cff-38a4-4a80-871a-8bbd158fdde4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2972718116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2972718116
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2435324385
Short name T752
Test name
Test status
Simulation time 168899943 ps
CPU time 0.81 seconds
Started Jul 09 05:12:32 PM PDT 24
Finished Jul 09 05:12:33 PM PDT 24
Peak memory 206084 kb
Host smart-2d1e6f0c-462a-4318-ad79-28f74ef78994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353
24385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2435324385
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1169799597
Short name T2503
Test name
Test status
Simulation time 204122545 ps
CPU time 0.85 seconds
Started Jul 09 05:12:31 PM PDT 24
Finished Jul 09 05:12:32 PM PDT 24
Peak memory 206152 kb
Host smart-54fa52b1-913d-4698-a266-87148b77a26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
99597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1169799597
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.4125422790
Short name T1762
Test name
Test status
Simulation time 279010799 ps
CPU time 1.07 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:32 PM PDT 24
Peak memory 206056 kb
Host smart-4ed1b47b-81bc-406d-8a68-26fa94d6ff47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41254
22790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.4125422790
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3298774555
Short name T598
Test name
Test status
Simulation time 15793752425 ps
CPU time 29.93 seconds
Started Jul 09 05:12:29 PM PDT 24
Finished Jul 09 05:13:00 PM PDT 24
Peak memory 206260 kb
Host smart-2e86f63c-8970-4b0f-bded-74e76dcd83b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32987
74555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3298774555
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1516219715
Short name T347
Test name
Test status
Simulation time 486031286 ps
CPU time 1.5 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:32 PM PDT 24
Peak memory 206060 kb
Host smart-992d3ce1-f2d1-46b5-af5b-a75c57152bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15162
19715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1516219715
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.990329414
Short name T2689
Test name
Test status
Simulation time 136950259 ps
CPU time 0.76 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:32 PM PDT 24
Peak memory 206064 kb
Host smart-3e6cfd4c-c335-4fab-93ef-d5f03cd7200e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99032
9414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.990329414
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2083072035
Short name T381
Test name
Test status
Simulation time 68008234 ps
CPU time 0.71 seconds
Started Jul 09 05:12:30 PM PDT 24
Finished Jul 09 05:12:32 PM PDT 24
Peak memory 206088 kb
Host smart-40a5c4b8-9cd8-48fc-9cef-86ef3711dea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20830
72035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2083072035
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3449208922
Short name T1289
Test name
Test status
Simulation time 854803093 ps
CPU time 2.01 seconds
Started Jul 09 05:12:36 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206276 kb
Host smart-49813060-3f67-4d81-9701-fe615c4f3b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34492
08922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3449208922
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1646320090
Short name T755
Test name
Test status
Simulation time 183734974 ps
CPU time 2.25 seconds
Started Jul 09 05:12:33 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206384 kb
Host smart-64d7db9a-14b9-4e71-9fb0-d0acd10e49b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16463
20090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1646320090
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.463274327
Short name T1942
Test name
Test status
Simulation time 200194863 ps
CPU time 0.86 seconds
Started Jul 09 05:12:33 PM PDT 24
Finished Jul 09 05:12:34 PM PDT 24
Peak memory 206156 kb
Host smart-f20dff8d-ee04-4beb-b7c9-2a2a98aa94b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46327
4327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.463274327
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.638413144
Short name T1179
Test name
Test status
Simulation time 153763013 ps
CPU time 0.73 seconds
Started Jul 09 05:12:36 PM PDT 24
Finished Jul 09 05:12:38 PM PDT 24
Peak memory 206016 kb
Host smart-b69404ea-4b08-4735-bccb-1a8ed60521c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63841
3144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.638413144
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1737995685
Short name T1343
Test name
Test status
Simulation time 221892902 ps
CPU time 0.98 seconds
Started Jul 09 05:12:33 PM PDT 24
Finished Jul 09 05:12:35 PM PDT 24
Peak memory 206024 kb
Host smart-77010290-903a-47a7-8e72-cbbf9513bd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17379
95685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1737995685
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3642334339
Short name T2648
Test name
Test status
Simulation time 160916978 ps
CPU time 0.79 seconds
Started Jul 09 05:12:35 PM PDT 24
Finished Jul 09 05:12:37 PM PDT 24
Peak memory 206108 kb
Host smart-579d1f39-21d4-4a11-95e6-6a08331bf3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
34339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3642334339
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1762894147
Short name T1253
Test name
Test status
Simulation time 23328046677 ps
CPU time 21.08 seconds
Started Jul 09 05:12:35 PM PDT 24
Finished Jul 09 05:12:57 PM PDT 24
Peak memory 206080 kb
Host smart-b054801c-c414-43ba-8fc0-111c9f6a9c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
94147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1762894147
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.4068938493
Short name T586
Test name
Test status
Simulation time 3350474680 ps
CPU time 4.14 seconds
Started Jul 09 05:12:32 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206120 kb
Host smart-a7ef61da-7a7a-40fe-bbbc-1c32b2e798d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40689
38493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.4068938493
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3342600964
Short name T1155
Test name
Test status
Simulation time 8194252934 ps
CPU time 235.36 seconds
Started Jul 09 05:12:34 PM PDT 24
Finished Jul 09 05:16:31 PM PDT 24
Peak memory 206512 kb
Host smart-847477b3-a7f9-4ee5-b984-8758ed39a2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
00964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3342600964
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3727323963
Short name T1471
Test name
Test status
Simulation time 5869996405 ps
CPU time 159.27 seconds
Started Jul 09 05:12:35 PM PDT 24
Finished Jul 09 05:15:15 PM PDT 24
Peak memory 206364 kb
Host smart-1c71e5a0-28f0-481c-844c-c39edf718993
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3727323963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3727323963
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1615597374
Short name T1979
Test name
Test status
Simulation time 272744988 ps
CPU time 0.94 seconds
Started Jul 09 05:12:33 PM PDT 24
Finished Jul 09 05:12:35 PM PDT 24
Peak memory 206140 kb
Host smart-9f8f711e-3094-47f4-a9ea-1fb6a124e325
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1615597374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1615597374
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2414873044
Short name T1257
Test name
Test status
Simulation time 214332769 ps
CPU time 0.88 seconds
Started Jul 09 05:12:35 PM PDT 24
Finished Jul 09 05:12:37 PM PDT 24
Peak memory 206120 kb
Host smart-187fe823-2878-4802-9480-2b7a5d558b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
73044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2414873044
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1024548190
Short name T2239
Test name
Test status
Simulation time 6226277807 ps
CPU time 181.54 seconds
Started Jul 09 05:12:36 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 206352 kb
Host smart-071fdd29-9c21-4782-ad5f-7abb3fa222c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
48190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1024548190
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.727916014
Short name T1081
Test name
Test status
Simulation time 6095664923 ps
CPU time 175.3 seconds
Started Jul 09 05:12:36 PM PDT 24
Finished Jul 09 05:15:32 PM PDT 24
Peak memory 206260 kb
Host smart-ddfe553d-5c29-463e-8058-c85856072a17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=727916014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.727916014
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.932909447
Short name T678
Test name
Test status
Simulation time 167359105 ps
CPU time 0.83 seconds
Started Jul 09 05:12:34 PM PDT 24
Finished Jul 09 05:12:35 PM PDT 24
Peak memory 205972 kb
Host smart-a8cf585c-94cf-46f7-8899-2d720930181d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=932909447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.932909447
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3099846869
Short name T608
Test name
Test status
Simulation time 158917605 ps
CPU time 0.83 seconds
Started Jul 09 05:12:35 PM PDT 24
Finished Jul 09 05:12:37 PM PDT 24
Peak memory 205996 kb
Host smart-f8b4b31e-b338-46ce-9ad5-3575abf91348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
46869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3099846869
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2669930306
Short name T2063
Test name
Test status
Simulation time 200224602 ps
CPU time 0.85 seconds
Started Jul 09 05:12:36 PM PDT 24
Finished Jul 09 05:12:38 PM PDT 24
Peak memory 206028 kb
Host smart-4c119d85-58b1-4e20-8d8b-b70c752bdb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26699
30306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2669930306
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.770082822
Short name T1785
Test name
Test status
Simulation time 175512012 ps
CPU time 0.81 seconds
Started Jul 09 05:12:33 PM PDT 24
Finished Jul 09 05:12:35 PM PDT 24
Peak memory 206052 kb
Host smart-5188023b-7840-44b9-8e3b-248c70189a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77008
2822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.770082822
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2123585768
Short name T1414
Test name
Test status
Simulation time 184358242 ps
CPU time 0.84 seconds
Started Jul 09 05:12:34 PM PDT 24
Finished Jul 09 05:12:35 PM PDT 24
Peak memory 206160 kb
Host smart-cb55ed1e-8e65-46a3-b834-2dc8f271957d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21235
85768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2123585768
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3571044368
Short name T1827
Test name
Test status
Simulation time 192064206 ps
CPU time 0.88 seconds
Started Jul 09 05:12:32 PM PDT 24
Finished Jul 09 05:12:33 PM PDT 24
Peak memory 206148 kb
Host smart-e22674a1-ef44-4bed-be2c-b50e6fde5df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35710
44368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3571044368
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.200247203
Short name T1885
Test name
Test status
Simulation time 151936444 ps
CPU time 0.77 seconds
Started Jul 09 05:12:35 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206096 kb
Host smart-4f8fbe1d-e400-4517-933b-863cf00fd520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20024
7203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.200247203
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1275860367
Short name T650
Test name
Test status
Simulation time 252296840 ps
CPU time 1 seconds
Started Jul 09 05:12:34 PM PDT 24
Finished Jul 09 05:12:36 PM PDT 24
Peak memory 206140 kb
Host smart-64968893-f073-4fb5-9cae-688a6cd0ddff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1275860367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1275860367
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.587271272
Short name T2048
Test name
Test status
Simulation time 159019562 ps
CPU time 0.8 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206160 kb
Host smart-2ba57292-5936-4536-880f-9a8b14086113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58727
1272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.587271272
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.689175289
Short name T2106
Test name
Test status
Simulation time 94873574 ps
CPU time 0.71 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:12:42 PM PDT 24
Peak memory 206124 kb
Host smart-7df54328-9aa8-4221-a89c-6b087813b002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68917
5289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.689175289
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3574392671
Short name T871
Test name
Test status
Simulation time 15182457758 ps
CPU time 35.26 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:13:15 PM PDT 24
Peak memory 206356 kb
Host smart-5ad297d1-6a84-4369-bea6-2ac9740873d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
92671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3574392671
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3941326231
Short name T2040
Test name
Test status
Simulation time 155242435 ps
CPU time 0.82 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206124 kb
Host smart-366edfbb-71ac-420f-94d6-e4cbd8544d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39413
26231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3941326231
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.416522858
Short name T1084
Test name
Test status
Simulation time 182603470 ps
CPU time 0.85 seconds
Started Jul 09 05:12:36 PM PDT 24
Finished Jul 09 05:12:38 PM PDT 24
Peak memory 206112 kb
Host smart-14fe194e-4616-474c-a5b5-33bbe9c8c99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41652
2858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.416522858
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2349247610
Short name T1834
Test name
Test status
Simulation time 5640167988 ps
CPU time 48.4 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:13:28 PM PDT 24
Peak memory 206284 kb
Host smart-dd0af3cd-67fe-42ca-9839-ec910193b4bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2349247610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2349247610
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1665443057
Short name T2457
Test name
Test status
Simulation time 13520458124 ps
CPU time 94.53 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206448 kb
Host smart-2e21fa42-5092-4dca-ab6a-dd358a4847ac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1665443057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1665443057
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1938646698
Short name T1337
Test name
Test status
Simulation time 15126378077 ps
CPU time 108.93 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:14:28 PM PDT 24
Peak memory 206428 kb
Host smart-aac42831-899c-41d3-9835-66f8cbcd7078
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1938646698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1938646698
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2137226595
Short name T1574
Test name
Test status
Simulation time 191687220 ps
CPU time 0.79 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:12:38 PM PDT 24
Peak memory 206068 kb
Host smart-3e700dd0-624a-4bd1-b420-8ea3c3a43901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21372
26595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2137226595
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1222558
Short name T731
Test name
Test status
Simulation time 167328569 ps
CPU time 0.8 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206152 kb
Host smart-eaed19f8-95d8-4822-a7d1-2ad40b44b22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12225
58 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1222558
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.373926289
Short name T1585
Test name
Test status
Simulation time 140613379 ps
CPU time 0.78 seconds
Started Jul 09 05:12:38 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206152 kb
Host smart-bdfc488b-8f6a-4b3e-a91d-952cca3950ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37392
6289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.373926289
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.877929109
Short name T350
Test name
Test status
Simulation time 149522146 ps
CPU time 0.77 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206160 kb
Host smart-db2495ad-53fa-465b-936d-8c5c694c929b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87792
9109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.877929109
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1517951641
Short name T1723
Test name
Test status
Simulation time 158130483 ps
CPU time 0.85 seconds
Started Jul 09 05:12:39 PM PDT 24
Finished Jul 09 05:12:41 PM PDT 24
Peak memory 206056 kb
Host smart-128c6516-f423-47d2-8d7b-7c4e7309892d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
51641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1517951641
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.192206726
Short name T492
Test name
Test status
Simulation time 208300425 ps
CPU time 1.08 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206052 kb
Host smart-8dab0ef2-e002-4bac-9dd0-e49fd96cce3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
6726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.192206726
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.113128838
Short name T916
Test name
Test status
Simulation time 6859424095 ps
CPU time 188.18 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:15:46 PM PDT 24
Peak memory 206436 kb
Host smart-3ec2199c-c306-47a6-b119-fb96ffbb2a75
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=113128838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.113128838
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1773410475
Short name T679
Test name
Test status
Simulation time 157476586 ps
CPU time 0.81 seconds
Started Jul 09 05:12:39 PM PDT 24
Finished Jul 09 05:12:40 PM PDT 24
Peak memory 206036 kb
Host smart-483eac79-f407-4e1d-9d50-569cf0fcb3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
10475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1773410475
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.671530008
Short name T913
Test name
Test status
Simulation time 215782544 ps
CPU time 0.83 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 206052 kb
Host smart-07ba0a26-bff5-4e77-b6a3-aab8c00e9b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67153
0008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.671530008
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2619219793
Short name T1521
Test name
Test status
Simulation time 812744700 ps
CPU time 1.95 seconds
Started Jul 09 05:12:39 PM PDT 24
Finished Jul 09 05:12:41 PM PDT 24
Peak memory 206188 kb
Host smart-0712c9ba-1e42-425e-8e26-7e8980720541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26192
19793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2619219793
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3045302870
Short name T1843
Test name
Test status
Simulation time 5432720765 ps
CPU time 152.95 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:15:11 PM PDT 24
Peak memory 206368 kb
Host smart-ee5c5730-9098-495d-ab06-e4419fed6d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30453
02870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3045302870
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.4259669407
Short name T1961
Test name
Test status
Simulation time 31001610 ps
CPU time 0.66 seconds
Started Jul 09 05:12:51 PM PDT 24
Finished Jul 09 05:12:53 PM PDT 24
Peak memory 206156 kb
Host smart-3d951224-35e6-4521-98dd-af5214c8aa11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4259669407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.4259669407
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1704122169
Short name T2317
Test name
Test status
Simulation time 3755366762 ps
CPU time 5.53 seconds
Started Jul 09 05:12:37 PM PDT 24
Finished Jul 09 05:12:43 PM PDT 24
Peak memory 206084 kb
Host smart-81a869b1-fd6e-4262-82cd-ab44a5a7497a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1704122169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1704122169
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.587535374
Short name T188
Test name
Test status
Simulation time 13378957945 ps
CPU time 13.15 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:13:01 PM PDT 24
Peak memory 206168 kb
Host smart-3cfd22a6-cc3f-43ef-8f94-67ba80a1f8cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=587535374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.587535374
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2473677888
Short name T739
Test name
Test status
Simulation time 23364121109 ps
CPU time 22.76 seconds
Started Jul 09 05:12:39 PM PDT 24
Finished Jul 09 05:13:03 PM PDT 24
Peak memory 206172 kb
Host smart-e0a174ba-60bb-449c-9e5a-f82cb1343ead
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2473677888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2473677888
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2801171057
Short name T1015
Test name
Test status
Simulation time 148271918 ps
CPU time 0.78 seconds
Started Jul 09 05:12:42 PM PDT 24
Finished Jul 09 05:12:44 PM PDT 24
Peak memory 206148 kb
Host smart-2d41832a-4505-4a4f-a310-e479ae250128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28011
71057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2801171057
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3636220672
Short name T1466
Test name
Test status
Simulation time 146803707 ps
CPU time 0.78 seconds
Started Jul 09 05:12:42 PM PDT 24
Finished Jul 09 05:12:44 PM PDT 24
Peak memory 206140 kb
Host smart-1d94cbf3-6d72-4e89-8ede-a09b4ca730f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362
20672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3636220672
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3148563167
Short name T1855
Test name
Test status
Simulation time 410733293 ps
CPU time 1.32 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:12:50 PM PDT 24
Peak memory 206120 kb
Host smart-a9bf22dd-e629-4cbf-a880-25dc175d5825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
63167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3148563167
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3343903605
Short name T175
Test name
Test status
Simulation time 909849303 ps
CPU time 1.97 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:12:44 PM PDT 24
Peak memory 206284 kb
Host smart-b09f6fac-0584-45c7-8030-5e2c8d1e1b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33439
03605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3343903605
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.1671368898
Short name T745
Test name
Test status
Simulation time 8893984973 ps
CPU time 17.12 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:12:59 PM PDT 24
Peak memory 206256 kb
Host smart-145e309a-17a9-46b1-93f2-1693fc724e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
68898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1671368898
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.1356128441
Short name T1513
Test name
Test status
Simulation time 464414747 ps
CPU time 1.41 seconds
Started Jul 09 05:12:42 PM PDT 24
Finished Jul 09 05:12:44 PM PDT 24
Peak memory 206168 kb
Host smart-4a8a4eba-b089-4cb6-b40a-334e769fc405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13561
28441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1356128441
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1510789034
Short name T18
Test name
Test status
Simulation time 183670160 ps
CPU time 0.82 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:12:42 PM PDT 24
Peak memory 206068 kb
Host smart-1d1a5a56-e8ae-49dc-bc30-284741a90309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15107
89034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1510789034
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3723037135
Short name T239
Test name
Test status
Simulation time 62691934 ps
CPU time 0.73 seconds
Started Jul 09 05:12:40 PM PDT 24
Finished Jul 09 05:12:41 PM PDT 24
Peak memory 206116 kb
Host smart-b87bad71-313f-4908-864b-84b332d8b4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37230
37135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3723037135
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3636677038
Short name T1534
Test name
Test status
Simulation time 736352447 ps
CPU time 1.85 seconds
Started Jul 09 05:12:40 PM PDT 24
Finished Jul 09 05:12:43 PM PDT 24
Peak memory 206292 kb
Host smart-ad4480a4-b33f-4081-8b85-7a5ee46b64d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
77038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3636677038
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3117163488
Short name T862
Test name
Test status
Simulation time 299039160 ps
CPU time 2.02 seconds
Started Jul 09 05:12:42 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206364 kb
Host smart-4e137a7d-b604-4d61-ba71-8ace07125df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31171
63488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3117163488
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1342082280
Short name T1821
Test name
Test status
Simulation time 250297210 ps
CPU time 0.92 seconds
Started Jul 09 05:12:43 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206108 kb
Host smart-e82c3b59-ad2a-409d-a46f-7ddd7d3c9e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13420
82280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1342082280
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1248298033
Short name T1452
Test name
Test status
Simulation time 147795755 ps
CPU time 0.8 seconds
Started Jul 09 05:12:43 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206108 kb
Host smart-6003f317-4d9c-495e-8000-9cf484fbe8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
98033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1248298033
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.172592791
Short name T19
Test name
Test status
Simulation time 228005576 ps
CPU time 0.86 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206124 kb
Host smart-7d16ae66-9945-49c8-a17b-34e0f46c1ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17259
2791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.172592791
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1197909644
Short name T504
Test name
Test status
Simulation time 205253559 ps
CPU time 0.91 seconds
Started Jul 09 05:12:42 PM PDT 24
Finished Jul 09 05:12:44 PM PDT 24
Peak memory 206108 kb
Host smart-e2cbc866-a021-45bc-aced-96445d45e5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
09644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1197909644
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.4259772784
Short name T889
Test name
Test status
Simulation time 23329669213 ps
CPU time 29.71 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:13:12 PM PDT 24
Peak memory 206192 kb
Host smart-c159d355-cc84-44c0-950d-a6d4297a5298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42597
72784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.4259772784
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3728728584
Short name T2243
Test name
Test status
Simulation time 3311362569 ps
CPU time 3.59 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:12:48 PM PDT 24
Peak memory 206084 kb
Host smart-bfbe5aa6-0c93-4c0b-9fbb-8e57ae02ce38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
28584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3728728584
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2881994185
Short name T550
Test name
Test status
Simulation time 7743787985 ps
CPU time 52.52 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:13:41 PM PDT 24
Peak memory 206440 kb
Host smart-95bd574c-8a42-4b98-93e7-d461160e2bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28819
94185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2881994185
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.973239594
Short name T2210
Test name
Test status
Simulation time 4108672323 ps
CPU time 29.2 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:13:19 PM PDT 24
Peak memory 206412 kb
Host smart-cf3873f2-a460-41e3-8cdf-7f0f71c6be7f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=973239594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.973239594
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.1447405046
Short name T1819
Test name
Test status
Simulation time 253176928 ps
CPU time 0.95 seconds
Started Jul 09 05:12:47 PM PDT 24
Finished Jul 09 05:12:49 PM PDT 24
Peak memory 206144 kb
Host smart-2af6e758-ff76-4b50-a557-d190e85684a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1447405046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.1447405046
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.70429269
Short name T1258
Test name
Test status
Simulation time 204269638 ps
CPU time 0.88 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206116 kb
Host smart-3d69bb6b-2228-486a-aa9e-dd5949754d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70429
269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.70429269
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1482435501
Short name T2212
Test name
Test status
Simulation time 6577009990 ps
CPU time 49.97 seconds
Started Jul 09 05:12:43 PM PDT 24
Finished Jul 09 05:13:34 PM PDT 24
Peak memory 206392 kb
Host smart-e3dfd195-9dc5-47c3-9dd4-6de16e77d5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14824
35501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1482435501
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3812847194
Short name T2663
Test name
Test status
Simulation time 4982632553 ps
CPU time 51.06 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:13:35 PM PDT 24
Peak memory 206248 kb
Host smart-60d703fb-4c93-4554-a19d-b9672f4d4ae2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3812847194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3812847194
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3772539147
Short name T357
Test name
Test status
Simulation time 153331498 ps
CPU time 0.8 seconds
Started Jul 09 05:12:42 PM PDT 24
Finished Jul 09 05:12:43 PM PDT 24
Peak memory 206108 kb
Host smart-887fafa9-76f2-401d-a9e2-6be70b5e188e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3772539147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3772539147
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.465364553
Short name T789
Test name
Test status
Simulation time 152327119 ps
CPU time 0.81 seconds
Started Jul 09 05:12:46 PM PDT 24
Finished Jul 09 05:12:48 PM PDT 24
Peak memory 206116 kb
Host smart-44fa58ce-534a-45c1-8eba-e39d36da4c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46536
4553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.465364553
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2076809483
Short name T2252
Test name
Test status
Simulation time 218315913 ps
CPU time 0.96 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:12:43 PM PDT 24
Peak memory 206148 kb
Host smart-9ea87c64-91d4-4cf1-82a8-39fdd55327aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20768
09483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2076809483
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.165657112
Short name T1749
Test name
Test status
Simulation time 188321862 ps
CPU time 0.85 seconds
Started Jul 09 05:12:45 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206124 kb
Host smart-4e17a071-4604-415e-a740-1c292a14cba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16565
7112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.165657112
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2940936885
Short name T1835
Test name
Test status
Simulation time 174682453 ps
CPU time 0.8 seconds
Started Jul 09 05:12:40 PM PDT 24
Finished Jul 09 05:12:41 PM PDT 24
Peak memory 206132 kb
Host smart-e7454b44-c3fc-46ef-8534-8fa42eff6a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
36885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2940936885
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4207199150
Short name T2045
Test name
Test status
Simulation time 184810998 ps
CPU time 0.91 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 206124 kb
Host smart-431eea97-0267-484a-8dcf-a83e1ba0aaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42071
99150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4207199150
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.503365517
Short name T2115
Test name
Test status
Simulation time 204388712 ps
CPU time 0.83 seconds
Started Jul 09 05:12:41 PM PDT 24
Finished Jul 09 05:12:42 PM PDT 24
Peak memory 206132 kb
Host smart-1b184210-8939-4ac5-ba7f-55303394f456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50336
5517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.503365517
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.373022881
Short name T526
Test name
Test status
Simulation time 214913503 ps
CPU time 0.9 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 206060 kb
Host smart-8b70d2c1-33c6-462c-9ee3-3fe138e00bbf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=373022881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.373022881
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.789185031
Short name T2606
Test name
Test status
Simulation time 154281365 ps
CPU time 0.76 seconds
Started Jul 09 05:12:45 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206164 kb
Host smart-40225577-3b6a-453d-87b5-252e356d9c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78918
5031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.789185031
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1757998404
Short name T1999
Test name
Test status
Simulation time 35529883 ps
CPU time 0.65 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206136 kb
Host smart-409738d7-a144-429d-9604-991bb2a4ff28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
98404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1757998404
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1260722565
Short name T1956
Test name
Test status
Simulation time 8808106823 ps
CPU time 18.59 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:13:08 PM PDT 24
Peak memory 214556 kb
Host smart-45d37321-4d8b-4356-8456-42ec29795918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
22565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1260722565
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1502496682
Short name T2000
Test name
Test status
Simulation time 168437353 ps
CPU time 0.82 seconds
Started Jul 09 05:12:47 PM PDT 24
Finished Jul 09 05:12:48 PM PDT 24
Peak memory 206116 kb
Host smart-84d337af-abef-49bd-89da-1e9b6b582230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15024
96682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1502496682
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2147749062
Short name T2277
Test name
Test status
Simulation time 217613143 ps
CPU time 0.91 seconds
Started Jul 09 05:12:43 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 205992 kb
Host smart-2e11cb70-a6c1-458c-b234-804d0cb00784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
49062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2147749062
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2436286826
Short name T2310
Test name
Test status
Simulation time 7485930334 ps
CPU time 39.61 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 206364 kb
Host smart-1dbd4051-899b-4ebc-8602-670afda225ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2436286826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2436286826
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2787579338
Short name T32
Test name
Test status
Simulation time 11327471806 ps
CPU time 59.49 seconds
Started Jul 09 05:12:47 PM PDT 24
Finished Jul 09 05:13:47 PM PDT 24
Peak memory 206404 kb
Host smart-1e8c6cae-034a-4c64-bc1f-d7c6ac27d07b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2787579338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2787579338
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2709277510
Short name T1126
Test name
Test status
Simulation time 16949555024 ps
CPU time 98.11 seconds
Started Jul 09 05:12:46 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206352 kb
Host smart-7881bb39-ae61-4b56-af26-0fc6d78e5e81
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2709277510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2709277510
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2855417856
Short name T1166
Test name
Test status
Simulation time 194259099 ps
CPU time 0.91 seconds
Started Jul 09 05:12:46 PM PDT 24
Finished Jul 09 05:12:47 PM PDT 24
Peak memory 206152 kb
Host smart-439d2669-43d4-4e2c-a7b9-811ae0893c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28554
17856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2855417856
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2914910116
Short name T639
Test name
Test status
Simulation time 155637654 ps
CPU time 0.8 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:12:45 PM PDT 24
Peak memory 206092 kb
Host smart-f846934b-92af-466d-911c-705e9469e314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29149
10116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2914910116
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3366806907
Short name T2047
Test name
Test status
Simulation time 166065016 ps
CPU time 0.78 seconds
Started Jul 09 05:12:46 PM PDT 24
Finished Jul 09 05:12:47 PM PDT 24
Peak memory 206148 kb
Host smart-54b3d31a-74c6-4f2e-a508-908db784a819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33668
06907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3366806907
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3142691580
Short name T826
Test name
Test status
Simulation time 172748630 ps
CPU time 0.77 seconds
Started Jul 09 05:12:45 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206000 kb
Host smart-66cb1ffa-2128-4043-b460-5053bedfad12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31426
91580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3142691580
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1861714226
Short name T1188
Test name
Test status
Simulation time 204189027 ps
CPU time 0.82 seconds
Started Jul 09 05:12:43 PM PDT 24
Finished Jul 09 05:12:44 PM PDT 24
Peak memory 206108 kb
Host smart-bac7e8ad-648d-417d-8c55-95570ef6aaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18617
14226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1861714226
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3577895540
Short name T2441
Test name
Test status
Simulation time 235591135 ps
CPU time 0.99 seconds
Started Jul 09 05:12:46 PM PDT 24
Finished Jul 09 05:12:47 PM PDT 24
Peak memory 206016 kb
Host smart-68733141-764a-4e23-b6bd-9b4fb0c045b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35778
95540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3577895540
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1221013260
Short name T2486
Test name
Test status
Simulation time 3507440258 ps
CPU time 91 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 206404 kb
Host smart-46690305-888a-4fd7-85d4-80925a6a1fb2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1221013260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1221013260
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.966689787
Short name T1007
Test name
Test status
Simulation time 235768318 ps
CPU time 0.85 seconds
Started Jul 09 05:12:46 PM PDT 24
Finished Jul 09 05:12:48 PM PDT 24
Peak memory 206020 kb
Host smart-ba0c393e-44e8-4b53-942e-daa7b9434bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96668
9787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.966689787
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.4294236469
Short name T1121
Test name
Test status
Simulation time 151937174 ps
CPU time 0.78 seconds
Started Jul 09 05:12:44 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 206124 kb
Host smart-9b32c3d7-7343-432f-a19f-72bef99b7869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42942
36469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.4294236469
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3183195566
Short name T782
Test name
Test status
Simulation time 545282117 ps
CPU time 1.42 seconds
Started Jul 09 05:12:47 PM PDT 24
Finished Jul 09 05:12:49 PM PDT 24
Peak memory 206112 kb
Host smart-a8f8a183-f198-4fe1-a38e-53fc1d7c36bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
95566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3183195566
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1661696966
Short name T331
Test name
Test status
Simulation time 5952466330 ps
CPU time 165.59 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:15:35 PM PDT 24
Peak memory 206388 kb
Host smart-1ee26b1a-decc-4303-837f-a19991f217e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16616
96966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1661696966
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3212392725
Short name T893
Test name
Test status
Simulation time 70785021 ps
CPU time 0.71 seconds
Started Jul 09 05:13:02 PM PDT 24
Finished Jul 09 05:13:04 PM PDT 24
Peak memory 206148 kb
Host smart-e07a7205-1e0b-4168-90c1-1c89bff08329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3212392725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3212392725
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.4104710274
Short name T1520
Test name
Test status
Simulation time 4215011056 ps
CPU time 5.31 seconds
Started Jul 09 05:12:50 PM PDT 24
Finished Jul 09 05:12:57 PM PDT 24
Peak memory 206376 kb
Host smart-97093a2a-6694-4412-ba29-7fb5565a0b2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4104710274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.4104710274
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1583981115
Short name T838
Test name
Test status
Simulation time 13413542178 ps
CPU time 13.07 seconds
Started Jul 09 05:12:50 PM PDT 24
Finished Jul 09 05:13:04 PM PDT 24
Peak memory 206256 kb
Host smart-ca880f26-ef7d-4c82-9dd4-bd9709ce13e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1583981115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1583981115
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2750696235
Short name T1115
Test name
Test status
Simulation time 23377804824 ps
CPU time 28.89 seconds
Started Jul 09 05:12:51 PM PDT 24
Finished Jul 09 05:13:21 PM PDT 24
Peak memory 206096 kb
Host smart-87ce7206-3435-4c75-b3de-9444fe7b3962
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2750696235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2750696235
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1052347059
Short name T2355
Test name
Test status
Simulation time 179958058 ps
CPU time 0.88 seconds
Started Jul 09 05:12:50 PM PDT 24
Finished Jul 09 05:12:52 PM PDT 24
Peak memory 206160 kb
Host smart-b18032af-809f-485d-a3c5-623321103425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
47059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1052347059
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.998180911
Short name T628
Test name
Test status
Simulation time 171054496 ps
CPU time 0.82 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 206088 kb
Host smart-90f9aeef-0eec-4028-9b1f-dc0b2b0f24c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99818
0911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.998180911
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1472415689
Short name T1894
Test name
Test status
Simulation time 491609166 ps
CPU time 1.74 seconds
Started Jul 09 05:12:50 PM PDT 24
Finished Jul 09 05:12:53 PM PDT 24
Peak memory 206128 kb
Host smart-1c3eac73-5102-4b41-869e-9573ac2ed990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14724
15689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1472415689
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3694593385
Short name T1987
Test name
Test status
Simulation time 1180550356 ps
CPU time 2.49 seconds
Started Jul 09 05:12:50 PM PDT 24
Finished Jul 09 05:12:53 PM PDT 24
Peak memory 206196 kb
Host smart-9a51efb9-44cd-4974-aa6f-b78c0e7f755d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36945
93385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3694593385
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.225905159
Short name T2575
Test name
Test status
Simulation time 20900234162 ps
CPU time 36.44 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:13:27 PM PDT 24
Peak memory 206404 kb
Host smart-f17417a7-b1cc-45c2-bc62-90aec1a03a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22590
5159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.225905159
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.1585034126
Short name T2326
Test name
Test status
Simulation time 482785390 ps
CPU time 1.39 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 205996 kb
Host smart-b1be4b5d-aab2-4266-a219-f71f93d71d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15850
34126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.1585034126
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1081993768
Short name T2360
Test name
Test status
Simulation time 140912900 ps
CPU time 0.78 seconds
Started Jul 09 05:12:50 PM PDT 24
Finished Jul 09 05:12:52 PM PDT 24
Peak memory 206132 kb
Host smart-13f4dd4e-3282-4689-a661-a7d36b90f68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
93768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1081993768
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2322077486
Short name T2233
Test name
Test status
Simulation time 32828399 ps
CPU time 0.65 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 206080 kb
Host smart-6321b61e-0e9d-4ab7-8e0a-0c11719a95f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23220
77486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2322077486
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2331317255
Short name T2607
Test name
Test status
Simulation time 1052982097 ps
CPU time 2.28 seconds
Started Jul 09 05:12:48 PM PDT 24
Finished Jul 09 05:12:51 PM PDT 24
Peak memory 206320 kb
Host smart-fb0142f3-c7d7-4f71-9113-06bafdf89893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
17255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2331317255
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2932901228
Short name T364
Test name
Test status
Simulation time 359319693 ps
CPU time 1.95 seconds
Started Jul 09 05:12:49 PM PDT 24
Finished Jul 09 05:12:52 PM PDT 24
Peak memory 206268 kb
Host smart-2cbbe9ca-81dc-45d9-8c30-86f884c4cc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29329
01228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2932901228
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.574274246
Short name T1902
Test name
Test status
Simulation time 265457450 ps
CPU time 0.92 seconds
Started Jul 09 05:12:54 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206136 kb
Host smart-907f7b28-21a2-4870-92ef-35779f678a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57427
4246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.574274246
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3984225920
Short name T2196
Test name
Test status
Simulation time 138794666 ps
CPU time 0.79 seconds
Started Jul 09 05:12:55 PM PDT 24
Finished Jul 09 05:12:57 PM PDT 24
Peak memory 205948 kb
Host smart-617203ae-9645-4f77-a97e-916aec207e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39842
25920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3984225920
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.23040621
Short name T978
Test name
Test status
Simulation time 272222690 ps
CPU time 1.01 seconds
Started Jul 09 05:12:53 PM PDT 24
Finished Jul 09 05:12:55 PM PDT 24
Peak memory 206140 kb
Host smart-6b8238e3-b0e3-47e9-aa64-7cddfacde7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23040
621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.23040621
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1985189715
Short name T1994
Test name
Test status
Simulation time 232702194 ps
CPU time 0.93 seconds
Started Jul 09 05:12:54 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206112 kb
Host smart-4a492abc-587a-437e-b0a2-a1cb348be02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19851
89715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1985189715
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2940074168
Short name T740
Test name
Test status
Simulation time 23375415852 ps
CPU time 23.91 seconds
Started Jul 09 05:12:52 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206100 kb
Host smart-356f1311-d7c3-422f-96a8-e65f171c9893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29400
74168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2940074168
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.4141920599
Short name T2567
Test name
Test status
Simulation time 3324852717 ps
CPU time 4.54 seconds
Started Jul 09 05:12:55 PM PDT 24
Finished Jul 09 05:13:00 PM PDT 24
Peak memory 206172 kb
Host smart-23e92d0f-13ab-4c71-a279-548ab5327e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
20599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.4141920599
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.4173805387
Short name T2245
Test name
Test status
Simulation time 6575577866 ps
CPU time 46.16 seconds
Started Jul 09 05:12:52 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206468 kb
Host smart-72b41861-edab-4651-86c9-601d5ee7e863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41738
05387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.4173805387
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.383511922
Short name T2295
Test name
Test status
Simulation time 3325251611 ps
CPU time 93.31 seconds
Started Jul 09 05:12:53 PM PDT 24
Finished Jul 09 05:14:27 PM PDT 24
Peak memory 206228 kb
Host smart-e16973b2-69fd-48eb-82c6-3b27d09c9cf1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=383511922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.383511922
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.945505547
Short name T517
Test name
Test status
Simulation time 274549804 ps
CPU time 0.9 seconds
Started Jul 09 05:12:56 PM PDT 24
Finished Jul 09 05:12:58 PM PDT 24
Peak memory 205940 kb
Host smart-55a0db83-3d67-4770-b940-6b93aa378d0d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=945505547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.945505547
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1842713299
Short name T2538
Test name
Test status
Simulation time 191854967 ps
CPU time 0.87 seconds
Started Jul 09 05:12:54 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206056 kb
Host smart-62131093-ffb5-404b-9feb-cdcd778ab40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
13299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1842713299
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.4282212250
Short name T552
Test name
Test status
Simulation time 4295035109 ps
CPU time 115.98 seconds
Started Jul 09 05:12:54 PM PDT 24
Finished Jul 09 05:14:51 PM PDT 24
Peak memory 206348 kb
Host smart-b7871d72-5327-4fab-86ca-4b8f6cbd639a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42822
12250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.4282212250
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2411712232
Short name T1459
Test name
Test status
Simulation time 4902438833 ps
CPU time 131.19 seconds
Started Jul 09 05:12:54 PM PDT 24
Finished Jul 09 05:15:06 PM PDT 24
Peak memory 206272 kb
Host smart-4e8bdbb4-2fbb-473e-a613-aa14e36f55ff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2411712232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2411712232
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1622278195
Short name T478
Test name
Test status
Simulation time 164360177 ps
CPU time 0.79 seconds
Started Jul 09 05:12:53 PM PDT 24
Finished Jul 09 05:12:55 PM PDT 24
Peak memory 206140 kb
Host smart-410783c6-5faf-40da-bb37-445aed8a1389
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1622278195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1622278195
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3287087425
Short name T1781
Test name
Test status
Simulation time 177820997 ps
CPU time 0.78 seconds
Started Jul 09 05:12:54 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206056 kb
Host smart-a4741725-1848-41ef-b9a3-0af3e980ec56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
87425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3287087425
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2290101290
Short name T132
Test name
Test status
Simulation time 208083895 ps
CPU time 0.99 seconds
Started Jul 09 05:12:56 PM PDT 24
Finished Jul 09 05:12:58 PM PDT 24
Peak memory 205964 kb
Host smart-05bb677d-2e71-40d1-b3f8-863cbcd4384e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22901
01290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2290101290
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1378822472
Short name T1946
Test name
Test status
Simulation time 190219222 ps
CPU time 0.89 seconds
Started Jul 09 05:12:53 PM PDT 24
Finished Jul 09 05:12:56 PM PDT 24
Peak memory 206136 kb
Host smart-ba0e57cb-94c5-4cd7-8c6a-7d7b557442f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13788
22472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1378822472
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2653908753
Short name T1974
Test name
Test status
Simulation time 180260372 ps
CPU time 0.81 seconds
Started Jul 09 05:12:53 PM PDT 24
Finished Jul 09 05:12:55 PM PDT 24
Peak memory 206108 kb
Host smart-628d0a01-8a33-4341-89d8-b186e293a396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
08753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2653908753
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.431485807
Short name T590
Test name
Test status
Simulation time 202178985 ps
CPU time 0.83 seconds
Started Jul 09 05:12:52 PM PDT 24
Finished Jul 09 05:12:53 PM PDT 24
Peak memory 205992 kb
Host smart-520675e6-53c1-45b2-8ed7-a9ff4ba79f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43148
5807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.431485807
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3349115617
Short name T1079
Test name
Test status
Simulation time 144526537 ps
CPU time 0.74 seconds
Started Jul 09 05:12:56 PM PDT 24
Finished Jul 09 05:12:58 PM PDT 24
Peak memory 206112 kb
Host smart-53a727c5-1033-447d-9eb8-0cdfad769233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33491
15617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3349115617
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.816134475
Short name T1150
Test name
Test status
Simulation time 257620874 ps
CPU time 0.95 seconds
Started Jul 09 05:12:58 PM PDT 24
Finished Jul 09 05:13:00 PM PDT 24
Peak memory 206128 kb
Host smart-a9b26bef-938d-4d3e-903a-1232a624a2be
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=816134475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.816134475
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3142097975
Short name T879
Test name
Test status
Simulation time 138600925 ps
CPU time 0.77 seconds
Started Jul 09 05:12:59 PM PDT 24
Finished Jul 09 05:13:01 PM PDT 24
Peak memory 206024 kb
Host smart-0766e1d3-9c53-45e0-84d8-06b9cde86103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31420
97975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3142097975
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3075677963
Short name T1712
Test name
Test status
Simulation time 44314624 ps
CPU time 0.69 seconds
Started Jul 09 05:12:58 PM PDT 24
Finished Jul 09 05:12:59 PM PDT 24
Peak memory 206056 kb
Host smart-7a50e664-2835-4004-a03b-d581902547e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30756
77963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3075677963
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3040980064
Short name T688
Test name
Test status
Simulation time 23159725343 ps
CPU time 53.28 seconds
Started Jul 09 05:12:57 PM PDT 24
Finished Jul 09 05:13:51 PM PDT 24
Peak memory 206300 kb
Host smart-378846a7-8d43-40dc-acaf-1ea29d9811a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30409
80064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3040980064
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3416717796
Short name T1916
Test name
Test status
Simulation time 165006822 ps
CPU time 0.77 seconds
Started Jul 09 05:12:59 PM PDT 24
Finished Jul 09 05:13:00 PM PDT 24
Peak memory 206152 kb
Host smart-b1a800d4-f09c-49e3-a222-9aa828b7bbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
17796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3416717796
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3993267612
Short name T1770
Test name
Test status
Simulation time 256667615 ps
CPU time 0.9 seconds
Started Jul 09 05:12:57 PM PDT 24
Finished Jul 09 05:12:59 PM PDT 24
Peak memory 206160 kb
Host smart-18cb31eb-71b7-4b63-b3e8-a5bceb88aca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39932
67612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3993267612
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1615046038
Short name T325
Test name
Test status
Simulation time 13232708788 ps
CPU time 272.22 seconds
Started Jul 09 05:12:58 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 206372 kb
Host smart-b6cd5263-188e-4bc1-aee3-89dc2dbe86e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1615046038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1615046038
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1699661402
Short name T611
Test name
Test status
Simulation time 12190788182 ps
CPU time 62.1 seconds
Started Jul 09 05:12:56 PM PDT 24
Finished Jul 09 05:13:59 PM PDT 24
Peak memory 206444 kb
Host smart-cba6a13d-7392-43ad-af59-9442ea8ca2c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1699661402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1699661402
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1993383540
Short name T469
Test name
Test status
Simulation time 15993675885 ps
CPU time 87.31 seconds
Started Jul 09 05:12:56 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 206332 kb
Host smart-71a09b6e-4187-4c92-89f7-c87b92c6a6ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1993383540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1993383540
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3155060119
Short name T2111
Test name
Test status
Simulation time 246696320 ps
CPU time 0.89 seconds
Started Jul 09 05:12:59 PM PDT 24
Finished Jul 09 05:13:01 PM PDT 24
Peak memory 206068 kb
Host smart-cb63209f-fe6a-4ea4-bfbc-1cc48a2a4cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31550
60119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3155060119
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2757985852
Short name T1878
Test name
Test status
Simulation time 159509303 ps
CPU time 0.81 seconds
Started Jul 09 05:12:59 PM PDT 24
Finished Jul 09 05:13:01 PM PDT 24
Peak memory 206164 kb
Host smart-ab61e279-2c3e-46a7-9e68-49600f6eba74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
85852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2757985852
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.603891665
Short name T1801
Test name
Test status
Simulation time 161490278 ps
CPU time 0.8 seconds
Started Jul 09 05:12:57 PM PDT 24
Finished Jul 09 05:12:58 PM PDT 24
Peak memory 206056 kb
Host smart-c7ea044f-dc88-442c-a2fe-09ab0fb206af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60389
1665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.603891665
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1382067719
Short name T903
Test name
Test status
Simulation time 148509584 ps
CPU time 0.76 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:03 PM PDT 24
Peak memory 206156 kb
Host smart-5a9af75b-5ea1-44c2-858a-23dc827c23cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13820
67719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1382067719
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2547397940
Short name T2021
Test name
Test status
Simulation time 196966742 ps
CPU time 0.82 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:03 PM PDT 24
Peak memory 206108 kb
Host smart-48e45b87-771a-44b4-a91d-20b2b60ed424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25473
97940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2547397940
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2203479115
Short name T2244
Test name
Test status
Simulation time 259061438 ps
CPU time 0.99 seconds
Started Jul 09 05:13:00 PM PDT 24
Finished Jul 09 05:13:02 PM PDT 24
Peak memory 206084 kb
Host smart-1b95497d-0961-4370-9db7-d960f8994cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22034
79115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2203479115
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2445437940
Short name T546
Test name
Test status
Simulation time 5150867944 ps
CPU time 139.66 seconds
Started Jul 09 05:13:02 PM PDT 24
Finished Jul 09 05:15:23 PM PDT 24
Peak memory 206464 kb
Host smart-359269dc-2a6b-41f8-bf62-10df3341c2af
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2445437940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2445437940
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3807960967
Short name T2172
Test name
Test status
Simulation time 170159396 ps
CPU time 0.88 seconds
Started Jul 09 05:13:02 PM PDT 24
Finished Jul 09 05:13:04 PM PDT 24
Peak memory 206132 kb
Host smart-25abaebe-6dfd-453d-b458-3c212286a289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38079
60967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3807960967
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2682935865
Short name T766
Test name
Test status
Simulation time 195589529 ps
CPU time 0.83 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:04 PM PDT 24
Peak memory 206052 kb
Host smart-185ace49-2669-4999-ab91-cf51cff7393e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26829
35865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2682935865
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2913387256
Short name T2162
Test name
Test status
Simulation time 1249343731 ps
CPU time 3.04 seconds
Started Jul 09 05:13:02 PM PDT 24
Finished Jul 09 05:13:07 PM PDT 24
Peak memory 206332 kb
Host smart-cb35d8e6-cdfd-4388-a2fc-f012269acf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29133
87256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2913387256
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.615997527
Short name T2634
Test name
Test status
Simulation time 3238314539 ps
CPU time 30.41 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206368 kb
Host smart-4b765618-6cb3-4cda-9eb5-99c020d2edb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61599
7527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.615997527
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.352746981
Short name T2504
Test name
Test status
Simulation time 77949320 ps
CPU time 0.71 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:13:20 PM PDT 24
Peak memory 206096 kb
Host smart-0e4e1297-e901-4f52-b873-d59fbd6c2848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=352746981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.352746981
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.369212586
Short name T2357
Test name
Test status
Simulation time 4325233622 ps
CPU time 5.25 seconds
Started Jul 09 05:13:03 PM PDT 24
Finished Jul 09 05:13:10 PM PDT 24
Peak memory 206368 kb
Host smart-cacf1910-0b74-4420-b7de-e46163fca126
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=369212586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.369212586
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.145357115
Short name T881
Test name
Test status
Simulation time 13368949973 ps
CPU time 13.67 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206288 kb
Host smart-000647e2-ac00-465f-b362-6ede87decf30
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=145357115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.145357115
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2211839359
Short name T1768
Test name
Test status
Simulation time 23346467889 ps
CPU time 21.22 seconds
Started Jul 09 05:13:02 PM PDT 24
Finished Jul 09 05:13:25 PM PDT 24
Peak memory 206432 kb
Host smart-0bf1e70e-ae24-4872-8ea2-03e1fb572607
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2211839359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2211839359
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.937143363
Short name T865
Test name
Test status
Simulation time 151074607 ps
CPU time 0.77 seconds
Started Jul 09 05:13:02 PM PDT 24
Finished Jul 09 05:13:05 PM PDT 24
Peak memory 206056 kb
Host smart-23668b17-9fe8-4bc9-a260-a9f8fb7d24ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93714
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.937143363
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.267177486
Short name T61
Test name
Test status
Simulation time 139875150 ps
CPU time 0.76 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:03 PM PDT 24
Peak memory 206104 kb
Host smart-00839617-faec-4e17-ab67-0b25fca34d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717
7486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.267177486
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2647079109
Short name T2435
Test name
Test status
Simulation time 196879216 ps
CPU time 0.92 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:03 PM PDT 24
Peak memory 206152 kb
Host smart-ad063670-99dc-4fa3-b100-05cc2e1c6887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470
79109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2647079109
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3638834910
Short name T2697
Test name
Test status
Simulation time 976832076 ps
CPU time 2.21 seconds
Started Jul 09 05:13:01 PM PDT 24
Finished Jul 09 05:13:04 PM PDT 24
Peak memory 206316 kb
Host smart-85d91f0b-1e30-4d96-a9be-1638b44d5435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
34910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3638834910
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.515147929
Short name T2656
Test name
Test status
Simulation time 14129556859 ps
CPU time 24.43 seconds
Started Jul 09 05:13:06 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206328 kb
Host smart-c11746f5-0b59-43ae-8dbe-2928c1f221dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51514
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.515147929
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1681068887
Short name T2305
Test name
Test status
Simulation time 399846464 ps
CPU time 1.34 seconds
Started Jul 09 05:13:04 PM PDT 24
Finished Jul 09 05:13:06 PM PDT 24
Peak memory 206160 kb
Host smart-303726f8-1569-45b9-8552-76001759441a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16810
68887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1681068887
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3983671953
Short name T1063
Test name
Test status
Simulation time 143725305 ps
CPU time 0.77 seconds
Started Jul 09 05:13:04 PM PDT 24
Finished Jul 09 05:13:06 PM PDT 24
Peak memory 205992 kb
Host smart-2f17d88a-45cc-4d01-bcb9-a39c2885d62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
71953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3983671953
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.141374857
Short name T1488
Test name
Test status
Simulation time 50035382 ps
CPU time 0.66 seconds
Started Jul 09 05:13:08 PM PDT 24
Finished Jul 09 05:13:09 PM PDT 24
Peak memory 206088 kb
Host smart-6c0a4f21-d47d-4d5d-be4b-3df3e1b85740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
4857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.141374857
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.684221345
Short name T2386
Test name
Test status
Simulation time 884359832 ps
CPU time 2.11 seconds
Started Jul 09 05:13:08 PM PDT 24
Finished Jul 09 05:13:11 PM PDT 24
Peak memory 206292 kb
Host smart-1143f856-de3f-4662-b60f-88f67dbd78e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68422
1345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.684221345
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.102996091
Short name T1817
Test name
Test status
Simulation time 215722109 ps
CPU time 1.4 seconds
Started Jul 09 05:13:05 PM PDT 24
Finished Jul 09 05:13:07 PM PDT 24
Peak memory 206388 kb
Host smart-f20fd77a-a92a-4ebf-af4e-ee599ee6d089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10299
6091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.102996091
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.391614076
Short name T1927
Test name
Test status
Simulation time 189381090 ps
CPU time 0.83 seconds
Started Jul 09 05:13:05 PM PDT 24
Finished Jul 09 05:13:06 PM PDT 24
Peak memory 206120 kb
Host smart-c7d3308e-1fc7-4771-9700-4a43daf7b224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161
4076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.391614076
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.262698683
Short name T2308
Test name
Test status
Simulation time 158794049 ps
CPU time 0.8 seconds
Started Jul 09 05:13:08 PM PDT 24
Finished Jul 09 05:13:09 PM PDT 24
Peak memory 206148 kb
Host smart-a76ee0a7-2e50-4e40-92eb-abc7883e98f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26269
8683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.262698683
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2729551343
Short name T830
Test name
Test status
Simulation time 168166482 ps
CPU time 0.89 seconds
Started Jul 09 05:13:06 PM PDT 24
Finished Jul 09 05:13:08 PM PDT 24
Peak memory 206160 kb
Host smart-d054bc70-28a6-4abf-8fc4-b3f854e21ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
51343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2729551343
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3105957197
Short name T1211
Test name
Test status
Simulation time 183051294 ps
CPU time 0.88 seconds
Started Jul 09 05:13:06 PM PDT 24
Finished Jul 09 05:13:08 PM PDT 24
Peak memory 206160 kb
Host smart-24c2260b-d631-4d70-bb08-a29463a38cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31059
57197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3105957197
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3957484981
Short name T2262
Test name
Test status
Simulation time 23306304594 ps
CPU time 22.54 seconds
Started Jul 09 05:13:08 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206220 kb
Host smart-68cd313b-7fce-468b-b007-7d00f3c86e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39574
84981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3957484981
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3237533117
Short name T953
Test name
Test status
Simulation time 3340426633 ps
CPU time 3.87 seconds
Started Jul 09 05:13:05 PM PDT 24
Finished Jul 09 05:13:10 PM PDT 24
Peak memory 206220 kb
Host smart-54295fbd-8fa7-459f-a732-a07bfcf09ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32375
33117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3237533117
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.554624017
Short name T2095
Test name
Test status
Simulation time 9630560909 ps
CPU time 92.66 seconds
Started Jul 09 05:13:04 PM PDT 24
Finished Jul 09 05:14:38 PM PDT 24
Peak memory 206480 kb
Host smart-d88a4b96-a283-4b13-88ce-03d8c17d6645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55462
4017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.554624017
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2662331840
Short name T2275
Test name
Test status
Simulation time 6919211298 ps
CPU time 67.73 seconds
Started Jul 09 05:13:05 PM PDT 24
Finished Jul 09 05:14:14 PM PDT 24
Peak memory 206412 kb
Host smart-2fafc820-9e94-4bbe-83e4-377533ef1293
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2662331840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2662331840
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3575008442
Short name T2590
Test name
Test status
Simulation time 240324911 ps
CPU time 0.93 seconds
Started Jul 09 05:13:05 PM PDT 24
Finished Jul 09 05:13:07 PM PDT 24
Peak memory 206080 kb
Host smart-1d457a65-42b3-4f21-8fbb-4eec9ff24508
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3575008442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3575008442
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.53528862
Short name T839
Test name
Test status
Simulation time 201485775 ps
CPU time 0.89 seconds
Started Jul 09 05:13:04 PM PDT 24
Finished Jul 09 05:13:06 PM PDT 24
Peak memory 206008 kb
Host smart-36ce9937-0c16-4059-97a4-1ad6163ec95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53528
862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.53528862
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1612910144
Short name T689
Test name
Test status
Simulation time 6553414577 ps
CPU time 173.51 seconds
Started Jul 09 05:13:06 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206404 kb
Host smart-8680cfee-afe2-42e2-90bd-7c70d6b90cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129
10144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1612910144
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2504329902
Short name T153
Test name
Test status
Simulation time 3382527063 ps
CPU time 23.52 seconds
Started Jul 09 05:13:11 PM PDT 24
Finished Jul 09 05:13:35 PM PDT 24
Peak memory 206356 kb
Host smart-8a59ba9a-3353-47f2-90b8-01998e1c1484
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2504329902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2504329902
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.890177385
Short name T772
Test name
Test status
Simulation time 208107975 ps
CPU time 0.89 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 206036 kb
Host smart-ace11019-94bf-4720-abed-d2ed111f2b81
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=890177385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.890177385
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.265529330
Short name T541
Test name
Test status
Simulation time 183787466 ps
CPU time 0.82 seconds
Started Jul 09 05:13:11 PM PDT 24
Finished Jul 09 05:13:12 PM PDT 24
Peak memory 206068 kb
Host smart-32b1d01b-92bb-469f-80a6-2ba62cd84d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
9330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.265529330
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2178719284
Short name T2344
Test name
Test status
Simulation time 194252631 ps
CPU time 0.83 seconds
Started Jul 09 05:13:08 PM PDT 24
Finished Jul 09 05:13:09 PM PDT 24
Peak memory 206112 kb
Host smart-9deaf0e5-9567-4601-b5d5-d702ac657416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21787
19284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2178719284
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1216676339
Short name T1408
Test name
Test status
Simulation time 178959748 ps
CPU time 0.85 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 206064 kb
Host smart-65e70e88-2541-4ee6-8d20-a0b76fd64cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12166
76339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1216676339
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2115856264
Short name T1623
Test name
Test status
Simulation time 206281563 ps
CPU time 0.84 seconds
Started Jul 09 05:13:10 PM PDT 24
Finished Jul 09 05:13:11 PM PDT 24
Peak memory 206120 kb
Host smart-cd53c7c4-53d5-445e-8843-0741a4576c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21158
56264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2115856264
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.558729837
Short name T1782
Test name
Test status
Simulation time 159513211 ps
CPU time 0.79 seconds
Started Jul 09 05:13:10 PM PDT 24
Finished Jul 09 05:13:12 PM PDT 24
Peak memory 206140 kb
Host smart-f0cfc0f7-4eac-412e-9941-0793f7cf6a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55872
9837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.558729837
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3531062833
Short name T1178
Test name
Test status
Simulation time 155026227 ps
CPU time 0.81 seconds
Started Jul 09 05:13:13 PM PDT 24
Finished Jul 09 05:13:14 PM PDT 24
Peak memory 206060 kb
Host smart-fb7fa1ab-fa5c-4a82-b75a-a10b112d860a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
62833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3531062833
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3223982405
Short name T2356
Test name
Test status
Simulation time 248870112 ps
CPU time 0.94 seconds
Started Jul 09 05:13:09 PM PDT 24
Finished Jul 09 05:13:11 PM PDT 24
Peak memory 206108 kb
Host smart-f6a84a71-4001-47bc-862a-7b2e0f542e3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3223982405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3223982405
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.890304990
Short name T216
Test name
Test status
Simulation time 153014858 ps
CPU time 0.74 seconds
Started Jul 09 05:13:13 PM PDT 24
Finished Jul 09 05:13:15 PM PDT 24
Peak memory 206064 kb
Host smart-96542e39-87d4-44a2-8ec2-a045d8066720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89030
4990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.890304990
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2086466054
Short name T1163
Test name
Test status
Simulation time 54262272 ps
CPU time 0.69 seconds
Started Jul 09 05:13:12 PM PDT 24
Finished Jul 09 05:13:13 PM PDT 24
Peak memory 206144 kb
Host smart-6eb41705-8300-437f-a8f6-16478b1829f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
66054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2086466054
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3222412677
Short name T217
Test name
Test status
Simulation time 17057083906 ps
CPU time 40.16 seconds
Started Jul 09 05:13:13 PM PDT 24
Finished Jul 09 05:13:53 PM PDT 24
Peak memory 206520 kb
Host smart-8e6bf356-4881-4203-8dc6-af5e14bb7e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32224
12677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3222412677
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1050658726
Short name T684
Test name
Test status
Simulation time 244422973 ps
CPU time 0.91 seconds
Started Jul 09 05:13:11 PM PDT 24
Finished Jul 09 05:13:12 PM PDT 24
Peak memory 206060 kb
Host smart-8e582fb9-a97b-4c7a-9f15-28e07db8a3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
58726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1050658726
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.95931194
Short name T1013
Test name
Test status
Simulation time 172799110 ps
CPU time 0.83 seconds
Started Jul 09 05:13:12 PM PDT 24
Finished Jul 09 05:13:14 PM PDT 24
Peak memory 206052 kb
Host smart-c69c17b3-0ae1-48e4-a27a-8471323873c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95931
194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.95931194
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1880714434
Short name T1940
Test name
Test status
Simulation time 4316607342 ps
CPU time 24.07 seconds
Started Jul 09 05:13:15 PM PDT 24
Finished Jul 09 05:13:40 PM PDT 24
Peak memory 206276 kb
Host smart-bcdb87b3-f125-4dc5-9856-34cae27be39b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1880714434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1880714434
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3944741200
Short name T1992
Test name
Test status
Simulation time 21524957642 ps
CPU time 475.8 seconds
Started Jul 09 05:13:19 PM PDT 24
Finished Jul 09 05:21:16 PM PDT 24
Peak memory 206356 kb
Host smart-62939951-4b08-4424-bb1b-0a59c58bddb5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3944741200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3944741200
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3982319652
Short name T1006
Test name
Test status
Simulation time 12832543195 ps
CPU time 261.44 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:17:37 PM PDT 24
Peak memory 206388 kb
Host smart-12616879-8ba0-4ddc-b40b-2fec1ad766f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3982319652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3982319652
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1247209545
Short name T2412
Test name
Test status
Simulation time 162168779 ps
CPU time 0.8 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206068 kb
Host smart-d8c9fc86-0d1b-4657-8417-493f0e511de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12472
09545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1247209545
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3295824191
Short name T2609
Test name
Test status
Simulation time 210827322 ps
CPU time 0.89 seconds
Started Jul 09 05:13:09 PM PDT 24
Finished Jul 09 05:13:10 PM PDT 24
Peak memory 206164 kb
Host smart-3aed21d3-811c-41f2-b3b4-42d706c4b632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
24191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3295824191
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3849274125
Short name T619
Test name
Test status
Simulation time 186659560 ps
CPU time 0.93 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 206164 kb
Host smart-19367a62-8a5b-417a-8a7a-7c1dece670a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38492
74125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3849274125
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2877129205
Short name T248
Test name
Test status
Simulation time 167702908 ps
CPU time 0.79 seconds
Started Jul 09 05:13:19 PM PDT 24
Finished Jul 09 05:13:21 PM PDT 24
Peak memory 206056 kb
Host smart-1f5dc416-c800-4ab9-be8f-d80078afacfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
29205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2877129205
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2968107929
Short name T1321
Test name
Test status
Simulation time 147614531 ps
CPU time 0.79 seconds
Started Jul 09 05:13:15 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206060 kb
Host smart-1ed1660d-660d-4d87-92e2-7bc709a9b484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29681
07929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2968107929
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1271027991
Short name T1328
Test name
Test status
Simulation time 248297066 ps
CPU time 0.99 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 206056 kb
Host smart-5c228060-9d37-4b9b-adf6-88b0b9398ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12710
27991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1271027991
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1408578774
Short name T1217
Test name
Test status
Simulation time 3247725500 ps
CPU time 93.9 seconds
Started Jul 09 05:13:13 PM PDT 24
Finished Jul 09 05:14:48 PM PDT 24
Peak memory 206244 kb
Host smart-c4621ec7-4aec-434a-8b56-1cc1e6c8744a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1408578774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1408578774
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.411201841
Short name T1625
Test name
Test status
Simulation time 150446195 ps
CPU time 0.84 seconds
Started Jul 09 05:13:16 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206128 kb
Host smart-b433e49c-e608-43eb-8620-eae561a3b137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41120
1841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.411201841
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2611420387
Short name T2068
Test name
Test status
Simulation time 227206214 ps
CPU time 0.88 seconds
Started Jul 09 05:13:20 PM PDT 24
Finished Jul 09 05:13:21 PM PDT 24
Peak memory 206136 kb
Host smart-2475278c-f4af-4156-aa4a-081980eeacd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26114
20387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2611420387
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2687297170
Short name T543
Test name
Test status
Simulation time 563246147 ps
CPU time 1.59 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206080 kb
Host smart-e4f8d741-ff25-48aa-85a4-5145e86fd89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26872
97170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2687297170
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2056218164
Short name T465
Test name
Test status
Simulation time 4914987615 ps
CPU time 139.4 seconds
Started Jul 09 05:13:16 PM PDT 24
Finished Jul 09 05:15:37 PM PDT 24
Peak memory 206408 kb
Host smart-eda64a75-6fc1-4880-b5cf-4135f935b6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20562
18164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2056218164
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1311857200
Short name T1306
Test name
Test status
Simulation time 50222916 ps
CPU time 0.74 seconds
Started Jul 09 05:13:22 PM PDT 24
Finished Jul 09 05:13:23 PM PDT 24
Peak memory 206168 kb
Host smart-418c819b-4814-4e3f-b3ac-73363968ff9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1311857200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1311857200
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3671965703
Short name T225
Test name
Test status
Simulation time 3419924019 ps
CPU time 4.57 seconds
Started Jul 09 05:13:16 PM PDT 24
Finished Jul 09 05:13:21 PM PDT 24
Peak memory 206356 kb
Host smart-0ceb1db3-1b52-4591-b9ef-53ac2357159e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3671965703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3671965703
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1192397034
Short name T1064
Test name
Test status
Simulation time 13335035545 ps
CPU time 12.69 seconds
Started Jul 09 05:13:13 PM PDT 24
Finished Jul 09 05:13:27 PM PDT 24
Peak memory 206156 kb
Host smart-a0743165-6a69-40e7-9ae7-6b4ca7bbb439
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1192397034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1192397034
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.53796217
Short name T2287
Test name
Test status
Simulation time 23324578689 ps
CPU time 20.69 seconds
Started Jul 09 05:13:15 PM PDT 24
Finished Jul 09 05:13:37 PM PDT 24
Peak memory 206264 kb
Host smart-1ff3c44d-e5d5-46be-9356-bfd432d8738d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=53796217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.53796217
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.806628452
Short name T2418
Test name
Test status
Simulation time 197876524 ps
CPU time 0.85 seconds
Started Jul 09 05:13:16 PM PDT 24
Finished Jul 09 05:13:18 PM PDT 24
Peak memory 206148 kb
Host smart-dff60716-104a-4931-813c-513392e3f128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80662
8452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.806628452
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1111021721
Short name T1366
Test name
Test status
Simulation time 174023374 ps
CPU time 0.85 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 205956 kb
Host smart-58834033-6166-43ec-a644-fc3dde9711d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
21721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1111021721
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.717263487
Short name T170
Test name
Test status
Simulation time 487799746 ps
CPU time 1.59 seconds
Started Jul 09 05:13:20 PM PDT 24
Finished Jul 09 05:13:22 PM PDT 24
Peak memory 206060 kb
Host smart-2552aa64-9053-4ce9-ab91-9976a6095966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71726
3487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.717263487
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.677764587
Short name T2483
Test name
Test status
Simulation time 360863898 ps
CPU time 1.08 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 205996 kb
Host smart-67000b35-9e90-4d6d-87f4-bc43a771a09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67776
4587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.677764587
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3980506691
Short name T1793
Test name
Test status
Simulation time 13606979819 ps
CPU time 27.05 seconds
Started Jul 09 05:13:20 PM PDT 24
Finished Jul 09 05:13:48 PM PDT 24
Peak memory 206364 kb
Host smart-f013eacd-9aa2-47a8-a2f8-773b0de5bc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
06691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3980506691
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3458216875
Short name T1114
Test name
Test status
Simulation time 344388821 ps
CPU time 1.32 seconds
Started Jul 09 05:13:20 PM PDT 24
Finished Jul 09 05:13:22 PM PDT 24
Peak memory 206132 kb
Host smart-d7b19d27-8bd2-4b23-a547-f27fcea8a471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
16875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3458216875
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.25377003
Short name T2530
Test name
Test status
Simulation time 138122885 ps
CPU time 0.8 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 206156 kb
Host smart-47c2bcd0-2f9e-4e71-9592-c7247c570ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25377
003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.25377003
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3542339004
Short name T1614
Test name
Test status
Simulation time 51946891 ps
CPU time 0.67 seconds
Started Jul 09 05:13:14 PM PDT 24
Finished Jul 09 05:13:16 PM PDT 24
Peak memory 206152 kb
Host smart-1bd1f570-ef40-4b20-bab1-2f4c6378cdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35423
39004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3542339004
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3940071531
Short name T453
Test name
Test status
Simulation time 834753691 ps
CPU time 2.12 seconds
Started Jul 09 05:13:13 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206344 kb
Host smart-88824594-783d-4760-b3ae-9db239c1e667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
71531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3940071531
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1218968078
Short name T1939
Test name
Test status
Simulation time 217512567 ps
CPU time 1.32 seconds
Started Jul 09 05:13:20 PM PDT 24
Finished Jul 09 05:13:22 PM PDT 24
Peak memory 206348 kb
Host smart-02b42767-20a9-4502-a0bd-d3088c48cad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12189
68078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1218968078
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.4136392983
Short name T1777
Test name
Test status
Simulation time 252535214 ps
CPU time 0.98 seconds
Started Jul 09 05:13:19 PM PDT 24
Finished Jul 09 05:13:21 PM PDT 24
Peak memory 206056 kb
Host smart-b8012d2e-c819-4b25-97ad-3058e2912c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41363
92983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.4136392983
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2620766585
Short name T488
Test name
Test status
Simulation time 151028234 ps
CPU time 0.77 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:13:20 PM PDT 24
Peak memory 206116 kb
Host smart-3ddbb6e0-87b4-45d2-874f-e1c7fd690886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26207
66585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2620766585
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1233110244
Short name T876
Test name
Test status
Simulation time 246548097 ps
CPU time 0.92 seconds
Started Jul 09 05:13:19 PM PDT 24
Finished Jul 09 05:13:20 PM PDT 24
Peak memory 206160 kb
Host smart-f7f4f688-658b-4fb9-8b9f-113ae47af6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12331
10244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1233110244
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.632985821
Short name T1234
Test name
Test status
Simulation time 9579919290 ps
CPU time 263.75 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:17:42 PM PDT 24
Peak memory 206480 kb
Host smart-8982d4b7-0bf0-4507-97fe-dc9a55c74ad3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=632985821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.632985821
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3212917481
Short name T1241
Test name
Test status
Simulation time 246911974 ps
CPU time 1 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:13:19 PM PDT 24
Peak memory 206156 kb
Host smart-d4a1a618-f8cc-4bbb-b37a-3cc7845936f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129
17481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3212917481
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3425851769
Short name T1478
Test name
Test status
Simulation time 23362303405 ps
CPU time 28.83 seconds
Started Jul 09 05:13:21 PM PDT 24
Finished Jul 09 05:13:50 PM PDT 24
Peak memory 206216 kb
Host smart-778b830d-f33b-4587-a0c0-abf7dea37c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34258
51769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3425851769
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4126122111
Short name T2668
Test name
Test status
Simulation time 3349083934 ps
CPU time 4.94 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:13:24 PM PDT 24
Peak memory 206180 kb
Host smart-c59ce793-40f9-40e7-938d-a506e32339e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41261
22111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4126122111
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1197102870
Short name T2039
Test name
Test status
Simulation time 9815824224 ps
CPU time 263.28 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:17:41 PM PDT 24
Peak memory 206344 kb
Host smart-ff559c06-df64-447e-94d7-2b48ec6bd02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11971
02870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1197102870
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.64554175
Short name T2382
Test name
Test status
Simulation time 5667389266 ps
CPU time 160.34 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:15:58 PM PDT 24
Peak memory 206272 kb
Host smart-92ad3aa2-0c09-455e-92dd-77846e826d6d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=64554175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.64554175
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2486120003
Short name T1491
Test name
Test status
Simulation time 267329480 ps
CPU time 0.99 seconds
Started Jul 09 05:13:19 PM PDT 24
Finished Jul 09 05:13:21 PM PDT 24
Peak memory 206044 kb
Host smart-f777a6f4-4589-488e-b1ef-0120a21a61e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2486120003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2486120003
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1106174031
Short name T1245
Test name
Test status
Simulation time 194674910 ps
CPU time 0.89 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:13:19 PM PDT 24
Peak memory 206060 kb
Host smart-80b51f1e-5402-48c5-a75f-829c95ed50b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11061
74031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1106174031
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3194292712
Short name T1086
Test name
Test status
Simulation time 6099113759 ps
CPU time 43.01 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:14:01 PM PDT 24
Peak memory 206464 kb
Host smart-99a67bd1-15c9-4e44-9534-5d1fcb0b593e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31942
92712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3194292712
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3821576047
Short name T334
Test name
Test status
Simulation time 4759024446 ps
CPU time 130.75 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:15:29 PM PDT 24
Peak memory 206312 kb
Host smart-04de2708-0d36-41df-9c28-6185d74dc050
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3821576047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3821576047
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.213694724
Short name T1684
Test name
Test status
Simulation time 146975780 ps
CPU time 0.82 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:13:19 PM PDT 24
Peak memory 206072 kb
Host smart-8e30dcde-25f5-456b-8b07-8ad9d6393940
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=213694724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.213694724
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1293755518
Short name T1977
Test name
Test status
Simulation time 151788444 ps
CPU time 0.77 seconds
Started Jul 09 05:13:21 PM PDT 24
Finished Jul 09 05:13:22 PM PDT 24
Peak memory 206164 kb
Host smart-e6708273-d3d7-4f0f-8192-e56ff7b970cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12937
55518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1293755518
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2586928485
Short name T119
Test name
Test status
Simulation time 270899676 ps
CPU time 0.97 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:13:20 PM PDT 24
Peak memory 206152 kb
Host smart-f32bc73c-5fbd-49d8-b57f-48d6afbe8297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
28485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2586928485
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3142776126
Short name T1109
Test name
Test status
Simulation time 183295703 ps
CPU time 0.86 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:13:19 PM PDT 24
Peak memory 206064 kb
Host smart-6d35e2be-b98d-404b-932a-0e6ca6aed7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31427
76126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3142776126
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3329941386
Short name T962
Test name
Test status
Simulation time 161754328 ps
CPU time 0.78 seconds
Started Jul 09 05:13:19 PM PDT 24
Finished Jul 09 05:13:20 PM PDT 24
Peak memory 206164 kb
Host smart-42b1f950-7451-4f94-ad45-077066ca37b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
41386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3329941386
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.122293085
Short name T982
Test name
Test status
Simulation time 160138738 ps
CPU time 0.81 seconds
Started Jul 09 05:13:15 PM PDT 24
Finished Jul 09 05:13:17 PM PDT 24
Peak memory 206376 kb
Host smart-ec88ea3c-3ba1-44ee-8939-791a1cc86cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12229
3085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.122293085
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2190906633
Short name T149
Test name
Test status
Simulation time 149592047 ps
CPU time 0.88 seconds
Started Jul 09 05:13:21 PM PDT 24
Finished Jul 09 05:13:22 PM PDT 24
Peak memory 206160 kb
Host smart-f860e6cc-b6d1-4679-9781-662edf9f9cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21909
06633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2190906633
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.746601260
Short name T1748
Test name
Test status
Simulation time 185847450 ps
CPU time 0.87 seconds
Started Jul 09 05:13:16 PM PDT 24
Finished Jul 09 05:13:18 PM PDT 24
Peak memory 206036 kb
Host smart-0607016c-ccf2-4d86-8d83-e5bed5adcc23
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=746601260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.746601260
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3829558309
Short name T1271
Test name
Test status
Simulation time 157008947 ps
CPU time 0.83 seconds
Started Jul 09 05:13:17 PM PDT 24
Finished Jul 09 05:13:18 PM PDT 24
Peak memory 206116 kb
Host smart-df3bc189-8b5a-4d40-8db0-bd78d998d90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38295
58309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3829558309
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.4245779605
Short name T1277
Test name
Test status
Simulation time 79598309 ps
CPU time 0.68 seconds
Started Jul 09 05:13:18 PM PDT 24
Finished Jul 09 05:13:19 PM PDT 24
Peak memory 206112 kb
Host smart-ef344860-5b67-4414-ab80-2c9b2be1623e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457
79605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.4245779605
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.719705651
Short name T805
Test name
Test status
Simulation time 18345817952 ps
CPU time 38.2 seconds
Started Jul 09 05:13:30 PM PDT 24
Finished Jul 09 05:14:10 PM PDT 24
Peak memory 206472 kb
Host smart-609771ae-7355-4d63-af3c-09746db49038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71970
5651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.719705651
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.4019961880
Short name T994
Test name
Test status
Simulation time 166835807 ps
CPU time 0.82 seconds
Started Jul 09 05:13:21 PM PDT 24
Finished Jul 09 05:13:22 PM PDT 24
Peak memory 206128 kb
Host smart-3cd4e071-38da-4a50-8ed5-f43f9e647a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199
61880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.4019961880
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3177394836
Short name T1734
Test name
Test status
Simulation time 250289495 ps
CPU time 0.95 seconds
Started Jul 09 05:13:27 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 206016 kb
Host smart-65f12fc5-dc5f-4d9f-b477-ee7f3e80df15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
94836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3177394836
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.817673380
Short name T2385
Test name
Test status
Simulation time 7796782397 ps
CPU time 68.84 seconds
Started Jul 09 05:13:22 PM PDT 24
Finished Jul 09 05:14:31 PM PDT 24
Peak memory 206364 kb
Host smart-a60dd15f-58cd-4e57-881c-a26b190f4e29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=817673380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.817673380
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2659246352
Short name T328
Test name
Test status
Simulation time 17247829283 ps
CPU time 377.67 seconds
Started Jul 09 05:13:22 PM PDT 24
Finished Jul 09 05:19:41 PM PDT 24
Peak memory 206392 kb
Host smart-f0b4be5f-9ffd-4b39-93a1-c7ba28579fd9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2659246352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2659246352
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.289285055
Short name T1054
Test name
Test status
Simulation time 19232093377 ps
CPU time 150.14 seconds
Started Jul 09 05:13:26 PM PDT 24
Finished Jul 09 05:15:57 PM PDT 24
Peak memory 206232 kb
Host smart-53dbf790-0374-4bca-8cd7-e3d134758fb4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=289285055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.289285055
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3638736749
Short name T1669
Test name
Test status
Simulation time 260864193 ps
CPU time 0.96 seconds
Started Jul 09 05:13:26 PM PDT 24
Finished Jul 09 05:13:28 PM PDT 24
Peak memory 206108 kb
Host smart-0e26a7dd-6274-4e7e-8567-c2663278907f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36387
36749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3638736749
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1898657148
Short name T417
Test name
Test status
Simulation time 179453996 ps
CPU time 0.9 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:31 PM PDT 24
Peak memory 206164 kb
Host smart-53948672-892d-4f3c-96a9-d68e99e04aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
57148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1898657148
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.60776663
Short name T1426
Test name
Test status
Simulation time 139688807 ps
CPU time 0.75 seconds
Started Jul 09 05:13:23 PM PDT 24
Finished Jul 09 05:13:24 PM PDT 24
Peak memory 206140 kb
Host smart-932ff0aa-57b1-4c11-b59b-d937d8b01990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60776
663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.60776663
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.564441674
Short name T493
Test name
Test status
Simulation time 156222341 ps
CPU time 0.81 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 206128 kb
Host smart-4858711c-57e1-4f6a-8c94-a6ad7e3fd1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56444
1674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.564441674
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1985458265
Short name T1933
Test name
Test status
Simulation time 165680347 ps
CPU time 0.84 seconds
Started Jul 09 05:13:32 PM PDT 24
Finished Jul 09 05:13:33 PM PDT 24
Peak memory 206136 kb
Host smart-c4fafbba-ab83-4e0f-9d27-1effbfb66b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19854
58265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1985458265
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.961322567
Short name T804
Test name
Test status
Simulation time 222186125 ps
CPU time 0.92 seconds
Started Jul 09 05:13:27 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 206116 kb
Host smart-0ed4a8b0-b063-4851-96da-2c5068feb1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96132
2567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.961322567
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.3742967299
Short name T425
Test name
Test status
Simulation time 5731373792 ps
CPU time 157.53 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:16:07 PM PDT 24
Peak memory 206348 kb
Host smart-b6a72c51-296c-4430-a437-8b9a84b45a2f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3742967299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.3742967299
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.515251678
Short name T568
Test name
Test status
Simulation time 170167985 ps
CPU time 0.87 seconds
Started Jul 09 05:13:26 PM PDT 24
Finished Jul 09 05:13:28 PM PDT 24
Peak memory 206108 kb
Host smart-0769993f-7e48-4e3c-8c83-bb8402d81e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51525
1678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.515251678
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3441807977
Short name T850
Test name
Test status
Simulation time 180286047 ps
CPU time 0.89 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:30 PM PDT 24
Peak memory 206060 kb
Host smart-3bf1c01f-4a39-4ad9-9c20-86d47ff0c048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
07977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3441807977
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.2887484700
Short name T1231
Test name
Test status
Simulation time 507496292 ps
CPU time 1.4 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:13:30 PM PDT 24
Peak memory 206128 kb
Host smart-f75cd1b4-5fb8-44e3-93ac-64287feb9e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28874
84700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2887484700
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1707940171
Short name T1700
Test name
Test status
Simulation time 5511241884 ps
CPU time 151.39 seconds
Started Jul 09 05:13:28 PM PDT 24
Finished Jul 09 05:16:00 PM PDT 24
Peak memory 206316 kb
Host smart-56103c43-98ca-4dee-894f-9d587a58ad2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17079
40171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1707940171
Directory /workspace/9.usbdev_streaming_out/latest
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