Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	166937	1		T1	2		T2	2		T3	2
all_values[1]	166937	1		T1	2		T2	2		T3	2
all_values[2]	166937	1		T1	2		T2	2		T3	2
all_values[3]	166937	1		T1	2		T2	2		T3	2
all_values[4]	166937	1		T1	2		T2	2		T3	2
all_values[5]	166937	1		T1	2		T2	2		T3	2
all_values[6]	166937	1		T1	2		T2	2		T3	2
all_values[7]	166937	1		T1	2		T2	2		T3	2
all_values[8]	166937	1		T1	2		T2	2		T3	2
all_values[9]	166937	1		T1	2		T2	2		T3	2
all_values[10]	166937	1		T1	2		T2	2		T3	2
all_values[11]	166937	1		T1	2		T2	2		T3	2
all_values[12]	166937	1		T1	2		T2	2		T3	2
all_values[13]	166937	1		T1	2		T2	2		T3	2
all_values[14]	166937	1		T1	2		T2	2		T3	2
all_values[15]	166937	1		T1	2		T2	2		T3	2
all_values[16]	166937	1		T1	2		T2	2		T3	2
all_values[17]	166937	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2998001	1		T1	36		T2	36		T3	36
auto[1]	6865	1		T29	3		T7	2		T18	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2999750	1		T1	36		T2	36		T3	36
auto[1]	5116	1		T204	67		T201	72		T202	122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	165955	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	164	1		T204	3		T202	6		T203	3
all_values[0]	auto[1]	auto[0]	700	1		T29	3		T50	3		T51	3
all_values[0]	auto[1]	auto[1]	118	1		T202	1		T203	2		T205	4
all_values[1]	auto[0]	auto[0]	165126	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	142	1		T201	1		T205	4		T286	4
all_values[1]	auto[1]	auto[0]	1522	1		T7	2		T18	2		T8	2
all_values[1]	auto[1]	auto[1]	147	1		T204	5		T201	3		T202	8
all_values[2]	auto[0]	auto[0]	166526	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	158	1		T204	4		T201	4		T202	4
all_values[2]	auto[1]	auto[0]	128	1		T39	2		T45	2		T46	2
all_values[2]	auto[1]	auto[1]	125	1		T204	1		T202	4		T203	1
all_values[3]	auto[0]	auto[0]	165200	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	144	1		T204	1		T201	4		T203	1
all_values[3]	auto[1]	auto[0]	1466	1		T70	1429		T204	1		T202	4
all_values[3]	auto[1]	auto[1]	127	1		T204	3		T201	1		T202	3
all_values[4]	auto[0]	auto[0]	166627	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	144	1		T204	2		T201	4		T202	4
all_values[4]	auto[1]	auto[0]	33	1		T71	2		T205	1		T206	4
all_values[4]	auto[1]	auto[1]	133	1		T204	3		T201	1		T202	4
all_values[5]	auto[0]	auto[0]	166630	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	128	1		T204	3		T201	3		T202	6
all_values[5]	auto[1]	auto[0]	37	1		T201	1		T205	3		T287	1
all_values[5]	auto[1]	auto[1]	142	1		T201	1		T202	1		T203	1
all_values[6]	auto[0]	auto[0]	166623	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	158	1		T201	4		T202	7		T203	3
all_values[6]	auto[1]	auto[0]	27	1		T204	2		T202	1		T203	1
all_values[6]	auto[1]	auto[1]	129	1		T201	1		T205	4		T206	1
all_values[7]	auto[0]	auto[0]	166613	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	156	1		T204	1		T201	1		T202	5
all_values[7]	auto[1]	auto[0]	24	1		T52	2		T53	2		T54	2
all_values[7]	auto[1]	auto[1]	144	1		T204	4		T201	4		T202	3
all_values[8]	auto[0]	auto[0]	166610	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	136	1		T204	4		T201	4		T202	3
all_values[8]	auto[1]	auto[0]	40	1		T55	11		T286	2		T288	1
all_values[8]	auto[1]	auto[1]	151	1		T204	1		T201	1		T202	4
all_values[9]	auto[0]	auto[0]	166610	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	128	1		T204	1		T201	4		T202	3
all_values[9]	auto[1]	auto[0]	53	1		T67	5		T68	5		T69	5
all_values[9]	auto[1]	auto[1]	146	1		T204	4		T201	1		T202	5
all_values[10]	auto[0]	auto[0]	166617	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	151	1		T201	3		T202	5		T203	3
all_values[10]	auto[1]	auto[0]	21	1		T204	5		T201	1		T203	1
all_values[10]	auto[1]	auto[1]	148	1		T201	1		T202	2		T203	1
all_values[11]	auto[0]	auto[0]	166526	1		T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	139	1		T204	1		T201	1		T202	2
all_values[11]	auto[1]	auto[0]	117	1		T49	2		T75	2		T76	2
all_values[11]	auto[1]	auto[1]	155	1		T204	4		T201	4		T202	4
all_values[12]	auto[0]	auto[0]	166616	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	140	1		T204	5		T202	3		T203	3
all_values[12]	auto[1]	auto[0]	43	1		T78	3		T79	3		T80	3
all_values[12]	auto[1]	auto[1]	138	1		T202	3		T203	1		T206	5
all_values[13]	auto[0]	auto[0]	166628	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	167	1		T204	1		T201	4		T202	6
all_values[13]	auto[1]	auto[0]	18	1		T286	2		T288	1		T283	3
all_values[13]	auto[1]	auto[1]	124	1		T204	4		T201	1		T202	2
all_values[14]	auto[0]	auto[0]	166638	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	113	1		T201	5		T202	1		T205	4
all_values[14]	auto[1]	auto[0]	23	1		T204	4		T202	1		T206	3
all_values[14]	auto[1]	auto[1]	163	1		T202	5		T203	5		T205	1
all_values[15]	auto[0]	auto[0]	166626	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	149	1		T204	3		T202	5		T203	3
all_values[15]	auto[1]	auto[0]	27	1		T204	1		T202	2		T203	1
all_values[15]	auto[1]	auto[1]	135	1		T201	4		T202	1		T203	1
all_values[16]	auto[0]	auto[0]	166592	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	159	1		T204	4		T201	4		T202	8
all_values[16]	auto[1]	auto[0]	41	1		T72	8		T73	8		T74	8
all_values[16]	auto[1]	auto[1]	145	1		T204	1		T203	3		T205	3
all_values[17]	auto[0]	auto[0]	166623	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	139	1		T204	4		T202	3		T203	2
all_values[17]	auto[1]	auto[0]	44	1		T59	2		T60	2		T201	1
all_values[17]	auto[1]	auto[1]	131	1		T201	3		T202	1		T203	3