Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	166937	1		T1	2		T2	2		T3	2
all_pins[1]	166937	1		T1	2		T2	2		T3	2
all_pins[2]	166937	1		T1	2		T2	2		T3	2
all_pins[3]	166937	1		T1	2		T2	2		T3	2
all_pins[4]	166937	1		T1	2		T2	2		T3	2
all_pins[5]	166937	1		T1	2		T2	2		T3	2
all_pins[6]	166937	1		T1	2		T2	2		T3	2
all_pins[7]	166937	1		T1	2		T2	2		T3	2
all_pins[8]	166937	1		T1	2		T2	2		T3	2
all_pins[9]	166937	1		T1	2		T2	2		T3	2
all_pins[10]	166937	1		T1	2		T2	2		T3	2
all_pins[11]	166937	1		T1	2		T2	2		T3	2
all_pins[12]	166937	1		T1	2		T2	2		T3	2
all_pins[13]	166937	1		T1	2		T2	2		T3	2
all_pins[14]	166937	1		T1	2		T2	2		T3	2
all_pins[15]	166937	1		T1	2		T2	2		T3	2
all_pins[16]	166937	1		T1	2		T2	2		T3	2
all_pins[17]	166937	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3002576	1		T1	36		T2	36		T3	36
values[0x1]	2290	1		T7	1		T18	1		T8	1
transitions[0x0=>0x1]	1999	1		T7	1		T18	1		T8	1
transitions[0x1=>0x0]	2011	1		T7	1		T18	1		T8	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	166833	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	104	1		T289	1		T290	1		T291	1
all_pins[0]	transitions[0x0=>0x1]	94	1		T289	1		T290	1		T291	1
all_pins[0]	transitions[0x1=>0x0]	1004	1		T7	1		T18	1		T8	1
all_pins[1]	values[0x0]	165923	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1014	1		T7	1		T18	1		T8	1
all_pins[1]	transitions[0x0=>0x1]	995	1		T7	1		T18	1		T8	1
all_pins[1]	transitions[0x1=>0x0]	105	1		T39	1		T45	1		T46	1
all_pins[2]	values[0x0]	166813	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	124	1		T39	1		T45	1		T46	1
all_pins[2]	transitions[0x0=>0x1]	105	1		T39	1		T45	1		T46	1
all_pins[2]	transitions[0x1=>0x0]	55	1		T70	1		T201	1		T202	2
all_pins[3]	values[0x0]	166863	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	74	1		T70	1		T201	1		T202	2
all_pins[3]	transitions[0x0=>0x1]	64	1		T70	1		T201	1		T202	2
all_pins[3]	transitions[0x1=>0x0]	57	1		T71	1		T204	2		T202	2
all_pins[4]	values[0x0]	166870	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	67	1		T71	1		T204	2		T202	2
all_pins[4]	transitions[0x0=>0x1]	49	1		T71	1		T204	2		T202	2
all_pins[4]	transitions[0x1=>0x0]	45	1		T201	1		T202	1		T206	2
all_pins[5]	values[0x0]	166874	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	63	1		T201	1		T202	1		T203	1
all_pins[5]	transitions[0x0=>0x1]	49	1		T201	1		T202	1		T203	1
all_pins[5]	transitions[0x1=>0x0]	44	1		T205	1		T287	1		T288	2
all_pins[6]	values[0x0]	166879	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	58	1		T205	1		T287	1		T288	3
all_pins[6]	transitions[0x0=>0x1]	46	1		T205	1		T287	1		T288	2
all_pins[6]	transitions[0x1=>0x0]	51	1		T52	1		T53	1		T54	1
all_pins[7]	values[0x0]	166874	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	63	1		T52	1		T53	1		T54	1
all_pins[7]	transitions[0x0=>0x1]	49	1		T52	1		T53	1		T54	1
all_pins[7]	transitions[0x1=>0x0]	47	1		T55	1		T201	1		T202	1
all_pins[8]	values[0x0]	166876	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	61	1		T55	1		T204	1		T201	1
all_pins[8]	transitions[0x0=>0x1]	47	1		T55	1		T201	1		T202	1
all_pins[8]	transitions[0x1=>0x0]	66	1		T67	2		T68	2		T69	2
all_pins[9]	values[0x0]	166857	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	80	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x0=>0x1]	59	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x1=>0x0]	44	1		T201	1		T202	1		T203	1
all_pins[10]	values[0x0]	166872	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	65	1		T201	1		T202	1		T203	1
all_pins[10]	transitions[0x0=>0x1]	51	1		T201	1		T202	1		T205	2
all_pins[10]	transitions[0x1=>0x0]	97	1		T49	1		T75	1		T76	1
all_pins[11]	values[0x0]	166826	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x1]	111	1		T49	1		T75	1		T76	1
all_pins[11]	transitions[0x0=>0x1]	93	1		T49	1		T75	1		T76	1
all_pins[11]	transitions[0x1=>0x0]	67	1		T78	1		T79	1		T80	1
all_pins[12]	values[0x0]	166852	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	85	1		T78	1		T79	1		T80	1
all_pins[12]	transitions[0x0=>0x1]	66	1		T78	1		T79	1		T80	1
all_pins[12]	transitions[0x1=>0x0]	35	1		T204	2		T201	1		T202	1
all_pins[13]	values[0x0]	166883	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	54	1		T204	2		T201	1		T202	2
all_pins[13]	transitions[0x0=>0x1]	33	1		T204	2		T201	1		T202	1
all_pins[13]	transitions[0x1=>0x0]	58	1		T202	3		T205	1		T292	2
all_pins[14]	values[0x0]	166858	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	79	1		T202	4		T203	4		T205	1
all_pins[14]	transitions[0x0=>0x1]	59	1		T202	3		T203	3		T205	1
all_pins[14]	transitions[0x1=>0x0]	44	1		T201	3		T205	1		T286	2
all_pins[15]	values[0x0]	166873	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	64	1		T201	3		T202	1		T203	1
all_pins[15]	transitions[0x0=>0x1]	51	1		T201	3		T202	1		T203	1
all_pins[15]	transitions[0x1=>0x0]	58	1		T72	4		T73	4		T74	4
all_pins[16]	values[0x0]	166866	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	71	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	57	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	39	1		T59	1		T60	1		T201	1
all_pins[17]	values[0x0]	166884	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	53	1		T59	1		T60	1		T201	1
all_pins[17]	transitions[0x0=>0x1]	32	1		T59	1		T60	1		T201	1
all_pins[17]	transitions[0x1=>0x0]	95	1		T289	1		T290	1		T291	1